Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: in response to a trigger condition, determining a plurality of first-class source units and at least one target unit; determining a plurality of pieces of first mapping information from the plurality of pieces of first-class candidate mapping information according to the first-class source units; performing integration comparison on the first mapping information to obtain an integration comparison result; determining second mapping information from a plurality of pieces of second-class candidate mapping information according to an integrated comparison result; and copying the first valid data stored in the first type of source units to the target unit according to the second mapping information. Therefore, the working efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of memory control technology, and in particular to a memory management method and a storage device. Background Art

[0002] In the field of storage, garbage collection (GC) technology is particularly important, especially in non-volatile storage devices such as solid-state drives (SSDs) and flash memory. With the continuous increase in data volume and the widespread application of storage devices, it is crucial to effectively manage storage space and improve data writing efficiency. Garbage collection is a method for managing and optimizing storage space. It frees up storage space by regularly organizing and cleaning invalid data blocks that are no longer used in storage devices so that new data can be written effectively.

[0003] Therefore, the garbage collection efficiency and even the overall working efficiency of the storage device are crucial. Summary of the invention

[0004] The present invention provides a memory management method and a storage device, which can improve the collection, copying and / or movement efficiency of valid data by the storage device by integrating and comparing specific types of mapping information, thereby improving the overall working efficiency of the storage device.

[0005] An embodiment of the present invention provides a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: in response to a trigger condition, determining multiple first-class source units and at least one target unit from the multiple physical units; determining multiple first mapping information from multiple first-class candidate mapping information based on the multiple first-class source units, wherein the multiple first mapping information respectively reflects the association between the multiple first-class source units and multiple second-class candidate mapping information; performing integrated comparison on the multiple first mapping information to obtain an integrated comparison result; based on the integrated comparison result, determining at least one second mapping information from the multiple second-class candidate mapping information, wherein the at least one second mapping information reflects the distribution of first valid data in the multiple first-class source units; and based on the at least one second mapping information, copying the first valid data stored in the multiple first-class source units to the at least one target unit.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: determine a plurality of first-class source units and at least one target unit from the plurality of physical units in response to a trigger condition; determine a plurality of first mapping information from a plurality of first-class candidate mapping information according to the plurality of first-class source units, wherein the plurality of first mapping information respectively reflects the association between the plurality of first-class source units and a plurality of second-class candidate mapping information; perform integrated comparison on the plurality of first mapping information to obtain an integrated comparison result; determine at least one second mapping information from the plurality of second-class candidate mapping information according to the integrated comparison result, wherein the at least one second mapping information reflects the distribution of the first valid data in the plurality of first-class source units; and copy the first valid data stored in the plurality of first-class source units to the at least one target unit according to the at least one second mapping information. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a data consolidation operation according to an embodiment of the present invention;

[0011] Figure 5 is a flowchart of a memory management method according to an embodiment of the present invention;

[0012] Figure 6 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1, the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0015] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0016] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0017] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0018] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0019] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0020] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0021] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0022] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0023] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (C). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0024] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0025] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0026] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0027] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0028] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A), 301(A+1)-301(B) and 301(B+1)-301(C) to the data area 31, the idle area 32 and the system area 33 respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. The physical units 301(A+1)-301(B) in the idle area 32 do not store data (for example, valid data). In addition, the physical units 301(B+1)-301(C) in the system area 33 are used to store system data (also called management data). This system data can be used to manage the storage device 12 and maintain the normal operation of the storage device 12.

[0029] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0030] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0031] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0032] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0033] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0034] In one embodiment, the memory control circuit 23 may not map any logical unit to the system area 33 (eg, physical units 301 (B+1) 301 (C)). This prevents the system data stored in the system area 33 from being accidentally modified or deleted by the user.

[0035] In one embodiment, the system data stored in the system area 33 may include a logic-to-physical mapping table, a bad block management table, a valid data management table, a voltage management table, or other types of management tables. The bad block management table may be used to record information related to damaged physical units (also referred to as bad blocks) in the memory module 122. The memory control circuit 23 may determine and manage the bad blocks in the memory module 122 according to the information recorded in the bad block management table. The valid data management table may be used to record information related to valid data stored in at least some physical units in the memory module 122. The memory control circuit 23 may determine and manage valid data stored in at least some physical units in the memory module 122 according to the information recorded in the valid data management table. In addition, the voltage management table may be used to record information related to the read voltage used by the memory module 122. The memory control circuit 23 may determine and manage the voltage (e.g., read voltage, write voltage, and / or erase voltage) used by the memory module 122 according to the information recorded in the voltage management table.

[0036] In one embodiment, the memory control circuit 23 may detect a trigger condition. In response to the trigger condition, the memory control circuit 23 may initiate and perform a data consolidation operation to determine a plurality of source cells (also referred to as first-type source cells) and at least one target cell from the memory module 122. However, in one embodiment, if the trigger condition is not detected, the memory control circuit 23 may not initiate the data consolidation operation.

[0037] In one embodiment, the memory control circuit 23 may detect the total number of idle physical cells in the memory module 122. For example, each physical cell in the idle area 32 (e.g., each physical cell in the physical cells 301(A+1) to 301(B)) may be considered as an idle physical cell. For example, the total number of idle physical cells in the memory module 122 may be the same as the total number of all physical cells in the idle area 32 (e.g., each physical cell in the physical cells 301(A+1) to 301(B)). In addition, each physical cell in the data area 31 (e.g., each physical cell in the physical cells 301(1) to 301(A)) may be considered as a non-idle physical cell.

[0038] In one embodiment, the trigger condition is that the total number of idle physical units in the memory module 122 is less than a critical value. For example, the memory control circuit 23 can determine whether the total number of idle physical units in the memory module 122 is less than (or equal to) a critical value. For example, this critical value can be 3, 5, 10 or other integers greater than zero. If this total number is less than (or equal to) this critical value, the memory control circuit 23 can determine that the trigger condition is detected and start and execute the aforementioned data consolidation operation. This data consolidation operation can be used to release new idle physical units in the memory module 122. For example, this data consolidation operation may include a garbage collection (GC) operation. By performing this data consolidation operation, the memory control circuit 23 can gradually increase the total number of idle physical units in the memory module 122. However, if this total number is not less than (or greater than) this critical value, the memory control circuit 23 can determine that the trigger condition is not detected and does not start this data consolidation operation. It should be noted that, in one embodiment, the aforementioned data consolidation operation may also be initiated based on other types of trigger conditions, depending on practical requirements, and the present invention is not limited thereto.

[0039] In one embodiment, after starting the data consolidation operation, the memory control circuit 23 may determine a plurality of source units (also referred to as first-type source units) and at least one target unit from the memory module 122 according to a screening condition. Each first-type source unit may include a physical unit in the data area 31. In addition, each target unit may include a physical unit in the idle area 32. Thereafter, in the data consolidation operation, the memory control circuit 23 may copy (or move) the valid data currently stored in the source unit to the target unit. If the valid data stored in a certain source unit has been completely copied (or moved) to the target unit, the source unit may be erased and become a new idle physical unit. Thus, the purpose of releasing a new idle physical unit is achieved.

[0040] In one embodiment, the memory control circuit 23 may obtain valid count information corresponding to a plurality of non-idle physical units in the memory module 122. The valid count information may reflect the total number of at least one physical programming unit storing valid data in each non-idle physical unit. In one embodiment, the valid count information may belong to part of the data in the aforementioned valid data management table, and the valid count information may be stored in the system area 33. Alternatively, in one embodiment, the valid count information may be stored in each non-idle physical unit. For example, the valid count information corresponding to a certain non-idle physical unit may be stored in a specific physical programming unit (e.g., the last physical page or other physical pages) in the non-idle physical unit.

[0041] In one embodiment, after obtaining the valid count information, the memory control circuit 23 may sort the plurality of non-idle physical units according to the valid count information to obtain a sorting result. For example, the memory control circuit 23 may sort the plurality of non-idle physical units from most to least or from least to most according to the valid count information based on the amount of valid data stored in each non-idle physical unit to obtain the sorting result.

[0042] In one embodiment, the memory control circuit 23 may determine a value (also referred to as a decision value) based on the sorting result, the valid count information, and the available capacity of the determined target unit. This decision value may be used to define the total number of the plurality of first-type source units. Thereafter, the memory control circuit 23 may determine the plurality of first-type source units from the plurality of non-idle physical units after sorting based on this decision value. For example, assuming that this decision value is "4", the memory control circuit 23 may determine the 4 physical units storing the least (or relatively less) valid data from the plurality of non-idle physical units after sorting as the plurality of first-type source units.

[0043] In one embodiment, the memory control circuit 23 can dynamically adjust the decision value according to the sorting result, the valid count information and the determined available capacity of the target unit. By adjusting the decision value, the memory control circuit 23 can ensure as much as possible that, in the data consolidation operation, each time a target unit is filled with valid data copied (or moved) from a source unit (e.g., a first type of source unit), at least two (or more) idle physical units can be released. Thus, the efficiency of the data consolidation operation can be effectively improved.

[0044] In one embodiment, it is assumed that the determined available capacity of the target unit is the total capacity of 512 physical programming units. The sorting result and the valid count information reflect that the valid count information of the non-idle physical units storing the least valid data in the current memory module 122 are "102", "120", "140" and "150" respectively. According to the sorting result, the valid count information and the determined available capacity of the target unit, the memory control circuit 23 can set the decision value to "4". Then, the memory control circuit 23 can determine the 4 non-idle physical units storing the least valid data in the current memory module 122 as the multiple first-class source units. In this way, it can be ensured that the total amount of valid data stored in the multiple first-class source units is not greater than the determined available capacity of the target unit.

[0045] In one embodiment, after determining the first type of source units and the target units, the memory control circuit 23 may determine a plurality of specific mapping information (also referred to as first mapping information) from a plurality of mapping information (also referred to as first type candidate mapping information) according to the determined first type of source units. The plurality of first mapping information respectively (i.e., one-to-one) corresponds to the plurality of first type of source units. In particular, the plurality of first mapping information may respectively reflect the association between the plurality of first type of source units and a plurality of mapping information (also referred to as second type candidate mapping information).

[0046] In one embodiment, it is assumed that the plurality of first-type source units include a first source unit and a second source unit. The first source unit may be a certain physical unit in the data area 31, and the second source unit may be another physical unit in the data area 31. After determining the first source unit and the second source unit, the memory control circuit 23 may obtain a plurality of mapping information (i.e., first mapping information) corresponding to the first source unit and the second source unit respectively from the plurality of first-type candidate mapping information.

[0047] In one embodiment, the first mapping information corresponding to the first source unit includes first bitmap information, and the first mapping information corresponding to the second source unit includes second bitmap information. The first bitmap information may reflect the association between the first source unit and the plurality of second-category candidate mapping information (also referred to as the first association). The second bitmap information may reflect the association between the second source unit and the plurality of second-category candidate mapping information (also referred to as the second association). The first association may be the same as or different from the second association.

[0048] In one embodiment, the first bit mapping information includes a plurality of bits (also referred to as first bits). The second bit mapping information includes a plurality of bits (also referred to as second bits). The numerical distribution state of the plurality of first bits (also referred to as the first numerical distribution state) may reflect that the first source unit is related to part of the information in the plurality of second-category candidate mapping information (also referred to as the first partial information). The numerical distribution state of the plurality of second bits (also referred to as the second numerical distribution state) may reflect that the second source unit is related to part of the information in the plurality of second-category candidate mapping information (also referred to as the second partial information). The first partial information may be the same as or different from the second partial information.

[0049] In one embodiment, it is assumed that the first numerical distribution state is "0101" and the second numerical distribution state is "0110". The first numerical distribution state (i.e., the first, second, third and fourth bits in the first bit are "0", "1", "0" and "1" in sequence) reflects that the first source unit is related to the second and fourth mapping information in the multiple second-category candidate mapping information, and the first source unit is irrelevant to the first and third mapping information in the multiple second-category candidate mapping information. On the other hand, the second numerical distribution state (i.e., the first, second, third and fourth bits in the second bit are "0", "1", "1" and "0" in sequence) reflects that the second source unit is related to the second and third mapping information in the multiple second-category candidate mapping information, and the second source unit is irrelevant to the first and fourth mapping information in the multiple second-category candidate mapping information. It should be noted that the total number of the first bit, the total number of the second bit, the first numerical distribution state and the second numerical distribution state can all be adjusted according to practical needs, and the present invention is not limited thereto.

[0050] In one embodiment, after obtaining the plurality of first mapping information (e.g., the aforementioned first bit mapping information and the second bit mapping information), the memory control circuit 23 may perform an integrated comparison on the plurality of first mapping information to obtain an integrated comparison result. Based on this integrated comparison result, the memory control circuit 23 may determine at least one mapping information (also referred to as the second mapping information) from the plurality of second-category candidate mapping information. In particular, the second mapping information may reflect the distribution of valid data (also referred to as the first valid data) in the plurality of first-category source units. For example, the second mapping information may reflect which physical programming units in each first-category source unit store valid data. In addition, the plurality of second-category candidate mapping information may be stored in the system area 33 of the memory module 122.

[0051] In one embodiment, assuming that the value distribution state of the first bit (i.e., the first value distribution state) reflects that the first source unit is related to the first part of the plurality of second-type candidate mapping information, and the value distribution state of the second bit (i.e., the second value distribution state) reflects that the second source unit is related to the second part of the plurality of second-type candidate mapping information, then both the first part of the information and the second part of the information will be included in the determined second mapping information. Thereafter, the second mapping information read from the memory module 122 will include the first part of the information and the second part of the information.

[0052] In one embodiment, after determining the second mapping information, the memory control circuit 23 may read the second mapping information from the memory module 122. For example, the memory control circuit 23 may read the second mapping information from the system area 33 of the memory module 122. However, the remaining mapping information of the plurality of second-category candidate mapping information that does not belong to the second mapping information will not be read from the system area 33.

[0053] In one embodiment, after reading the second mapping information from the memory module 122, the memory control circuit 23 may copy the valid data (i.e., the first valid data) stored in the plurality of first-type source units to the determined target unit according to the second mapping information. For example, according to the aforementioned first portion of information in the second mapping information, the memory control circuit 23 may determine which physical programming units (also referred to as first physical programming units) in the first source unit have stored valid data. According to the aforementioned second portion of information in the second mapping information, the memory control circuit 23 may determine which physical programming units (also referred to as second physical programming units) in the second source unit have stored valid data. Then, the memory control circuit 23 may read the valid data (i.e., the first valid data) from the first physical programming unit in the first source unit and the second physical programming unit in the second source unit and store the first valid data in the determined target unit.

[0054] In one embodiment, the aforementioned integrated comparison result may include mapping information (also referred to as third mapping information). The memory control circuit 23 may generate the third mapping information according to the numerical distribution states of the aforementioned plurality of first bits (i.e., the first numerical distribution states) and the numerical distribution states of the aforementioned plurality of second bits (i.e., the second numerical distribution states). In particular, the third mapping information may include a plurality of bits (also referred to as third bits). The numerical distribution states of the plurality of third bits (also referred to as third numerical distribution states) may reflect the distribution of the aforementioned second mapping information in the plurality of second-category candidate mapping information.

[0055] In one embodiment, assuming that the first numerical distribution state is "0101" and the second numerical distribution state is "0110", the third numerical distribution state may be "0111". In this example, the third numerical distribution state (i.e., the first, second, third and fourth bits in the third bit are "0", "1", "1" and "1" respectively) reflects that, on the whole, the multiple first-class source units are related to the second, third and fourth mapping information in the multiple second-class candidate mapping information, but are not related to the first mapping information in the multiple second-class candidate mapping information. Based on the integrated comparison result (i.e., the third numerical distribution state), the memory control circuit 23 may determine the second, third and fourth mapping information in the multiple second-class candidate mapping information as the second mapping information. Then, the memory control circuit 23 may read this second mapping information from the memory module 122.

[0056] In one embodiment, after the data consolidation operation is initiated, before starting to read valid data (i.e., first valid data) from any one of the plurality of first-type source units, the memory control circuit 23 first completely reads all second mapping information (e.g., the second, third, and fourth mapping information in the aforementioned second-type candidate mapping information) from the memory module 122. After completely reading all the second mapping information, the memory control circuit 23 will start to read valid data (i.e., first valid data) from any one of the plurality of first-type source units. Thus, the execution efficiency of the data consolidation operation can be improved.

[0057] In one embodiment, the first type of candidate mapping information is used to record and query the second type of candidate mapping information corresponding to each source unit. For example, in the aforementioned embodiment, based on the first type of candidate mapping information corresponding to the first source unit (i.e., the first bit mapping information), the second type of candidate mapping information related to the first source unit (i.e., the first part of the information in the second type of candidate mapping information) can be determined. Similarly, based on the first type of candidate mapping information corresponding to the second source unit (i.e., the second bit mapping information), the second type of candidate mapping information related to the second source unit (i.e., the second part of the information in the second type of candidate mapping information) can be determined. After the second mapping information (including the first part of the information and the second part of the information in the second type of candidate mapping information) is read from the memory module 122 in batches (e.g., synchronously or continuously), the second mapping information can be used to read, copy or move valid data stored in each source unit (e.g., the first type of source unit) in a data consolidation operation.

[0058] In one embodiment, before starting to execute the data consolidation operation, the memory control circuit 23 may store and maintain (e.g., update) the aforementioned first-category candidate mapping information in advance. In particular, if a certain physical unit (e.g., the aforementioned first source unit) is a closed unit, the memory control circuit 23 may store the first-category candidate mapping information (e.g., the aforementioned first bit mapping information) corresponding to this physical unit (e.g., the aforementioned first source unit) in a specific physical page (e.g., the last physical page) in this physical unit. Alternatively, if a certain physical unit (e.g., the aforementioned first source unit) is an open unit, the memory control circuit 23 may store the first-category candidate mapping information (e.g., the aforementioned first bit mapping information) corresponding to this physical unit (e.g., the aforementioned first source unit) in a specific physical unit (also referred to as a management unit) in the memory module 122. For example, the management unit may refer to at least one physical unit in the system area 33.

[0059] In one embodiment, the closed cell may include at least one physical cell that has been fully written in the data area 31. In addition, the open cell may include at least one physical cell that has been written with data but has not been fully written in the data area 31.

[0060] In one embodiment, if a certain physical unit (e.g., the aforementioned first source unit) is switched from an open unit to a closed unit, the memory control circuit 23 may move the first type of candidate mapping information (e.g., the aforementioned first bit mapping information) corresponding to the physical unit (e.g., the aforementioned first source unit) from the management unit to a specific physical page (e.g., the last physical page) in the physical unit for storage. Thus, the subsequent query efficiency of the first type of candidate mapping information may be improved.

[0061] In one embodiment, after starting the data consolidation operation, the memory control circuit 23 may allow more physical units to be pre-selected as the multiple first-category source units by increasing the decision value. For example, pre-selecting more physical units as the multiple first-category source units may achieve advantages such as improving the execution efficiency of the subsequent data consolidation operation. However, if more physical units are pre-selected as the multiple first-category source units, the total amount of valid data (i.e., the aforementioned first valid data) stored in the determined first-category source units may be greater than the available capacity of the currently determined target units. In this case, during the execution of the data consolidation operation, even if the currently determined target units have been filled with the first valid data, the release rate of the idle physical units may be lower than expected.

[0062] In one embodiment, if the total amount of valid data (i.e., the aforementioned first valid data) stored in the determined first-category source unit is greater than the available capacity of the currently determined target unit, the memory control circuit 23 may additionally determine at least one of the determined first-category source units as another type of source unit (also referred to as a second-category source unit). Thus, the total number of first-category source units can be reduced, thereby reducing the total amount of valid data (i.e., the aforementioned first valid data) stored in the first-category source unit to no more than the available capacity of the currently determined target unit. Then, the memory control circuit 23 may exclude the mapping information corresponding to the second-category source unit in the aforementioned multiple first-category candidate mapping information from the performed integration comparison (i.e., not including the mapping information corresponding to the second-category source unit in the aforementioned multiple first-category candidate mapping information in the performed integration comparison). Thus, it can be ensured that the release rate of idle physical units in the performed data consolidation operation meets expectations.

[0063] In one embodiment, after the valid data (i.e., the first valid data) stored in the plurality of first-type source units are copied to the target unit according to the second mapping information, if there is still available capacity in the target unit currently storing the first valid data (i.e., the target unit is not fully written by the first valid data), the memory control circuit 23 may obtain the second-type source unit according to the sorting result of the aforementioned non-idle physical units. For example, the memory control circuit 23 may select at least one of the remaining non-idle physical units as the second-type source unit according to the sorting result of the aforementioned non-idle physical units. For example, the second-type source unit may include at least one physical unit storing relatively less valid data among the remaining physical units of the non-idle physical units that do not include the first-type source units. After determining the second-type source unit, according to the available capacity still existing in the target unit, the memory control circuit 23 may perform a data consolidation operation on the second-type source unit to copy the valid data (also referred to as the second valid data) stored in the second-type source unit to the target unit to fully write the target unit. Thus, it can be further ensured that the utilization rate of the target unit by the executed data consolidation operation meets expectations.

[0064] Figure 4 is a schematic diagram of a data consolidation operation according to an embodiment of the present invention. Figure 4In one embodiment, after the data consolidation operation is initiated, the memory control circuit 23 pre-selects the physical units 401(1)-401(3) and 402 as the first type of source units. However, based on the valid count information corresponding to the physical units 401(1)-401(3) and 402 and the determined available capacity of the target unit, the memory control circuit 23 may determine that the total amount of valid data stored in the physical units 401(1)-401(3) and 402 is greater than the determined available capacity of the target unit. In this case, the memory control circuit 23 may exclude the physical unit 402 from the first type of source unit and determine the physical unit 402 as the second type of source unit.

[0065] Alternatively, in one embodiment, after the data merge operation is initiated, the memory control circuit 23 may directly select the physical units 401 ( 1 ) to 401 ( 3 ) as the first type of source units. Later, the memory control circuit 23 may select the physical unit 402 as the second type of source unit.

[0066] In one embodiment, after determining that the physical units 401(1)-401(3) are the first type of source units, the memory control circuit 23 can determine the mapping information 411(1)-411(3) (i.e., the first mapping information) corresponding to the physical units 401(1)-401(3) from the aforementioned plurality of first type candidate mapping information. Then, the memory control circuit 23 can perform an integrated comparison 41 on the mapping information 411(1)-411(3) to obtain an integrated comparison result 42. According to the integrated comparison result 42, the memory control circuit 23 can batch read the mapping information 412 (i.e., the second mapping information) from the system area 33 in the memory module 122. The mapping information 412 can reflect the distribution of valid data in the physical units 401(1)-401(3). Then, the memory control circuit 23 can determine the valid data (ie, first valid data) in the physical units 401 ( 1 ) to 401 ( 3 ) according to the mapping information 412 , and copy (or move) the valid data in the physical units 401 ( 1 ) to 401 ( 3 ) to the target unit.

[0067] In one embodiment, after completing the data consolidation operation for the physical units 401(1)-401(3) (i.e., the first type of source units), for the physical unit 402 determined as the second type of source unit, the memory control circuit 23 may determine the mapping information 413 corresponding to the physical unit 402 from the aforementioned plurality of first type candidate mapping information. It should be noted that the mapping information 413 will not be included in the consolidation comparison 41 for the mapping information 411(1)-411(3). Based on the mapping information 413, the memory control circuit 23 may read the mapping information 414 separately from the system area 33 in the memory module 122. The mapping information 414 may reflect the distribution of valid data in the physical unit 402. Then, the memory control circuit 23 may determine the valid data (i.e., the second valid data) in the physical unit 402 based on the mapping information 414, and copy (or move) the valid data in the physical unit 402 to the target unit.

[0068] Figure 5 is a flow chart of a memory management method according to an embodiment of the present invention. Figure 5 In step S501, in response to a trigger condition, multiple first-class source units and at least one target unit are determined from a memory module. In step S502, multiple first mapping information are determined from multiple first-class candidate mapping information based on the multiple first-class source units, wherein the first mapping information respectively reflects the association between the multiple first-class source units and multiple second-class candidate mapping information. In step S503, an integrated comparison is performed on the multiple first mapping information to obtain an integrated comparison result. In step S504, at least one second mapping information is determined from the multiple second-class candidate mapping information based on the integrated comparison result. The second mapping information reflects the distribution of the first valid data in the multiple first-class source units.

[0069] After determining the second mapping information, in step S505, the second mapping information is read from the memory module. In step S506, valid data stored in the plurality of first-type source units are copied to the target unit according to the second mapping information.

[0070] Figure 6 is a flow chart of a memory management method according to an embodiment of the present invention. Figure 6In step S601, it is determined whether the total amount of valid data (i.e., the first valid data) stored in multiple first-category source units is greater than the available capacity of the target unit. If the total amount of valid data (i.e., the first valid data) in the first-category source units is greater than the available capacity of the target unit, in step S602, at least one of the multiple first-category source units is determined as a second-category source unit. Thus, the total amount of valid data (i.e., the first valid data) stored in the first-category source units can be reduced to less than or equal to the available capacity of the target unit, thereby ensuring that the release rate of idle physical units by the executed data consolidation operation meets expectations. However, if the total amount of valid data (i.e., the first valid data) in the first-category source units is not greater than the available capacity of the target unit, then in step S603, the first-category source units are not changed (i.e., the currently determined first-category source units are maintained).

[0071] On the other hand, since the second mapping information needs to be read into the cache for processing, if the cache capacity is small, the second mapping information can be read one by one. Since the second mapping information corresponding to each first-type source unit has been predetermined, even if the cache capacity can only accommodate one second mapping information, after reading a second mapping information, the valid data in multiple second-type source units corresponding to the second mapping information can be transferred, and after the transfer, the next second mapping information can be loaded, thereby avoiding repeated loading of the same second mapping information and improving efficiency.

[0072] However, Figure 5 and Figure 6 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 5 and Figure 6 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 5 and Figure 6 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0073] In summary, the memory management method and storage device proposed in the embodiment of the present invention can integrate and compare multiple first mapping information and read the second mapping information from the memory module in batches (for example, synchronously) based on the integrated comparison results. As a result, the efficiency of the data consolidation operation performed in the storage device can be effectively improved, thereby improving the overall working efficiency of the storage device. In addition, when the total amount of valid data in the first type of source units is greater than the available capacity of the target unit, some of the source units can be switched to the second type of source units to ensure that the release rate of the idle physical units in the executed data consolidation operation meets expectations. As a result, the efficiency of the data consolidation operation performed in the storage device can also be effectively improved, thereby improving the overall working efficiency of the storage device.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: In response to a trigger condition, determining a plurality of first-type source units and at least one target unit from the plurality of physical units; Determine, according to the plurality of first-category source units, a plurality of first mapping information from a plurality of first-category candidate mapping information, wherein the plurality of first mapping information respectively reflects the association between the plurality of first-category source units and a plurality of second-category candidate mapping information; Performing integrated comparison on the plurality of first mapping information to obtain an integrated comparison result; Determining at least one second mapping information from the plurality of second-category candidate mapping information according to the integrated comparison result, wherein the at least one second mapping information reflects the distribution of the first valid data in the plurality of first-category source units; and The first valid data stored in the plurality of first-type source units are copied to the at least one target unit according to the at least one second mapping information.

2. The memory management method according to claim 1, wherein the plurality of physical units include a plurality of non-idle physical units, and the step of determining the plurality of first-type source units from the plurality of physical units comprises: Obtaining valid counting information corresponding to the plurality of non-idle physical units; Sorting the plurality of non-idle physical units according to the valid counting information to obtain a sorting result; Determining a decision value according to the sorting result, the valid count information, and the available capacity of the at least one target unit, wherein the decision value is used to define the total number of the plurality of first-type source units; as well as According to the decision value, the plurality of first-category source units are determined from the sorted plurality of non-idle physical units.

3. The memory management method according to claim 1, wherein the multiple first-category source units include a first source unit and a second source unit, the multiple first mapping information include first bit mapping information and second bit mapping information, the first bit mapping information reflects a first association between the first source unit and the multiple second-category candidate mapping information, and the second bit mapping information reflects a second association between the second source unit and the multiple second-category candidate mapping information.

4. The memory management method according to claim 3, wherein the first bit mapping information includes a plurality of first bits, the second bit mapping information includes a plurality of second bits, a first value distribution state of the plurality of first bits reflects that the first source unit is related to a first portion of information in the plurality of second-category candidate mapping information, a second value distribution state of the plurality of second bits reflects that the second source unit is related to a second portion of information in the plurality of second-category candidate mapping information, and The first portion of information and the second portion of information are both included in the at least one second mapping information.

5. The memory management method according to claim 3, wherein the first bit mapping information includes a plurality of first bits, the second bit mapping information includes a plurality of second bits, the integrated comparison result includes third mapping information, the third mapping information includes a plurality of third bits, and the step of performing the integrated comparison on the plurality of first mapping information to obtain the integrated comparison result comprises: generating the third mapping information according to the first numerical distribution state of the plurality of first bits and the second numerical distribution state of the plurality of second bits, and The third value distribution state of the plurality of third bits reflects the distribution of the at least one second mapping information in the plurality of second-category candidate mapping information.

6. The memory management method according to claim 1, wherein the integrated comparison result comprises third mapping information, the third mapping information comprises a plurality of third bits, and the step of determining the at least one second mapping information from the plurality of second-category candidate mapping information according to the integrated comparison result comprises: According to the third numerical value distribution state of the plurality of third bits, the at least one second mapping information is determined from the plurality of second-category candidate mapping information.

7. The memory management method according to claim 1, wherein before determining the plurality of first-type source units and the at least one target unit from the plurality of physical units in response to the trigger condition, the memory management method further comprises: detecting a total number of idle entity units among the plurality of entity units; The trigger condition is that the total number is less than a critical value.

8. The memory management method according to claim 1, further comprising: If a first source unit among the plurality of first-type source units is a closed unit, storing first bit mapping information corresponding to the first source unit among the plurality of first mapping information in a specific physical page of the first source unit; as well as If the first source unit is an enabled unit, the first bit mapping information is stored in a management unit among the plurality of physical units.

9. The memory management method according to claim 2, after copying the first valid data stored in the plurality of first-type source units to the at least one target unit according to the at least one second mapping information, the memory management method further comprises: If the at least one target unit still has available capacity, obtaining a second type of source unit according to the sorting result of the plurality of non-idle physical units, where the second type of source unit is a non-idle physical unit that has not been confirmed as the first type of source unit; as well as According to the available capacity of the at least one target unit, the second valid data stored in the second type source unit is copied to the at least one target unit to fill up the at least one target unit.

10. The memory management method according to claim 1, further comprising: If the total data volume of the first valid data is larger than the available capacity of the at least one target unit, determining at least one of the plurality of first-type source units as at least one second-type source unit so that the total data volume of the first valid data is not larger than the available capacity; as well as The mapping information corresponding to the at least one second-type source unit in the plurality of first-type candidate mapping information is excluded from the integrated comparison.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: In response to a trigger condition, determining a plurality of first-type source units and at least one target unit from the plurality of physical units; Determine, according to the plurality of first-category source units, a plurality of first mapping information from a plurality of first-category candidate mapping information, wherein the plurality of first mapping information respectively reflects the association between the plurality of first-category source units and a plurality of second-category candidate mapping information; Performing integrated comparison on the plurality of first mapping information to obtain an integrated comparison result; Determine at least one second mapping information from the plurality of second-category candidate mapping information according to the integrated comparison result, wherein the at least one second mapping information reflects the distribution of the first valid data in the plurality of first-category source units; as well as The first valid data stored in the plurality of first-type source units are copied to the at least one target unit according to the at least one second mapping information.

12. The storage device according to claim 11, wherein the plurality of physical units include a plurality of non-idle physical units, and the operation of determining the plurality of first-type source units from the plurality of physical units comprises: Obtaining valid counting information corresponding to the plurality of non-idle physical units; Sorting the plurality of non-idle physical units according to the valid counting information to obtain a sorting result; Determining a decision value according to the sorting result, the valid count information, and the available capacity of the at least one target unit, wherein the decision value is used to define the total number of the plurality of first-type source units; as well as According to the decision value, the plurality of first-category source units are determined from the sorted plurality of non-idle physical units.

13. A storage device according to claim 11, wherein the multiple first-category source units include a first source unit and a second source unit, the multiple first mapping information include first bit mapping information and second bit mapping information, the first bit mapping information reflects a first association between the first source unit and the multiple second-category candidate mapping information, and the second bit mapping information reflects a second association between the second source unit and the multiple second-category candidate mapping information.

14. The storage device according to claim 13, wherein the first bit mapping information includes a plurality of first bits, the second bit mapping information includes a plurality of second bits, a first value distribution state of the plurality of first bits reflects that the first source unit is related to a first portion of information in the plurality of second-category candidate mapping information, a second value distribution state of the plurality of second bits reflects that the second source unit is related to a second portion of information in the plurality of second-category candidate mapping information, and The first portion of information and the second portion of information are both included in the at least one second mapping information.

15. The storage device according to claim 13, wherein the first bit mapping information includes a plurality of first bits, the second bit mapping information includes a plurality of second bits, the integrated comparison result includes third mapping information, the third mapping information includes a plurality of third bits, and performing the integrated comparison on the plurality of first mapping information to obtain the integrated comparison result comprises: generating the third mapping information according to the first numerical distribution state of the plurality of first bits and the second numerical distribution state of the plurality of second bits, and The third value distribution state of the plurality of third bits reflects the distribution of the at least one second mapping information in the plurality of second-category candidate mapping information.

16. The storage device according to claim 11, wherein the integrated comparison result comprises third mapping information, the third mapping information comprises a plurality of third bits, and the operation of determining the at least one second mapping information from the plurality of second-category candidate mapping information according to the integrated comparison result comprises: According to the third numerical value distribution state of the plurality of third bits, the at least one second mapping information is determined from the plurality of second-category candidate mapping information.

17. The storage device according to claim 11, wherein in response to the trigger condition, the plurality of first-type source units and the at least one target unit are determined from the plurality of physical units, and the memory controller is further configured to: detecting a total number of idle entity units among the plurality of entity units, The trigger condition is that the total number is less than a critical value.

18. The storage device according to claim 11, wherein the memory controller is further configured to: If a first source unit among the plurality of first-type source units is a closed unit, storing first bit mapping information corresponding to the first source unit among the plurality of first mapping information in a specific physical page of the first source unit; and If the first source unit is an enabled unit, the first bit mapping information is stored in a management unit among the plurality of physical units.

19. The storage device according to claim 12, wherein after copying the first valid data stored in the plurality of first-type source units to the at least one target unit according to the at least one second mapping information, the memory controller is further configured to: If the at least one target unit still has available capacity, obtaining a second type of source unit according to the sorting result of the plurality of non-idle physical units, where the second type of source unit is a non-idle physical unit that has not been confirmed as the first type of source unit; and According to the available capacity of the at least one target unit, the second valid data stored in the second type source unit is copied to the at least one target unit to fill up the at least one target unit.

20. The storage device according to claim 11, wherein the memory controller is further configured to: If the total data volume of the first valid data is larger than the available capacity of the at least one target unit, determining at least one of the plurality of first-type source units as at least one second-type source unit so that the total data volume of the first valid data is not larger than the available capacity; and The mapping information corresponding to the at least one second-type source unit in the plurality of first-type candidate mapping information is excluded from the integrated comparison.

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