DTOF distance measurement histogram construction device and method

Abstract

The invention provides a histogram construction device and method for DTOF ranging, and a data prediction unit can pre-fetch histogram information corresponding to TDC (Time-to-Digital Converter) data, which may be needed, from an SRAM (Static Random Access Memory) to a cache unit in advance. Due to the fact that the access speed of the cache is far higher than that of the SRAM, the design remarkably reduces delay of data access when the histogram is constructed, and therefore the overall data processing speed and efficiency are improved. Due to the use of the cache unit, the frequently accessed data can be kept in the cache, and the number of direct accesses to the SRAM is reduced. Not only is the access pressure of the SRAM reduced, but also the power consumption is reduced by reducing unnecessary memory access.

Description

Technical Field

[0001] The present application relates to the technical field of DTOF ranging, and in particular to a histogram construction device and method for DTOF ranging. Background Art

[0002] The histogram construction process of DTOF (Direct Time-Of-Flight) ranging is an important step in DTOF technology for processing time data and extracting useful information. Histogram construction involves the statistics and analysis of a large number of time measurement results in order to more accurately determine the distance of the target object. In the histogram construction stage, it is usually necessary to read the time difference data from the SRAM, and the read data is then assigned to the time interval of the histogram, and the counter of the corresponding interval is updated. However, the power consumption of each read and write of SRAM is large, and frequent reading and writing of SRAM will cause the entire system to consume too much power during the ranging process. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a DTOF ranging histogram construction device and method, so as to solve the problem that in the existing DTOF ranging histogram construction process, frequent reading and writing of SRAM leads to excessive power consumption of the entire system during the ranging process.

[0004] The embodiment of the present application provides a DTOF ranging histogram construction device, comprising: a data prediction unit and a static random access memory; wherein the data prediction unit comprises a cache unit;

[0005] The data prediction unit is used to pre-fetch the histogram information corresponding to the TDC data from the static random access memory to the cache unit; construct a histogram according to the histogram information in the cache unit; when the histogram construction is completed, write the histogram information in the cache unit back to the static random access memory.

[0006] In the above technical solution, the data prediction unit can pre-fetch the histogram information corresponding to the TDC (Time-to-Digital Converter) data that may be needed from the SRAM to the cache unit in advance. Since the access speed of the cache is much faster than that of the SRAM, this design significantly reduces the delay in data access when building the histogram, thereby improving the overall data processing speed and efficiency. The use of the cache unit allows frequently accessed data to be kept in the cache, reducing the number of direct accesses to the SRAM. This not only reduces the access pressure on the SRAM, but also reduces power consumption by reducing unnecessary memory accesses.

[0007] In DTOF ranging applications with high real-time requirements, fast data processing and response are essential. Through data prediction and high-speed caching mechanisms, the system can respond to external signals faster and complete the construction of histograms in a timely manner, thereby improving the responsiveness and real-time performance of the entire system.

[0008] In addition, as a buffer layer for data access, the cache unit can alleviate the system instability caused by SRAM access conflicts or delays to a certain extent. When external conditions change and the data access pattern changes, the data prediction unit can also adapt to the new access pattern by adjusting the prefetch strategy, thereby maintaining the stable operation of the system.

[0009] In scenarios where multiple ranging requests need to be processed simultaneously, the cache unit can support fast data processing and histogram construction to meet the needs of high concurrent processing. This is of great significance for improving the overall throughput and processing capacity of the system.

[0010] In some optional embodiments, the cache unit includes a cache line, and the cache line includes a tag information and 2N+1 data blocks, where N is a positive integer greater than 0;

[0011] 2N+1 data blocks are BIN X-N ,BIN X-N+1 ,…,BIN X ,…,BIN X+N-1 ,BIN X+N ; Label information is BIN X-N The address of.

[0012] In the above technical solution, the histogram data of DTOF ranging presents continuity and locality characteristics. By organizing the continuous BINs (time intervals) of the histogram in the same cache line, when the system accesses a certain BIN, the adjacent BIN is also likely to be accessed at the same time, which can significantly improve the cache hit rate, because once a certain BIN is loaded into the cache line, its adjacent BIN can also be quickly accessed without having to read it from SRAM again. In addition, when transferring data from SRAM to the cache unit, since the cache line contains multiple BINs, more data blocks can be transferred at one time, thereby improving the utilization of memory bandwidth and reducing the delay and power consumption caused by frequent memory access.

[0013] In some optional implementations, the number of data blocks in the cache unit satisfies the following conditions:

[0014] T LSB ×(2N+1)=T laser

[0015] Among them, T LSBis the temporal resolution of the histogram data block, T laser is the pulse width of the emitted laser.

[0016] In the above technical solution, by associating the number of data blocks in the cache unit with the time resolution of the histogram data block and the laser pulse width, it is possible to ensure that the accuracy of the histogram construction matches the actual needs of laser ranging. This means that each data block can accurately correspond to a time interval within the laser pulse width, thereby improving the accuracy and reliability of the ranging results. By adapting the number of data blocks to the laser pulse width, the hit rate of data in the cache can be maximized while using limited storage resources, thereby making the data processing process more efficient.

[0017] In some optional implementations, the data prediction unit is used to use part of the TDC data for fast integration during the histogram construction process of the current frame to obtain a fast integration histogram; find the target data block with the largest value in the fast integration histogram, and update the target data block and N data blocks before and after the target data block to the cache line; based on the fast integration histogram, continue to perform the integration process using the cache line to obtain the overall histogram of the current frame.

[0018] In the above technical solution, by performing fast integration during the histogram construction process of the current frame, the data prediction unit can quickly generate a fast integration histogram that is approximate but sufficient to reflect the data distribution trend. This enables the system to obtain a preliminary estimate of the target position or distance before the complete histogram is built. Find the target data block with the largest value in the fast integration histogram, and update the data block and the N data blocks before and after it to the cache line. This strategy ensures that the cache line stores the data blocks that are most likely to contain important information. Doing so not only reduces the waste of cache lines, but also improves the hit rate of cache lines.

[0019] In some optional embodiments, the data prediction unit is used to find the target data block with the largest value in the histogram of the current frame when the histogram construction of the current frame is completed, and update the target data block and the N data blocks before and after the target data block to the cache line for use in the histogram construction of the next frame.

[0020] In the above technical solution, since the multi-frame histogram of DTOF ranging is consistent and continuous, the next frame can be predicted by the target data block with the largest value in the histogram of the previous frame. This prediction capability enables the system to prepare cache resources in advance, thereby processing the data of the next frame more efficiently.

[0021] The present application provides a method for constructing a histogram of DTOF ranging, including:

[0022] The histogram information corresponding to the TDC data is pre-fetched from the static random access memory to the cache unit; a histogram is constructed according to the histogram information in the cache unit; when the histogram construction is completed, the histogram information in the cache unit is written back to the static random access memory.

[0023] In some optional embodiments, the cache unit includes a cache line, and the cache line includes a tag information and 2N+1 data blocks, where N is a positive integer greater than 0;

[0024] 2N+1 data blocks are BIN X-N ,BIN X-N+1 ,…,BIN X ,…,BIN X+N-1 ,BIN X+N ; Label information is BIN X-N The address of.

[0025] In some optional implementations, the number of data blocks in the cache unit satisfies the following conditions:

[0026] T LSB ×(2N+1)=T laser

[0027] Among them, T LSB is the temporal resolution of the histogram data block, T laser is the pulse width of the emitted laser.

[0028] In some optional embodiments, the method further comprises:

[0029] In the process of constructing the histogram of the current frame, part of the TDC data is used for fast integration to obtain a fast integration histogram; the target data block with the largest value is found in the fast integration histogram, and the target data block and the N data blocks before and after the target data block are updated to the cache line; based on the fast integration histogram, the cache line is used to continue the integration process to obtain the overall histogram of the current frame.

[0030] In some optional implementations, the method further includes: when the histogram construction of the current frame is completed, finding the target data block with the largest value in the histogram of the current frame, and updating the target data block and the N data blocks before and after the target data block to the cache line for use in the histogram construction of the next frame.

[0031] An electronic device provided in an embodiment of the present application includes: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the machine-readable instructions are executed by the processor, any of the above methods is performed.

[0032] A computer program product provided in an embodiment of the present application includes a computer program / instruction, which implements the steps of any of the above methods when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a histogram construction device for DTOF ranging provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of a cache line provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the laser pulse width provided in the embodiment of the present application;

[0037] Figure 4 A schematic diagram of a histogram provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the frame prediction algorithm steps provided in this embodiment;

[0039] Figure 6 A schematic diagram of a fast integral histogram and an overall histogram provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the steps and nodes of the previous frame prediction algorithm provided in this embodiment;

[0041] Figure 8 A possible structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0043] Please refer to Figure 1 , Figure 1A structural schematic diagram of a histogram construction device for DTOF ranging provided in an embodiment of the present application includes: a data prediction unit DPU and a static random access memory SRAM; wherein the data prediction unit includes a cache unit CACHE. The data prediction unit is used to pre-fetch the histogram information corresponding to the TDC data from the static random access memory to the cache unit; construct a histogram according to the histogram information in the cache unit; when the histogram construction is completed, the histogram information in the cache unit is written back to the static random access memory.

[0044] Among them, SRAM (Static Random-Access Memory) is a type of random access memory. Its "static" means that as long as the power is on, the data stored in it can be kept constant, and does not need to be refreshed periodically like DRAM (Dynamic Random Access Memory). Cache (CACHE) is a small but high-speed memory located between the CPU and the main memory DRAM. It is used to cache data and instructions frequently accessed by the CPU to reduce the number of CPU accesses to the main memory and improve system performance. In the hierarchical structure of computer storage systems, CACHE is a high-speed, small-capacity memory between the central processing unit and the main memory.

[0045] In an embodiment of the present application, the data prediction unit can pre-fetch the histogram information corresponding to the TDC (Time-to-Digital Converter) data that may be needed from the SRAM to the cache unit in advance. Since the access speed of the cache is much faster than that of the SRAM, this design significantly reduces the delay in data access when building the histogram, thereby improving the overall data processing speed and efficiency. The use of the cache unit allows frequently accessed data to be kept in the cache, reducing the number of direct accesses to the SRAM. This not only reduces the access pressure on the SRAM, but also reduces power consumption by reducing unnecessary memory accesses.

[0046] In DTOF ranging applications with high real-time requirements, fast data processing and response are essential. Through data prediction and high-speed caching mechanisms, the system can respond to external signals faster and complete the construction of histograms in a timely manner, thereby improving the responsiveness and real-time performance of the entire system.

[0047] In addition, as a buffer layer for data access, the cache unit can alleviate the system instability caused by SRAM access conflicts or delays to a certain extent. When external conditions change and the data access pattern changes, the data prediction unit can also adapt to the new access pattern by adjusting the prefetch strategy, thereby maintaining the stable operation of the system.

[0048] In scenarios where multiple ranging requests need to be processed simultaneously, the cache unit can support fast data processing and histogram construction to meet the needs of high concurrent processing. This is of great significance for improving the overall throughput and processing capacity of the system.

[0049] Please refer to Figure 2 , Figure 2 A cache line schematic diagram provided in an embodiment of the present application, wherein the cache unit includes a cache line, the cache line includes a tag information and 2N+1 data blocks, wherein N is a positive integer greater than 0; the 2N+1 data blocks are BIN X-N ,BIN X-N+1 ,…,BIN X ,…,BIN X+N-1 ,BIN X+N ; Label information is BIN X-N The address of.

[0050] In the embodiment of the present application, the histogram data of DTOF ranging presents continuity and locality characteristics. By organizing the continuous BINs (time intervals) of the histogram in the same cache line, when the system accesses a certain BIN, the adjacent BIN is also likely to be accessed at the same time, which can significantly improve the cache hit rate, because once a certain BIN is loaded into the cache line, its adjacent BIN can also be quickly accessed without having to read it from SRAM again. In addition, when transferring data from SRAM to the cache unit, since the cache line contains multiple BINs, more data blocks can be transferred at one time, thereby improving the utilization of memory bandwidth and reducing the delay and power consumption caused by frequent memory access.

[0051] Please refer to Figure 3 and Figure 4 , Figure 3 A schematic diagram of the laser pulse width provided in the embodiment of the present application, Figure 4 A histogram diagram provided in an embodiment of the present application. The number of data blocks in the cache unit of this embodiment meets the following conditions:

[0052] T LSB ×(2N+1)=T laser

[0053] Among them, T LSB is the temporal resolution of the histogram data block, T laser is the pulse width of the emitted laser.

[0054] In the embodiment of the present application, by associating the number of data blocks in the cache unit with the time resolution of the histogram data block and the laser pulse width, it is possible to ensure that the accuracy of the histogram construction matches the actual needs of laser ranging. This means that each data block can accurately correspond to a time interval within the laser pulse width, thereby improving the accuracy and reliability of the ranging results. By adapting the number of data blocks to the laser pulse width, the hit rate of data in the cache can be maximized while using limited storage resources, thereby making the data processing process more efficient.

[0055] The following two embodiments provide two replacement strategy algorithms for cache units:

[0056] The first replacement strategy algorithm is the current frame prediction algorithm, such as Figure 5 and Figure 6 As shown, Figure 5 A schematic diagram of the frame prediction algorithm steps provided in this embodiment. Figure 6 The data prediction unit of this embodiment is used to use part of the TDC data to perform fast integration during the histogram construction process of the current frame to obtain a fast integration histogram, such as Figure 6 As shown in the figure on the left; find the target data block with the largest value in the fast integral histogram, and update the target data block and the N data blocks before and after the target data block to the cache line; based on the fast integral histogram, continue to perform the integration process using the cache line to obtain the overall histogram of the current frame, as shown in Figure 6 As shown in the figure on the right.

[0057] In an embodiment of the present application, by performing fast integration during the histogram construction process of the current frame, the data prediction unit can quickly generate a fast integration histogram that is approximate but sufficient to reflect the data distribution trend. This enables the system to obtain a preliminary estimate of the target position or distance before the complete histogram is constructed. Find the target data block with the largest value in the fast integration histogram, and update the data block and the N data blocks before and after it to the cache line. This strategy ensures that the data blocks stored in the cache line are the most likely to contain important information. Doing so not only reduces the waste of cache lines, but also improves the hit rate of cache lines.

[0058] The second replacement strategy algorithm is the previous frame prediction algorithm, such as Figure 7 As shown, Figure 7 A schematic diagram of the previous frame prediction algorithm step nodes provided for this embodiment. The data prediction unit of this embodiment is used to find the target data block with the largest value in the histogram of the current frame when the histogram construction of the current frame is completed, and update the target data block and the N data blocks before and after the target data block to the cache line for use in the histogram construction of the next frame.

[0059] In an embodiment of the present application, since the multi-frame histogram of DTOF ranging is consistent and continuous, the next frame can be predicted by the target data block with the largest value in the histogram of the previous frame. This prediction capability enables the system to prepare cache resources in advance, thereby processing the data of the next frame more efficiently.

[0060] A histogram construction method for DTOF ranging provided in an embodiment of the present application includes: pre-fetching histogram information corresponding to TDC data from a static random access memory to a cache unit; constructing a histogram according to the histogram information in the cache unit; and when the histogram construction is completed, writing the histogram information in the cache unit back to the static random access memory.

[0061] In some optional embodiments, the cache unit includes a cache line, the cache line includes a tag information and 2N+1 data blocks, where N is a positive integer greater than 0; the 2N+1 data blocks are BIN X-N ,BIN X-N+1 ,…,BIN X ,…,BIN X+N-1 ,BIN X+N ; Label information is BIN X-N The address of.

[0062] In some optional implementations, the number of data blocks in the cache unit satisfies the following conditions:

[0063] T LSB ×(2N+1)=T laser

[0064] Among them, T LSB is the temporal resolution of the histogram data block, T laser is the pulse width of the emitted laser.

[0065] In some optional implementations, the method further includes: in the process of constructing the histogram of the current frame, using part of the TDC data for fast integration to obtain a fast integration histogram; finding the target data block with the largest value in the fast integration histogram, and updating the target data block and N data blocks before and after the target data block to the cache line; based on the fast integration histogram, continuing the integration process using the cache line to obtain the overall histogram of the current frame.

[0066] In some optional implementations, the method further includes: when the histogram construction of the current frame is completed, finding the target data block with the largest value in the histogram of the current frame, and updating the target data block and the N data blocks before and after the target data block to the cache line for use in the histogram construction of the next frame.

[0067] Figure 8A possible structure of an electronic device provided in an embodiment of the present application is shown. Figure 8 The electronic device includes: a processor, a memory and a communication interface. These components are interconnected and communicate with each other through a communication bus and / or other forms of connection mechanisms (not shown).

[0068] The memory includes one or more (only one is shown in the figure), which may be, but not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The processor and other possible components can access the memory and read and / or write data therein.

[0069] The processor includes one or more (only one is shown in the figure), which can be an integrated circuit chip with signal processing capabilities. The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a microcontroller unit (MCU), a network processor (NP) or other conventional processors; it can also be a special-purpose processor, including a neural network processor (NPU), a graphics processor (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. In addition, when there are multiple processors, some of them can be general-purpose processors and the other part can be special-purpose processors.

[0070] The communication interface includes one or more (only one is shown in the figure), which can be used to communicate directly or indirectly with other devices to exchange data. The communication interface can include an interface for wired and / or wireless communication.

[0071] One or more computer program instructions may be stored in the memory, and the processor may read and execute these computer program instructions to implement the method provided in the embodiment of the present application.

[0072] Understandably, Figure 8 The structure shown is for illustration only. The electronic device may also include Figure 8 More or fewer components as shown, or with Figure 8 Different structures are shown. Figure 8 The components shown in the figure can be implemented by hardware, software or a combination thereof. The electronic device may be a physical device, such as a PC, a laptop, a tablet computer, a mobile phone, a server, an embedded device, etc., or a virtual device, such as a virtual machine, a virtualized container, etc. Moreover, the electronic device is not limited to a single device, but may also be a combination of multiple devices or a cluster consisting of a large number of devices.

[0073] A computer program product provided in an embodiment of the present application includes a computer program / instruction, which implements the steps of any of the above methods when executed by a processor.

[0074] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0075] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0076] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0077] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0078] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A histogram construction device for DTOF ranging, characterized in that: include: A data prediction unit and a static random access memory; wherein the data prediction unit includes a cache unit; The data prediction unit is used to pre-fetch the histogram information corresponding to the TDC data from the static random access memory to the cache unit; construct a histogram according to the histogram information in the cache unit; when the histogram construction is completed, write the histogram information in the cache unit back to the static random access memory.

2. The device according to claim 1, characterized in that The cache unit includes a cache line, and the cache line includes a tag information and 2N+1 data blocks, wherein N is a positive integer greater than 0; The 2N+1 data blocks are BIN X-N ,BIN X-N+1 ,…,BIN X ,…,BIN X+N-1 ,BIN X+N ; The label information is BIN X-N The address of.

3. The device according to claim 2, characterized in that The number of data blocks in the cache unit meets the following conditions: T LSB ×(2N+1)=T laser Among them, T LSB is the temporal resolution of the histogram data block, T laser is the pulse width of the emitted laser.

4. The device according to claim 2, characterized in that The data prediction unit is used to use part of the TDC data for fast integration during the histogram construction process of the current frame to obtain a fast integration histogram; find the target data block with the largest value in the fast integration histogram, and update the target data block and N data blocks before and after the target data block to the cache line; based on the fast integration histogram, continue to perform the integration process using the cache line to obtain the overall histogram of the current frame.

5. The device according to claim 2, characterized in that The data prediction unit is used to find the target data block with the largest value in the histogram of the current frame when the histogram construction of the current frame is completed, and update the target data block and the N data blocks before and after the target data block to the cache line for use in the histogram construction of the next frame.

6. A method for constructing a histogram of DTOF ranging, characterized in that: include: pre-fetching histogram information corresponding to the TDC data from the static random access memory to a cache unit; constructing a histogram according to the histogram information in the cache unit; When the histogram construction is finished, the histogram information in the cache unit is written back to the static random access memory.

7. The method according to claim 6, characterized in that The cache unit includes a cache line, and the cache line includes a tag information and 2N+1 data blocks, wherein N is a positive integer greater than 0; The 2N+1 data blocks are BIN X-N ,BIN X-N+1 ,…,BIN X ,…,BIN X+N-1 ,BIN X+N ; The label information is BIN X-N The address of.

8. The method according to claim 7, characterized in that The number of data blocks in the cache unit meets the following conditions: T LSB ×(2N+1)=T laser Among them, T LSB is the temporal resolution of the histogram data block, T laser is the pulse width of the emitted laser.

9. The method according to claim 7, characterized in that Also includes: In the process of constructing the histogram of the current frame, a part of the TDC data is used for fast integration to obtain a fast integration histogram; Find the target data block with the largest value in the fast integration histogram, and update the target data block and the N data blocks before and after the target data block to the cache line; based on the fast integration histogram, continue to perform the integration process using the cache line to obtain the overall histogram of the current frame.

10. The method according to claim 7, characterized in that Also includes: When the histogram construction of the current frame is finished, the target data block with the largest value in the histogram of the current frame is found, and the target data block and the N data blocks before and after the target data block are updated to the cache line for use in the histogram construction of the next frame.

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