Abnormality analysis method for logic-to-physical mapping table, terminal equipment and storage medium

Abstract

The invention is suitable for the field of data processing, and discloses a logic-to-physical mapping table anomaly analysis method, terminal equipment and a storage medium. The logic-to-physical mapping table anomaly analysis method comprises the steps that when a target logic-to-physical mapping table set is detected, physical block addresses in the target logic-to-physical mapping table set are extracted, and a physical block address set is obtained; obtaining a binary bit set corresponding to the physical block address set, and obtaining a physical cluster state table; and in the physical cluster state table, if each first state bit in a first state bit set corresponding to the binary bit set has a target state bit which is not 1, judging that an abnormal table exists in the target logic-to-physical mapping table set. According to the method, the abnormal physical block addresses can be quickly identified without checking one by one, so that the abnormality positioning time is remarkably shortened.

Description

Technical Field

[0001] The present invention belongs to the field of data processing, and in particular relates to an abnormality analysis method of a logic-to-physical mapping table, a terminal device and a storage medium. Background Art

[0002] The Logical to Physical Table (L2P) is a data structure used in the storage system to map the logical address (Logical Block Address, LBA) to the physical address (Physical Block Address, physical block address). The Embedded MultiMedia Card (eMMC) sample refers to a preliminary sample or prototype chip used to evaluate, test or verify the eMMC storage chip. For the embedded multimedia card sample test, after the test is abnormal, the logical to physical mapping table abnormality analysis will be performed first.

[0003] Traditional logic-to-physical mapping table analysis methods rely on manual verification, but the number of logic-to-physical mapping tables is often tens of thousands. It can be seen that manual verification will reduce the efficiency of abnormal analysis of logic-to-physical mapping tables. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a method for analyzing anomalies of a logical-to-physical mapping table, a terminal device, and a storage medium, which can solve the problem of low efficiency of analyzing anomalies of a logical-to-physical mapping table in the related art.

[0005] A first aspect of the present invention provides a method for analyzing anomalies of a logical-to-physical mapping table, comprising:

[0006] When a target logical-to-physical mapping table set is detected, a physical block address in the target logical-to-physical mapping table set is extracted to obtain a physical block address set;

[0007] Obtain the binary bit set corresponding to the physical block address set, and obtain the physical cluster status table;

[0008] In the physical cluster status table, if there is a target status bit that is not 1 in each first status bit set in the first status bit set corresponding to the binary bit set, it is determined that there is an exception table in the target logical-to-physical mapping table set.

[0009] Optionally, in a first implementation of the first aspect of the present invention, after the steps of obtaining a binary bit set corresponding to a physical block address set and obtaining a physical cluster status table, the method further includes:

[0010] In the physical cluster status table, if each first state bit in the first state bit set corresponding to the binary bit set is 1, then in the physical cluster status table, it is determined whether each second state bit in the remaining second state bit set is 0, and the state bit in the physical cluster status table consists of the first state bit set and the second state bit set;

[0011] If all second state bits in the second state bit set are not 0, it is determined that there is an exception table in the target logical-to-physical mapping table set;

[0012] If all second state bits in the second state bit set are 0, it is determined that there is no exception table in the target logical-to-physical mapping table set.

[0013] Optionally, in a second implementation of the first aspect of the present invention, when a target logical-to-physical mapping table set is detected, before the step of extracting a physical block address in the target logical-to-physical mapping table set to obtain a physical block address set, the method further includes:

[0014] When a mapping table to be analyzed is detected, if the total physical block data volume corresponding to the mapping table to be analyzed is greater than or equal to the preset physical block data volume, the mapping table to be analyzed is split into a plurality of sets of logical to physical mapping tables to be analyzed;

[0015] Select target sets from the set of logic-to-physical mapping tables to be analyzed in turn as the target logic-to-physical mapping table set.

[0016] Optionally, in a third implementation of the first aspect of the present invention, when a target logical-to-physical mapping table set is detected, before the step of extracting a physical block address in the target logical-to-physical mapping table set to obtain a physical block address set, the method further includes:

[0017] When a mapping table to be analyzed is detected, if the total physical block data volume corresponding to the mapping table to be analyzed is less than the preset physical block data volume, the mapping table to be analyzed is taken as a target logical-to-physical mapping table set.

[0018] Optionally, in a fourth implementation of the first aspect of the present invention, after the step of determining whether an abnormal table exists in the target logical-to-physical mapping table set, the step further includes:

[0019] Get log records;

[0020] Output log records.

[0021] Optionally, in a fifth implementation of the first aspect of the present invention, the step of obtaining the log record includes:

[0022] The step of sequentially selecting a target set from the set of logical-to-physical mapping tables to be analyzed as a target logical-to-physical mapping table set is terminated, and log records are obtained.

[0023] Optionally, in a sixth implementation of the first aspect of the present invention, the step of obtaining a binary bit set corresponding to a physical block address set and obtaining a physical cluster status table includes:

[0024] If there is a target physical block address in the physical block address set that exceeds the preset maximum physical block address value, it is determined that there is an abnormality in the target logical to physical mapping table corresponding to the target physical block address, otherwise the binary bit set corresponding to the physical block address set is obtained, and the physical cluster status table is obtained.

[0025] Optionally, in a seventh implementation manner of the first aspect of the present invention, after the step of determining whether there is an abnormality in the target logical-to-physical mapping table corresponding to the target physical block address, the method further includes:

[0026] Record the target logical-to-physical mapping table exceptions in the log record.

[0027] In a second aspect, an embodiment of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned logic-to-physical mapping table exception analysis method when executing the computer program.

[0028] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned logic-to-physical mapping table exception analysis method are implemented.

[0029] In a fourth aspect, an embodiment of the present invention provides a computer program product. When the computer program product is run on a terminal device, the terminal device executes the above-mentioned logic-to-physical mapping table exception analysis method.

[0030] When the target logic-to-physical mapping table set is detected, the physical block address in the target logic-to-physical mapping table set is extracted to obtain the physical block address set; the binary bit set corresponding to the physical block address set is obtained, and the physical cluster status table is obtained; in the physical cluster status table, if each first state bit in the first state bit set corresponding to the binary bit set has a target state bit that is not 1, it is determined that there is an abnormal table in the target logic-to-physical mapping table set. By extracting the physical block address in the mapping table, a physical block address set is formed, which avoids the tedious process of checking one by one in the traditional method. After obtaining the binary bit set and the physical cluster status table, the abnormality can be quickly located by batch comparing the state bits in the two sets. Since the state bits are compared in the form of a set, the physical block address with abnormalities can be quickly identified without checking them one by one, which significantly shortens the time for locating the abnormality. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0032] Figure 1 A schematic diagram of an embodiment of a method for analyzing anomalies of a logical-to-physical mapping table in an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of a specific embodiment of step 103 of the method for analyzing anomalies of a logical-to-physical mapping table in an embodiment of the present invention;

[0034] Figure 3 It is a schematic diagram of a specific embodiment before step 101 of the method for analyzing anomalies of a logical to physical mapping table in an embodiment of the present invention;

[0035] Figure 4 It is a schematic diagram of a specific embodiment after step 202 of the method for analyzing anomalies of a logical-to-physical mapping table in an embodiment of the present invention;

[0036] Figure 5 The figure is a schematic diagram of an embodiment of a terminal device in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are protected by the present invention.

[0038] It should be noted that the terms "include", "comprises" and "have" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, terminal, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In the claims, specifications and drawings of the present invention, relational terms such as "first" and "second" are merely used to distinguish one entity / operation / object from another entity / operation / object, and do not necessarily require or imply any such real-time relationship or order between these entities / operations / objects.

[0039] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0040] The Logical to Physical Table is a data structure used in the storage system to map the logical address (LBA, Logical Block Address) to the physical address (Physical Block Address). eMMC (Embedded MultiMedia Card) samples refer to preliminary samples or prototype chips used to evaluate, test or verify eMMC storage chips. For eMMC sample testing, after the test is abnormal, the Logical to Physical Table analysis will be performed first.

[0041] Traditional logic-to-physical mapping table analysis methods rely on manual verification, but the number of logic-to-physical mapping tables is often tens of thousands. It can be seen that manual verification will reduce the efficiency of abnormal analysis of logic-to-physical mapping tables.

[0042] In view of this, an embodiment of the present invention provides a method for analyzing anomalies of a logical to physical mapping table, a terminal device, and a storage medium. By extracting the physical block addresses in the mapping table, a physical block address set is formed, thereby avoiding the tedious process of checking one by one in the traditional method. After obtaining the binary bit set and the physical cluster status table, the anomaly can be quickly located by batch comparing the status bits in the two sets. Since the status bits are compared in the form of a set, the physical block addresses with anomalies can be quickly identified without checking them one by one, which significantly shortens the time for locating the anomaly.

[0043] In order to illustrate the technical solution of the present invention, specific embodiments are provided below for illustration.

[0044] The professional terms involved in the embodiments of the present invention include but are not limited to:

[0045] Logical to Physical Table: Logical to physical address mapping table, used to map logical address (LBA, Logical Block Address) to physical address (Physical Block Address).

[0046] Physical Block Address (PBA): an address used to uniquely identify a physical storage block (such as a flash memory block).

[0047] Logical Block Address (LBA): An address used to uniquely identify a data block. LBA and physical block address are mapped via a logical-to-physical mapping table.

[0048] Binary bit set: A set of multiple binary bits used to represent a state or data.

[0049] Physical cluster status table: a table that records the status of a physical storage cluster (such as a flash memory cluster). A physical cluster is a group of physical blocks on a storage medium that have common management attributes.

[0050] Exception analysis operation: An analysis operation performed on the logical-to-physical mapping table to detect and identify anomalies or errors in the logical-to-physical mapping table.

[0051] Status bit: In the physical cluster status table, a bit used to indicate the physical cluster status. The status bit can be a binary bit (0 or 1) to indicate different states.

[0052] Preset physical block data volume: A threshold value of the physical block data volume set before performing logical-to-physical mapping table analysis. It is used to determine whether the mapping table to be analyzed needs to be processed in segments.

[0053] Segmentation: An operation that divides the mapping table to be analyzed into multiple smaller sets of logical-to-physical mapping tables to be analyzed. It is used to process sets of logical-to-physical mapping tables with large amounts of data.

[0054] Logging: Log information during abnormal analysis operations. Used for debugging, monitoring, and troubleshooting.

[0055] Figure 1 The present invention provides a flowchart of a method for analyzing anomalies of a logical-to-physical mapping table, which can be applied to a terminal device, such as a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, etc.

[0056] Specifically, the above-mentioned method for analyzing anomalies of a logic-to-physical mapping table may include the following steps S101 to S103.

[0057] Step S101 : when a target logical-to-physical mapping table set is detected, a physical block address in the target logical-to-physical mapping table set is extracted to obtain a physical block address set.

[0058] In an embodiment of the present invention, the logic-to-physical mapping table data corresponding to the test target is directly read, for example, by connecting to a storage device to be tested (such as an SSD, HDD, etc.) or accessing a test environment (such as an emulator, a test bench, etc.).

[0059] Optionally, the logical-to-physical mapping table data sent by the remote server is received through a network interface. For example, a network interface (such as Ethernet, Wi-Fi, etc.) is configured, a network protocol (such as TCP / IP, HTTP, etc.) is used to establish a connection with the remote server, and the logical-to-physical mapping table data sent by the remote server is received.

[0060] Step S102, obtaining a binary bit set corresponding to a physical block address set, and obtaining a physical cluster status table.

[0061] In an embodiment of the present invention, each logical-to-physical mapping table in the target logical-to-physical mapping table set is traversed, and a loop structure can be used to traverse each logical-to-physical mapping table in the target logical-to-physical mapping table set to extract physical block address information.

[0062] According to the physical block address set, the corresponding binary bit mapping table is queried to obtain the binary bit set. At the same time, the physical cluster status table is read from the storage device.

[0063] Optionally, multi-threading technology is used to process multiple logical-to-physical mapping tables simultaneously to increase the speed of extracting physical block addresses.

[0064] Step S103, in the physical cluster status table, if there is a target status bit that is not 1 in each first status bit set in the first status bit set corresponding to the binary bit set, it is determined that there is an exception table in the target logical to physical mapping table set.

[0065] In the embodiment of the present invention, the binary bit set is traversed to check whether the state of each binary bit is consistent with the corresponding state in the physical cluster state table. If an inconsistency is found, the abnormality is recorded and subsequent processing (such as alarm, log recording, etc.) is performed.

[0066] Specifically, in the physical cluster state table, a first state bit set corresponding to the binary bit set is searched, and it is checked whether all first state bits are 1. If there is a target state bit that is not 1, it is determined that an abnormal table exists in the target logical-to-physical mapping table set.

[0067] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: when a target logic-to-physical mapping table set is detected, the physical block address in the target logic-to-physical mapping table set is extracted to obtain a physical block address set; a binary bit set corresponding to the physical block address set is obtained, and a physical cluster status table is obtained; in the physical cluster status table, if each first state bit in the first state bit set corresponding to the binary bit set has a target state bit that is not 1, it is determined that an abnormal table exists in the target logic-to-physical mapping table set. By extracting the physical block address in the mapping table, a physical block address set is formed, which avoids the tedious process of checking one by one in the traditional method. After obtaining the binary bit set and the physical cluster status table, the abnormality can be quickly located by batch comparing the state bits in the two sets. Since the state bits are compared in the form of a set, the physical block address with abnormalities can be quickly identified without checking them one by one, which significantly shortens the time for locating the abnormality.

[0068] Due to various reasons (such as hardware failure, software error, etc.), anomalies or errors may occur in the logical-to-physical mapping table. If these anomalies or errors are not discovered and handled in time, they may cause data to be damaged, lost or inaccessible. Based on this, the present invention proposes an optional embodiment.

[0069] Reference Figure 2 , Figure 2 This is a schematic diagram of a specific embodiment of step 103 of the method for analyzing anomalies of a logical-to-physical mapping table in an embodiment of the present invention. Step S103 also includes the following specific implementation methods.

[0070] Step S1031, in the physical cluster status table, if all first state bits in the first state bit set corresponding to the binary bit set are 1, then in the physical cluster status table, determine whether all second state bits in the remaining second state bit sets are 0, and the status bits in the physical cluster status table are composed of the first state bit set and the second state bit set.

[0071] In an embodiment of the present invention, the binary bit set is traversed to find the portion corresponding to the first state bit set in the physical cluster state table.

[0072] Optionally, a bit operation or a bit mask is used to quickly check whether all status bits in the first status bit set are 1.

[0073] Specifically, if the first state bit set check passes, the physical cluster state table is traversed continuously to check whether all state bits in the second state bit set are 0.

[0074] Optionally, bit operations or bit masks may also be used to quickly determine the state of the second state bit set.

[0075] Step S1032: if all second state bits in the second state bit set are not 0, it is determined that an exception table exists in the target logical-to-physical mapping table set.

[0076] In an embodiment of the present invention, if it is found that there is a non-zero status bit in the second status bit set, it is immediately determined that there is an exception table in the target logical-to-physical mapping table set.

[0077] Optionally, a flag or status code may be set to indicate whether an exception exists, and corresponding processing may be performed in subsequent steps based on the flag or status code.

[0078] Step S1033: if all second state bits in the second state bit set are 0, it is determined that there is no abnormal table in the target logical-to-physical mapping table set.

[0079] In the embodiment of the present invention, by simultaneously checking the first state bit set and the second state bit set, it is possible to accurately determine whether there is an abnormality in the logical-to-physical mapping table. Timely discovering and processing the abnormality in the logical-to-physical mapping table can avoid data damage or loss, thereby enhancing the reliability of the system.

[0080] Due to various reasons (such as hardware failure, software error, etc.), anomalies or errors may occur in the logical-to-physical mapping table. If these anomalies or errors are not discovered and handled in time, they may cause data to be damaged, lost or inaccessible. Based on this, the present invention proposes an optional embodiment.

[0081] Reference Figure 3 , Figure 3 This is a schematic diagram of a specific embodiment before step 101 of the method for analyzing anomalies of a logical to physical mapping table in an embodiment of the present invention. Before step S101, the following specific implementation methods are also included.

[0082] Step S201 , when a mapping table to be analyzed is detected, if the total physical block data volume corresponding to the mapping table to be analyzed is greater than or equal to a preset physical block data volume, a segmentation operation is performed on the mapping table to be analyzed to obtain a plurality of logical-to-physical mapping table sets to be analyzed.

[0083] In an embodiment of the present invention, all logical-to-physical mapping tables are traversed, and the number of physical blocks in each table is accumulated.

[0084] Optionally, if the logical-to-physical mapping table has metadata or header information containing the total number of physical blocks, the information is directly read.

[0085] Optionally, use a database query statement to quickly obtain the total number of physical blocks.

[0086] Specifically, the calculated total physical block data volume is compared with a preset physical block data volume threshold.

[0087] Optionally, the threshold is dynamically adjusted based on system resources (eg, memory, processing power) of the terminal device.

[0088] Optionally, if the end device is under high load, the threshold is lowered to reduce the number of segments.

[0089] Specifically, the mapping table to be analyzed is evenly divided into a plurality of sets of logical-to-physical mapping tables to be analyzed.

[0090] Optionally, segmentation is performed based on certain characteristics of the logical-to-physical mapping table (such as timestamp, physical block address range).

[0091] Optionally, a load balancing algorithm is used to distribute the logical-to-physical mapping tables to different sets.

[0092] Step S202 : selecting target sets from the set of logical-to-physical mapping tables to be analyzed in turn as target logical-to-physical mapping table sets.

[0093] In an embodiment of the present invention, each set of logical-to-physical mapping tables to be analyzed is selected in sequence as a target set of logical-to-physical mapping tables.

[0094] Optionally, multithreading or concurrent processing is used to simultaneously process multiple sets of logic-to-physical mapping tables to be analyzed.

[0095] In the embodiment of the present invention, by simultaneously checking the first state bit set and the second state bit set, it is possible to accurately determine whether there is an abnormality in the logical-to-physical mapping table. Timely discovering and processing the abnormality in the logical-to-physical mapping table can avoid data damage or loss, thereby enhancing the reliability of the system.

[0096] The amount of data in the mapping table to be analyzed may vary greatly, some may contain tens of thousands of physical block addresses, while others may contain only a few or dozens. The inability of traditional analysis methods to cope with this flexibly will lead to over-segmentation. The amount of data in each segment may be small, but a series of operations (such as reading, parsing, and analyzing) are required to process each segment, which will increase unnecessary processing overhead. Based on this, the present invention proposes an optional embodiment.

[0097] The following specific implementation is also included before step S101.

[0098] Step S203: when a mapping table to be analyzed is detected, if the total physical block data volume corresponding to the mapping table to be analyzed is less than a preset physical block data volume, the mapping table to be analyzed is taken as a target logical-to-physical mapping table set.

[0099] In an embodiment of the present invention, the total physical block data volume corresponding to the to-be-processed and to-be-analyzed mapping table is calculated.

[0100] The calculated total physical block data volume is compared with a preset physical block data volume, wherein the preset physical block data volume is a threshold value used to determine whether the mapping table to be analyzed can be processed as a whole.

[0101] If the total physical block data volume is less than the preset physical block data volume, then this batch of logical-to-physical mapping tables can be directly used as a target logical-to-physical mapping table set for subsequent analysis operations.

[0102] If the total physical block data amount is greater than or equal to the preset physical block data amount, other operations (such as the segmentation operation described above) need to be performed.

[0103] In the embodiment of the present invention, when the total physical block data volume of the mapping table to be analyzed is small, processing it as a whole can reduce the overhead of segmentation, reorganization and other operations, thereby improving processing efficiency. For a small amount of data in the mapping table to be analyzed, there is no need to perform complex segmentation operations, and subsequent analysis operations can be performed directly, simplifying the operation process.

[0104] When detecting anomalies, the traditional logic-to-physical mapping table analysis method often lacks sufficient recording and feedback mechanisms, which makes it difficult to find the problem in time. Based on this, the present invention proposes an optional embodiment.

[0105] Reference Figure 4 , Figure 4 This is a schematic diagram of a specific embodiment after step 202 of the method for analyzing anomalies of a logical-to-physical mapping table in an embodiment of the present invention. Step S202 also includes the following specific implementation methods.

[0106] Step S203, obtaining log records.

[0107] In an embodiment of the present invention, when it is determined that there is an exception table in the target logical-to-physical mapping table set, the log recording mechanism is automatically triggered to extract records related to the current exception analysis operation from the log file. The records include but are not limited to the time when the exception occurred, the type of exception, the logical-to-physical mapping table entries involved, the system status and other key information. Through automated log recording, the integrity and accuracy of the exception information is guaranteed, which can provide support for subsequent troubleshooting.

[0108] If it is determined that there is an exception table in the target logical-to-physical mapping table set, a log record corresponding to the exception analysis operation is obtained. Records related to the current exception analysis operation can be extracted from the log file.

[0109] Step S204, output log records.

[0110] In the embodiment of the present invention, through log recording, R&D personnel can obtain abnormal information more quickly, thereby shortening the time for troubleshooting and reducing business losses caused by failures.

[0111] Traditional logic-to-physical mapping table anomaly analysis methods may lack a timely termination mechanism. Once the logic-to-physical mapping table set is processed, even if an anomaly is detected, the abnormal mapping table may continue to be processed, resulting in resources being wasted on invalid data processing. Based on this, the present invention proposes an optional embodiment.

[0112] Step S203 also includes the following specific implementation methods.

[0113] Step S2031, terminating the step of sequentially selecting a target set from the set of logical-to-physical mapping tables to be analyzed as a target logical-to-physical mapping table set, and obtaining log records.

[0114] Specifically, if it is determined that an abnormal table exists, the step of selecting a target set from the current set of logical to physical mapping tables to be analyzed as the target logical to physical mapping table set will be stopped, so that in an abnormal situation, the data that may have problems will not be processed further.

[0115] After the analysis is terminated, the log records related to the current abnormality determination will be obtained. The log records may include information such as the specific cause of the abnormality, the time when the abnormality occurred, and the scope of the abnormality.

[0116] By obtaining and outputting log records, developers or system administrators can detect and handle exceptions in a timely manner, thereby preventing the impact of exceptions on the normal operation of the system from further expanding.

[0117] In the embodiment of the present invention, when an abnormality is detected in a certain logical-to-physical mapping table set, if the set or subsequent sets are continued to be processed, more resources (such as computing resources, storage resources, etc.) may be wasted on invalid data processing, which is extremely disadvantageous to the scenario of batch abnormality analysis. Aborting the current step can stop the invalid processing, thereby avoiding further waste of resources.

[0118] Traditional analysis methods may only focus on the anomalies of logic or data in the logical-to-physical mapping table, while ignoring the important aspect of whether the physical block address exceeds the physical capacity limit of the flash memory. Based on this, the present invention proposes an optional embodiment.

[0119] Step S101 also includes the following specific implementation methods.

[0120] Step S1011, if there is a target physical block address in the physical block address set that exceeds the preset maximum physical block address value, it is determined that there is an abnormality in the target logical to physical mapping table corresponding to the target physical block address, otherwise the binary bit set corresponding to the physical block address set is obtained, and the physical cluster status table is obtained.

[0121] In the implementation manner of the present invention, a preset maximum physical block address value is set according to the physical capacity size of the test target (flash memory, NandFlash).

[0122] Each physical block address in the physical block address set is traversed and compared with a preset maximum physical block address value.

[0123] If it is found that a certain physical block address exceeds the maximum physical block address value, it is determined that an abnormality exists in the target logical-to-physical mapping table corresponding to the physical block address exceeding the maximum physical block address value.

[0124] The information of the exception table is recorded in the log record for subsequent R&D analysis.

[0125] Optionally, the preset maximum physical block address value is dynamically adjusted according to the actual physical capacity of the flash memory, which can be achieved by reading the capacity information of the flash memory.

[0126] Optionally, the exceptions are divided into different levels according to the extent to which the physical block address exceeds the maximum physical block address value. For example, an exception exceeding a certain threshold but not exceeding twice the threshold is a first-level exception, and an exception exceeding twice the threshold is a second-level exception.

[0127] Optionally, different handling strategies can be adopted according to the abnormality level. For example, for a level 1 abnormality, only logs can be recorded and analysis can be continued; for a level 2 abnormality, analysis can be terminated and R&D personnel can be notified.

[0128] Optionally, in the analysis process, a plurality of logical-to-physical mapping table sets are processed simultaneously using parallel processing technology. When an abnormality is detected, only the analysis process of the currently processed logical-to-physical mapping table set is terminated without affecting other parallel processed logical-to-physical mapping table sets.

[0129] Optionally, when recording exception information, in addition to recording the abnormal logical-to-physical mapping table information, other information related to the logical-to-physical mapping table, such as timestamp, operation type, etc., can also be recorded, so that subsequent R&D analysis can have a more comprehensive understanding of the abnormal situation.

[0130] In the embodiment of the present invention, by setting the maximum physical block address value, a logical-to-physical mapping table anomaly that exceeds the physical capacity limit of the flash memory can be detected, thereby avoiding potential problems caused by physical block address errors.

[0131] In the traditional analysis method, when an anomaly is detected in the logical-to-physical mapping table, the anomaly information may be lost due to various reasons (such as system crash, data loss, etc.), so that effective analysis and resolution cannot be performed. Based on this, the present invention proposes an optional embodiment.

[0132] Step S101 also includes the following specific implementation methods.

[0133] Step S1011, recording the abnormality of the target logical-to-physical mapping table in a log record.

[0134] In an embodiment of the present invention, according to the preset maximum physical block address value, it is determined whether there is a target physical block address in the physical block address set that exceeds the value. If there is, it is determined that there is an abnormality in the corresponding target logical-to-physical mapping table.

[0135] Prepare a log file to record exception information. Record the relevant information of the target logical-to-physical mapping table of the exception (such as physical block address, exception type, timestamp, etc.) in the log file. You can use a specific log format or template to record.

[0136] Optionally, when an exception is determined, the exception information is immediately recorded in the log record to achieve real-time logging. Problems can be discovered and solved in a timely manner, reducing the risk of potential data loss or damage.

[0137] Optionally, the exception information can be classified and recorded in different log files according to the type or severity of the exception, which can help R&D personnel locate and analyze specific types of exceptions more quickly.

[0138] Optionally, log files can be compressed and backed up regularly to reduce storage space usage and improve data security. Automated tools can be used to periodically compress logs.

[0139] Optionally, set a log cleanup policy to delete old or no longer needed log files based on time range or file size.

[0140] In the embodiment of the present invention, the R&D personnel can quickly discover and analyze abnormal problems in the logic-to-physical mapping table by viewing the log record file, thereby improving the efficiency of problem solving.

[0141] like Figure 5, which is a schematic diagram of a terminal device provided in an embodiment of the present invention. The terminal device 5 may include: a processor 501, a memory 502, and a computer program 503 stored in the memory 502 and executable on the processor 501, such as an abnormality analysis program for a logical-to-physical mapping table. When the processor 501 executes the computer program 503, the steps in the above-mentioned abnormality analysis embodiments of the logical-to-physical mapping table are implemented.

[0142] The computer program may be divided into one or more modules / units, one or more modules / units are stored in the memory 502 and executed by the processor 501 to complete the present invention. One or more modules / units may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device.

[0143] The terminal device may include, but is not limited to, a processor 501 and a memory 502. Those skilled in the art will appreciate that Figure 5 It is only an example of a terminal device and does not constitute a limitation of the terminal device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the terminal device may also include input and output devices, network access devices, buses, etc.

[0144] The processor 501 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0145] The memory 502 may be an internal storage unit of the terminal device, such as a hard disk or memory of the terminal device. The memory 502 may also be an external storage device of the terminal device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal device. Further, the memory 502 may also include both an internal storage unit of the terminal device and an external storage device. The memory 502 is used to store computer programs and other programs and data required by the terminal device. The memory 502 may also be used to temporarily store data that has been output or is to be output.

[0146] It should be noted that, for the convenience and brevity of description, the structure of the above-mentioned terminal device can also refer to the specific description of the structure in the method embodiment, which will not be repeated here.

[0147] An embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned logic-to-physical mapping table exception analysis method can be implemented.

[0148] An embodiment of the present invention provides a computer program product. When the computer program product is run on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned logic-to-physical mapping table abnormality analysis method when executing the computer program product.

[0149] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0150] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0151] In the embodiments provided by the present invention, it should be understood that the disclosed terminal devices and methods can be implemented in other ways. For example, the terminal device embodiments described above are only exemplary. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0152] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0153] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0154] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0155] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above-described embodiments, a person skilled in the art should understand that the technical solutions described in the above-described embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A method for analyzing anomalies of a logical to physical mapping table, characterized in that: include: When a target logical-to-physical mapping table set is detected, a physical block address in the target logical-to-physical mapping table set is extracted to obtain a physical block address set; Obtaining a binary bit set corresponding to the physical block address set, and obtaining a physical cluster state table; In the physical cluster status table, if there is a target status bit that is not 1 in each first status bit set corresponding to the binary bit set, it is determined that there is an exception table in the target logical-to-physical mapping table set.

2. The method for analyzing anomalies of a logical-to-physical mapping table according to claim 1, characterized in that: After the steps of obtaining the binary bit set corresponding to the physical block address set and obtaining the physical cluster status table, the method further includes: In the physical cluster status table, if each first state bit in the first state bit set corresponding to the binary bit set is 1, then in the physical cluster status table, it is determined whether each second state bit in the remaining second state bit set is 0, and the state bits in the physical cluster status table are composed of the first state bit set and the second state bit set; If all the second state bits in the second state bit set are not 0, it is determined that there is an exception table in the target logical-to-physical mapping table set; If all the second state bits in the second state bit set are 0, it is determined that there is no exception table in the target logical-to-physical mapping table set.

3. The method for analyzing anomalies of a logical-to-physical mapping table according to claim 1, characterized in that: Before the step of extracting the physical block addresses in the target logical-to-physical mapping table set to obtain the physical block address set when the target logical-to-physical mapping table set is detected, the method further comprises: When a mapping table to be analyzed is detected, if the total physical block data volume corresponding to the mapping table to be analyzed is greater than or equal to the preset physical block data volume, the mapping table to be analyzed is split into a plurality of logical-to-physical mapping table sets to be analyzed; A target set is selected in sequence from the set of logical-to-physical mapping tables to be analyzed as the target set of logical-to-physical mapping tables.

4. The method for analyzing anomalies of a logical-to-physical mapping table according to claim 1, characterized in that: Before the step of extracting the physical block addresses in the target logical-to-physical mapping table set to obtain the physical block address set when the target logical-to-physical mapping table set is detected, the method further comprises: When a mapping table to be analyzed is detected, if the total physical block data volume corresponding to the mapping table to be analyzed is less than the preset physical block data volume, the mapping table to be analyzed is used as a target logical-to-physical mapping table set.

5. The method for analyzing anomalies of a logical-to-physical mapping table according to claim 1, wherein: After the step of determining whether an abnormal table exists in the target logical-to-physical mapping table set, the method further includes: Get log records; Output the log record.

6. The method for analyzing anomalies of a logical-to-physical mapping table according to claim 5, characterized in that: The step of obtaining log records includes: The step of sequentially selecting a target set from the set of logical-to-physical mapping tables to be analyzed as the target set of logical-to-physical mapping tables is terminated, and the log record is obtained.

7. The method for analyzing anomalies of a logical-to-physical mapping table according to any one of claims 1, characterized in that: The step of obtaining a binary bit set corresponding to the physical block address set and obtaining a physical cluster status table comprises: If there is a target physical block address in the physical block address set that exceeds the preset maximum physical block address value, it is determined that there is an abnormality in the target logical to physical mapping table corresponding to the target physical block address, otherwise the binary bit set corresponding to the physical block address set is obtained, and the physical cluster status table is obtained.

8. The method for analyzing anomalies of a logical-to-physical mapping table according to any one of claims 1 to 7, characterized in that: After the step of determining that there is an abnormality in the target logical-to-physical mapping table corresponding to the target physical block address, the method further includes: An exception existing in the target logical-to-physical mapping table is recorded in the log record.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for analyzing anomalies of a logical-to-physical mapping table as claimed in any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for analyzing anomalies of a logical-to-physical mapping table according to any one of claims 1 to 8 are implemented.

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