Encoding method and decoding method of nonvolatile memory and related device

Abstract

The invention provides a coding and decoding method of a nonvolatile memory and a related device. According to the coding method, a minimum common multiple expression of a primitive polynomial of a finite field primitive element and an inverted polynomial of the primitive polynomial is adopted as a generator polynomial; the decoding method comprises the following steps: reading a receiving sequence and calculating an initial syndrome of the receiving sequence, if the initial syndrome is not 0, determining that an error exists, respectively adjusting the value of each bit datum, obtaining two flipping syndromes, namely a first flipping syndrome and a second flipping syndrome, and if both the first flipping syndrome and the second flipping syndrome are 0, determining that the error exists, respectively adjusting the value of each bit datum, and obtaining a second flipping syndrome; or if the product of the first flipping syndrome and the second flipping syndrome is 1, it is determined that the bits are flipped. The present application can perform parallel bit-by-bit decoding according to flipping syndromes. Compared with a BCH code error correction scheme, the method has the advantages that different polynomials are generated, high-order power operation of finite field elements is avoided during decoding, decoding complexity and decoding delay are reduced, and the requirement of rapid decoding is met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an encoding method and a decoding method of a non-volatile memory and related devices. Background Art

[0002] With the development of semiconductor-related technologies, the types of semiconductor devices are also developing rapidly, including low-cost, high-density non-volatile memory. In order to improve the storage density of non-volatile memory, multi-level storage technology can be used. Although multi-level storage technology can improve storage density and reduce costs, it reduces the distance between adjacent storage cells, resulting in a decrease in the reliability of non-volatile memory. Under 45nm technology, the bit error rate of non-volatile memory is higher than 10 -6 However, in practical applications, non-volatile memory needs to meet the bit error rate of less than 10 -12 In order to reduce the bit error rate, error correction codes can be introduced into the encoding and decoding process of non-volatile memory to improve the reliability of non-volatile memory.

[0003] Error-correcting codes add redundant bits to the original information sequence, enabling the receiving end to detect or correct errors during transmission. BCH codes are an important type of cyclic error-correcting code with an excellent algebraic structure and efficient encoding algorithm, making them suitable for improving the reliability of non-volatile memory. However, decoding using BCH codes is complex and time-consuming, making them inadequate for fast decoding. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide an encoding method and a decoding method of a non-volatile memory and related devices, which can reduce the decoding complexity, reduce the decoding time, and meet the needs of fast decoding.

[0005] To achieve the above objectives, this application has the following technical solutions:

[0006] The present application provides a decoding method for a non-volatile memory, characterized by comprising:

[0007] Reading a received sequence from a non-volatile memory to obtain an initial syndrome of the received sequence, wherein the received sequence includes n binary bit data; the non-volatile memory stores an encoding codeword, and during data storage or reading, the encoding codeword is superimposed with error data to form a received sequence; encoding information bits using a generating polynomial to obtain the encoding codeword, wherein the generating polynomial is composed of a primitive polynomial of a finite field primitive element and its inverse polynomial;

[0008] determining whether the value of the initial syndrome is 0, if the value of the initial syndrome is not 0, then there is an error in the received sequence;

[0009] Adjust the value of the i-th bit data respectively, 0≤i≤n-1; obtain two flip syndromes of the received sequence after adjusting the value of the i-th bit data, determine whether the values ​​of the flip syndromes are both 0, and if the values ​​of the flip syndromes are both 0, determine to flip the i-th bit data to obtain a flipped bit;

[0010] If the values ​​of the flip syndromes are not all 0, determining whether the product of the two flip syndromes is 1; if the product of the two flip syndromes is 1, determining to flip the i-th bit data to obtain a flipped bit;

[0011] The received sequence is decoded according to the flipped bits.

[0012] Optionally, the method further includes:

[0013] The steps of adjusting the value of the i-th bit data are performed simultaneously, and the results of adjusting the values ​​of different bit data, whether the flip syndromes are all 0, and whether the product of the two flip syndromes is 1 are obtained simultaneously.

[0014] Optionally, the two flip accompanying formulas include a first flip accompanying formula and a second flip accompanying formula;

[0015] If the values ​​of the flip syndromes are not all 0, determining whether the product of two flip syndromes is 1, and if the product of the two flip syndromes is 1, determining to flip the i-th bit data includes:

[0016] If the values ​​of the first flip syndrome and the second flip syndrome are not both 0, it is determined whether the product of the first flip syndrome and the second flip syndrome is 1; if the product of the first flip syndrome and the second flip syndrome is 1, it is determined to flip the i-th bit data.

[0017] Optionally, the initial syndrome is a polynomial equation corresponding to the received sequence and the coefficients of the finite field GF(2 m ) is obtained by performing an XOR operation on the elements in the received sequence, and the length of the received sequence is n=2 m -1.

[0018] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is a finite field GF(2 m ), the inverse polynomial is the inverse polynomial of the minimum polynomial.

[0019] The present application provides a non-volatile memory encoding method, comprising:

[0020] Get information bits;

[0021] The length of the check bit and the finite field GF(2 m ) in the primitive polynomial and the reverse polynomial of the primitive element, the length of the check bit is 2m;

[0022] The information bits are encoded using a generating polynomial to obtain an encoded codeword, and the encoded codeword is stored in a non-volatile memory; the generating polynomial is composed of the primitive polynomial and the inverse polynomial.

[0023] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is a finite field GF(2 m ), the inverse polynomial is the inverse polynomial of the minimum polynomial.

[0024] Optionally, m is an odd number greater than or equal to 5.

[0025] The present application provides a decoding device for a non-volatile memory, comprising:

[0026] a reading unit, configured to read a received sequence from a non-volatile memory and obtain an initial syndrome of the received sequence, wherein the received sequence includes n binary bits; the non-volatile memory stores a coding codeword, and during data storage or reading, the coding codeword is superimposed with error data to form a received sequence; and the coding codeword is obtained by encoding information bits using a generating polynomial, wherein the generating polynomial is composed of a primitive polynomial of a finite field primitive element and its inverse polynomial;

[0027] a first determining unit, configured to determine whether a value of the initial syndrome is 0, and if the value of the initial syndrome is not 0, an error exists in the received sequence;

[0028] a second determining unit, configured to adjust the value of the i-th bit data respectively, where 0≤i≤n-1; obtain two flip syndromes of the received sequence after the value of the i-th bit data is adjusted, determine whether the values ​​of the flip syndromes are both 0, and if the values ​​of the flip syndromes are both 0, determine to flip the i-th bit data to obtain a flipped bit;

[0029] a third determining unit, configured to, if the values ​​of the flip syndromes are not both 0, determine whether a product of two flip syndromes is 1, and if the product of the two flip syndromes is 1, determine to flip the i-th bit of data to obtain a flipped bit;

[0030] A decoding unit is used to decode the received sequence according to the flipped bit.

[0031] The present application provides a non-volatile memory encoding device, comprising:

[0032] an acquisition unit, for acquiring information bits;

[0033] A configuration unit is configured to configure the length of the check bit and the finite field GF(2 m ) in the primitive polynomial and the reverse polynomial of the primitive element, the length of the check bit is 2m;

[0034] The encoding unit is used to encode the information bit using a generating polynomial to obtain an encoded codeword, and store the encoded codeword in a non-volatile memory; the generating polynomial is composed of the primitive polynomial and the inverse polynomial.

[0035] The present application provides a decoding method for a non-volatile memory, comprising: reading a received sequence from the non-volatile memory, obtaining an initial syndrome of the received sequence, the received sequence comprising n binary bits of data, determining whether the value of the initial syndrome is 0; if the value of the initial syndrome is not 0, the received sequence contains an error. Specifically, the initial syndrome is used to determine whether the received sequence read from the non-volatile memory contains an error. When it is determined that the read received sequence contains an error, a decoding error correction process is initiated, wherein the value of the i-th bit of data is adjusted, 0≤i≤n-1, and two flip syndromes of the received sequence after adjusting the value of the i-th bit of data are obtained. It is determined whether the values ​​of the flip syndromes are both 0; if the values ​​of the flip syndromes are both 0, the i-th bit of data is flipped to obtain a flipped bit. If the values ​​of the flip syndromes are not both 0, the product of the two flip syndromes is determined to be 1; if the product of the two flip syndromes is 1, the i-th bit of data is flipped to obtain a flipped bit. That is, by adjusting the value of the bit data at each position in the received sequence, the value of the flipped syndrome after adjustment is used to determine whether the bit data at that position is erroneous when read. If an error occurs, the received sequence is decoded based on the flipped bit. Furthermore, the coded codeword is obtained by encoding the information bits using a generating polynomial. The generating polynomial is composed of a primitive polynomial and a reverse polynomial of a finite field primitive element. The coded codeword is stored in a non-volatile memory. During data storage or reading, the coded codeword is superimposed with the erroneous data to form the received sequence.

[0036] It can be seen that the present application can perform bit-by-bit decoding based on the flip syndrome, avoiding the complex calculations when using BCH code for decoding, greatly reducing the decoding difficulty, improving the decoding efficiency, and reducing the decoding time. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A schematic diagram showing a flow chart of a non-volatile memory encoding method provided in an embodiment of the present application is shown;

[0039] Figure 2 A schematic diagram of a circuit structure of a system encoding method provided in an embodiment of the present application is shown;

[0040] Figure 3 A schematic diagram of a flow chart of a decoding method for a non-volatile memory provided in an embodiment of the present application is shown;

[0041] Figure 4 A schematic diagram of a decision flow of a decoding method provided in an embodiment of the present application is shown;

[0042] Figure 5 A schematic diagram of codeword error probability provided by an embodiment of the present application is shown;

[0043] Figure 6 A schematic diagram of the data format of a (26,16) code provided in an embodiment of the present application is shown;

[0044] Figure 7 A schematic structural diagram of a non-volatile memory encoding device provided in an embodiment of the present application is shown;

[0045] Figure 8 A schematic structural diagram of a decoding device for a non-volatile memory provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0047] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0048] With the development of semiconductor-related technologies, the types of semiconductor devices are also developing rapidly, including low-cost, high-density non-volatile memory. In order to improve the storage density of non-volatile memory, multi-level storage technology can be used. Although multi-level storage technology can improve storage density and reduce costs, it reduces the distance between adjacent storage cells, resulting in a decrease in the reliability of non-volatile memory. Under 45nm technology, the bit error rate of non-volatile memory is higher than 10 -6 However, in practical applications, non-volatile memory needs to meet the bit error rate of less than 10 -12 In order to reduce the bit error rate, error correction codes can be introduced into the encoding and decoding process of non-volatile memory to improve the reliability of non-volatile memory.

[0049] Error-correcting codes add a certain number of redundant bits to the original information sequence, enabling the receiving end to detect or correct errors during transmission. BCH codes are an important class of cyclic error-correcting codes with excellent algebraic structure and efficient encoding algorithms. Binary BCH codes, which correct two errors, are a subclass of BCH codes and meet the reliability requirements of non-volatile memory. They can achieve high bit rates with short to medium code lengths, making them widely used in high-data-rate scenarios such as storage.

[0050] BCH codes can be used to improve the reliability of non-volatile memory. Although encoding with BCH codes is relatively simple, decoding is complex. Decoding requires calculating high-order powers of each element in the finite field, resulting in high decoding complexity and time delay, making it difficult to achieve fast decoding.

[0051] Based on this, the present application provides a decoding method for a non-volatile memory, comprising: reading a received sequence from the non-volatile memory, obtaining an initial syndrome of the received sequence, the received sequence comprising n binary bits of data, determining whether the value of the initial syndrome is 0; if the value of the initial syndrome is not 0, the received sequence contains an error. Specifically, the initial syndrome is used to determine whether the received sequence read from the non-volatile memory contains an error. When it is determined that the read received sequence contains an error, a decoding error correction process is initiated, wherein the value of the i-th bit of data is adjusted, 0≤i≤n-1, and two flip syndromes of the received sequence after adjusting the value of the i-th bit of data are obtained. It is determined whether the values ​​of the flip syndromes are both 0; if the values ​​of the flip syndromes are both 0, the i-th bit of data is flipped to obtain a flipped bit. If the values ​​of the flip syndromes are not both 0, the product of the two flip syndromes is determined to be 1; if the product of the two flip syndromes is 1, the i-th bit of data is flipped to obtain a flipped bit. That is to say, by adjusting the value of the bit data at each position in the received sequence, it is determined whether the bit data at that position is erroneous when reading according to the value of the flipped companion formula after adjustment. If an error occurs, the received sequence is decoded according to the flipped bit position. In addition, the encoding codeword is obtained by encoding the information bit using a generating polynomial. The generating polynomial is composed of a primitive polynomial and a reverse polynomial of a finite field primitive element. The encoding codeword is stored in a non-volatile memory. During the data storage or reading process, the encoding codeword is superimposed on the erroneous data to form a received sequence. It can be seen that the present application can perform bit-by-bit decoding based on the flipped companion formula, avoiding the complex calculations when decoding using the BCH code, greatly reducing the decoding difficulty, improving the decoding efficiency, and reducing the decoding time.

[0052] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0053] refer to Figure 1 The figure shows a flowchart of a non-volatile memory encoding method provided by an embodiment of the present application. To reduce decoding complexity and decoding time, it is necessary to construct an encoding scheme for an error-correcting code to obtain the same error correction capability as a BCH code that corrects two errors, while avoiding the calculation of high-order powers of finite field elements during BCH decoding, thereby reducing decoding complexity.

[0054] As an example, the non-volatile memory may be a NOR-type flash memory.

[0055] The encoding method of the non-volatile memory provided in the embodiment of the present application includes the following steps:

[0056] S101, obtain information bits.

[0057] In the embodiments of the present application, information bits may also be referred to as information bits. Information bits may include multiple binary bit data. Information bits may be expressed using polynomials. Information bits may be encoded, and the encoded codewords may be stored in a non-volatile memory.

[0058] As an example, the information bits may be z=(z0, z1, ..., z k-1 ), and the corresponding polynomial is z(x)=z0+z1x+…+z k-1 x k-1 .

[0059] S102, configure the length of the check bit and the finite field GF(2 m ) is the primitive polynomial and inverse polynomial of the primitive elements in .

[0060] In embodiments of the present application, the length of the check bits can be preconfigured to facilitate subsequent encoding of the information bits using a generator polynomial. Specifically, the length of the check bits can be configured based on the length of the information bits and a threshold for the number of error corrections. The threshold for the number of error corrections refers to the error correction capability of the error correction code provided in embodiments of the present application. For example, the error correction capability of an error correction code that corrects 2 errors is 2.

[0061] According to the length of the information bit and the error correction number threshold, the appropriate finite field GF(2 m ), we can determine that the length of the check bit is t×m, where t is the error correction number threshold.

[0062] As an example, if the error correction number threshold is 2, the length of the check bit may be 2m.

[0063] In the embodiment of the present application, the information bits can be encoded using a generating polynomial. Specifically, the value of m can be determined according to the length of the information bits and the error correction capability of the error correction code, and then the finite field GF(2 m ) and the inverse polynomial of the primitive elements in the primitive polynomial. The primitive polynomial and the inverse polynomial can form a generating polynomial. In other words, the length of the information bit and the error correction capability of the error correction code are related to the generating polynomial that encodes the information bit.

[0064] In the embodiment of the present application, the information bits can be encoded using a generator polynomial to obtain an encoded codeword. Both the check bits and the encoded codeword can be represented by a polynomial.

[0065] As an example, the check bit can be s=(s0,s1,…s 2m-1 ), and the corresponding polynomial is s(x)=s0+s1x+…+s 2m-1 x 2m-1The encoding codeword can be c=(c0,c1,…,c n-1 ), the corresponding polynomial is the codeword polynomial, and the codeword polynomial can be c(x)=c0+c1x+…+c n-1 x n-1 .

[0066] As an example, the length of the encoded codeword after encoding using the generating polynomial is n=2 m -1, the information bit length is k = n-2m, and the check bit length is 2m. Where m is an odd number greater than or equal to 5. As the value of m increases, the encoded codeword has a higher code rate. For example, when m = 9, the encoded codeword length is 511 and the code rate is 0.9648. The error correction code provided in the embodiment of the present application has the same error correction capability and code rate as the BCH code that corrects two errors, and is also suitable for application in high data rate scenarios.

[0067] In the embodiment of the present application, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, wherein the primitive polynomial is a finite field GF(2 m ) is the minimum polynomial of the primitive element in the finite field GF(2 m ) primitive element, then the generating polynomial g(x) is -1 The least common multiple of the minimum polynomial with roots can be expressed as g(x)=LCM{g1(x),g -1 (x)}, where g1(x) is the minimum polynomial of element α, that is, the primitive polynomial, g -1 (x) is the element α -1 The minimum polynomial of g -1 (x) is a reverse polynomial, and LCM is the least common multiple of several polynomials.

[0068] S103, encoding the information bits using a generating polynomial to obtain an encoded codeword, and storing the encoded codeword in a non-volatile memory.

[0069] In an embodiment of the present application, after obtaining the generating polynomial, the information bits may be encoded using the generating polynomial to obtain an encoded codeword, which is then stored in a non-volatile memory.

[0070] As an example, the polynomial for obtaining the encoding codeword can be expressed using the following formula: c(x)=s(x)+x 2m z(x)=s0+s1x+…+s 2m-1 x 2m-1 +z0x 2m +…+z k-1 xn-1 , that is, [s,z]=c.

[0071] The specific encoding method using the generating polynomial can be selected according to the actual situation. The encoding method can include non-systematic encoding or systematic encoding. For non-systematic encoding, the encoding codeword can be obtained by c(x)=z(x)g(x). For systematic encoding, there are two ways: one is to use s(x)=x n-k z(x) mod g(x) to get the check bit, set the right side to be the high bit, and then get the code word c(x). Another way is to use h(x) = x n -1 / g(x) to get the check polynomial, and then let the code polynomial c(x) = x n-k z(x), let the right side be high, and then pass Get the encoded codeword c(x), refer to Figure 2 shown.

[0072] From the above description, it can be seen that the encoding method of the non-volatile memory provided by the present application only needs to use a generating polynomial for encoding, the encoding is simple, and the generating polynomial avoids using the minimum polynomial of high-order power elements. During subsequent decoding, there is no need to calculate the high-order power operations of the finite field elements, which helps reduce the complexity of decoding.

[0073] The addition and multiplication in the embodiments of the present application are mod2 addition and mod2 multiplication respectively.

[0074] refer to Figure 3 FIG. 1 is a flowchart of a decoding method for a non-volatile memory provided in an embodiment of the present application, the method comprising the following steps:

[0075] S201, reading a received sequence from a non-volatile memory to obtain an initial syndrome of the received sequence.

[0076] In an embodiment of the present application, after the coded codeword is stored in a non-volatile memory, the received sequence can be read from the non-volatile memory to determine whether the received sequence has an error. If an error is found, decoding and error correction are performed. That is, during the data storage or reading process, the coded codeword and the error data are superimposed to form a received sequence. Specifically, the received sequence includes n binary bit data, that is, the length of the received sequence is n=2 m -1.

[0077] In the embodiment of the coding method of the non-volatile memory, the coding codeword is obtained by encoding the information bit using a generating polynomial, and the generating polynomial is a finite field GF(2 m) is composed of the primitive polynomial of the primitive elements and the reverse polynomial of the primitive polynomial. The generating polynomial is the least common multiple of the primitive polynomial and the reverse polynomial. The primitive polynomial is a finite field GF(2 m ) is the minimal polynomial of the primitive elements in , and the inverse polynomial is the inverse polynomial of the minimal polynomial.

[0078] In an embodiment of the present application, a non-volatile memory stores an encoded codeword, which, combined with error data, forms a received sequence. Assuming r(x) is the received sequence polynomial corresponding to the received sequence read from the non-volatile memory, c(x) is the codeword polynomial corresponding to the encoded codeword stored in the non-volatile memory, and e(x) is the error polynomial, then r(x) = c(x) + e(x).

[0079] In the embodiment of the present application, the syndrome of the received sequence may be used to determine whether erroneous data exists in the received sequence.

[0080] Finite field GF(2 m ) in each element α i Can be expressed as an m-dimensional vector, and the syndrome can be expressed by element α i The vector addition representation is also an m-dimensional vector, such as the syndrome S1=r0+r1α 1 +…+r n-1 α (n-1) , its vector representation is when r i =1(0≤i≤n-1), the corresponding α i The vectors of are added. Accordingly, the syndrome S -i is to transform the element α in the finite field -i That is to say, the initial syndrome is the coefficient of the polynomial corresponding to the received sequence for the finite field GF(2 m ) is obtained by performing XOR operation on the elements in .

[0081] According to the received sequence polynomial r(x) read from the non-volatile memory, the corresponding syndrome S1=r(α), S -1 =r(α -1 ). Because r(α)=c(α)+e(α)=z(α)·g(α)+e(α),α,α -1 is the root of g(x), that is, g(α)=g(α -1 )=0, so S1=r(α)=e(α), and similarly, S -1 =r(α -1 )=e(α -1 ). In other words, the syndrome of the received sequence can be directly used to determine whether the received sequence contains errors, thereby achieving relatively simple error data identification.

[0082] Since the error correction capability of the decoding method provided in the embodiment of the present application is t=2, it is only necessary to consider the case where there are at most 2 erroneous data:

[0083] (1) When there is no error in the received sequence, that is, e(x) = 0, then r(x) = c(x), S1 = S -1 =0.

[0084] (2) When an error occurs in the received sequence, that is, e(x) = x i (0≤i≤n-1), at this time S1=α i ,S -1 =α -i , that is, S1·S -1 =1.

[0085] (3) When two errors occur in the received sequence, that is, e(x) = x i +x j (0≤i≠j≤n-1), then S1=α i +α j ,S -1 =α -i +α -j , S1·S -1 =α i-j +α j-i ≠1.

[0086] It can be seen that when e(x)=0, S1=S -1 = 0. When e(x) = x i (0≤i≤n-1), S1·S -1 = 1. When e(x) = x i +x j (0≤i≠j≤n-1), S1·S -1 =α i-j +α j-i ≠1, S1≠S -1 ≠ 0. That is, the value of the syndrome is different depending on the number of erroneous data. In this way, it is possible to directly determine whether erroneous data exists through the syndrome value and perform error correction decoding based on the syndrome.

[0087] S202: Determine whether the value of the initial syndrome is 0. If the value of the initial syndrome is not 0, an error exists in the received sequence.

[0088] In an embodiment of the present application, the syndrome of the received sequence can determine whether there is erroneous data. Therefore, the initial syndrome of the received sequence can be calculated by a lookup table, and whether the received sequence has an error can be confirmed based on whether the value of the initial syndrome is 0.

[0089] If the value of the initial syndrome is not 0, then there is an error in the received sequence and the decoding error correction process is entered. -1 =0, it is considered that there is no error in the received sequence and the decoding is exited.

[0090] S203, respectively adjust the value of the i-th bit data, obtain two flip syndromes of the received sequence after adjusting the value of the i-th bit data, and determine whether the values ​​of the flip syndromes are both 0. If the values ​​of the flip syndromes are both 0, determine to flip the i-th bit data to obtain a flipped bit position, 0≤i≤n-1.

[0091] In an embodiment of the present application, if the received sequence is determined to contain erroneous data based on the value of the initial syndrome being non-zero, the value of the i-th bit data can be adjusted separately, 0≤i≤n-1, to obtain two flip syndromes of the received sequence after adjusting the value of the i-th bit data. It is then determined whether the values ​​of the flip syndromes are both 0. If the values ​​of the flip syndromes are both 0, it is determined that the i-th bit data is flipped to obtain a flipped bit. If the values ​​of the flip syndromes are not both 0, it is determined that the received sequence after adjusting the value of the i-th bit data contains erroneous data. Flipping the i-th bit data refers to adjusting the value of the binary bit data to the opposite value. For example, if the value of the i-th bit data is 0, flipping the value of the i-th bit data adjusts the value of the i-th bit data to 1.

[0092] That is, when it is determined that erroneous data exists in the received sequence, the received sequence can be decoded step by step. By adjusting the value of one bit of data each time, the flip syndrome after adjusting the value of the bit of data is obtained, until the values ​​of all the bit data are adjusted. If there is only one erroneous data in the received sequence, the position of the erroneous data can be obtained by the value of the flip syndrome.

[0093] Specifically, when an error data appears in the received sequence, decoding begins bit by bit. Assuming that the value of the i-th bit data is adjusted, the error polynomial after adjustment is e'(x)=e(x)+x i , the adjusted flip companion is S 1,i =e'(α),S -1,i =e'(α -1 ). If the i-th bit data is not the error data, e'(x)=x i +x j , assuming that j represents the position of the error data in the received sequence, 0≤i≠j≤n-1, then S 1,i ·S -1,i ≠1. If the i-th bit data is the erroneous data, e'(x)=x i +x i =0, then S 1,i =S -1,i =0.

[0094] In practical applications, after adjusting the bit data at each position of the received sequence and obtaining the flip syndrome, if the flip syndrome values ​​are all 0, set e i =1, it is determined to flip the i-th bit data to get the flipped bit, so that the subsequent i =1 to perform error correction decoding on the received sequence.

[0095] Since the received sequence includes a plurality of binary bit data, the value of the i-th bit data is adjusted, that is, the value of the i-th bit data is flipped from 1 to 0, or from 0 to 1.

[0096] S204: If the values ​​of the flip syndromes are not all 0, determine whether the product of the two flip syndromes is 1. If the product of the two flip syndromes is 1, determine to flip the i-th bit data to obtain a flipped bit.

[0097] In an embodiment of the present application, when the presence of erroneous data in a received sequence is determined based on the initial syndrome, the value of one bit of data is adjusted each time to obtain a flip syndrome after adjusting the value of the bit of data until all the bit values ​​are adjusted. If the received sequence contains two erroneous data, even if one of the erroneous data is adjusted to correct data, the flip syndrome values ​​are still not all 0. In this case, whether the product of the two flip syndromes is 1 can be used to determine whether the number of erroneous data in the received sequence has decreased, for example, from 2 to 1, after adjusting the value of the one bit of data, thereby determining whether to flip the i-th bit of data. As long as the value of any flip syndrome is not 0, it is considered that the flip syndrome values ​​are still not all 0.

[0098] That is, if the values ​​of the flip syndromes are not all 0, it is determined whether the product of the two flip syndromes is 1. If the product of the two flip syndromes is 1, it is determined that the i-th bit data is flipped to obtain a flipped bit.

[0099] In the embodiment of the present application, the flip syndrome includes a first flip syndrome and a second flip syndrome. Therefore, if the values ​​of the flip syndromes are not both 0, determining whether the product of the two flip syndromes is 1 can be performed by determining whether the product of the first flip syndrome and the second flip syndrome is 1. If the product of the first flip syndrome and the second flip syndrome is 1, it is determined that the i-th bit data is flipped to obtain a flipped bit. The first flip syndrome and the second flip syndrome can be S respectively. 1.i =S1+α i ,S -1,i =S -1 +α -i, 0≤i≤n-1.

[0100] Specifically, when two errors occur in the received sequence, decoding begins bit by bit. If the i-th bit is not one of the error data, e'(x) = x i +x j +x l , 0≤i≠j≠l≤n-1, assuming (l,j) represents the position of two erroneous data in the received sequence, then S 1,i ·S -1,i ≠1. If the i-th bit data is one of the erroneous data, e'(x)=x i +x j +x i =x j , then S 1,i ·S -1,i =1.

[0101] In practical applications, after adjusting the bit data at each position of the received sequence and obtaining the flip syndrome, if the flip syndrome value is not 0, it means that there is erroneous data in the received sequence after adjusting the value of the i-th bit data, and then continue to determine whether the product of the first flip syndrome and the second flip syndrome is 1 to flip the bit data and obtain the flipped bit. 1,i ·S -1,i =1, 0≤i≤n-1, then set e i =1, indicating that the i-th bit data is flipped to obtain the flipped bit, otherwise set e i =0, so that the subsequent i =1 to perform error correction decoding on the received sequence.

[0102] S205: Decode the received sequence according to the flipped bits.

[0103] In the embodiment of the present application, when the received sequence r(x) is read out from the non-volatile memory, the initial syndromes S1, S -1 , if S1=S -1 =0, no decoding is performed, otherwise all i∈[0,n-1] bits of data are flip-decoded to obtain the flip syndrome S 1,i ,S -1,i , if S 1,i =S -1,i =0, then set e i =1, otherwise determine S 1,i ·S -1,i =1, if S 1,i ·S -1,i =1, then set e i =1, otherwise set e i=0, so we can get the wrong data and the wrong polynomial Finally, the codeword after error correction of the received sequence is obtained Decode output. Figure 5 As shown, by adopting the encoding and decoding method of the embodiment of the present application, the error probability when the receiving sequence reads data is greatly reduced.

[0104] In the embodiments of the present application, because whether the value of each bit of data is flipped is independent of each other, decoding can be performed in parallel. That is, the steps of adjusting the value of the i-th bit of data can be performed in parallel and simultaneously, and the results of whether the flip syndromes are all 0 and whether the product of the two flip syndromes is 1 can be obtained. For example, the steps of adjusting the value of the 0th bit of data, adjusting the value of the 1st bit of data, adjusting the value of the 2nd bit of data, and so on until the value of the n-1th bit of data is adjusted can be performed in parallel and simultaneously, which can greatly improve decoding efficiency and reduce decoding time.

[0105] It can be seen that the embodiment of the present application adopts g(x)=LCM{g1(x),g -1 (x)} as the generating polynomial, according to the syndrome S1=r(α), S -1 =r(α -1 ) to perform bit-by-bit decoding, ensuring effective double-error correction, comparable to the double-error-correcting BCH code. This avoids the exponential calculations required to decode finite field elements, reducing decoding complexity. Furthermore, because decoding can be performed in parallel, decoding efficiency is greatly improved and decoding time is reduced.

[0106] refer to Figure 4 The following is a schematic diagram of the decoding steps:

[0107] S301: Read the received sequence r(x) from the non-volatile memory.

[0108] S302: Obtain the initial syndrome S1, S of r(x) -1 .

[0109] S303: Determine whether an error is found in the read received sequence by checking whether the initial syndrome is 0. If the initial syndrome is 0, there is no error and the decoding is exited. Otherwise, an error occurs and the process goes to S304.

[0110] S304: Through S 1,i ,S -1,i Whether the i-th bit is wrong is determined by whether all are 0. 1,i ,S -1,i All are 0, 0≤i≤n-1, indicating that the i-th bit is wrong, set e i =1, go to S306, otherwise go to S305.

[0111] S305: Through S 1,i ·S -1,i Whether the i-th bit is 1 is used to determine whether it is an error. 1,i ·S -1,i =1, 0≤i≤n-1, set e i =1, otherwise set e i =0.

[0112] S306: Obtaining an error polynomial And codewords Decoded output.

[0113] As an example, the (31, 21) code is taken as an example to further illustrate the encoding and decoding methods provided in the embodiments of the present application.

[0114] In the (31,21) code, 31 is the length of the encoded codeword n ​​= 31 = 2 5 -1, 21 is the length of the information bit, 10 is the length of the check bit, and m≥5 is an odd number. Assume that α is a finite field GF(2 5 ) is a primitive element, and its primitive polynomial is g1(x)=x 5 +x 2 +1, the vector is represented as [1 0 0 1 0 1], and the inverse polynomial can be obtained by reversing the vector back and forth, that is, the inverse polynomial vector is represented as [1 0 1 0 0 1], then the inverse polynomial is g -1 (x) = x 5 +x 3 +1, through g(x)=LCM{g1(x),g -1 (x)}, we can get the generating polynomial of the (31,21) code as g(x)=x 10 +x 8 +x 7 +x 5 +x 3 +x 2 +1, the vector is represented as [10 1 1 0 1 0 1 1 0 1].

[0115] The (31,21) code uses a check polynomial for encoding. First, we get the check polynomial h(x) = x 31 -1 / g(x), then follow Figure 2 The encoding is performed in the following way: at the beginning, sw1 is turned on and sw2 is turned off, and the 21-bit information bit z is filled into the shift register and output at the same time. Then sw1 is turned off and sw2 is turned on, and the cyclic shift is performed 10 times, and a check bit s is obtained each time. i And output, we get the encoded codeword c(x).

[0116] The decoding adopts the bit-by-bit decoding method, flipping 1 bit of data at a time, and flipping in parallel. Assuming r(x) is the received sequence polynomial, e(x) is the error polynomial, and the initial syndrome S1, S of r(x) are obtained by lookup table. -1 First, according to x i modg1(x)(0≤i≤n), we get the finite field GF(2 5 ) are stored in a table. When obtaining the initial syndrome, the corresponding element vector is used for XOR operation, S1 = r(α) = r0·α 0 +r1·α 1 +r2·α 2 +…+r 30 α 30 S -1 =r(α -1 )=r0·α 0 +r1·α 30 +r2·α 29 +…+r 30 α 1 ,r0,…,r 30 are the coefficients of the r(x) receiving sequence polynomial, α 0 ,α 1 ,…,α 30 is a finite field GF(2 5 ) in the vector of elements, when r i =1(0≤i≤n-1), the multiplied α i Add the vectors.

[0117] Then, it is determined whether there is erroneous data according to the values ​​of the initial syndrome and the flip syndrome, and if there is erroneous data, the number and position of the erroneous data.

[0118] (1) When there is no error data, the initial syndrome S1 = S -1 =0, such as Figure 3 As shown in S303, exit decoding.

[0119] (2) When an error data appears, assuming that the error position is the second bit, that is, e(x) = x 2 , S1=α in S303 2 ≠0, execute the bit-by-bit decoding error correction process, when flipping the second bit data, flip the syndrome S 1,2 =α 2 +α 2 =0,S -1,2 =α -2 +α -2 =0 satisfies the condition S in S304 1,2 =S -1,2=0, so e2 = 1. When flipping other bits, flip the syndrome S 1,2 =α 2 +α i ,S -1,2 =α -2 +α -i , neither satisfies S304 1,i =S -1,i =0, and does not satisfy S in S305 1,i ·S -1,i =1, (0≤i≤n-1,i≠2) so e i = 0. Get the error polynomial Encoding codeword

[0120] (3) When two erroneous data appear, assuming that the error positions are at the 5th and 6th bits, that is, e(x) = x 5 +x 6 , S1≠0 in S303, execute the bit-by-bit decoding error correction process, no matter which bit data is flipped, it does not satisfy the flip syndrome S in S304 1,i =S -1,i =0(0≤i≤31), when the 5th bit data and the 6th bit data are flipped, S 1,5 =α 5 +α 6 +α 5 =α 6 ,S -1,5 =α -5 +α -6 +α -5 =α -6 , meeting the S in S305 1,5 ·S -1,5 =1, so e5=1, S 1,6 =α 5 +α 6 +α 6 =α 5 ,S -1,6 =α -5 +α -6 +α -6 =α -5 , meeting the S in S305 1,6 ·S -1,6 =1, e6=1. When other bits are flipped, S 1,j =α 5 +α 6 +α j ,S -1,j =α -5 +α -6 +α -j , neither satisfies S3041,j =S -1,j =0, and does not satisfy S in S305 1,j ·S -1,j =1, (0≤j≤n-1,j≠5,6) so e j = 0. Get the error polynomial Encoding codeword

[0121] From the above, we can get the encoding codeword Retaining z'(x) yields the information bit.

[0122] (26,16) code is a shortened code, which is shortened from (31,21) code to (26,16) code. Let the right side be the high bit, and add zeros to the high bit of the information bit to a length of 21. Then use the (31,21) code encoding method to encode it. When the code word is obtained, the zeros added to the high bit are removed to obtain the corresponding shortened code word. The shortening process refers to Figure 6 As shown:

[0123] S401 represents information bits. S402 represents a sequence of information bits with zeros added to the upper bits. S403 represents a codeword obtained by encoding the zero-added sequence. S404 represents a codeword after removing the zeros added to the upper bits.

[0124] The decoding process is consistent with the (31,21) code. The 26-bit received sequence read from the non-volatile memory is decoded bit by bit, and the high bits do not need to be padded with zeros.

[0125] The present application provides a decoding method for a non-volatile memory, comprising: reading a received sequence from the non-volatile memory, obtaining an initial syndrome of the received sequence, the received sequence comprising n binary bits of data, determining whether the value of the initial syndrome is 0, and if the value of the initial syndrome is not 0, determining that the received sequence contains an error. Specifically, the method utilizes the initial syndrome to determine whether the received sequence read from the non-volatile memory contains an error, which is simple and intuitive. Upon determining that the read received sequence contains an error, a decoding error correction process is initiated, wherein the value of the i-th bit of data is adjusted, two flip syndromes of the received sequence after adjusting the value of the i-th bit of data are obtained, and determining whether the values ​​of the flip syndromes are both 0. If the values ​​of the flip syndromes are both 0, determining to flip the i-th bit of data to obtain a flipped bit position; 0≤i≤n-1. If the values ​​of the flip syndromes are not both 0, determining whether the product of the two flip syndromes is 1. If the product of the two flip syndromes is 1, determining to flip the i-th bit of data to obtain a flipped bit position; 0≤i≤n-1. That is to say, by adjusting the value of the bit data at each position in the received sequence, it is determined whether the bit data at that position is erroneous when reading according to the value of the flipped companion formula after adjustment. If an error occurs, the received sequence is decoded according to the flipped bit position. In addition, the encoding codeword is obtained by encoding the information bit using a generating polynomial. The generating polynomial is composed of a primitive polynomial and a reverse polynomial of a finite field primitive element. The encoding codeword is stored in a non-volatile memory. During the data storage or reading process, the encoding codeword is superimposed on the erroneous data to form a received sequence. It can be seen that the present application can perform bit-by-bit decoding based on the flipped companion formula, avoiding the complex calculations when decoding using the BCH code, greatly reducing the decoding difficulty, improving the decoding efficiency, and reducing the decoding time.

[0126] Based on the encoding method of the non-volatile memory provided in the above embodiment, the embodiment of the present application also provides an encoding device of the non-volatile memory, referring to Figure 7 FIG. 1 is a schematic diagram of a structure of a coding device for a non-volatile memory provided in an embodiment of the present application. The coding device 100 for a non-volatile memory provided in an embodiment of the present application includes:

[0127] An acquisition unit 110, configured to acquire information bits;

[0128] The configuration unit 120 is configured to configure the length of the check bit and the finite field GF(2 m ) in the primitive polynomial and the reverse polynomial of the primitive element, the length of the check bit is 2m;

[0129] The encoding unit 130 is used to encode the information bits using a generating polynomial to obtain an encoded codeword, and store the encoded codeword in a non-volatile memory; the generating polynomial is composed of the primitive polynomial and the inverse polynomial.

[0130] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is a finite field GF(2 m ), the inverse polynomial is the inverse polynomial of the minimum polynomial.

[0131] Optionally, m is an odd number greater than or equal to 5.

[0132] Based on the decoding method of the non-volatile memory provided in the above embodiment, the embodiment of the present application also provides a decoding device of the non-volatile memory, referring to Figure 8 FIG2 is a schematic diagram of a decoding device for a non-volatile memory according to an embodiment of the present application. The decoding device 200 for a non-volatile memory according to an embodiment of the present application includes:

[0133] A reading unit 210 is configured to read a received sequence from a non-volatile memory and obtain an initial syndrome of the received sequence, wherein the received sequence includes n binary bits of data; the non-volatile memory stores a coding codeword, and during data storage or reading, the coding codeword is superimposed with error data to form a received sequence; and the coding codeword is obtained by encoding information bits using a generating polynomial, wherein the generating polynomial is composed of a primitive polynomial of a finite field primitive element and its inverse polynomial.

[0134] a first determining unit 220, configured to determine whether the value of the initial syndrome is 0; if the value of the initial syndrome is not 0, an error exists in the received sequence;

[0135] The second determining unit 230 is configured to adjust the value of the i-th bit data respectively, obtain two flip syndromes of the received sequence after the value of the i-th bit data is adjusted, determine whether the values ​​of the flip syndromes are both 0, and if the values ​​of the flip syndromes are both 0, determine to flip the i-th bit data to obtain a flipped bit position; 0≤i≤n-1;

[0136] a third determining unit 240, configured to, if the values ​​of the flip syndromes are not both 0, determine whether a product of two flip syndromes is 1; and if the product of the two flip syndromes is 1, determine to flip the i-th bit of data to obtain a flipped bit;

[0137] The decoding unit 250 is configured to decode the received sequence according to the flipped bits.

[0138] Optionally, the apparatus further includes a parallel and simultaneous execution unit, wherein the parallel and simultaneous execution unit is configured to:

[0139] The steps of adjusting the value of the i-th bit data are performed in parallel and simultaneously, and the results of adjusting the values ​​of different bit data, whether the flip syndromes are all 0, and whether the product of two flip syndromes is 1 are obtained.

[0140] Optionally, the two flip accompanying formulas include a first flip accompanying formula and a second flip accompanying formula;

[0141] The third determining unit 240 is configured to:

[0142] If the values ​​of the first flip syndrome and the second flip syndrome are not both 0, it is determined whether a product of the first flip syndrome and the second flip syndrome is 1; if the product of the first flip syndrome and the second flip syndrome is 1, it is determined that the i-th bit of data is flipped to obtain a flipped bit.

[0143] Optionally, the initial syndrome is a polynomial equation corresponding to the received sequence and the coefficients of the finite field GF(2 m ) is obtained by performing an XOR operation on the elements in the received sequence, and the length of the received sequence is n=2 m -1.

[0144] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is a finite field GF(2 m ), the inverse polynomial is the inverse polynomial of the minimum polynomial.

[0145] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0146] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A decoding method for a non-volatile memory, characterized in that: include: Reading a receiving sequence from a non-volatile memory to obtain an initial syndrome of the receiving sequence, wherein the receiving sequence includes n binary bit data; The non-volatile memory stores a coded codeword, and during the data storage or reading process, the coded codeword is superimposed with the error data to form a receiving sequence; the coded codeword is obtained by encoding the information bit using a generating polynomial, and the generating polynomial is composed of a primitive polynomial of a finite field primitive element and its inverse polynomial; Determining whether the value of the initial syndrome is 0, if the value of the initial syndrome is not 0, then there is an error in the received sequence; respectively adjusting the value of the i-th bit data, 0≤i≤n-1; obtaining two flip syndromes of the received sequence after adjusting the value of the i-th bit data, and determining whether the values ​​of the flip syndromes are both 0, and if the values ​​of the flip syndromes are both 0, determining to flip the i-th bit data to obtain a flipped bit; If the values ​​of the flip syndromes are not all 0, determine whether the product of the two flip syndromes is 1; if the product of the two flip syndromes is 1, determine to flip the i-th bit data to obtain a flipped bit; The received sequence is decoded according to the flipped bits.

2. The method according to claim 1, characterized in that: The method further comprises: The steps of adjusting the value of the i-th bit data are performed in parallel and simultaneously; and the results of adjusting the values ​​of different bit data, whether the flip syndromes are all 0, and whether the product of two flip syndromes is 1 are obtained at the same time.

3. The method according to claim 1, characterized in that The two flip accompanying formulas include a first flip accompanying formula and a second flip accompanying formula; If the values ​​of the flip syndromes are not all 0, determining whether the product of two flip syndromes is 1, and if the product of the two flip syndromes is 1, determining to flip the i-th bit of data comprises: If the values ​​of the first flip syndrome and the second flip syndrome are not both 0, determine whether the product of the first flip syndrome and the second flip syndrome is 1; if the product of the first flip syndrome and the second flip syndrome is 1, determine to flip the i-th bit data.

4. The method according to claim 1, characterized in that The initial syndrome is a polynomial corresponding to the received sequence and its coefficients in the finite field GF(2 m ) is obtained by performing an XOR operation on the elements in the received sequence, and the length of the received sequence is n=2 m -1.

5. The method according to claim 1, characterized in that The generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is a finite field GF(2 m ), and the inverse polynomial is the inverse polynomial of the minimum polynomial.

6. A coding method for a non-volatile memory, characterized in that: include: Get information bits; The length of the check bit and the finite field GF(2 m ) in the primitive polynomial and the inverse polynomial of the primitive element, the length of the check bit is 2m; Encoding the information bit using a generating polynomial to obtain an encoded codeword, and storing the encoded codeword in a non-volatile memory; The generator polynomial is composed of the primitive polynomial and the inverse polynomial.

7. The method according to claim 6, characterized in that The generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is a finite field GF(2 m ), and the inverse polynomial is the inverse polynomial of the minimum polynomial.

8. The method according to claim 6, characterized in that m is an odd number greater than or equal to 5.

9. A decoding device for a non-volatile memory, characterized in that: include: A reading unit is used to read a receiving sequence from a non-volatile memory to obtain an initial syndrome of the receiving sequence, wherein the receiving sequence includes n binary bit data; the non-volatile memory stores a coding codeword, and during the data storage or reading process, the coding codeword is superimposed with the error data to form a receiving sequence; the information bit is encoded using a generating polynomial to obtain the coding codeword, wherein the generating polynomial is composed of a primitive polynomial of a finite field primitive element and its inverse polynomial; a first determining unit, configured to determine whether the value of the initial syndrome is 0, and if the value of the initial syndrome is not 0, an error exists in the received sequence; a second determining unit, configured to respectively adjust the value of the i-th bit data, obtain two flip syndromes of the received sequence after the value of the i-th bit data is adjusted, determine whether the values ​​of the flip syndromes are both 0, and if the values ​​of the flip syndromes are both 0, determine to flip the i-th bit data to obtain a flipped bit position, 0≤i≤n-1; a third determining unit, configured to determine whether the product of two flip syndromes is 1 if the values ​​of the flip syndromes are not all 0, and if the product of the two flip syndromes is 1, determine to flip the i-th bit data to obtain a flipped bit, 0≤i≤n-1; A decoding unit is used to decode the received sequence according to the flipped bit.

10. A coding device for a non-volatile memory, characterized in that: include: An acquisition unit, used for acquiring information bits; A configuration unit is used to configure the length of the check bit and the finite field GF(2 m ) in the primitive polynomial and the inverse polynomial of the primitive element, the length of the check bit is 2m; An encoding unit, used for encoding the information bit using a generating polynomial to obtain an encoding codeword, and storing the encoding codeword in a non-volatile memory; The generator polynomial is composed of the primitive polynomial and the inverse polynomial.

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