Error Correction In-Memory Computing System, Method and Device Based on Dynamic Instantiation

Abstract

The present invention provides an error correction in-memory computing system, method and device based on dynamic instantiation, belonging to the technical field of in-memory computing. The system includes an in-memory computing input module, an error correction in-memory computing module, and an in-memory computing output module. The in-memory computing input module is used to divide the feature values and generate parity check bits. In the error correction in-memory computing module, the on-chip radiation-hardened MRAM cells send the weights to the instantiated in-memory computing units for in-memory computing with the feature values, and the calculation results are sent to the result decision unit. If the parity check is correct, the results are output; if the parity check is incorrect, new instantiated in-memory computing units are added to output the correct results. The in-memory computing output module is used to receive the output results of the error correction in-memory computing module to obtain output feature values. The present invention supports the flexible dynamic instantiation of in-memory computing units, instantiates or releases hardware resources according to the calculation results, and enhances the flexibility and system performance of the in-memory computing system.

Description

Technical Field

[0001] The present invention relates to the technical field of in-memory computing, and specifically, to an error-correcting in-memory computing system, method, and device based on dynamic instantiation. Background Art

[0002] With the rapid development of space technology, on-board computing systems are facing increasingly complex computing requirements. Especially in tasks such as image processing and navigation positioning, on-board computing systems are required to have high processing capabilities and reliability. However, due to the frequent transfer of data between the memory and the processor in the traditional von Neumann architecture, data bottleneck problems occur, limiting the performance improvement of on-board computing systems. In addition, the radiation effects and space electromagnetic interference in the space environment pose severe challenges to the reliability of electronic devices. How to ensure the high reliability of the computing system has become an important issue in space electronics design.

[0003] In recent years, in-memory computing technology has gradually become an effective way to solve the bottlenecks of computing performance and energy efficiency. In-memory computing integrates storage and computing functions into the same hardware unit, improves computing efficiency and reduces energy consumption by reducing data transfer, and is suitable for space applications with strict limitations on energy efficiency and volume. The in-memory computing architecture directly executes computing tasks such as matrix multiplication in the memory, greatly reducing the data movement overhead and improving the parallel processing ability. However, due to the harsh conditions of the space environment and the long-term operation requirements of on-board computing systems, traditional in-memory computing architectures face many challenges in radiation resistance, fault tolerance, etc., and cannot fully meet the requirements of high reliability.

[0004] In on-board computing systems, problems such as radiation effects and hardware aging cause permanent or temporary errors in computing units. To ensure the stable operation of the system, traditional error correction methods mainly rely on redundant hardware design (such as triple modular redundancy), and detect and repair errors by comparing the output results of multiple identical computing units. However, this static redundancy method increases the complexity and power consumption of the hardware, resulting in waste of hardware resources and insufficient system flexibility. Summary of the Invention

[0005] Aiming at the defects in the prior art, the purpose of the present invention is to provide an error-correcting in-memory computing system, method, and device based on dynamic instantiation.

[0006] An error-correcting in-memory computing system based on dynamic instantiation according to the present invention includes: an in-memory computing input module, an error-correcting in-memory computing module, and an in-memory computing output module;

[0007] The in-memory computing input module is used to divide the eigenvalue and generate parity check bits, and send them to the error-correcting in-memory computing module;

[0008] The error correction in-memory computing module performs in-memory computing on the eigenvalues, performs parity check on the calculation results, outputs the correct results according to the check results, and sends the results to the in-memory computing output module;

[0009] The in-memory computing output module is used to receive the output results of the error correction in-memory computing module to obtain the output eigenvalues.

[0010] Preferably, a parity check generation unit is provided in the in-memory computing input module to generate parity check bits.

[0011] Preferably, the error correction in-memory computing module includes an on-chip radiation-hardened MRAM unit, an instantiated in-memory computing unit, and a result judgment unit;

[0012] The on-chip radiation-hardened MRAM unit sends the weights to the instantiated in-memory computing unit, performs in-memory computing with the eigenvalues, and sends the calculation results to the result judgment unit. If the parity check is correct, the results are output. If the parity check is incorrect, a new instantiated in-memory computing unit is added to output the correct results.

[0013] Preferably, the result judgment unit performs parity check according to the parity check bits from the in-memory computing input module, the parity check bits of the instantiated in-memory computing unit, and the parity values of the number of groups of eigenvalues and weights to determine whether the current calculation result is correct. If the calculation result is correct, the result is sent to the in-memory computing output module; if the calculation result is incorrect, a new instantiated in-memory computing unit is instantiated to recalculate, and the calculation results are sent to the in-memory computing output module.

[0014] Preferably, the on-chip radiation-hardened MRAM unit is used to store neural network weight parameters.

[0015] Preferably, the instantiated in-memory computing unit and the to-be-instantiated in-memory computing unit have the same hardware structure for performing in-memory computing.

[0016] Preferably, the result judgment unit is provided with a parity check unit and a parity check generation unit for performing parity check.

[0017] According to an error correction in-memory computing method based on dynamic instantiation provided by the present invention, it includes:

[0018] Step S1: Send the same neural network weight parameters from the on-chip radiation-hardened MRAM unit to the instantiated in-memory computing units #0 and #1;

[0019] Step S2: Send the input eigenvalue to the in-memory computing input module, generate parity check bits through the parity check generation unit, split the input eigenvalue into output eigenvalues #0 and #1, and send the output eigenvalues #0, #1, and the parity check bits to the error correction in-memory computing module;

[0020] Step S3: Instantiate in-memory computing units #0 and #1 to receive the eigenvalues from the in-memory computing input module and the weights of the on-chip radiation-hardened MRAM units, obtain the calculation results and send them to the result decision unit. The result decision unit performs parity check based on the parity check bits from the in-memory computing input module, the parity check bits of instantiated in-memory computing units #0 and #1, and the parity value of the number of (1,0) groups of eigenvalues and weights to determine whether the current calculation result is correct;

[0021] Step S4: If the calculation result is correct, send the result to the in-memory computing output module; if the calculation result is incorrect, instantiate a new said to-be-instantiated in-memory computing unit #2 to recalculate and send the calculation result to the in-memory computing output module.

[0022] An error correction in-memory computing device based on dynamic instantiation provided by the present invention includes a processor and a memory. Executable program instructions are stored in the memory. When the processor calls the program instructions in the memory, the processor is used for the steps of the error correction in-memory computing method based on dynamic instantiation.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] An error correction in-memory computing system and method based on dynamic instantiation provided by the present invention support the flexible and dynamic instantiation of in-memory computing units, instantiate or release hardware resources according to the calculation results, and enhance the flexibility and system performance of the in-memory computing system. Compared with traditional methods, this system significantly improves the computing power and radiation resistance of the spaceborne computing system, ensuring long-term stable operation in a complex space environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By reading the detailed description of the non-restrictive embodiments with reference to the following drawings, other features, objectives, and advantages of the present invention will become more obvious:

[0026] Figure 1 It is a schematic structural diagram of an error correction in-memory computing system based on dynamic instantiation provided by the present invention;

[0027] Figure 2 It is a schematic structural diagram of the in-memory computing input module provided by the present invention;

[0028] Figure 3 It is a schematic structural diagram of the result decision unit in the error correction in-memory computing module provided by the present invention;

[0029] Figure 4 It is a schematic flowchart of an error-correcting in-memory computing method based on dynamic instantiation provided by the present invention.

[0030] Explanation of reference numerals:

[0031] In-memory computing input module 101, error-correcting in-memory computing module 102, in-memory computing output module 103, on-chip radiation-hardened MRAM cell 1021, instantiated in-memory computing unit 1022, to-be-instantiated in-memory computing unit 1023, result decision unit 1024. Detailed implementation manners

[0032] The present invention will be described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several changes and improvements can still be made. These all belong to the protection scope of the present invention.

[0033] Figure 1 It is a schematic structural diagram of an error-correcting in-memory computing system based on dynamic instantiation provided by the present invention, as Figure 1 shown, the present invention provides an error-correcting in-memory computing system based on dynamic instantiation, including an in-memory computing input module 101, an error-correcting in-memory computing module 102, and an in-memory computing output module 103, wherein:

[0034] The in-memory computing input module 101 is used to divide the eigenvalue and generate parity check bits, and send them to the error-correcting in-memory computing module 102.

[0035] First, the eigenvalue is split according to its bits. For example, an 8-bit eigenvalue is split into 8 1-bit binary numbers. Secondly, count the number of 1s in these bits. If the number of 1s is odd, the parity check bit is 1; if it is even, the parity check bit is 0.

[0036] In the present invention, the in-memory computing input module 101 is provided with a parity check generation unit for generating parity check bits.

[0037] In the error-correcting in-memory computing module 102, the on-chip radiation-hardened MRAM cell 1021 sends the weight to the instantiated in-memory computing unit 1022, performs in-memory computing with the eigenvalue, and sends the calculation result to the result decision unit 1024. If the parity check is correct, the result is output. If the parity check is incorrect, a new to-be-instantiated in-memory computing unit 1023 is instantiated to recalculate, and the calculation result is sent to the in-memory computing output module 103.

[0038] The parity check bit of the input eigenvalue only reflects the number of 1s in the eigenvalue and cannot directly reflect the number of 1s in the result after multiplying the eigenvalue by the weight. According to Figure 3 the analysis of the table in

[0039] : When the eigenvalue is 0, regardless of the value of the weight, the multiplication result is 0 and will not cause a parity check failure; when the eigenvalue is 1 and the weight is 1, the multiplication result is 1 and will not cause a parity check failure; when the eigenvalue is 1 and the weight is 0, the multiplication result is 0, and at this time, the parity check result of the eigenvalue and the parity check result of the multiplication result will be inconsistent. To solve this problem, on the basis of the eigenvalue parity check, a correction term is added, that is, the parity check bit in the case where the eigenvalue is 1 and the weight is 0 is counted, and it is XOR-operated with the parity check bit of the eigenvalue to obtain a new parity check bit. This new parity check bit can accurately reflect the parity of the multiplication result. Finally, by comparing with the parity check bit of the true multiplication result, it can be judged whether an error occurs in the calculation process.

[0040] In the present invention, the on-chip radiation-hardened MRAM unit 1021 is used to store neural network weight parameters.

[0041] In the present invention, the instantiated in-memory computing unit 1022 and the to-be-instantiated in-memory computing unit 1023 are set with the same hardware structure and are used for in-memory computing.

[0042] The in-memory computing output module 103 is used to receive the output result of the error-corrected in-memory computing module 102 to obtain the output eigenvalue.

[0043] A dynamic instantiation-based error-corrected in-memory computing system and method provided by the present invention support the flexible dynamic instantiation of in-memory computing units, instantiate or release hardware resources according to the calculation results, and enhance the flexibility and system performance of the in-memory computing system.

[0044] In the present invention, Figure 2 is a schematic structural diagram of the in-memory computing input module 101 provided by the present invention. As Figure 2 shown, the present invention sends the input eigenvalue to the in-memory computing input module 101, generates a parity check bit through a parity check generation unit, and splits the input eigenvalue into output eigenvalues #0 and #1, and sends the output eigenvalues #0, #1 and the parity check bit to the error-corrected in-memory computing module 102.

[0045] In the present invention, Figure 3 is a schematic structural diagram of the result judgment unit in the error-corrected in-memory computing module provided by the present invention. As Figure 3As shown, the instantiated in-memory computing units 1022 #0 and #1 receive the eigenvalue from the in-memory computing input module 101 and the weight of the on-chip radiation-hardened MRAM unit 1021, obtain the calculation result and send it to the result decision unit 1024. The result decision unit 1024 performs parity check according to the parity check bit from the in-memory computing input module 101, the parity check bits of the instantiated in-memory computing units 1022 #0 and #1, and the parity value of the number of (1,0) groups of the eigenvalue and the weight, to determine whether the current calculation result is correct. If the calculation result is correct, the result is sent to the in-memory computing output module 103; if the calculation result is incorrect, a new to-be-instantiated in-memory computing unit 1023 #2 is instantiated to recalculate, and the calculation result is sent to the in-memory computing output module 103.

[0046] In the present invention, the reasons for the establishment of the decision basis of the result decision unit 1024 are as follows: ① The probability of bit flipping caused by space radiation is not high, and the probability of multiple-bit flipping occurring at the same time is extremely low; ② The parity check bit of the eigenvalue cannot correspond to the parity check bit of the in-memory computing result. The reason is that there is a parity flip problem in the calculation result when the eigenvalue is 1 and the weight is 0. Therefore, by adding the parity value of the number of (1,0) groups where the eigenvalue is 1 and the weight is 0 to the parity check bit of the eigenvalue, a new parity check bit can be obtained, and compared with the parity check bit of the calculation result to determine whether the calculation result is correct.

[0047] Figure 4 It is a flowchart of a dynamic instantiation-based error-correcting in-memory computing method provided by the present invention, as Figure 4 As shown, the present invention provides dynamic instantiation-based error-correcting in-memory computing, including:

[0048] Step S1, sending the same neural network weight parameter from the on-chip radiation-hardened MRAM unit to the instantiated in-memory computing units #0 and #1;

[0049] Step S2, sending the input eigenvalue to the in-memory computing input module, generating a parity check bit through the parity check generation unit, splitting the input eigenvalue into output eigenvalues #0 and #1, and sending the output eigenvalues #0, #1 and the parity check bit to the error-correcting in-memory computing module;

[0050] Step S3, the instantiated in-memory computing units #0 and #1 receive the eigenvalue from the in-memory computing input module and the weight of the on-chip radiation-hardened MRAM unit, obtain the calculation result and send it to the result judgment unit. The result judgment unit performs parity check based on the parity check bit from the in-memory computing input module, the parity check bits of the instantiated in-memory computing units #0 and #1, and the parity value of the number of (1,0) groups of the eigenvalue and the weight, to determine whether the current calculation result is correct;

[0051] Step S4, if the calculation result is correct, send the result to the in-memory computing output module; if the calculation result is incorrect, instantiate a new said to-be-instantiated in-memory computing unit #2 to recalculate, and send the calculation result to the in-memory computing output module.

[0052] The present invention also provides an error-correcting in-memory computing device based on dynamic instantiation, including: a processor and a memory. The memory stores executable program instructions. When the processor calls the program instructions in the memory, the processor is used to execute the steps of the error-correcting in-memory computing method based on dynamic instantiation as described above.

[0053] The present invention also provides a computer-readable storage medium for storing a program, and when the program is executed, it implements the steps of the error-correcting in-memory computing method based on dynamic instantiation as described above.

[0054] It should be noted that those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuit", "module" or "platform" here.

[0055] In addition, the embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions. When at least one processor of the user device executes the computer-executable instructions, the user device executes the above various possible methods. Among them, the computer-readable medium includes a computer storage medium and a communication medium. The communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in the user device. Of course, the processor and the storage medium can also exist as discrete components in the communication device.

[0056] The present application also provides a program product, which includes a computer program stored in a readable storage medium. At least one processor of the server can read the computer program from the readable storage medium, and the execution of the computer program by at least one processor enables the server to implement the method according to any one of the above embodiments of the present invention.

[0057] The program product may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, but not be limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0058] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. An in-memory computing system with error correction based on dynamic instantiation, characterized in that: include: An in-memory calculation input module (101), an error correction in-memory calculation module (102), and an in-memory calculation output module (103); The in-memory calculation input module (101) is used to divide the characteristic values and generate parity check bits, and send them to the error correction in-memory calculation module (102); The error correction in-memory calculation module (102) performs in-memory calculation on the characteristic value, performs parity check on the calculation result, outputs a correct result according to the check result, and sends the result to the in-memory calculation output module (103); The in-memory calculation output module (103) is used to receive the output result of the error correction in-memory calculation module (102) to obtain an output characteristic value; The error correction in-memory computing module (102) comprises an on-chip radiation-resistant MRAM unit (1021), an instantiated in-memory computing unit (1022), an in-memory computing unit to be instantiated (1023), and a result judgment unit (1024); The on-chip radiation-resistant MRAM unit (1021) sends the weight to the instantiated in-memory calculation unit (1022), performs in-memory calculation with the eigenvalue, and sends the calculation result to the result judgment unit (1024). If the parity check is correct, the result is output; if the parity check is incorrect, a new in-memory calculation unit to be instantiated is added to output the correct result; The result judgment unit (1024) performs parity check based on the parity check bits from the in-memory calculation input module (101), the parity check bits of the instantiated in-memory calculation unit (1022), the eigenvalues and the parity values of the (1,0) groups of weights to determine whether the current calculation result is correct. If the calculation result is correct, the result is sent to the in-memory calculation output module (103); if the calculation result is incorrect, a new in-memory calculation unit to be instantiated (1023) is instantiated to recalculate and the calculation result is sent to the in-memory calculation output module (103).

2. The in-memory computing system based on dynamic instantiation of an error correction according to claim 1, characterized in that: A parity check generating unit is provided in the in-memory calculation input module (101) for generating parity check bits.

3. The in-memory computing system based on dynamic instantiation of an error correction according to claim 1, characterized in that: The on-chip radiation-resistant MRAM unit (1021) is used to store neural network weight parameters.

4. The in-memory computing system based on dynamic instantiation of an error correction according to claim 1, characterized in that: The instantiated in-memory computing unit (1022) and the in-memory computing unit to be instantiated (1023) are configured with the same hardware structure for performing in-memory computing.

5. The in-memory computing system based on dynamic instantiation of error correction according to claim 1, characterized in that: The result judgment unit (1024) is provided with a parity check unit and a parity check generation unit for performing parity check.

6. A method for in-memory error correction calculation based on dynamic instantiation, based on the in-memory error correction calculation system based on dynamic instantiation according to any one of claims 1 to 5, characterized in that: include: Step S1: sending the same neural network weight parameters from the on-chip radiation-resistant MRAM unit (1021) to the instantiated in-memory computing units (1022) #0 and #1; Step S2: sending the input eigenvalue to the in-memory calculation input module (101), generating parity bits through the parity generation unit, splitting the input eigenvalue into output eigenvalues #0 and #1, and sending the output eigenvalues #0, #1 and the parity bits to the error correction in-memory calculation module (102); Step S3: the instantiated in-memory computing units (1022) #0 and #1 receive the characteristic values from the in-memory computing input module (101) and the weights of the on-chip radiation-resistant MRAM unit (1021), obtain the calculation results and send them to the result judgment unit (1024), and the result judgment unit (1024) performs parity check based on the parity check bits from the in-memory computing input module (101), the parity check bits of the instantiated in-memory computing units (1022) #0 and #1, the characteristic values and the parity values of the (1,0) groups of the weights to determine whether the current calculation result is correct; Step S4: If the calculation result is correct, the result is sent to the in-memory calculation output module (103); if the calculation result is incorrect, a new in-memory calculation unit to be instantiated is instantiated to recalculate and the calculation result is sent to the in-memory calculation output module (103).

7. An in-memory computing device for error correction based on dynamic instantiation, comprising a processor and a memory, wherein the memory stores executable program instructions, and when the processor calls the program instructions in the memory, the processor is used to execute the steps of the in-memory computing method for error correction based on dynamic instantiation described in claim 6.

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