Heterogeneous dual-core processor system of power electronic equipment and power electronic equipment

Abstract

The invention provides a heterogeneous dual-core processor system of power electronic equipment and the power electronic equipment. The system comprises a main processor, and a coprocessor, a universal peripheral subsystem, a special peripheral subsystem, a special acceleration subsystem, an interrupt subsystem and a storage subsystem which communicate with the main processor through a bus. The heterogeneous dual-core special processor system architecture of the main processor and the coprocessor is constructed, the main processor is used for executing a high-real-time and high-reliability control algorithm, and a special peripheral subsystem is expanded through a standard bus to meet the requirements of control-intensive applications such as high switching frequency and a multi-level topological structure; acceleration control based on hardware is achieved through the special acceleration subsystem, the coprocessor is used for executing a calculation-intensive edge intelligence algorithm, and the calculation-intensive application requirements of power electronic equipment for edge intelligence calculation such as fault prediction and health management in the future are met.

Description

Technical Field

[0001] The present disclosure relates to the field of industrial control technology, and in particular to a heterogeneous dual-core processor system of a power electronic device and a power electronic device. Background Art

[0002] With the rapid development of the global economy and the continuous advancement of science and technology, the demand for highly reliable, high-quality and controllable electric energy in many fields such as smart grid, rail transportation, new energy vehicles, distributed new energy and military equipment is becoming increasingly urgent. As the core equipment of energy conversion, power electronic equipment is widely valued by various countries. Its reliability, automation and intelligence level will have an important impact on the safe and stable operation and intelligence level of the entire power grid system. Therefore, it is of great significance to carry out research on the key technologies of power electronic equipment.

[0003] The next generation of wide bandgap power semiconductor devices represented by SiC (silicon carbide) and GaN (gallium nitride) have the advantages of high voltage tolerance, high junction temperature stability and high reliability, and will become an important development direction for future power electronic devices. Compared with silicon-based power semiconductor devices, wide bandgap power semiconductor devices improve power quality by increasing the switching frequency by more than ten times. The deployment of control-intensive applications such as new topologies, high-precision control algorithms and high switching frequencies brought by wide bandgap power semiconductors in power electronic devices places higher requirements on the control performance of core processors. In addition, the application of edge intelligent algorithms in power electronic devices also places higher requirements on the computing efficiency of core processor computing-intensive applications. It is difficult to meet the requirements of control-intensive applications such as multi-level topologies, high-performance control algorithms and high switching frequencies brought by future wide bandgap power semiconductors through simple selection and hardware stacking of existing processors, and it is also difficult to meet the requirements of computing-intensive applications such as edge intelligent computing. Therefore, the core processor has become an important factor restricting the deployment of control-intensive applications and edge intelligent computing capabilities of future power electronic devices. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a heterogeneous dual-core processor system of a power electronic device and a power electronic device, so as to solve the problems existing in the prior art.

[0005] The embodiment of the present disclosure adopts the following technical scheme: a heterogeneous dual-core processor system of a power electronic device, comprising at least: a main processor and a coprocessor communicating with the main processor through a bus, a general peripheral subsystem, a dedicated peripheral subsystem, a dedicated acceleration subsystem, an interrupt subsystem and a storage subsystem; wherein the main processor is designed and implemented based on the RISCV instruction set, and is configured to execute a complete control process of the power electronic device; the coprocessor is configured to perform edge computing on the data transmitted by the main processor, and feed back the computing results to the main processor; the general peripheral subsystem is configured to realize data communication between the main processor and a general external device; the dedicated peripheral subsystem is configured to generate a multi-channel control pulse signal of a multi-level topology device according to the control requirements of the main processor for the multi-level topology device; the dedicated acceleration subsystem is configured to perform accelerated computing on the input data according to the control algorithm selected by the main processor; and the interrupt subsystem is configured to process interrupt requests.

[0006] In some embodiments, the coprocessor at least includes: a pre-fetch and write-back module, an intermediate memory, a first data movement and formatting module, a first-in-first-out queue, a processing unit array, and a second data movement and formatting module; wherein the pre-fetch and write-back module communicates with the main processor through a bus interface, obtains data to be processed, and sends it to the intermediate memory, the intermediate memory sends the data to the first data movement and formatting module, the first data movement and formatting module sends the data to the first-in-first-out queue, the first-in-first-out queue inputs the data into the processing unit corresponding to the current operation type in the processing unit array, and the current processing unit completes the calculation and sends the calculation result to the right or downward. The first data movement and formatting module determines whether the edge computing is completed according to the iterative computing result. If it is completed, the iterative computing result is written into the intermediate memory. The pre-fetch and write-back module writes the computing result in the intermediate memory back to the main processor. If the edge computing is not completed, the first data movement and formatting module writes the iterative computing result into the second data movement and formatting module. The second data movement and formatting module writes the iterative computing result into the processing unit array to complete the next round of iterative computing until the first data movement and formatting module determines that the edge computing is completed.

[0007] In some embodiments, the operation types include at least: element-by-element operation, activation operation, RNN activation operation, normalization operation, pooling operation and pulsation operation.

[0008] In some embodiments, the dedicated peripheral subsystem includes at least: a PWM pulse generation module, an ADC pulse generation module, and a QEP pulse generation module.

[0009] In some embodiments, the PWM pulse generation module includes at least: a time base unit, which is used to generate the basic time reference and control logic required for the PWM pulse; a counting and comparing unit, which is used to start the counter according to the configuration of the time base unit, and generate the state signal of the current counter according to the period register, comparison value register and comparison logic register set by the kernel; an action unit, which is used to generate multiple PWM pulse signals according to the state signal and the basic time reference; a dead zone control unit, which is used to perform dead zone control on the multiple PWM pulse signals; an error control unit, which is used to monitor whether the pulse signal output outside the dedicated peripheral subsystem needs to be urgently blocked, and if no emergency blocking is required, the multiple PWM pulse signals are output to the multi-level topology device through the general input and output interface; an event triggering unit, which is used to generate an interrupt request according to the current state of the time base unit, the counting and comparing unit and the action unit.

[0010] In some embodiments, the multiple PWM pulse signals are 8-channel PWM pulse signals.

[0011] In some embodiments, the control algorithm includes at least: a vector control algorithm, a PID control algorithm, an adaptive control algorithm, a fuzzy logic control algorithm, a predictive control algorithm and a synovial membrane control algorithm; the dedicated acceleration subsystem includes at least: a vector control acceleration module, a PID control acceleration module, an adaptive control acceleration module, a fuzzy logic control acceleration module, a predictive control acceleration module and a synovial membrane control acceleration module.

[0012] In some embodiments, the universal peripheral subsystem includes at least: a universal input and output interface, a serial communication interface, a multi-master bus interface, and a full-duplex synchronous serial communication interface.

[0013] In some embodiments, the bus is an Advanced Microcontroller Bus (AMBA).

[0014] The embodiment of the present disclosure also provides a power electronic device, which at least includes the heterogeneous dual-core processor system as described above.

[0015] The beneficial effects of the embodiments of the present disclosure are: building a heterogeneous dual-core dedicated processor architecture of a main processor and a coprocessor, the main processor is used to execute high-real-time and high-reliability control algorithms, and expands dedicated peripheral subsystems through a standard bus to meet control-intensive application requirements such as high switching frequency and multi-level topology, and implements hardware-based acceleration control through a dedicated acceleration subsystem, and the coprocessor is used to execute computationally intensive edge intelligent algorithms to meet the computationally intensive application requirements of future power electronic equipment for edge intelligent computing such as fault prediction and health management. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A schematic diagram of the architecture of a heterogeneous dual-core processor system of a power electronic device provided for one or more embodiments of this specification;

[0018] Figure 2 A schematic diagram of the structure of a coprocessor provided for one or more embodiments of this specification;

[0019] Figure 3 A schematic diagram of the structure of a PWM pulse generation module provided in one or more embodiments of this specification. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0021] With the rapid development of the global economy and the continuous advancement of science and technology, the demand for highly reliable, high-quality and controllable electric energy in many fields such as smart grid, rail transportation, new energy vehicles, distributed new energy and military equipment is becoming increasingly urgent. As the core equipment of energy conversion, power electronic equipment is widely valued by various countries. Its reliability, automation and intelligence level will have an important impact on the safe and stable operation and intelligence level of the entire power grid system. Therefore, it is of great significance to carry out research on the key technologies of power electronic equipment.

[0022] The next generation of wide bandgap power semiconductor devices represented by SiC (silicon carbide) and GaN (gallium nitride) have the advantages of high voltage tolerance, high junction temperature stability and high reliability, and will become an important development direction for future power electronic devices. Compared with silicon-based power semiconductor devices, wide bandgap power semiconductor devices improve power quality by increasing the switching frequency by more than ten times. The deployment of control-intensive applications such as new topologies, high-precision control algorithms and high switching frequencies brought by wide bandgap power semiconductors in power electronic devices places higher requirements on the control performance of core processors. In addition, the application of edge intelligent algorithms in power electronic devices also places higher requirements on the computing efficiency of core processor computing-intensive applications. It is difficult to meet the requirements of control-intensive applications such as multi-level topologies, high-performance control algorithms and high switching frequencies brought by future wide bandgap power semiconductors through simple selection and hardware stacking of existing processors, and it is also difficult to meet the requirements of computing-intensive applications such as edge intelligent computing. Therefore, the core processor has become an important factor restricting the deployment of control-intensive applications and edge intelligent computing capabilities of future power electronic devices.

[0023] In order to solve the above problems, the dedicated processor architecture for future power electronic equipment needs to meet not only the control-intensive application requirements such as multi-level topology, high-performance control algorithms, and high switching frequencies brought by future wide-bandgap power semiconductors, but also the computing-intensive application requirements of future edge intelligent algorithms. The first embodiment of the present disclosure provides a heterogeneous dual-core processor system for power electronic equipment, and its architecture diagram is shown in FIG. Figure 1As shown, it mainly includes a main processor 10 and a coprocessor 20 communicating with the main processor through a bus, a general peripheral subsystem 30, a dedicated peripheral subsystem 40, a dedicated acceleration subsystem 50, an interrupt subsystem 60 and a storage subsystem 70; wherein the main processor 10 is designed and implemented based on the RISC V instruction set, and is configured to execute a complete control process of the power electronic equipment; the coprocessor 20 is configured to perform edge computing on the data transmitted by the main processor 10, and feed back the computing results to the main processor 10; the general peripheral subsystem 30 is configured to realize data communication between the main processor 10 and the general external device; the dedicated peripheral subsystem 40 is configured to generate multi-channel control pulse signals of the multi-level topology device according to the control requirements of the main processor 10 for the multi-level topology device; the dedicated acceleration subsystem 50 is configured to accelerate the operation of the input data according to the control algorithm selected by the main processor 10; the interrupt subsystem 60 is configured to process interrupt requests.

[0024] Specifically, as a bridge between the underlying hardware of the processor and the application software running on it, the choice of instruction set architecture is crucial to the processor's hardware and software design, application software execution efficiency, and compatibility between various series of processor versions. Based on the advantages of the RISC V instruction set in open source, modularity, scalability, power consumption, cost, performance, and security, the main processor 10 of this embodiment is a high-performance embedded processor core built on the basis of the RISC V instruction set, designed with a 5-stage pipeline, and uses the standard Advanced Microcontroller Bus Architecture (AMBA) to implement the expansion of various functional peripherals such as communication and control, and is mainly used to implement the entire control process of power electronic equipment, including but not limited to: peripheral initialization, algorithm control process, communication with the upper system, and display functions.

[0025] Introducing computationally intensive edge intelligent algorithms in power electronic equipment to achieve equipment fault diagnosis, fault prediction and health management has become one of the important trends in the development of power electronic equipment in the future. The coprocessor 20 of this embodiment implements equipment fault diagnosis, fault prediction and health management functions by introducing computationally intensive edge intelligent algorithms to meet the functional realization requirements of power electronic equipment. Specifically, the coprocessor 20 in this embodiment is designed based on the instruction set constructed by the edge intelligent computing operator to perform different types of operations on data, including but not limited to: element-by-element operations, activation operations, RNN activation operations, normalization operations, pooling operations and pulsation operations.

[0026] The edge intelligent computing instruction set of the coprocessor 20 is shown in Table 1. Among them, the element-by-element operation refers to performing the same or similar operations on each element in the data structure (such as vectors, matrices, tensors, etc.) separately. Although most of these operations can be implemented on general-purpose cores, this embodiment uses the setting of the processing unit array in the coprocessor 20 to realize the parallel execution of multiple computing cores, which can significantly improve the data bandwidth, thereby greatly improving the performance; the activation operation is used to implement the activation function in the field of machine learning. The activation function is a type of function used to introduce nonlinear characteristics in the neural network. It is usually applied to each neuron of the neural network; the RNN activation operation mainly includes the long short-term memory network activation (LSTMACT) operation and the gated recurrent unit activation (GRUACT) operation, which is used to implement all activation functions of the LSTM or GRU layer at one time; the normalization operation is mainly used to convert the output of the model into a probability distribution. The edge intelligent computing coprocessor for power electronic equipment mainly includes two operations: SOFTMAX and BATCH NORMALIZATION. Among them, the SOFTMAX operation is usually used in multi-category classification problems to convert the original output of the model into a probability distribution, and the BATCH NORMALIZATION performs normalization on each small batch of samples so that the input features have zero mean and unit variance, which helps to reduce the gradient vanishing and gradient exploding problems, thereby accelerating the convergence of the neural network. The pooling operation has many important functions in the convolutional neural network, such as feature dimensionality reduction, improving model invariance, reducing overfitting, suppressing noise, and improving computing efficiency. The edge intelligent computing coprocessor for power electronic equipment mainly includes two operations: AVERAGEPOOL2D and MAXPOOL2D. Among them, AVERAGEPOOL2D averages the values ​​of all pixels (or feature values) within the specified pooling window (Pooling Window), and then uses this average value as the output value of the window area. MAXPOOL2D selects the maximum value in each pooling window as the output to achieve downsampling and dimensionality reduction of the input feature map. The pulsation operation allows data to flow between processing units in the array in a rhythmic and regular manner and be processed in parallel. It has the advantages of high parallelism, high modularity, and reduced memory access times. It mainly includes FUSED The two operations, CONVOLUTION and MATMUL-OP, are used to implement fused convolution operations and matrix multiplication operations, respectively.

[0027] Table 1

[0028]

[0029]

[0030] Figure 2The schematic diagram of the structure of the coprocessor 20 in this embodiment is shown. It mainly includes: a pre-fetch and write-back module 21, an intermediate memory 22, a first data moving and formatting module 23, a first-in first-out queue 24, a processing unit array 25 and a second data moving and formatting module 26. The functions of the above modules are described below in conjunction with the process of data processing by the coprocessor 20.

[0031] S1, the pre-fetch and write-back module 21 communicates with the main processor 10 through the bus interface, obtains the data required for edge computing from the main processor 10, and sends it to the intermediate memory 22;

[0032] S2, the intermediate storage 22 sends the data to the first data moving and formatting module 23;

[0033] S3, the first data moving and formatting module 23 sends the data to the first-in first-out queue 24;

[0034] S4, the first-in first-out queue 24 sends the input to the processing element array 25 composed of processing elements (PE) according to the current operation type, wherein each PE is a simple processor composed of three-stage pipelines, and can implement element-by-element operations and activation operations through instructions. After the current PE completes the calculation, it passes the calculation result to the right or downward. The specific operation and whether the calculation result is passed to the right or downward are determined by the instructions executed in the PE;

[0035] S5, the processing unit array 25 writes the result of this iteration calculation into the first data moving and formatting module 23;

[0036] S6, the first data movement and formatting module 23 determines whether the edge calculation is completed according to the iterative calculation result, and if completed, writes the iterative calculation result into the intermediate memory 22, and the pre-fetch and write-back module 21 writes the iterative calculation result in the intermediate memory 22 back to the main processor 10; if the first data movement and formatting module 23 determines that the edge calculation is not completed at present, the current iterative calculation result is sent to the second data movement and formatting module 26;

[0037] S7, the second data movement and formatting module 26 rewrites the current iterative calculation result into the processing unit array 25 for the next round of iterative calculation, until the first data movement and formatting module 23 determines that the edge calculation is completed.

[0038] In this embodiment, when the computing power required for this calculation is high and cannot be met by only one iterative calculation, the coprocessor 20 sends the data back to the processing unit array 25 through the first data movement and formatting module 23 and the second data movement and formatting module 26 for the next round of iterative calculation until the entire target operation is completed; when the computing power required for the calculation is low and can be met by only one iteration, the processing unit array 25 greatly improves the target operation bandwidth in the form of a systolic array.

[0039] It should be noted that the instructions implemented by each PE in the processing unit array 25 are not exactly the same, and calculations under any operation type can be completed through collaborative processing by multiple different PEs. After the current PE completes the calculation, it can determine to pass the calculation result to other PEs to the right or downward for subsequent calculations based on the current operation type and the instructions executed. The number of PEs and the array arrangement in this embodiment can be determined according to actual calculation requirements, and this embodiment does not impose specific restrictions.

[0040] The general peripheral subsystem 30 transmits data with the main processor 10 through a standard AMBA bus. The subsystem integrates common SOC peripherals such as a general-purpose input / output interface (GPIO), a serial communication interface (USART), a multi-master bus interface (CAN, Controller Area Network) and a full-duplex synchronous serial communication interface (SPI, Serial Peripheral Interface), to realize the function of the main processor 10 communicating with other conventional modules or devices.

[0041] The dedicated peripheral subsystem 40 and the main processor 10 also exchange data based on the standard AMBA bus. The subsystem is mainly designed for the special needs of power electronic equipment, and mainly includes PWM (Pulse Width Modulation) pulse generation module, QEP (Quadrature Encoder Pulse) pulse generation module and ADC (Analog-to-Digital Converter) pulse generation module and other commonly used modules in the field of power electronic control, which are used to drive the corresponding multi-level topology structure equipment. The signal lines between the modules realize the linkage control of the two modules to improve the control efficiency.

[0042] Figure 3The schematic diagram of the structure of the PWM pulse generation module in this embodiment is shown, which mainly includes: a time base unit, a counting and comparing unit, an action unit, a dead zone control unit, an error control unit and an event triggering unit. Among them, the time base unit is used to generate the basic time reference and control logic required for PWM pulses. The time base modules of multiple multi-level topology dedicated peripherals can be set to synchronize with each other through registers; the count comparison unit is used to start the counter according to the configuration of the time base unit, and generate the current counter status signal according to the period register, comparison value register and comparison logic register set by the core; the action unit is used to generate multiple PWM pulse signals according to the status signal and the basic time reference; the dead zone control unit is used to perform dead zone control on multiple PWM pulse signals, which is mainly used to solve the problem that the switch tubes on the same bridge arm cannot be turned on at the same time, and the output signal of the action module is processed according to the dead zone control register and then output; the error control unit is used to monitor whether the external dedicated peripheral subsystem needs to urgently block the output pulse signal to put the device into a protection state. If emergency blocking is not required, the multiple PWM pulse signals can be output to the multi-level topology device through the general input and output interface; the event trigger unit is used to generate interrupt requests and ADC sampling signals according to the current states of the time base unit, the count comparison unit and the action unit.

[0043] In actual use, each bridge arm of a mature two-level topology structure needs to control two switching tubes, each bridge arm of a three-level topology structure needs to control four switching tubes, and each bridge arm of a five-level topology structure needs to control eight switching tubes. This embodiment is designed for conventional two-level, three-level and five-level topologies. Therefore, the multi-channel PWM pulse signal in this embodiment is an 8-channel PWM pulse signal to meet the control implementation of the above-mentioned multi-level topology device.

[0044] The dedicated acceleration subsystem 50 is designed for the high real-time control requirements brought by the generation of wide bandgap power semiconductor devices. The control algorithms commonly used in power electronic equipment are implemented through hardware to improve the execution speed of the control algorithm and meet the high-performance and high-frequency control requirements. Specifically, the control algorithms that can be executed by the dedicated acceleration subsystem 50 include at least vector control algorithm, PID control algorithm, adaptive control algorithm, fuzzy logic control algorithm, predictive control algorithm and synovial control algorithm; then the corresponding dedicated acceleration subsystem 50 is integrated with at least vector control acceleration module, PID control acceleration module, adaptive control acceleration module, fuzzy logic control acceleration module, predictive control acceleration module and synovial control acceleration module, and each acceleration module is used to execute the control algorithm corresponding to the actuator. In actual use, the control algorithm is first selected by sending instructions through the main processor 10, and then parameters are sent to configure the corresponding acceleration module. Finally, the main processor 10 sends data through the bus and reads the output data of the acceleration module.

[0045] The interrupt subsystem 60 in this embodiment is used to process interrupt requests to ensure that the system can respond to and process internal or external events in a timely manner. The interrupt sources mainly include external interrupt sources represented by GPIO, DMA (Direct Memory Access), etc. and internal interrupt sources represented by program exceptions and hardware failures.

[0046] The storage subsystem 70 is responsible for storing program code and data, and participates in the system startup, runtime management, performance optimization and other aspects of work. Because the cache structure based on the temporal locality and spatial locality of the software program has the problem that the real-time performance cannot be guaranteed due to the Cache-Miss situation, and the processor software scale for power electronic equipment is usually small, the storage subsystem 70 of this embodiment is designed with a delayed determined ITCM (Instruction Tightly Coupled Memory) and DTCM (Data Tightly Coupled Memory) structure. The main processor 10 accesses the memory such as ROM (Read-Only Memory), RAM (Random Access Memory) and Flash (flash memory) through the storage bus.

[0047] This embodiment constructs a heterogeneous dual-core dedicated processor architecture of the main processor and the coprocessor. The main processor is used to execute high-real-time and high-reliability control algorithms, and expands the dedicated peripheral subsystem through the standard bus to meet the control-intensive application requirements such as high switching frequency and multi-level topology. The hardware-based acceleration control is realized through the dedicated acceleration subsystem, and the coprocessor is used to execute computationally intensive edge intelligent algorithms to meet the computationally intensive application requirements of future power electronic equipment for edge intelligent computing such as fault prediction and health management. In addition, the main processor and the coprocessor communicate through the bus, which facilitates the decoupling between the two during the design process.

[0048] Based on the same inventive concept, the second embodiment of the present disclosure provides a power electronic device, which at least includes the heterogeneous dual-core processor system provided by the first embodiment of the present disclosure, executes a high real-time and high-reliability control algorithm through the main processor, and expands a dedicated peripheral subsystem through a standard bus to meet control-intensive application requirements such as high switching frequency and multi-level topology structure, and implements hardware-based acceleration control through a dedicated acceleration subsystem. The coprocessor is used to execute computationally intensive edge intelligent algorithms to meet the computationally intensive application requirements of future power electronic equipment for edge intelligent computing such as fault prediction and health management.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A heterogeneous dual-core processor system for power electronic equipment, characterized in that: At least: A main processor and a coprocessor communicating with the main processor via a bus, a general peripheral subsystem, a dedicated peripheral subsystem, a dedicated acceleration subsystem, an interrupt subsystem and a storage subsystem; wherein, The main processor is designed and implemented based on the RISC V instruction set and is configured to execute the complete control process of the power electronic equipment; The coprocessor is configured to perform edge computing on the data transmitted by the main processor and feed back the computing result to the main processor; The general peripheral subsystem is configured to implement data communication between the main processor and the general peripheral device; The dedicated peripheral subsystem is configured to generate a multi-channel control pulse signal of the multi-level topology device according to the control requirements of the main processor for the multi-level topology device; The dedicated acceleration subsystem is configured to perform accelerated operations on input data according to a control algorithm selected by the main processor; The interrupt subsystem is configured to process interrupt requests.

2. The heterogeneous dual-core processor system according to claim 1, characterized in that: The coprocessor comprises at least: A pre-fetch and write-back module, an intermediate memory, a first data movement and formatting module, a first-in first-out queue, a processing unit array, and a second data movement and formatting module; wherein, The pre-fetch and write-back module communicates with the main processor through a bus interface, obtains data to be processed, and sends it to the intermediate memory. The intermediate memory sends the data to the first data movement and formatting module. The first data movement and formatting module sends the data to the first-in-first-out queue. The first-in-first-out queue inputs the data into the processing unit corresponding to the current operation type in the processing unit array. After the current processing unit completes the calculation, the calculation result is passed to the right or downward until an iterative calculation result is formed and written into the first data movement and formatting module. The first data movement and formatting module determines whether the edge calculation is completed according to the iterative calculation result. If completed, the iterative calculation result is written into the intermediate memory. The pre-fetch and write-back module writes the calculation result in the intermediate memory back to the main processor. If the edge calculation is not completed, the first data movement and formatting module writes the iterative calculation result into the second data movement and formatting module. The second data movement and formatting module writes the iterative calculation result into the processing unit array to complete the next round of iterative calculation until the first data movement and formatting module determines that the edge calculation is completed.

3. The heterogeneous dual-core processor system according to claim 2, characterized in that: The operation types include at least: element-by-element operation, activation operation, RNN activation operation, normalization operation, pooling operation and pulsation operation.

4. The heterogeneous dual-core processor system according to claim 1, characterized in that: The dedicated peripheral subsystem at least includes: a PWM pulse generating module, an ADC pulse generating module and a QEP pulse generating module.

5. The heterogeneous dual-core processor system according to claim 4, characterized in that: The PWM pulse generation module at least includes: The time base unit is used to generate the basic time base and control logic required for PWM pulses; A counting and comparing unit, used to start the counter according to the configuration of the time base unit, and generate a state signal of the current counter according to the period register, the comparison value register and the comparison logic register set by the core; An action unit, configured to generate a plurality of PWM pulse signals according to the state signal and the basic time reference; A dead zone control unit, used for performing dead zone control on the multiple PWM pulse signals; An error control unit is used to monitor whether the pulse signal outputted by the dedicated peripheral subsystem needs to be urgently blocked, and if emergency blocking is not required, the multi-channel PWM pulse signal is outputted to the multi-level topology device through the universal input and output interface; The event triggering unit is used to generate an interrupt request according to the current states of the time base unit, the counting and comparing unit and the action unit.

6. The heterogeneous dual-core processor system according to claim 5, characterized in that: The multiple PWM pulse signals are 8-channel PWM pulse signals.

7. The heterogeneous dual-core processor system according to claim 1, characterized in that: The control algorithm at least includes: vector control algorithm, PID control algorithm, adaptive control algorithm, fuzzy logic control algorithm, predictive control algorithm and synovial control algorithm; The dedicated acceleration subsystem includes at least: a vector control acceleration module, a PID control acceleration module, an adaptive control acceleration module, a fuzzy logic control acceleration module, a predictive control acceleration module and a synovial control acceleration module.

8. The heterogeneous dual-core processor system according to claim 1, characterized in that: The universal peripheral subsystem at least includes: a universal input and output interface, a serial communication interface, a multi-master bus interface and a full-duplex synchronous serial communication interface.

9. The heterogeneous dual-core processor system according to any one of claims 1 to 8, characterized in that: The bus is the Advanced Microcontroller Bus AMBA.

10. A power electronic device, characterized in that: At least comprising the heterogeneous dual-core processor system as claimed in any one of claims 1 to 9.

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