Testing system and method based on interface simulation
Through the test system based on interface simulation, the problems of long simulation cycles and difficult configuration of physical test environments in FPGA chip software testing are solved, and fast and efficient software function verification is achieved.
Patent Information
- Application Number
- CN202510092560.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-05-16
AI Technical Summary
In the prior art, when testing FPGA chip software, the simulation test cycle is long and the physical test environment is difficult to configure, resulting in limited test completion.
A test system based on interface simulation is adopted, which includes a host computer, an interface simulation board and a detection device. The upper computer outputs waveform generation instructions, and the interface simulation board generates the target waveform according to the instructions and transmits it to the external input interface of the chip being tested. The detection device is used to detect the processing results.
It quickly verifies the correctness of the preset software function modules in the chip being tested. The test cycle is short and there is no need to build a physical test environment, which avoids the coordination problem of the accompanying test equipment.
Smart Images
Figure CN120011158A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of testing technology, and in particular to a testing system and method based on interface simulation. Background Art
[0002] Field Programmable Gate Arrays (FPGA) is a programmable signal processing device. Users can define its functions by changing the configuration information to meet the design requirements. Due to the characteristics of high flexibility, short design cycle, strong real-time performance, and low power consumption, FPGA has become increasingly popular in data communication, image processing, instrument control, etc. in recent years, and has been widely used in aerospace, military and defense fields.
[0003] According to relevant statistical results, the number of failures of FPGA-based on-orbit equipment cannot be ignored. In severe cases, it may even lead to the failure of the entire mission. Therefore, the reliability design of FPGA and sufficient verification on the ground are becoming increasingly important.
[0004] At present, when testing FPGA chip configuration item software, it can usually be verified through functional simulation, gate-level simulation, timing simulation, and physical testing. However, as the scale of software becomes larger and larger, simulation, especially timing simulation, can hardly complete the evaluation task within a limited time, and physical testing will be limited in test completion due to the difficulty in coordinating accompanying test equipment, insufficient adjustable test cycles, and insufficient test input. Summary of the invention
[0005] In order to solve the problems in the prior art of long simulation test cycle and difficult deployment of physical test environment when testing chip software, the present invention proposes a test system and method based on interface simulation.
[0006] In order to achieve the above object, the present invention adopts the following technical solutions:
[0007] In a first aspect, the present invention provides a test system based on interface simulation, the system comprising:
[0008] The host computer is used to output waveform generation instructions;
[0009] an interface simulation board connected between the host computer and the chip under test, comprising a plurality of output interfaces corresponding one to one with the external input interfaces of the chip under test, for generating a corresponding target waveform based on the waveform generation instruction, and transmitting the target waveform to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through a preset software function module and obtain a processing result; and
[0010] A first detection device connected to the chip under test is used to detect the processing result.
[0011] Preferably, the interface simulation board comprises:
[0012] A communication module, used to communicate with the host computer and the chip under test respectively;
[0013] a parameter setting module, configured to set target waveform parameters based on the waveform generation instruction; and
[0014] The waveform generating module is used to generate a corresponding target waveform based on the target waveform parameters.
[0015] Preferably, the interface simulation board further includes at least one of the following modules:
[0016] A self-check module, used to detect whether the interface simulation board communicates successfully with the host computer;
[0017] The state feedback module is used to obtain the target waveform parameters set by the parameter setting module, and feed back the obtained target waveform parameters to the host computer.
[0018] Preferably, the system further comprises:
[0019] A second detection device connected to the interface simulation board is used to detect the target waveform.
[0020] Preferably, the waveform generation instruction includes preset waveform parameters, and the preset waveform parameters include preset encoding method, data content, data format, baud rate, transmission method and interface position.
[0021] Preferably, the transmission mode includes a single-ended transmission mode and a differential transmission mode.
[0022] In a second aspect, the present invention provides a test method based on interface simulation, which is applicable to the interface simulation board as described above, and the method comprises:
[0023] Get waveform generation instructions;
[0024] generating a corresponding target waveform based on the waveform generating instruction;
[0025] The target waveform is transmitted to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through a preset software function module and obtain a processing result.
[0026] Preferably, generating a corresponding target waveform based on the waveform generating instruction comprises:
[0027] setting target waveform parameters based on the waveform generation instruction;
[0028] The target waveform is generated based on the target waveform parameters.
[0029] Preferably, the method further comprises:
[0030] After receiving the status query instruction, obtaining the target waveform parameters;
[0031] The acquired target waveform parameters are fed back to the host computer.
[0032] In a third aspect, the present invention provides a test method based on interface simulation, which is applicable to the test system based on interface simulation as described above, and the method comprises:
[0033] Outputting waveforms through the host computer generates instructions;
[0034] Generate a corresponding target waveform based on the waveform generation instruction through the interface simulation board, and transmit the target waveform to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through a preset software function module and obtain a processing result;
[0035] The processing result is detected by the first detection device.
[0036] By adopting the above technical solution, the present invention has the following beneficial effects:
[0037] The present invention generates a waveform instruction through the host computer output, generates a corresponding target waveform based on the waveform generation instruction through the interface simulation board, and transmits the target waveform to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through the preset software function module and obtain the processing result, and then the processing result is detected by the first detection device to verify the correctness of the preset software function module in the chip under test. It can be seen that when the software function of the chip is tested using the solution of the present invention, not only the test cycle is short, but also there is no need to build a physical test environment, so there is no need to coordinate the accompanying test equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A circuit diagram of a test system based on interface simulation according to Embodiment 1 of the present invention;
[0039] Figure 2 is a structural block diagram of the interface simulation board in Example 1 of the present invention;
[0040] Figure 3 This is a schematic diagram of the state transition of the interface simulation board in Example 1 of the present invention;
[0041] Figure 4 This is a flow chart of a testing method based on interface simulation according to Embodiment 2 of the present invention;
[0042] Figure 5 This is a flow chart of a testing method based on interface simulation according to Embodiment 3 of the present invention. DETAILED DESCRIPTION
[0043] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0044] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "the" used in the present disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0045] At present, the software dynamic testing technology of FPGA chips mainly includes functional simulation, gate-level simulation, timing simulation and physical online testing. With the continuous expansion of FPGA application fields, large-scale and giant-scale software of FPGA is also common. Faced with this problem, the previous strategy of mainly relying on simulation to verify whether the software function is correct is particularly clumsy, and the test cycle becomes unpredictable; although the physical online testing method can be verified quickly, the coordination of the accompanying test equipment is not easy in system testing.
[0046] In this regard, the present invention provides a testing system and method based on interface simulation, so as to perform faster, more detailed and deeper testing on the software functions configured in chips such as FPGA under limited environment, so as to ensure the smooth progress of the project.
[0047] Example 1
[0048] This embodiment provides a test system based on interface simulation, such as Figure 1 and 2 As shown, the system includes: a host computer 1, an interface simulation board 2 connected between the host computer 1 and the chip under test 3, and a first detection device 4 and a power supply device 5 connected to the chip under test 3.
[0049] In the present embodiment, the host computer 1 is used to output a waveform generation instruction, which may include preset waveform parameters. Among them, the preset waveform parameters may include a preset encoding method, data content, data format, baud rate, transmission method, and interface position. The encoding method may be, for example, NRZ, NRZI, RZ, Manchester, differential Manchester, etc., the data format may be, for example, SPI, I2C, LVDS, etc., and the transmission method may be, for example, differential or single-ended transmission. Specifically, the host computer 1 is configured with a human-computer interaction interface so that the user can configure the above-mentioned waveform parameters through the artificial interaction interface.
[0050] In this embodiment, the interface simulation board 2 includes a number of output interfaces corresponding one-to-one to the external input interfaces of the chip under test 3, which are used to generate a corresponding target waveform based on the waveform generation instruction, and transmit the target waveform to the corresponding external input interface of the chip under test 3 through the output interface, so that the chip under test 3 can process the target waveform through a preset software function module and obtain the processing result.
[0051] In this embodiment, the first detection device is used to detect the processing result of the chip under test 3. Preferably, the first detection device can be an oscilloscope, through which the waveform corresponding to the processing result can be detected and displayed, so that the user can verify the correctness of the processing result, and then determine whether the corresponding software function module in the chip under test 3 is correct.
[0052] Specifically, in some actual application environments, the chip under test 3 receives waveforms output by other devices through its external input interface, and inputs the received waveforms into a preset software function module for processing to obtain a processing result. Each output interface on the interface simulation board 2 of this embodiment is used to simulate the interface of other devices corresponding to the external input interface of the chip under test 3 in the actual application environment.
[0053] See again Figure 2 The interface simulation board 2 of this embodiment may include a communication module 21, a self-checking module 22, a parameter setting module 23, a waveform generation module 24 and a state feedback module 25. The communication module 21 is used to communicate with the host computer 1 and the chip under test 3 respectively; the self-checking module 22 is used to detect whether the interface simulation board 2 and the host computer 1 have successfully communicated; the parameter setting module 23 is used to set the target waveform parameters based on the waveform generation instruction; the waveform generation module 24 is used to generate the corresponding target waveform based on the target waveform parameters; the state feedback module 25 is used to obtain the target waveform parameters set by the parameter setting module 23, and feed the obtained target waveform parameters back to the host computer 1.
[0054] Specifically, after power-on, the interface simulation board 2 first performs a self-test through the self-test function module, mainly to check whether the communication with the host computer 1 is successful. If the self-test is successful, the state machine will be returned to the host computer 1. After the host computer 1 receives the return state machine of the successful self-test, it can send instructions to the interface simulation board 2.
[0055] On the one hand, the host computer 1 can specify the waveform generation encoding method (such as NRZ, NRZI, RZ, Manchester, differential Manchester, etc.), data content, data format (such as SPI, I2C, LVDS, etc.), baud rate, differential / single-ended transmission mode, interface position and other information by issuing a waveform generation instruction including preset waveform parameters. After receiving the waveform generation instruction, the interface simulation board 2 will parse the instruction to obtain the preset waveform parameters, and then set the target waveform parameters based on the analysis result through the parameter setting module 23, for example, by configuring the relevant registers to set the target waveform parameters; then the waveform generation module 24 generates the corresponding target waveform based on the target waveform parameters, and transmits the target waveform to the corresponding external input interface of the chip under test 3 through the corresponding output interface.
[0056] On the other hand, the host computer 1 can check the target waveform parameters set by the interface module board by issuing a status query instruction. After the state feedback module 25 of the interface simulation board 2 receives the status query instruction, it packages the target waveform parameters set by the parameter setting module 23 in accordance with the agreed protocol format and sends them to the host computer 1, so that the host computer 1 can verify the correctness of the target waveform parameters.
[0057] Preferably, the test system of this embodiment may further include a second detection device (not shown) connected to the interface simulation board 2, which is used to detect the target waveform output by the interface simulation board 2. Preferably, the second detection device may be an oscilloscope, through which the target waveform output by the interface simulation board 2 can be detected and displayed, so that the user can verify the correctness of the target waveform.
[0058] In this embodiment, the interface simulation board 2 mainly has four states: initialization, self-test, standby and working. After power-on, it first enters the initialization state, and then directly enters the self-test state. When the self-test is unsuccessful, it returns to the initialization state. To enter the self-test state again, it needs to be controlled by corresponding instructions; secondly, after the self-test is successful, it automatically jumps to the standby state, and can also be switched to the initialization state through corresponding instructions; when on standby, it can jump to the working state through the status query or waveform generation instruction sent by the upper computer 1; when the target waveform is transmitted to the chip under test 3, the interface simulation board 2 automatically jumps from the working state to the standby state, and can also be switched to the self-test or initialization state through corresponding instructions. The specific state transfer is as follows Figure 3 shown.
[0059] In this embodiment, the upper computer 1 outputs a waveform generation instruction, the interface simulation board 2 generates a corresponding target waveform based on the waveform generation instruction, and transmits the target waveform to the corresponding external input interface of the chip under test 3 through the output interface, so that the chip under test 3 can process the target waveform through the preset software function module and obtain the processing result, and then the processing result is tested by the first detection device to verify the correctness of the preset software function module in the chip under test 3. It can be seen that when the solution of this embodiment is used to test the software function of the chip, not only the test cycle is short, but also there is no need to build a physical test environment, so there is no need to coordinate the accompanying test equipment.
[0060] In addition, this embodiment can realize multiple encoding modes (such as NRZ, NRZ I, RZ, Manchester, differential Manchester, etc.) output for the same waveform data, can simulate the output of data of various interface types (such as SPI, I2C, LVDS, etc.), can generate output of various types of data in parallel, and can realize single-ended or differential output of the same waveform data.
[0061] Example 2
[0062] This embodiment provides a test method based on interface simulation, which is applicable to the interface simulation board 2 in embodiment 1. Figure 4 As shown, the method includes:
[0063] S11, obtain waveform generation instructions.
[0064] In this embodiment, the waveform generation instruction is issued by the host computer 1 and may include preset waveform parameters. The preset waveform parameters may include preset encoding methods, data content, data format, baud rate, transmission method, and interface position. The encoding method may be, for example, NRZ, NRZ I, RZ, Manchester, differential Manchester, etc., the data format may be, for example, SPI, I2C, LVDS, etc., and the transmission method may be, for example, differential or single-ended transmission method.
[0065] S12, generating a corresponding target waveform based on the waveform generation instruction.
[0066] The implementation process of this step is as follows: first, the target waveform parameters are set based on the waveform generation instruction; and then the target waveform is generated based on the target waveform parameters. Specifically, after the interface simulation board 2 receives the waveform generation instruction and determines that the instruction is legal, it will parse the instruction to obtain the preset waveform parameters, and then set the target waveform parameters based on the parsing result through the parameter setting module 23, for example, by configuring the relevant registers to set the target waveform parameters; finally, the waveform generation module 24 generates the corresponding target waveform based on the target waveform parameters.
[0067] S13, transmitting the target waveform to the corresponding external input interface of the chip under test 3 through the corresponding output interface, so that the chip under test 3 can process the target waveform through the preset software function module and obtain the processing result.
[0068] When the chip under test 3 obtains the processing result, by verifying the correctness of the processing result, it can be determined whether the function implemented by the software function module built into the chip under test 3 is correct. When the solution of this embodiment is used to test the software function of the chip, not only the test cycle is short, but also there is no need to build a physical test environment, and thus there is no need to coordinate the accompanying test equipment.
[0069] In addition, the method of this embodiment may further include: after receiving the status query instruction, obtaining target waveform parameters, and feeding back the obtained target waveform parameters to the host computer 1, so that the host computer 1 verifies the correctness of the target waveform parameters.
[0070] Example 3
[0071] This embodiment provides a test method based on interface simulation, which is applicable to the test system based on interface simulation as above. Figure 5 As shown, the method includes:
[0072] S21, output waveform generation instruction through host computer 1;
[0073] S22, generating a corresponding target waveform based on the waveform generation instruction through the interface simulation board 2, and transmitting the target waveform to the corresponding external input interface of the chip under test 3 through the output interface, so that the chip under test 3 can process the target waveform through the preset software function module and obtain the processing result;
[0074] S23, testing the processing result by a first testing device, so as to determine whether the functions implemented by the software function module built into the tested chip 3 are correct.
[0075] When the solution of this embodiment is used to test the software function of the chip, not only the test cycle is short, but also there is no need to build a physical test environment, and thus there is no need to coordinate accompanying test equipment.
[0076] Preferably, before outputting the waveform generation instruction through the host computer 1 in step S21, the method of this embodiment also includes detecting through the interface simulation board 2 whether the communication between itself and the host computer 1 is successful, and when the communication is successful, starting to execute step S21.
[0077] In addition, the host computer 1 of the present embodiment is configured with a human-computer interaction interface so that the user can configure the above-mentioned waveform parameters through the human-computer interaction interface. Specifically, before configuring the waveform parameters, the user should first sort out the external input interface information corresponding to the software function module according to the software function module and its requirement specification document in the chip under test 3 to determine which external input interface input signals need to be simulated and output through the interface simulation board 2. For example, for the RS422 interface of the chip under test 3, the data signal can be directly output to the interface through the serial port assistant tool without the need to simulate the output through the interface simulation board 2. After determining the interface that needs to be simulated, sort out the waveform parameters corresponding to each interface, including the interface type and protocol, encoding method, baud rate, etc.
[0078] When the chip under test 3, the interface simulation board 2, and the host computer 1 are correctly electrically connected, the waveform parameters are preset through the manual interaction interface of the host computer 1, and the relevant waveform parameters are sent to the interface simulation board 2 after the interface simulation board 2 self-detects that the status is normal.
[0079] The following two specific application examples are used to illustrate:
[0080] Application Example 1: After analysis, the chip under test 3 has an LVDS input interface. The total length of the LVDS is 1024 bytes, with the high byte first and the low byte last. Inside the byte, the high bit is first and the low bit is last. The interface is a three-wire system (clock, data and enable signal), the clock frequency is 6MHz, the data and clock rising edges are aligned, the enable signal is valid at low level, and the data transmission frequency is 1Hz.
[0081] When configuring waveform parameters, select the "LVDS" interface in the upper computer 1 interface, configure the data length parameter to "1024" bytes, select the data format to "high byte first, low byte last", select the byte format to "high first, low last", and enter the 1024 bytes to be sent in the data input box. Select the interface signal to be "three-wire system", select the enable signal valid mode to be "low level valid", set the clock frequency to "6MHz", and select the clock valid mode to be "always valid", select the interface signal phase relationship to be "data, enable and clock rising edge aligned", and set the data frequency to "1Hz".
[0082] After all components of the system are connected and powered on, after the interface simulation board 2 has successfully completed the self-test, the host computer 1 sends a "waveform generation start" command, and the LVDS interface data with the above characteristics can be correctly captured on the interface simulation board 2 using an oscilloscope, and the chip under test 3 can report the status information of correctly receiving the LVDS data through telemetry.
[0083] Application Example 2: Set the data length parameter configuration to "1023" bytes in the upper computer 1 interface, enter 1024 bytes of data to be sent in the data input box, and keep the other parameters consistent with Example 1. Connect the system components, power on, and wait for the interface simulation board 2 to successfully self-check. Then, the upper computer 1 sends a "waveform generation start" command, and the LVDS interface data with the above characteristics can be correctly captured on the interface simulation board 2 using an oscilloscope. The chip under test 3 can report the status information of the received LVDS data error through telemetry to indicate that the received data length (1024) does not match the configured data length (1023).
[0084] It should be understood that the chip under test 3 in the present invention can be not only an FPGA chip, but also any other chip that needs to input a waveform signal through an external input interface to test the built-in software, and the present invention does not impose any specific limitation on this.
[0085] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.
Claims
1. A test system based on interface simulation, characterized in that: The system includes: The host computer is used to output waveform generation instructions; an interface simulation board connected between the host computer and the chip under test, comprising a plurality of output interfaces corresponding one to one with the external input interfaces of the chip under test, for generating a corresponding target waveform based on the waveform generation instruction, and transmitting the target waveform to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through a preset software function module and obtain a processing result; and A first detection device connected to the chip under test is used to detect the processing result.
2. The test system according to claim 1, characterized in that: The interface simulation board comprises: A communication module, used to communicate with the host computer and the chip under test respectively; a parameter setting module, configured to set target waveform parameters based on the waveform generation instruction; and The waveform generating module is used to generate a corresponding target waveform based on the target waveform parameters.
3. The test system according to claim 2, characterized in that: The interface simulation board also includes at least one of the following modules: A self-check module, used to detect whether the interface simulation board communicates successfully with the host computer; The state feedback module is used to obtain the target waveform parameters set by the parameter setting module, and feed back the obtained target waveform parameters to the host computer.
4. The test system according to claim 3, characterized in that: The system also includes: A second detection device connected to the interface simulation board is used to detect the target waveform.
5. The test system according to claim 1, characterized in that: The waveform generation instruction includes preset waveform parameters, and the preset waveform parameters include preset encoding method, data content, data format, baud rate, transmission method and interface position.
6. The test system according to claim 5, characterized in that: The transmission mode includes a single-ended transmission mode and a differential transmission mode.
7. A test method based on interface simulation, applicable to the interface simulation board in the test system as claimed in any one of claims 1 to 6, characterized in that: The method includes: Get waveform generation instructions; generating a corresponding target waveform based on the waveform generating instruction; The target waveform is transmitted to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through a preset software function module and obtain a processing result.
8. The testing method according to claim 7, characterized in that: The generating a corresponding target waveform based on the waveform generating instruction comprises: setting target waveform parameters based on the waveform generation instruction; The target waveform is generated based on the target waveform parameters.
9. The test system according to claim 8, characterized in that: The method further includes: After receiving the status query instruction, obtaining the target waveform parameters; The acquired target waveform parameters are fed back to the host computer.
10. A test method based on interface simulation, applicable to the test system as claimed in any one of claims 1 to 6, the method comprising: Outputting waveforms through the host computer generates instructions; Generate a corresponding target waveform based on the waveform generation instruction through the interface simulation board, and transmit the target waveform to the corresponding external input interface of the chip under test through the output interface, so that the chip under test can process the target waveform through a preset software function module and obtain a processing result; The processing result is detected by the first detection device.