CMP process simulation method and device, storage medium and electronic equipment

Abstract

The invention discloses a CMP process simulation method and device, a storage medium and electronic equipment, and the method comprises the steps: obtaining a chip layout of a to-be-simulated chip, and dividing the chip layout into a plurality of grids; converting the pattern information of each grid into a two-dimensional feature, and extracting a one-dimensional feature of each grid through a physical model; respectively inputting the one-dimensional features and the two-dimensional features into a full-connection neural network channel and a convolutional neural network channel of a CMP simulation model to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through a feature fusion layer of a CMP simulation model to generate a target feature vector; and inputting the target feature vector into a prediction layer of the CMP simulation model to generate a grid simulation result. According to the scheme, the simulation precision of the CMP process can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of chemical mechanical polishing, and specifically to a CMP process simulation method, device, storage medium and electronic equipment. Background Art

[0002] Chemical Mechanical Planning (CMP) is the most widely used and effective global planarization process in current integrated circuit manufacturing technology, especially in copper back-end interconnection processes. The CMP process generally includes multiple steps such as chemical reaction and physical removal. It is a complex process in which multiple factors such as the size of polishing particles, properties of polishing pads, composition of polishing liquid, down pressure, and relative speed between polishing pads and wafers interact with each other.

[0003] The CMP process is an important technology and one of the key process steps to ensure the flatness of the surface of the polished chip. In order to ensure the high flatness of the surface of the polished chip, collaboration between design and process is required. Therefore, technicians have conducted extensive research and attention on CMP process simulation methods. However, there are still many deficiencies in directly applying the existing CMP process simulation methods to the field of manufacturability design and process simulation of advanced process nodes, and the simulation accuracy needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a CMP process simulation method, device, storage medium and electronic device, which can improve the simulation accuracy of the CMP process.

[0005] In a first aspect, an embodiment of the present application provides a CMP process simulation method, comprising: Obtaining a chip layout of a chip to be simulated, and dividing the chip layout into a plurality of grids; Converting the pattern information of each of the grids into two-dimensional features, and extracting one-dimensional features of each of the grids through a physical model; Inputting the one-dimensional feature and the two-dimensional feature into a fully connected neural network channel and a convolutional neural network channel of a CMP simulation model respectively to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through a feature fusion layer of the CMP simulation model to generate a target feature vector; The target feature vector is input into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0006] In the CMP process simulation method provided in the embodiment of the present application, converting the pattern information of each grid into a two-dimensional feature includes: The pattern information of each grid is mapped into a grayscale image through an image algorithm to obtain a two-dimensional feature.

[0007] In the CMP process simulation method provided in the embodiment of the present application, after inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result, the method further includes: All the grid simulation results are combined to obtain a layout simulation result.

[0008] The CMP process simulation method provided in the embodiment of the present application also includes: Build a CMP simulation model.

[0009] In the CMP process simulation method provided in the embodiment of the present application, the construction of the CMP simulation model includes: Acquire a test layout of a test chip, wherein the test layout has a plurality of regions, each of the regions having a different pattern density, line width, and gap; Converting the pattern information of each of the regions into two-dimensional features, and extracting one-dimensional features of each of the regions through a physical model; Performing CMP process on the test pattern using fixed process parameters to obtain a process result; The one-dimensional features, the two-dimensional features and the processing results are used as training data to train the dual-channel fusion network model to obtain a CMP simulation model.

[0010] In the CMP process simulation method provided in the embodiment of the present application, the one-dimensional feature, the two-dimensional feature and the processing result are used as training data to train the dual-channel fusion network model to obtain the CMP simulation model, including: The one-dimensional features and the two-dimensional features are used as inputs of a dual-channel fusion network model, the processing results are used as target outputs of the dual-channel fusion model, and the dual-channel fusion network model is trained to obtain a CMP simulation model.

[0011] In the CMP process simulation method provided in the embodiment of the present application, the dual-channel fusion network model uses mean square error as the loss function.

[0012] In a second aspect, an embodiment of the present application provides a CMP process simulation device, comprising: A layout acquisition unit, used to acquire a chip layout of a chip to be simulated, and divide the chip layout into a plurality of grids; A feature acquisition unit, used to convert the pattern information of each of the grids into a two-dimensional feature, and extract a one-dimensional feature of each of the grids through a physical model; A feature input unit, used to input the one-dimensional feature and the two-dimensional feature into a fully connected neural network channel and a convolutional neural network channel of a CMP simulation model respectively, to obtain a first feature vector and a second feature vector; A feature fusion unit, configured to fuse the first feature vector and the second feature vector through a feature fusion layer of the CMP simulation model to generate a target feature vector; The CMP simulation unit is used to input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0013] In a third aspect, the present application provides a storage medium storing a plurality of instructions, wherein the instructions are suitable for loading by a processor to execute any of the above-mentioned CMP process simulation methods.

[0014] In a fourth aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described CMP process simulation methods when executing the computer program.

[0015] In summary, the CMP process simulation method provided by the embodiment of the present application includes obtaining the chip layout of the chip to be simulated, and dividing the chip layout into several grids; converting the pattern information of each grid into a two-dimensional feature, and extracting the one-dimensional feature of each grid through a physical model; inputting the one-dimensional feature and the two-dimensional feature into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution combines the stability of physical model data with the strong fitting ability of neural networks, thereby making CMP simulation more robust, reducing the overfitting defects of pure neural network modeling, and thus improving the simulation accuracy of the CMP process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a schematic diagram of an application scenario of the CMP process simulation method provided in an embodiment of the present application.

[0018] Figure 2 It is a flowchart of the CMP simulation model construction method provided in the embodiment of the present application.

[0019] Figure 3 It is a flow chart of the CMP process simulation method provided in the embodiment of the present application.

[0020] Figure 4 It is a structural schematic diagram of a CMP simulation model building device provided in an embodiment of the present application.

[0021] Figure 5 It is a schematic diagram of the structure of the CMP process simulation device provided in an embodiment of the present application.

[0022] Figure 6 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0024] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0025] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0027] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] The CMP process is an important technology and one of the key process steps to ensure the flatness of the surface of the polished chip. In order to ensure the high flatness of the surface of the polished chip, collaboration between design and process is required. Therefore, technicians have conducted extensive research and attention on CMP process simulation methods. However, there are still many deficiencies in directly applying the existing CMP process simulation methods to the field of manufacturability design and process simulation of advanced process nodes, and the simulation accuracy needs to be improved.

[0029] Based on this, the embodiments of the present application provide a CMP process simulation method, device, storage medium and electronic device. Specifically, the CMP process simulation device can be integrated in an electronic device, and the electronic device can be a server or a terminal. Among them, the terminal can include a mobile phone, a wearable smart device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0030] For example, Figure 1 As shown, the electronic device can obtain the chip layout of the chip to be simulated, and divide the chip layout into several grids; convert the pattern information of each grid into two-dimensional features, and extract the one-dimensional features of each grid through the physical model; input the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain the first feature vector and the second feature vector; fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0031] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.

[0032] See also Figure 2 , Figure 2: is a flow chart of a CMP simulation model construction method provided in an embodiment of the present application. The specific flow of the CMP simulation model construction method can be as follows: 101. Obtain a test layout of a test chip, where the test layout has a plurality of regions, each region having a different pattern density, line width, and gap.

[0033] version Figure 1 Generally, it is created by chip design software (such as Cadence, Mentor Graphics, Synopsys, etc.). In the semiconductor manufacturing industry, in order to ensure the standardization and compatibility of design data, specific file format standards such as GDS (Graphic Data System) or OASIS (Open Artwork System Interchange Standard) are usually used to save these layouts.

[0034] When designing a test chip, the test layout is divided into several areas of fixed size (for example, 10μm×10μm or 50μm×50μm), and each area is set with different pattern structures such as pattern density, line width and gap. For example, area A: high-density line array (line width = 0.1μm, spacing = 0.05μm). Area B: low-density isolated line (line width = 0.5μm, spacing = 0.3μm). Area C: mixed structure (containing randomly distributed line width and gap, simulating the actual chip layout).

[0035] It is understandable that during the CMP process, the CMP material removal rate, flattening effect, and polishing uniformity are closely related to the pattern structure. For example, the pattern density will affect the local removal rate, and the high-density area may have a lower polishing rate. The line width will affect the local uniformity, and the removal rate of wide lines and narrow lines may be different. The gap will affect the flow of the polishing liquid and the stress distribution, which may lead to different removal characteristics.

[0036] By designing regions with different pattern densities, line widths, and gaps, the removal characteristics of different pattern structures under the same process conditions can be analyzed. In addition, designing regions with multiple different pattern structures can simulate the diverse structures that may appear in actual chip manufacturing, avoid the model being only applicable to specific pattern structures, and improve generalization capabilities. If only relying on a single pattern structure, the neural network may overfit, resulting in inaccurate model predictions.

[0037] 102. The pattern information of each region is converted into a two-dimensional feature, and the one-dimensional feature of each region is extracted through a physical model.

[0038] Specifically, the pattern information of each area can be mapped into a grayscale image (for example, 256×256 pixels) through image processing technology to reflect the height difference of different areas. The grayscale image is a two-dimensional feature.

[0039] The one-dimensional feature refers to the numerical vector representation of key parameters such as pattern density, line width and gap, for example, density = 80%, line width = 0.2μm, minimum gap = 0.05μm.

[0040] The pattern density can be calculated by the density calculation formula. That is, density = (line width × line length) / area × 100%. For example, if the area of ​​a certain area is 100μm², the total line length is 50μm, and the line width is 0.1μm, then the density = (0.1×50) / 100×100% = 5%.

[0041] The line width and gap can be automatically extracted through image processing algorithms (such as edge detection) to avoid human errors.

[0042] 103. Use fixed process parameters to perform CMP process on the test layout to obtain a process result.

[0043] The fixed process parameters may include polishing pressure, polishing head rotation speed, slurry flow rate, polishing liquid type, etc.

[0044] After the CMP process is completed, the CMP processing results of each area (such as polishing height, material removal rate, etc.) can be obtained through measurement equipment.

[0045] 104. The one-dimensional features, the two-dimensional features and the processing results are used as training data to train the dual-channel fusion network model to obtain a CMP simulation model.

[0046] First, a number of one-dimensional features, two-dimensional features, and processing results can be divided into training sets, test sets, and validation sets according to the proportions. For example, the training set is 80%, the validation set is 10%, and the test set is 10%.

[0047] Then, the one-dimensional features and the two-dimensional features are used as the input of the dual-channel fusion network model, and the processing results are used as the target output of the dual-channel fusion model. The dual-channel fusion network model is trained to obtain the CMP simulation model.

[0048] Among them, the dual-channel fusion network model has a fully connected neural network channel, a convolutional neural network channel, a feature fusion layer and a prediction layer.

[0049] During the model training process, the fully connected neural network channel is used to process one-dimensional features. The prediction layer learns the nonlinear relationship between parameters (such as the correlation between density and material removal rate), and can output a low-dimensional feature vector (for example, 8 dimensions). The convolutional neural network channel is used to process two-dimensional features. The convolutional layer extracts local spatial features (such as edges and textures) to capture the sensitive areas of polishing to the pattern layout, and can output a high-dimensional feature vector (for example, 128 dimensions). The feature fusion layer is used to fuse the feature vector output by the convolutional neural network channel and the feature vector output by the fully connected neural network channel to generate a target vector. The prediction layer is actually a fully connected layer that can map the target features to the simulation results (such as height deviation and material removal rate).

[0050] The processing result obtained in step 103 can be used to compare with the simulation result to optimize the model parameters of the dual-channel fusion network model according to the comparison result. When the difference between the processing result and the simulation result is within the threshold, the model training is considered to be completed and the CMP simulation model is obtained.

[0051] The specific structures of the fully connected neural network channel and the convolutional neural network channel can be set according to actual conditions, and this embodiment does not limit them.

[0052] It is understandable that since all training data are generated under fixed process parameters, the model learns the mapping relationship between the features and simulation results under these parameters through training, and the influence of the process parameters is "encoded" into the weights of the model. In actual applications, the model defaults to the same process parameters as during training, and users do not need to enter additional process parameters. If the parameters need to be changed, the model needs to be retrained or adjusted through transfer learning.

[0053] In some embodiments, during the training process of the dual-channel fusion network model, an Adam or SGD optimization algorithm may be used for gradient descent optimization to improve the convergence speed and prevent overfitting.

[0054] In addition, the dual-channel fusion network model can use mean square error as the loss function and use mean square error to optimize the neural network weights.

[0055] After the CMP simulation model training is completed, the CMP simulation model can be encapsulated as a Python library or REST API and connected to a CMP simulation platform (such as COMSOL).

[0056] In summary, the CMP simulation model construction method provided by the embodiment of the present application includes obtaining a test layout of a test chip, wherein the test layout has several areas, each area having different pattern densities, line widths and gaps; converting the pattern information of each area into two-dimensional features, and extracting one-dimensional features of each area through a physical model; performing CMP process processing on the test layout using fixed process parameters to obtain processing results; using one-dimensional features, two-dimensional features and processing results as training data to train a dual-channel fusion network model to obtain a CMP simulation model. This solution can provide more stable input information by designing areas with different pattern densities, pattern widths, and pattern gaps, and combining one-dimensional features extracted by physical models, thereby reducing the dependence of the neural network on the distribution of training data and improving generalization capabilities. In addition, the introduction of one-dimensional features enables the neural network to maintain a high prediction accuracy even when data is insufficient, avoiding excessive reliance on large-scale training data.

[0057] In addition, the convolutional neural network channel is responsible for processing two-dimensional features and extracting pattern structure features in local areas, which can improve adaptability to different pattern structures. The fully connected neural network channel is responsible for processing one-dimensional features extracted from the physical model, which can enhance the understanding of global parameters and avoid the model relying only on local morphology. By fusing the outputs of the fully connected neural network channel and the convolutional neural network channel, the prediction accuracy and model stability of the CMP simulation model can be improved, while avoiding the problem of neural network overfitting.

[0058] See also Figure 3 , Figure 3 : is a flow chart of the CMP process simulation method provided in the embodiment of the present application. The specific flow of the CMP process simulation method can be as follows: 201. Obtain a chip layout of a chip to be simulated, and divide the chip layout into a plurality of grids.

[0059] In some embodiments, the chip layout may be divided into regular grids, for example, the chip may be divided into regular grids according to a fixed size (eg, 10 μm×10 μm or 50 μm×50 μm).

[0060] In some embodiments, the chip layout may also be adaptively meshed, for example, using smaller meshes for high-density areas and larger meshes for low-density areas to improve computational efficiency.

[0061] 202. Convert the pattern information of each grid into a two-dimensional feature, and extract the one-dimensional feature of each grid through a physical model.

[0062] Specifically, the pattern information of each grid is mapped into a grayscale image through an image algorithm to obtain a two-dimensional feature.

[0063] The one-dimensional feature refers to the numerical vector representation of key parameters such as pattern density, line width and gap, for example, density = 80%, line width = 0.2μm, minimum gap = 0.05μm.

[0064] The pattern density can be calculated by the density calculation formula. That is, density = (line width × line length) / area × 100%. For example, if the area of ​​a certain area is 100μm², the total line length is 50μm, and the line width is 0.1μm, then the density = (0.1×50) / 100×100% = 5%.

[0065] The line width and gap can be automatically extracted through image processing algorithms (such as edge detection) to avoid human errors.

[0066] 203. Input the one-dimensional feature and the two-dimensional feature into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector.

[0067] It should be noted that the CMP simulation model is a model constructed by the above-mentioned CMP simulation model construction method. The specific process of constructing the CMP simulation model can refer to the above-mentioned embodiment, which will not be described in detail in this embodiment.

[0068] Specifically, the one-dimensional feature can be input into a fully connected neural network channel to obtain a first feature vector, and the two-dimensional feature can be input into a convolutional neural network channel to obtain a second feature vector.

[0069] 204. Fusing the first feature vector and the second feature vector through a feature fusion layer of the CMP simulation model to generate a target feature vector.

[0070] In some embodiments, the first feature vector and the second feature vector can be directly spliced, for example, the 128-dimensional vector output by the convolutional neural network channel and the 8-dimensional vector output by the fully connected neural network channel can be spliced ​​into a 136-dimensional target feature vector. In some embodiments, the first feature vector and the second feature vector can also be weighted fused.

[0071] 205. Input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0072] It can be understood that by combining all the grid simulation results, a layout simulation result can be obtained.

[0073] In summary, the CMP process simulation method provided by the embodiment of the present application includes obtaining the chip layout of the chip to be simulated, and dividing the chip layout into several grids; converting the pattern information of each grid into two-dimensional features, and extracting the one-dimensional features of each grid through the physical model; inputting the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain the first feature vector and the second feature vector; fusing the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution combines the stability of physical model data with the strong fitting ability of neural networks, thereby making CMP simulation more robust, reducing the overfitting defects of pure neural network modeling, and thus improving the simulation accuracy of the CMP process.

[0074] In order to better implement the CMP simulation model construction method provided in the embodiment of the present application, the embodiment of the present application also provides a CMP simulation model construction device, wherein the meanings of the terms are the same as those in the above CMP simulation model construction method, and the specific implementation details can refer to the description in the method embodiment.

[0075] See also Figure 4 , Figure 4 30 is a schematic diagram of the structure of the CMP simulation model construction device provided in the embodiment of the present application. The CMP simulation model construction device may include a layout extraction unit 301, a feature extraction unit 302, a CMP processing unit 303 and a model training unit 304. The layout extraction unit 301 is used to obtain a test layout of the test chip, where the test layout has a plurality of regions, each region having a different pattern density, line width and gap; A feature extraction unit 302, used to convert the pattern information of each region into a two-dimensional feature, and extract a one-dimensional feature of each region through a physical model; A CMP processing unit 303 is used to perform CMP process on the test layout using fixed process parameters to obtain a process result; The model training unit 304 is used to train the dual-channel fusion network model using the one-dimensional features, the two-dimensional features and the processing results as training data to obtain a CMP simulation model.

[0076] The specific implementation of each of the above units can be found in the above-mentioned embodiment of the CMP process simulation method, which will not be described one by one here.

[0077] In summary, the CMP simulation model construction device provided in the embodiment of the present application obtains the test layout of the test chip through the layout extraction unit 301, and the test layout has several areas, each area has different pattern density, line width and gap; the feature extraction unit 302 converts the pattern information of each area into a two-dimensional feature, and extracts the one-dimensional feature of each area through the physical model; the CMP processing unit 303 uses fixed process parameters to perform CMP process processing on the test layout to obtain the processing result; the model training unit 304 uses the one-dimensional feature, the two-dimensional feature and the processing result as training data to train the dual-channel fusion network model to obtain the CMP simulation model. This solution can provide more stable input information by designing areas with different pattern density, pattern width, and pattern gap, and combining the one-dimensional features extracted by the physical model, reducing the dependence of the neural network on the distribution of training data and improving the generalization ability. In addition, the introduction of one-dimensional features enables the neural network to maintain a high prediction accuracy in the case of insufficient data, avoiding excessive reliance on large-scale training data.

[0078] In order to better implement the CMP process simulation method provided in the embodiment of the present application, the embodiment of the present application also provides a CMP process simulation device, wherein the meanings of the terms are the same as those in the above CMP process simulation method, and the specific implementation details can refer to the description in the method embodiment.

[0079] See also Figure 5 , Figure 5 404 is a schematic diagram of the structure of the CMP process simulation device provided in the embodiment of the present application. The CMP process simulation device may include a layout acquisition unit 401, a feature acquisition unit 402, a feature input unit 403, a feature fusion unit 404 and a CMP simulation unit 405. The layout acquisition unit 401 is used to acquire the chip layout of the chip to be simulated and divide the chip layout into a plurality of grids; A feature acquisition unit 402, used to convert the pattern information of each grid into a two-dimensional feature, and extract a one-dimensional feature of each grid through a physical model; A feature input unit 403 is used to input the one-dimensional feature and the two-dimensional feature into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; A feature fusion unit 404 is used to fuse the first feature vector and the second feature vector through a feature fusion layer of the CMP simulation model to generate a target feature vector; The CMP simulation unit 405 is used to input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0080] The specific implementation of each of the above units can be found in the above-mentioned embodiment of the CMP process simulation method, which will not be described one by one here.

[0081] In summary, the CMP process simulation device provided in the embodiment of the present application obtains the chip layout of the chip to be simulated through the layout acquisition unit 401, and divides the chip layout into several grids; the feature acquisition unit 402 converts the pattern information of each grid into a two-dimensional feature, and extracts the one-dimensional feature of each grid through the physical model; the feature input unit 403 inputs the one-dimensional feature and the two-dimensional feature into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain the first feature vector and the second feature vector; the feature fusion unit 404 fuses the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; the CMP simulation unit 405 inputs the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution combines the stability of physical model data and the strong fitting ability of neural networks to make CMP simulation more robust, reduce the overfitting defects of pure neural network modeling, and thus improve the simulation accuracy of the CMP process.

[0082] The present application also provides an electronic device, in which the CMP process simulation device of the present application can be integrated, such as Figure 6 As shown, it shows a schematic diagram of the structure of the electronic device involved in the embodiment of the present application, specifically: The electronic device may include one or more processors 501 of processing cores and one or more computer-readable storage media memories 502 and other components. Those skilled in the art will appreciate that Figure 6 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. The processor 501 is the control center of the electronic device, and uses various interfaces and lines to connect various parts of the entire electronic device. By running or executing the software program and / or the present application stored in the memory 502, and calling the data stored in the memory 502, the processor 501 performs various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor 501 may include one or more processing cores; preferably, the processor 501 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operation storage medium, user interface and application program, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 501.

[0083] The memory 502 can be used to store software programs and the present application. The processor 501 executes various functional applications and data processing by running the software programs and the present application stored in the memory 502. The memory 502 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating storage medium, an application required for at least one function, etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 502 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 502 may also include a memory controller to provide the processor 501 with access to the memory 502.

[0084] Although not shown, the electronic device may further include a display unit, an input unit, a power supply, etc., which will not be described in detail herein. Specifically in this embodiment, the processor 501 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 502 according to the following instructions, and the processor 501 will run the application programs stored in the memory 502, thereby realizing various functions, as follows: Obtain a chip layout of the chip to be simulated, and divide the chip layout into a number of grids; The pattern information of each grid is converted into a two-dimensional feature, and the one-dimensional feature of each grid is extracted through a physical model; Inputting the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; The first feature vector and the second feature vector are fused through a feature fusion layer of a CMP simulation model to generate a target feature vector; The target feature vector is input into the prediction layer of the CMP simulation model to generate the grid simulation results.

[0085] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0086] To this end, an embodiment of the present application provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any method provided in the embodiment of the present application. For example, the instructions can execute the following steps: Obtain a chip layout of the chip to be simulated, and divide the chip layout into a number of grids; The pattern information of each grid is converted into a two-dimensional feature, and the one-dimensional feature of each grid is extracted through a physical model; Inputting the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; The first feature vector and the second feature vector are fused through a feature fusion layer of a CMP simulation model to generate a target feature vector; The target feature vector is input into the prediction layer of the CMP simulation model to generate the grid simulation results.

[0087] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0088] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0089] Since the instructions stored in the storage medium can execute the steps in any method provided in the embodiments of the present application, the beneficial effects that can be achieved by any method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0090] The CMP process simulation method, device, storage medium and electronic device provided by the present application are respectively introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A CMP process simulation method, characterized in that: include: Obtaining a chip layout of a chip to be simulated, and dividing the chip layout into a plurality of grids; Converting the pattern information of each of the grids into two-dimensional features, and extracting one-dimensional features of each of the grids through a physical model; Inputting the one-dimensional feature and the two-dimensional feature into a fully connected neural network channel and a convolutional neural network channel of a CMP simulation model respectively to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through a feature fusion layer of the CMP simulation model to generate a target feature vector; The target feature vector is input into the prediction layer of the CMP simulation model to generate a grid simulation result.

2. The CMP process simulation method according to claim 1, characterized in that: The converting the pattern information of each grid into a two-dimensional feature comprises: The pattern information of each grid is mapped into a grayscale image through an image algorithm to obtain a two-dimensional feature.

3. The CMP process simulation method according to claim 1, characterized in that: After inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result, the method further includes: All the grid simulation results are combined to obtain a layout simulation result.

4. The CMP process simulation method according to claim 1, wherein: Also includes: Build a CMP simulation model.

5. The CMP process simulation method according to claim 4, characterized in that: The construction of the CMP simulation model comprises: Acquire a test layout of a test chip, wherein the test layout has a plurality of regions, each of the regions having a different pattern density, line width, and gap; Converting the pattern information of each of the regions into two-dimensional features, and extracting one-dimensional features of each of the regions through a physical model; Performing CMP process on the test pattern using fixed process parameters to obtain a process result; The one-dimensional features, the two-dimensional features and the processing results are used as training data to train the dual-channel fusion network model to obtain a CMP simulation model.

6. The CMP process simulation method according to claim 5, characterized in that: The one-dimensional feature, the two-dimensional feature and the processing result are used as training data to train the dual-channel fusion network model to obtain a CMP simulation model, including: The one-dimensional features and the two-dimensional features are used as inputs of a dual-channel fusion network model, the processing results are used as target outputs of the dual-channel fusion model, and the dual-channel fusion network model is trained to obtain a CMP simulation model.

7. The CMP process simulation method according to claim 5, characterized in that: The dual-channel fusion network model uses mean square error as the loss function.

8. A CMP process simulation device, characterized in that: include: A layout acquisition unit, used to acquire a chip layout of a chip to be simulated, and divide the chip layout into a plurality of grids; A feature acquisition unit, used to convert the pattern information of each of the grids into a two-dimensional feature, and extract a one-dimensional feature of each of the grids through a physical model; A feature input unit, used to input the one-dimensional feature and the two-dimensional feature into a fully connected neural network channel and a convolutional neural network channel of a CMP simulation model respectively, to obtain a first feature vector and a second feature vector; A feature fusion unit, configured to fuse the first feature vector and the second feature vector through a feature fusion layer of the CMP simulation model to generate a target feature vector; The CMP simulation unit is used to input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

9. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the CMP process simulation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the CMP process simulation method according to any one of claims 1 to 7 when executing the computer program.

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