Performance checking method and device of integrated circuit, computer equipment and storage medium

Abstract

The invention relates to a performance checking method and device of an integrated circuit, computer equipment and a storage medium. The method comprises the steps that simulation preparation data and circuit data corresponding to the integrated circuit are obtained, the simulation preparation data comprise parameter information of circuit detection nodes, and the circuit detection nodes are located at the input end and the output end of a circuit element; simulation is carried out based on the simulation preparation data and the circuit data, a simulation result is obtained, and the simulation result comprises simulation data of the circuit detection nodes; based on the simulation result, detecting whether the conversion time of each circuit detection node satisfies a preset condition, the conversion time being the switching time of a high-low level state switching process; and outputting node information of the circuit detection nodes which do not meet the preset condition. By adopting the method, circuit data can be automatically checked, a manual checking step is omitted, and the design efficiency of an integrated circuit is greatly improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202311517914.0, and the original application date is November 15, 2023. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of integrated circuit technology, and in particular to a method, device, computer equipment and storage medium for checking the performance of an integrated circuit. Background Art

[0003] In both digital integrated circuit design and analog integrated circuit design, staff are required to manually check data and modify problematic circuits. This is an iterative process. Every time the verification results do not meet actual requirements, manual inspection and modification must be repeated.

[0004] However, manual circuit inspection is less efficient and may miss some problematic nodes. Summary of the invention

[0005] Based on this, it is necessary to provide a performance inspection method, device, computer equipment and storage medium for integrated circuits to address the above technical problems, which can realize automated inspection of circuits.

[0006] In a first aspect, the present application provides a method for checking performance of an integrated circuit, the method comprising:

[0007] Acquire simulation preparation data and circuit data corresponding to the integrated circuit, wherein the simulation preparation data includes parameter information of circuit detection nodes, and the circuit detection nodes are located at input ends and output ends of circuit elements;

[0008] Perform simulation based on the simulation preparation data and the circuit data to obtain simulation results, wherein the simulation results include simulation data of each circuit detection node;

[0009] Detecting whether the conversion time of each of the circuit detection nodes meets a preset condition based on the simulation result, wherein the conversion time is the switching time of the high-low level state switching process;

[0010] Output node information of circuit detection nodes that do not meet preset conditions.

[0011] In one embodiment, the integrated circuit includes a plurality of cascaded sub-circuits; and the method further includes:

[0012] When the conversion time of the i-th level circuit detection node does not meet the preset conditions, the circuit parameters in the circuit data are adjusted based on the preset optimization rules and the circuit parameters of the i-th level sub-circuit; wherein i is a positive integer greater than 1, the i-th level sub-circuit is a circuit between the i-th level circuit detection node and the i-1-th level circuit detection node, and the levels of the circuit detection nodes increase in sequence from the input end to the output end of the integrated circuit.

[0013] In one embodiment, adjusting the circuit parameters in the circuit data based on the preset optimization rule and the circuit parameters of the i-th level sub-circuit includes:

[0014] In the case that there is a MOS transistor in the i-th sub-circuit, the size parameter of the MOS transistor in the i-th sub-circuit is increased according to a first preset rule.

[0015] In one embodiment, the method further comprises:

[0016] When the conversion time of the first-level circuit detection node does not meet the preset conditions and there are diodes in the first-level sub-circuit, the number of diodes in the first-level sub-circuit is increased according to the second preset rule, wherein the first-level sub-circuit is the circuit between the first-level circuit detection node and the input terminal of the integrated circuit.

[0017] In one embodiment, the method further comprises:

[0018] When the conversion time of the detection node of the i-th level circuit does not meet the preset condition and there is no MOS tube in the i-th level sub-circuit, it is detected whether the conversion time of the detection node of the i-1-th level circuit meets the preset condition.

[0019] In one embodiment, the method further comprises:

[0020] After the circuit data is adjusted, the adjustment information is output; wherein the adjustment information includes the conversion time corresponding to each circuit detection node and the circuit modification information.

[0021] In one embodiment, the detecting whether the conversion time of the circuit detection node meets a preset condition based on the simulation result includes:

[0022] When the difference between the conversion time of the circuit detection node and the preset time value is greater than a preset threshold, it is determined that the circuit detection node does not meet the preset condition.

[0023] In a second aspect, the present application further provides a performance inspection device for an integrated circuit, the device comprising:

[0024] An acquisition module, used for acquiring simulation preparation data and circuit data, wherein the simulation preparation data includes parameter information of circuit detection nodes, and the circuit detection nodes are located at the input end and the output end of the circuit element;

[0025] A simulation module, used to perform simulation based on the simulation preparation data and the circuit data to obtain simulation results;

[0026] A detection module, used for detecting whether the conversion time of each circuit detection node meets a preset condition based on the simulation result, wherein the conversion time is the change time of switching between high and low level states;

[0027] The output module is used to output the node information of the circuit detection nodes that do not meet the preset conditions.

[0028] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned method when executing the computer program.

[0029] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method described above are implemented.

[0030] The above-mentioned integrated circuit performance inspection method, device, computer equipment and storage medium perform simulation based on simulation preparation data and circuit data to obtain simulation results. Since the simulation preparation data includes parameter information of circuit detection nodes, and the circuit detection nodes are located at the input and output ends of circuit elements, the simulation results include the conversion time of each circuit detection node. Based on the simulation results, the conversion time of each circuit detection node is detected to see whether it meets the preset conditions, and the node information of the circuit detection nodes that do not meet the preset conditions is output. The circuit detection nodes with problems can be determined to achieve automatic inspection of the circuit. By automatically checking the circuit data of the corresponding integrated circuit, the manual inspection steps of the staff are omitted, which greatly improves the efficiency of integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a flowchart of the digital IC circuit design process in the related technology;

[0033] Figure 2A flowchart of a digital IC circuit front-end design process in the related art;

[0034] Figure 3 A flowchart of a back-end design process for a digital IC circuit in a related technology;

[0035] Figure 4 A flowchart of an analog IC circuit design process in the related art;

[0036] Figure 5 is a flow chart of a method for inspecting the performance of an integrated circuit in one embodiment;

[0037] Figure 6 A schematic diagram of the principle of conversion time in one embodiment;

[0038] Figure 7 is a flow chart of a method for inspecting the performance of an integrated circuit in another embodiment;

[0039] Figure 8 is a flow chart of a method for inspecting the performance of an integrated circuit in yet another embodiment;

[0040] Fig. 9 is a structural block diagram of a performance inspection device for an integrated circuit in one embodiment;

[0041] Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] In related technologies, such as Figure 1 As shown, the digital IC circuit design process includes front-end design and back-end design.

[0044] like Figure 1 and Figure 2As shown, the front-end design includes: RTL (register transfer level) design, functional simulation, logic synthesis and static timing analysis (STA). RTL design uses hardware description languages ​​such as VHDL, Verilog, and System Verilog to describe the circuit based on the transfer between registers. Functional simulation is usually completed by DV (design verification) engineers, who verify the circuit function by building a test bench. Logic synthesis is the process of converting the behavioral level description of the circuit, especially the RTL level description, into a gate-level expression. That is, translating the code into various actual components. STA applies a specific timing model to analyze whether a specific circuit violates the timing constraints given by the designer.

[0045] In addition to the above steps, front-end design also has a step called digital IC testability design (Design For Test, DFT). As chips become larger and larger, DFT becomes an essential step. After completing the above work, a netlist is generated and handed over to the back-end.

[0046] like Figure 1 and Figure 3 As shown, the back-end design includes: Auto Place and Route (APR), Extract RC, Design Rule Check (DRC) and Layout Circuit Figure 1 Layout Versus Schematic, LVS. First, perform automatic layout and routing, which is usually done by back-end staff. Then extract delay information. Then perform design rule checking. Design rule checking is to check whether the design rules meet the requirements of chip manufacturers, so that chips can be produced correctly. Finally, perform layout circuit Figure 1 Consistency check.

[0047] After the back-end design is completed, a GDSII format file will be generated and handed over to the chip manufacturer for tape-out.

[0048] like Figure 4As shown in the figure, analog IC circuit design includes the following steps: formulating circuit design indicators based on design requirements; selecting corresponding architectures according to circuit design indicators; interactive circuit diagram design. For analog chip design, Verilog code cannot be used for design. This is also the biggest difference between analog design and digital IC design. If it cannot be described in code, only graphical methods can be used to design analog circuits. Circuit simulation is similar to the functional verification in digital IC design. Software simulation is used to check whether the waveform is consistent with the design. Analog layout design is completed manually by layout staff. Layout verification mainly includes design rule checking (DRC), circuit layout comparison check (LVS), circuit extraction (NE) of the layout, electrical rule checking (ERC) and parasitic parameter extraction (PEX). Design rule checking (DRC) is an important tool in layout verification, including design rule checking to check whether the connection spacing, connection width, etc. meet the process requirements. Circuit layout comparison check (LVS) is also called physical verification. Post-simulation, according to the extracted parasitic parameters, software is used to verify whether the desired functions and performance can be achieved. Any errors found in the above process need to be modified repeatedly. Generate a GDS file and hand it over to the chip manufacturer for tape-out.

[0049] In both digital integrated circuit design and analog integrated circuit design, staff are required to manually check data and modify problematic circuits. This is an iterative process. Every time the verification results do not meet actual requirements, manual inspection and modification must be repeated.

[0050] However, manual circuit inspection is less efficient and may miss some problematic nodes.

[0051] In order to solve the above problems, the present application provides a performance inspection method for an integrated circuit. This embodiment is described by applying the performance inspection method to a processing terminal, wherein the terminal may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices may be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc. It can be understood that the method can also be applied to servers, and the server can be implemented with an independent server or a server cluster composed of multiple servers. It can also be applied to a system including a processing terminal and a server, and implemented through the interaction between the processing terminal and the server. As Figure 5 As shown, the performance inspection method of the integrated circuit includes: step S501 to step S504.

[0052] S501: Acquire simulation preparation data and circuit data of a corresponding integrated circuit.

[0053] Wherein, the integrated circuit includes an inverter, and the circuit detection node is located at the input end and the output end of the circuit element. The inverter can be a CMOS inverter, and the CMOS inverter can be composed of two MOS tubes. Wherein, the simulation preparation data can be stored in a simulation preparation file, and the circuit data can be stored in a circuit file. The simulation preparation data includes parameter information of the circuit detection node. The parameter information of the circuit detection node can include position information of the circuit detection node. It should be noted that the circuit detection node located between two adjacent circuit elements is the same circuit detection node.

[0054] S502: Perform simulation based on the simulation preparation data and the circuit data to obtain simulation results, where the simulation results include the conversion time of each circuit detection node.

[0055] Among them, since the simulation preparation data includes parameter information of the circuit detection node, which is located at the input and output ends of the circuit element, simulation is performed based on the simulation preparation data and the circuit data, and the obtained simulation results will include the conversion time of the circuit detection node.

[0056] S503: Detecting whether the conversion time of each circuit detection node meets a preset condition based on the simulation result, wherein the conversion time is the switching time of the high and low level state switching process.

[0057] It should be noted that the conversion time includes at least one of the rise time and the fall time, and the detected conversion time can be both the rise time and the fall time, or one of them. Figure 6 As shown, the rise time can be defined as the time required for point A to rise to point B, and the fall time can be defined as the time required for point D to fall to point C. For example, the rise time can be defined as the time required for 10% voltage amplitude (VDD) to rise to 90% VDD, and the fall time can be defined as the time required for 90% voltage amplitude (VDD) to fall to 90% VDD. In the application, it can also be the time required for other range values ​​to change. For example, the rise time can be defined as the time required for 20% VDD to rise to 80% VDD, and the fall time can be defined as the time required for 80% voltage amplitude VDD to fall to 20% VDD.

[0058] It can be understood that by detecting whether the conversion time of the circuit detection node meets the preset condition, it can be detected whether the circuit performance corresponding to the circuit detection node meets the requirements, thereby realizing automatic detection of the circuit. The preset condition can be set in advance, for example, the preset condition can be a time range, and when the conversion time of the circuit detection node is within the time range, it can be determined that the conversion time of the circuit detection node meets the preset condition.

[0059] S504: Output node information of circuit detection nodes that do not meet preset conditions.

[0060] It can be understood that after outputting the node information of the circuit detection node that does not meet the preset conditions, the staff can use the output node information to determine the node position and the corresponding circuit to be modified, thereby facilitating the staff to adjust the circuit to be modified.

[0061] The above-mentioned integrated circuit performance inspection method performs simulation based on simulation preparation data and circuit data to obtain simulation results. Since the simulation preparation data includes parameter information of circuit detection nodes, and the circuit detection nodes are located at the input and output ends of circuit elements, the simulation results include the conversion time of each circuit detection node. Based on the simulation results, the conversion time of each circuit detection node is detected to determine whether it meets the preset conditions, and the circuit detection nodes with problems can be determined. The node information of the circuit detection nodes that do not meet the preset conditions is output to realize the automatic inspection of the circuit. By automatically checking the circuit data, the manual inspection steps of the staff are omitted, which greatly improves the efficiency of integrated circuit design.

[0062] In one embodiment, in step S502, based on the simulation results, the conversion time of each circuit detection node is detected in turn to see whether it meets the preset conditions, including: based on the simulation results, from the output end to the input end of the integrated circuit, the conversion time of each circuit detection node is detected in turn to see whether it meets the preset conditions.

[0063] The circuit adjustment process needs to be performed in the order from the output end to the input end of the circuit, that is, from the back to the front. Similarly, the order of the circuit inspection process should be the same as the order of the circuit adjustment process, so as to adjust the circuit and optimize the circuit.

[0064] In one embodiment, the integrated circuit includes a plurality of cascaded sub-circuits. The integrated circuit performance inspection method further includes: when the conversion time of the i-th level circuit detection node does not meet the preset conditions, based on the preset optimization rules and the circuit parameters of the i-th level sub-circuit, the circuit parameters in the circuit data are adjusted. Wherein, i is a positive integer greater than 1, the i-th level sub-circuit is a circuit between the i-th level circuit detection node and the i-1-th level circuit detection node, and the levels of the circuit detection nodes are sequentially increased from the input end to the output end of the integrated circuit.

[0065] Among them, when the conversion time of the i-th level circuit detection node does not meet the preset conditions, the performance of the i-th level subcircuit does not meet the expected requirements. Therefore, it is necessary to adjust the i-th level subcircuit based on the preset optimization rules and the circuit parameters of the i-th level subcircuit, that is, adjust the circuit parameters in the circuit data to change the conversion time of the i-th level circuit detection node.

[0066] In the application, after adjusting the circuit parameters in the circuit data based on the preset optimization rules and the circuit parameters of the i-th level sub-circuit, the following processing can be performed: regardless of whether the conversion time of the i-th level circuit detection node meets the preset conditions, the conversion time of the i-1-th level circuit detection node is detected, thereby avoiding continuous adjustment of the i-th level sub-circuit.

[0067] It can be understood that when the conversion time of the i-th level circuit detection node meets the preset conditions, there is no need to adjust the circuit parameters in the circuit data, and the conversion time of the i-1th level circuit detection node can be directly detected.

[0068] In one embodiment, the circuit parameters in the circuit data are adjusted based on preset optimization rules and the circuit parameters of the i-th level sub-circuit, including: when there is a MOS tube in the i-th level sub-circuit, the size parameters of the MOS tube in the i-th level sub-circuit are increased according to the first preset rule.

[0069] Increasing the size parameter of the MOS tube in the i-th sub-circuit may be to increase the width of the MOS tube while keeping the length of the MOS tube unchanged. Increasing the size parameter of the MOS tube in the i-th sub-circuit according to the first preset rule may be to increase the width of the MOS tube in the i-th sub-circuit by a fixed value, for example, the width of the MOS tube in the i-th sub-circuit is X, the fixed value is Y, and the width of the MOS tube in the i-th sub-circuit is adjusted to X+Y. It may also be to increase the width of the MOS tube in the i-th sub-circuit by a fixed multiple, for example, the width of the MOS tube in the i-th sub-circuit is X, the fixed multiple is n, and the width of the MOS tube in the i-th sub-circuit is adjusted to nX.

[0070] When there is a MOS tube in the i-th sub-circuit, the switching response speed of the MOS tube can be optimized by increasing the size parameters of the MOS tube, thereby optimizing the performance of the i-th sub-circuit and reducing the conversion time of the i-th circuit detection node.

[0071] In one embodiment, the integrated circuit performance inspection method further includes: when the conversion time of the first-stage circuit detection node does not meet the preset condition and there are diodes in the first-stage sub-circuit, the step of increasing the number of diodes in the first-stage sub-circuit according to a second preset rule. The first-stage sub-circuit is a circuit between the first-stage circuit detection node and the circuit input terminal.

[0072] The second preset rule may include the number of diodes to be added and the connection method, which is determined according to actual needs.

[0073] It can be understood that since the size of the MOS tube of the first-level sub-circuit is to be as small as possible, it is difficult to optimize the performance of the i-th sub-circuit by increasing the size parameters of the MOS tube. In the case where there are diodes in the first-level sub-circuit, the number of diodes in the first-level sub-circuit can be increased. The diodes can be equivalent to being composed of multiple MOS tubes. Increasing the number of diodes in the first-level sub-circuit can be equivalent to increasing the number of MOS tubes, which is beneficial to optimizing the performance of the first-level sub-circuit and reducing the conversion time of the detection node of the first-level circuit.

[0074] In one embodiment, the performance inspection method of the integrated circuit also includes: when the conversion time of the i-th level circuit detection node does not meet the preset conditions and there is no MOS tube in the i-th level sub-circuit, detecting whether the conversion time of the i-1th level circuit detection node meets the preset conditions.

[0075] It can be understood that when the conversion time of the detection node of the i-th level circuit does not meet the preset conditions and there is no MOS tube in the i-th level sub-circuit, the i-th level sub-circuit needs to be adjusted, but since there is no MOS tube in the i-th level sub-circuit, it is impossible to optimize the i-th level sub-circuit by optimizing the size of the MOS tube. In this case, the optimization of the i-th level sub-circuit is skipped, and the detection of the next circuit detection node is performed, that is, whether the conversion time of the detection node of the i-1-th level circuit meets the preset conditions.

[0076] In one embodiment, the performance inspection method of the integrated circuit further includes: after the circuit data is adjusted, outputting adjustment information; wherein the adjustment information includes the conversion time corresponding to each circuit detection node and the circuit modification information. The conversion time of the circuit detection node may include at least one of the conversion time before adjustment and the conversion time after adjustment. The circuit modification information may include the size of the modified circuit detection node and the MOS tube before and after modification. In the application, the adjustment information may also include other information, such as the number of MOS tubes.

[0077] Among them, in the above embodiments, after the circuit data is adjusted, the modification information of the circuit and the conversion time of the corresponding circuit detection node can be recorded.

[0078] It can be understood that after the circuit data is adjusted, the adjustment information is output. Since the adjustment information includes the conversion time corresponding to each circuit detection node and the circuit modification information, the circuit modification information can be used to facilitate the staff to determine the circuit modification status, and the conversion time of the circuit detection node can be used to determine the subsequent processing status of the circuit. For example, when the number of circuit detection nodes whose conversion time does not meet the preset conditions is greater than the preset number threshold, the circuit data is processed again using the integrated circuit performance inspection method of any of the above schemes.

[0079] In one embodiment, detecting whether the conversion time of the circuit detection node meets the preset condition based on the simulation result includes: when the difference between the conversion time of the circuit detection node and the preset time value is greater than a preset threshold, determining that the circuit detection node does not meet the preset condition.

[0080] Among them, for the simulated conversion time, a reference value, i.e., a preset time value, can be determined. Therefore, by judging whether the difference between the conversion time of the circuit detection node and the preset time value is greater than a preset threshold, it can be determined whether the conversion time of the circuit detection node is within an acceptable range. If the difference between the conversion time of the circuit detection node and the preset time value is greater than the preset threshold, it can be considered that the conversion time of the circuit detection node deviates too much from the reference value, and it is determined that the circuit detection node does not meet the preset conditions, thereby automatically detecting the circuit detection node that does not meet the requirements.

[0081] Based on the above embodiments, in one embodiment, the present application also provides a performance inspection method for an integrated circuit. Figure 7 As shown, the performance inspection method of the integrated circuit includes the following steps S701 to S708.

[0082] S701: Acquire simulation preparation data and circuit data of a corresponding integrated circuit, wherein the simulation preparation data includes parameter information of a circuit detection node, the integrated circuit includes an inverter, and the circuit detection node is located at an input end and an output end of the circuit element.

[0083] S702: Perform simulation based on the simulation preparation data and the circuit data to obtain simulation results, where the simulation results include simulation data of each circuit detection node.

[0084] S703: Based on the simulation results, the conversion time of each circuit detection node is detected in turn from the output end to the input end of the integrated circuit to see if it meets the preset conditions. When the difference between the conversion time of the circuit detection node and the preset time value is greater than the preset threshold, it is determined that the circuit detection node does not meet the preset conditions, where the conversion time is the switching time of the high and low level state switching process.

[0085] S704: Output node information of circuit detection nodes that do not meet preset conditions.

[0086] S705: When the conversion time of the first-level circuit detection node does not meet the preset conditions and there are diodes in the first-level sub-circuit, increase the number of diodes in the first-level sub-circuit according to the second preset rule, wherein the first-level sub-circuit is a circuit between the first-level circuit detection node and the circuit input terminal.

[0087] S706: When the conversion time of the i-th level circuit detection node does not meet the preset conditions and there is a MOS tube in the i-th level sub-circuit, increase the size parameters of the MOS tube in the i-th level sub-circuit according to the first preset rule; wherein i is a positive integer greater than 1, the i-th level sub-circuit is a circuit between the i-th level circuit detection node and the i-1-th level circuit detection node, and the levels of the circuit detection nodes increase in sequence from the input end to the output end of the integrated circuit.

[0088] S707: When the conversion time of the detection node of the i-th level circuit does not meet the preset condition and there is no MOS tube in the i-th level sub-circuit, detect whether the conversion time of the detection node of the i-1-th level circuit meets the preset condition.

[0089] S708: After the circuit data is adjusted, output adjustment information; wherein the adjustment information includes the conversion time corresponding to each circuit detection node and circuit modification information.

[0090] The above-mentioned integrated circuit performance inspection method performs simulation based on simulation preparation data and circuit data to obtain simulation results. Since the simulation preparation data includes parameter information of circuit detection nodes, and the circuit detection nodes are located at the input and output ends of circuit elements, the simulation results include the conversion time of each circuit detection node. Based on the simulation results, the conversion time of each circuit detection node is detected to determine whether it meets the preset conditions. The circuit detection nodes with problems can be determined, and the node information of the circuit detection nodes that do not meet the preset conditions can be output to realize automatic inspection of the circuit. In addition, by adjusting the circuit corresponding to the problem circuit detection node, automatic optimization of the circuit can be realized. By automatically checking and optimizing circuit data, the manual inspection and optimization steps of the staff are omitted, which greatly improves the efficiency of integrated circuit design.

[0091] Based on the above embodiments, this solution is a performance inspection method for an integrated circuit, such as Figure 8 As shown, the following steps are included:

[0092] Step 1: Record the data detection nodes through simulation preparation files and correctly set the parameters of the data detection nodes.

[0093] Step 2: The processing terminal simulates the circuit file recording the integrated circuit data through simulation software (such as hspice or spectre simulation software) to obtain simulation results.

[0094] Step 3, using the simulation results from the output end to the input end of the integrated circuit (from back to front), check the conversion time of the data detection nodes in sequence.

[0095] Step 4, determine whether the conversion time of the data detection node meets the preset value. If the conversion time of the data detection node meets the preset value, check the next data detection node.

[0096] Step 5: If the conversion time of the data detection node does not meet the preset value, determine whether to print the node information according to the received instruction. If so, output the node information of the data detection node that does not meet the preset value (including the node position and the corresponding conversion time).

[0097] Step 6: Determine whether to automatically optimize the circuit according to the received instruction.

[0098] Step 7: Determine whether the sub-circuit corresponding to the current detection node is a first-level sub-circuit.

[0099] Step 8: If there are diodes in the first-level sub-circuit, increase the number of diodes in the first-level sub-circuit according to a preset rule, wherein the first-level sub-circuit is a circuit between the first-level circuit detection node and the circuit input terminal.

[0100] Step 9: If not, increase the size parameters of the MOS tube in the previous stage sub-circuit at a fixed ratio; wherein the previous stage sub-circuit is the circuit between the current data detection node and the next data detection node.

[0101] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0102] Based on the same inventive concept, the embodiment of the present application also provides an integrated circuit performance inspection device for implementing the integrated circuit performance inspection method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiment of the performance inspection device for one or more integrated circuits provided below can refer to the limitations of the integrated circuit performance inspection method above, and will not be repeated here.

[0103] In an exemplary embodiment, Fig. 9As shown, a performance inspection device 900 for an integrated circuit is provided, comprising: an acquisition module 901, a simulation module 902, a detection module 903 and an output module 904, wherein:

[0104] An acquisition module 901 is used to acquire simulation preparation data and circuit data, wherein the simulation preparation data includes parameter information of circuit detection nodes, and the circuit detection nodes are located at the input end and the output end of the circuit element;

[0105] A simulation module 902 is used to perform simulation based on simulation preparation data and circuit data to obtain simulation results;

[0106] A detection module 903 is used to detect whether the conversion time of each circuit detection node meets a preset condition based on the simulation result, wherein the conversion time is the change time of switching between high and low level states;

[0107] The output module 904 is used to output the node information of the circuit detection nodes that do not meet the preset conditions.

[0108] In one embodiment, the detection module 903 is further used to detect whether the conversion time of each circuit detection node meets a preset condition in sequence from the output end to the input end of the integrated circuit based on the simulation result.

[0109] In one embodiment, the integrated circuit performance inspection device 900 further includes: a first adjustment module. The first adjustment module is used to adjust the circuit parameters in the circuit data based on the preset optimization rules and the circuit parameters of the i-th level sub-circuit when the conversion time of the i-th level circuit detection node does not meet the preset conditions. Wherein, i is a positive integer greater than 1, the i-th level sub-circuit is a circuit between the i-th level circuit detection node and the i-1-th level circuit detection node, and the levels of the circuit detection nodes are sequentially increased from the input end to the output end of the integrated circuit.

[0110] In one embodiment, the first adjustment module is further used to increase the size parameters of the MOS transistor in the i-th level sub-circuit according to a first preset rule when there is a MOS transistor in the i-th level sub-circuit.

[0111] In one embodiment, the integrated circuit performance inspection device 800 further includes: a second adjustment module. The second adjustment module is used to increase the number of diodes in the first-level sub-circuit according to a second preset rule when the conversion time of the first-level circuit detection node does not meet the preset condition and there are diodes in the first-level sub-circuit, wherein the first-level sub-circuit is a circuit between the first-level circuit detection node and the circuit input terminal.

[0112] In one embodiment, the integrated circuit performance inspection device 900 further includes: a judgment module. The judgment module is used to detect whether the conversion time of the i-1th level circuit detection node meets the preset condition when the conversion time of the i-th level circuit detection node does not meet the preset condition and there is no MOS tube in the i-th level sub-circuit.

[0113] In one embodiment, the integrated circuit performance inspection device 900 further includes: an information output module. The output module is used to output adjustment information after the circuit data is adjusted; wherein the adjustment information includes the conversion time corresponding to each circuit detection node and circuit modification information.

[0114] In one embodiment, the detection module 903 is further configured to determine that the circuit detection node does not meet a preset condition when the difference between the switching time of the circuit detection node and a preset time value is greater than a preset threshold.

[0115] Each module in the integrated circuit performance inspection device 900 can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0116] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the integrated circuit performance inspection method described in any of the above schemes are implemented.

[0117] The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.10As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface, the display unit and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WI FI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a performance inspection method of an integrated circuit is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0118] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0119] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the integrated circuit performance inspection method described in any of the above schemes are implemented.

[0120] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0121] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0122] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for inspecting the performance of an integrated circuit, characterized in that: The method comprises: Acquire simulation preparation data and circuit data corresponding to the integrated circuit; wherein the simulation preparation data includes parameter information of a circuit detection node, the parameter information of the circuit detection node includes position information of the circuit detection node, and the circuit detection node is located at an input end and an output end of a circuit element; Perform simulation based on the simulation preparation data and the circuit data to obtain simulation results; wherein the simulation results include the conversion time of each circuit detection node; Detecting whether the conversion time of each of the circuit detection nodes meets a preset condition based on the simulation result, wherein the conversion time is the switching time of the high-low level state switching process; Output node information of circuit detection nodes that do not meet preset conditions.

2. The integrated circuit performance inspection method according to claim 1, characterized in that: The integrated circuit includes a plurality of cascaded sub-circuits; and the method further includes: When the conversion time of the i-th level circuit detection node does not meet the preset conditions, the circuit parameters in the circuit data are adjusted based on the preset optimization rules and the circuit parameters of the i-th level sub-circuit; wherein i is a positive integer greater than 1, the i-th level sub-circuit is a circuit between the i-th level circuit detection node and the i-1-th level circuit detection node, and the levels of the circuit detection nodes increase in sequence from the input end to the output end of the integrated circuit.

3. The integrated circuit performance inspection method according to claim 2, characterized in that: The adjusting the circuit parameters in the circuit data based on the preset optimization rule and the circuit parameters of the i-th level sub-circuit includes: In the case that there is a MOS transistor in the i-th sub-circuit, the size parameter of the MOS transistor in the i-th sub-circuit is increased according to a first preset rule.

4. The integrated circuit performance inspection method according to claim 1, characterized in that: The method further comprises: When the conversion time of the first-level circuit detection node does not meet the preset conditions and there are diodes in the first-level sub-circuit, the number of the diodes in the first-level sub-circuit is increased according to a second preset rule, wherein the first-level sub-circuit is a circuit between the first-level circuit detection node and the input terminal of the integrated circuit.

5. The integrated circuit performance inspection method according to claim 1, characterized in that: The method further comprises: When the conversion time of the detection node of the i-th level circuit does not meet the preset condition and there is no MOS tube in the i-th level sub-circuit, it is detected whether the conversion time of the detection node of the i-1-th level circuit meets the preset condition.

6. The integrated circuit performance inspection method according to any one of claims 2 to 5, characterized in that: The method further comprises: After the circuit data is adjusted, the adjustment information is output; wherein the adjustment information includes the conversion time corresponding to each circuit detection node and the circuit modification information.

7. The integrated circuit performance inspection method according to claim 1, characterized in that: The detecting, based on the simulation result, whether the conversion time of the circuit detection node meets a preset condition comprises: When the difference between the conversion time of the circuit detection node and the preset time value is greater than a preset threshold, it is determined that the circuit detection node does not meet the preset condition.

8. A performance inspection device for an integrated circuit, characterized in that: The device comprises: An acquisition module, used for acquiring simulation preparation data and circuit data, wherein the simulation preparation data includes parameter information of circuit detection nodes, the parameter information of the circuit detection nodes includes position information of the circuit detection nodes, and the circuit detection nodes are located at input ends and output ends of circuit elements; A simulation module, used to perform simulation based on the simulation preparation data and the circuit data to obtain simulation results; A detection module, used for detecting whether the conversion time of each circuit detection node meets a preset condition based on the simulation result, wherein the conversion time is the change time of switching between high and low level states; The output module is used to output the node information of the circuit detection nodes that do not meet the preset conditions.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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