Time sequence prediction method and system based on combined long short-term memory neural network

Abstract

The invention discloses a time sequence prediction method and system based on a combined long short-term memory neural network, and the method comprises the steps: obtaining each time sequence path in a target circuit, dividing each time sequence path into a transmitting clock sub-path, a capturing clock sub-path and a data sub-path, obtaining feature information of each binary body in each sub-path and sequentially splicing the feature information into a feature vector; grouping the feature vectors generated by each sub-path of each time sequence path to obtain grouped feature vectors, and splicing the grouped feature vectors to obtain a feature matrix; constructing a combined long-short-term memory neural network; constructing a main regression network; training a time sequence prediction model constructed by a combined long and short-term memory neural network and a main regression network based on the feature matrix to obtain a trained time sequence prediction model; and predicting a target circuit based on the trained time sequence prediction model to obtain a time sequence deviation value. The method has the advantages of high analysis efficiency, high prediction precision and the like.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit physical design, and in particular to a timing prediction method and system based on a combined long short-term memory neural network. Background Art

[0002] In the physical design of integrated circuits, static timing analysis (STA) is a key step to ensure that the circuit meets the timing constraints. As chip manufacturing processes continue to shrink, parasitic parameters and the number of process corners are growing exponentially, which significantly increases the complexity of design and causes a significant increase in the time and cost of STA. Traditional STA tools take a long time to process large-scale designs and are difficult to cope with the timing analysis requirements under multiple process corners (process, voltage & temperature, referred to as PVT).

[0003] In recent years, the application of machine learning technology in time series analysis has gradually become a research hotspot. Although the existing time series analysis methods based on machine learning have improved the efficiency of time series prediction to a certain extent, they still have the following problems: 1) Insufficient processing capability for long path sequences, which easily leads to gradient vanishing or gradient exploding problems, resulting in reduced analysis accuracy; 2) Insufficient feature extraction fails to fully explore the implicit connections between unit and network features in the temporal path, resulting in low prediction accuracy; 3) The adaptability of multiple process corners is poor and it is difficult to meet the needs of complex designs. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the present invention provides a time series prediction method and system based on a combined long short-term memory neural network with high analysis efficiency and high prediction accuracy.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is: A time series prediction method based on a combined long short-term memory neural network comprises the following steps: Obtain each timing path in the target circuit, divide each timing path into a transmitting clock sub-path, a capturing clock sub-path and a data sub-path, obtain feature information of each binary in each sub-path and sequentially splice them into feature vectors; The feature vectors generated by each subpath of each timing path are grouped to obtain grouped feature vectors, and then the grouped feature vectors are concatenated to obtain a feature matrix; Construct a combined long short-term memory neural network; Construct the main regression network; Based on the feature matrix, the time series prediction model constructed by the combined long short-term memory neural network and the main regression network is trained to obtain a trained time series prediction model; The target circuit is predicted based on the trained timing prediction model to obtain the timing deviation value.

[0006] Preferably, the specific process of sequentially splicing the feature information of each binary in each subpath into a feature vector is as follows: for each subpath, each unit and the line it drives are regarded as a binary, and then the feature information of each binary is sequentially extracted in the order of input to output; wherein the number / length of the feature information is num; Finally, the feature information of each binary in each subpath is concatenated into a feature vector in sequence; the length of the feature vector of the current subpath is N_bi, that is, the number of binary in the current subpath, and the number of feature elements in the current feature vector is N_ele = N_bi × num.

[0007] Preferably, for each subpath, each unit and the line it drives are regarded as a binary body, and then the specific process of extracting the characteristic information of each binary body in sequence from input to output includes: For each subpath, each unit and the line it drives are considered as a binary entity in combination with the logical characteristics; at the beginning of the subpath, if there is no unit, a virtual unit is set, and all its characteristics are filled with the number 0; Define the characteristic information of the unit and the characteristic information of the line; The feature information of each binary is extracted in sequence from input to output; the unit feature information is in the front and the line feature information is in the back, which together constitute a feature vector of a binary, and the feature vector of each binary has the same length.

[0008] Preferably, the characteristic information of the unit includes the threshold voltage Vt of the unit, the channel length Ch of the unit, the driving capability Dr of the unit, the area of ​​the unit, the load capacitance Cl of the unit and the input transition tr of the unit; the characteristic information of the line includes the line resistance, the line capacitance, the number of line deletions, the length of the line and the metal layer of the line.

[0009] Preferably, the feature vectors generated by each subpath of each time series path are grouped, and the specific process of obtaining the grouped feature vectors is as follows: First, the maximum value of the number of dyads N_bi in the three subpaths of each timing path is counted, denoted as N_bi_max; Secondly, according to the size of N_bi_max, set the block size, denoted as bat_size; Again, for each subpath of each timing path, bat_size grouped feature vectors are generated, and each grouped feature vector contains N_bb feature blocks; where N_bb = rounddown(N_bi_max / bat_size) + 1, and rounddown represents a rounding down function; Finally, the extracted feature vectors are normalized to eliminate the dimensional differences between different features.

[0010] Preferably, for each subpath of each timing path, bat_size grouped feature vectors are generated, and each grouped feature vector contains N_bb feature blocks. The specific process is: For each subpath of each timing path, there are N_bi binary bodies. Starting from the features of the first binary body, each bat_size binary body is divided into several blocks, and the number of blocks is N_block = roundup(N_bi / bat_size), where roundup represents the rounding up function; for the N_block block, if the number of binary bodies is less than bat_size, virtual binary bodies are added, and the features corresponding to the virtual binary bodies are all filled with 0; because N_block is not greater than N_bb, N_bb-N_block virtual binary bodies need to be added later, and the corresponding features are all filled with 0; thus, the first grouping feature vector of the subpath is produced; For each subpath of each timing path, there are N_bi binary bodies. A virtual binary body is filled before the first binary body, and its features are all filled with 0. Then, starting from the virtual binary body, it is divided into several blocks per bat_size binary bodies. The number of blocks is N_block = roundup((N_bi+1) / bat_size); where roundup represents a round-up function; for the N_block block, if there are less than bat_size, a virtual binary is added, and the features corresponding to the virtual binary are all filled with 0; since N_block is not greater than N_bb, N_bb-N_block virtual binary bodies need to be added later, and the corresponding features are all filled with 0; thus, the second grouping feature vector of the subpath is produced; if bat_size is equal to 2, end; if bat_size is greater than 2, for each subpath of each timing path, there are N_bi binary bodies, and 2 to bat_size-1 virtual binary bodies are filled before the first binary, and in accordance with this step, subsequent grouping feature vectors to the bat_sizeth are produced by analogy.

[0011] Preferably, the specific process of constructing a combined long short-term memory neural network is as follows: the number of layers of the combined network is set to Lc, and the number of long short-term memory units in each layer of the combined network is N_lstm = bat_size × N_bb × 2; wherein bat_size is the number of grouped feature vectors, and N_bb is the number of feature blocks in each grouped feature vector; Each layer of the combined network is divided into bat_size groups, and each group is connected according to the bidirectional LSTM network rules. The input of the bottom layer of the combined network corresponds to the bat_size grouped feature vectors of each timing path; Combine the first hidden state data of the top layer network h 1 And the last hidden state data h n spliced ​​together as the output of the combined long short-term memory neural network; where n=N_bb; The specific process of constructing the main regression network is as follows: using a multi-layer perceptron as the main framework of the main regression network; configuring regularization layers for the last two layers of the main regression network, and configuring activation functions for each layer; The input of the main regression network is the output of the combined long short-term memory neural network corresponding to the three sub-paths of each temporal path Ψ (cx), establish or maintain time constraint Tsh, clock period Tc of timing path check timing, and current PVT angle information, which is composed of four parts; the output of the main regression network corresponds to the timing deviation value of the timing path.

[0012] Preferably, each layer of the combined network is divided into bat_size groups, and each group is connected according to the bidirectional LSTM network rule, wherein the input of the bottom layer of the combined network corresponds to the bat_size grouped feature vectors of each timing path. The specific process is: Group each layer of the combined network: divide each layer of the combined network into bat_size groups, and the group name is Li_gj, where i represents the number of layers and j represents the number of groups; Perform intra-group connections on each layer of the combined network; Perform inter-group connections for each layer of the combined network: For the output of each LSTM unit in the j-th group network in the i-th layer h t , connect it to the input of the corresponding LSTM unit in the jth group network in the i+1th layer x t superior; Configure the first layer of combined network input: the input of the first layer j group network x t is the j-th eigenvector matrix.

[0013] Preferably, the specific process of performing intra-group connection on each layer of the combined network is as follows: for the j-th group network of the i-th layer, the output of the t-th forward LSTM unit is connected to C t , h t and the input of the t+1th forward LSTM unit C (t+1)-1 ,h (t+1)-1 Connect them separately and connect the output of the tth reverse LSTM unit C t , h t and the input of the t-1th reverse LSTM unit C (t-1)-1 , h (t-1)-1 connected separately; A single LSTM unit consists of a forget gate, a memory gate, and an output gate, and its input is three variables C t-1 , h t-1 , x t , the output is C t , h t ; The bidirectional LSTM unit is composed of two LSTM units, where the forward LSTM unit is used for forward propagation and the reverse LSTM unit is used for reverse propagation.

[0014] The present invention also discloses a time series prediction system based on a combined long short-term memory neural network, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and when the computer program is run by the processor, the steps of the method described above are executed.

[0015] Compared with the prior art, the advantages of the present invention are: The present invention is based on a timing prediction method and system of a combined long short-term memory neural network, which is applied to the field of chip design and EDA technology, and uses a trained model to perform timing prediction, thereby automatically extracting timing path features and combining process angle information to perform timing prediction under multiple process angles, greatly improving the efficiency of timing analysis, and greatly enhancing the timing analysis capability of long path sequences. By grouping long timing paths by binary bodies, the shortcomings of the traditional LSTM method in processing long sequences are effectively overcome; at the same time, by grouping features, the connection features between binary bodies in the binary grouping and the implicit continuity between the features are effectively mined, improving the accuracy of timing prediction; and by introducing process angle information, accurate timing prediction can be performed under different process angles, meeting the design requirements of digital integrated circuits under multi-mode and multi-process angles, and accelerating the STA process of integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The flowchart of the timing prediction method in an embodiment of the present invention.

[0017] Figure 2Schematic diagram of grouping feature vectors of the time series prediction method of the present invention.

[0018] Figure 3 Schematic diagram of the structure of the LSTM unit in the present invention.

[0019] Figure 4 This is a schematic diagram of the structure of the first layer combined long short-term memory neural network in the present invention. DETAILED DESCRIPTION

[0020] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] like Figure 1 As shown, the time series prediction method based on the combined long short-term memory neural network provided by the embodiment of the present invention includes the steps of: S101, extract the feature vector of the timing path: For each timing path in the target circuit Cir, firstly, the timing path is divided into a transmitting clock sub-path, a capturing clock sub-path and a data sub-path; Secondly, for each subpath, each unit (logic unit or storage unit) in each subpath and the line it drives are regarded as a binary body, and then the feature information of each binary body is extracted in sequence from input to output; the number / length of the feature information is num; Finally, the feature information of each dyad in each subpath is sequentially concatenated into a feature vector; the length of the feature vector of the current subpath is N_bi, that is, the number of dyads in the current subpath, and the number of feature elements in the current feature vector is N_ele = N_bi × num; S102, performing feature grouping: first, calculating the maximum value of the number of dyads N_bi in the three sub-paths in each time series path, recorded as N_bi_max; Secondly, according to the size of N_bi_max, set the batch size, denoted as bat_size, and its value range is recommended to be between 2 and 10; Again, for each subpath of each timing path, bat_size grouped feature vectors are generated, and each grouped feature vector contains N_bb feature blocks; where N_bb = rounddown(N_bi_max / bat_size) + 1, and rounddown represents a rounding down function; Finally, the extracted feature vectors are normalized to eliminate the dimensional differences between different features.

[0022] S103, constructing a combined long short-term memory neural network (referred to as the combined network); specifically, setting the number of layers of the combined network to Lc, and it is recommended that the value of Lc be no less than 3, and the number of long short-term memory (LSTM) units in each layer of the combined network to N_lstm = bat_size × N_bb × 2; Each layer of the combined network is divided into bat_size groups, and each group is connected according to the bidirectional LSTM network rules. The input of the bottom layer of the combined network corresponds to the bat_size grouped feature vectors of each timing path; Combine the first hidden state data of the top layer network h 1 And the last hidden state data h n spliced ​​together as the output of the combined long short-term memory neural network; where n=N_bb; S104, constructing the main regression network: using a multi-layer perceptron as the main framework of the main regression network, the number of layers can be determined according to the specific situation, generally more than 3 layers; configuring regularization layers for the last two layers, and configuring activation functions for each layer; The input of the main regression network is the output of the combined long short-term memory neural network corresponding to the three sub-paths of each temporal path Ψ (cx), establish or maintain time constraint Tsh, the clock period Tc of the timing path check timing, and the current PVT (process, voltage and temperature, referred to as PVT) angle information. The output of the main regression network is the timing deviation value (slack) of the timing path.

[0023] S105, perform model training: select several circuit modules {Cir 1 、……、Cir k}, k is any integer greater than or equal to 1, and the specific number may be determined according to the resources and target efficiency; for each circuit module, the characteristics of the timing path are extracted, and the specific operation is the same as S101; For each circuit module, the extracted features are grouped, and the specific operation is the same as S102; The group feature vectors corresponding to the selected k circuit modules are spliced ​​into bat_size feature matrices; for the k circuit modules, the timing deviation values ​​of each timing path are extracted and spliced ​​into a vector y as the label for model training; Select mean square error (MSE) as the loss function, use Adam optimizer with L2 regularization to optimize the model, so as to fit the relationship between bat_size feature matrices and label y, and finally record the trained model as time series prediction model my_model; S106, use the trained timing prediction model to perform timing prediction; specifically, for the target circuit Cir, the grouped feature vectors generated in S102 are concatenated into bat_size feature matrices, which are input into the timing prediction model my_model, and the fitted timing deviation value yp is output.

[0024] In step S101, for each subpath, each unit and the line it drives are regarded as a binary body, and then the feature information of each binary body is extracted in sequence from input to output. The specific process includes: S1011, for each sub-path, each unit and the line it drives are considered as a binary body in combination with the logical characteristics; for the beginning of the sub-path, if there is no unit, a virtual unit is set, and all its characteristics are filled with the number 0; S1012, defining characteristic information of the cell, generally including the threshold voltage Vt of the cell, the channel length Ch of the cell, the driving capability Dr of the cell, the area of ​​the cell, the load capacitance Cl of the cell, the input transition tr of the cell and other appropriate parameters; S1013, defining characteristic information of the line, generally including line resistance, line capacitance, number of lines to be deleted, line length, metal layer of the line, and other appropriate parameters; S1014, extracting feature information of each binary in order from input to output; wherein the unit feature information is in the front and the line feature information is in the back, together forming a feature vector of a binary, and the feature vector of each binary has the same length.

[0025] In step S102, for each subpath of each time series path, bat_size group feature vectors are generated, and each group feature vector contains N_bb feature blocks. The specific process includes: S1021, for each subpath of each timing path, there are N_bi binary bodies, starting from the features of the first binary body, each bat_size binary body is divided into several blocks, and the number of blocks is N_block = roundup(N_bi / bat_size), where roundup represents the rounding up function. For the N_block block, if the number of binary bodies is less than bat_size, virtual binary bodies are added, and the features corresponding to the virtual binary bodies are all filled with 0; because N_block is not greater than N_bb, N_bb-N_block virtual binary bodies need to be added later, and the corresponding features are all filled with 0; thus, the first grouping feature vector of the subpath is generated; S1022, for each subpath of each timing path, there are N_bi binary bodies, a virtual binary body is filled before the first binary body, and its features are all filled with 0, and then starting from the virtual binary body, each bat_size binary body is divided into several blocks, and the number of blocks is N_block = roundup((N_bi+1) / bat_size); where roundup represents the upward rounding function. For the N_block block, if Figure 2 As shown, there are only 2 binary bodies, which is less than bat_size. A virtual binary is added, and the features corresponding to the virtual binary are all filled with 0. Since N_block is not greater than N_bb, N_bb-N_block virtual binary bodies need to be added later, and the corresponding features are all filled with 0. This produces the second grouping feature vector of the subpath. If bat_size is equal to 2, end. S1023, if bat_size is greater than 2, for each subpath of each timing path, there are N_bi dyads, fill 2 to (bat_size-1) virtual dyads before the first dyad, and generate subsequent bat_size-th grouping feature vectors in the same manner as step S1022. The three grouping feature vectors finally generated in this embodiment are as follows Figure 2 shown.

[0026] In step S103, each layer of the combined network is divided into bat_size groups, and each group is connected according to the bidirectional LSTM network rule, wherein the input of the bottom layer of the combined network corresponds to the bat_size grouped feature vectors of each timing path. The specific process includes: S1031, grouping each layer of the combined network: divide each layer of the combined network into bat_size groups, and the group name is recorded as Li_gj, where i represents the number of layers, j represents the number of groups, and j ranges from 1 to bat_size; S1032, perform intra-group connection on each layer of the combined network: Figure 3 As shown in Figure 1, a single LSTM unit is composed of standard structural functions such as forget gate, memory gate and output gate. Its input is three variables, which are the unit state of the previous time step. C t-1 , the hidden state of the previous time step h t-1 , the input of the current time step x t , whose output is the cell state at the current time step C t , the hidden state at the current time step h t ; The bidirectional LSTM unit is composed of two LSTM units, where the forward LSTM unit is used for forward propagation and the reverse LSTM unit is used for reverse propagation; for the j-th group (i.e., Li_gj) network of the i-th layer, the output of the t-th forward LSTM unit is C t , h t and the input of the t+1th forward LSTM unit C (t+1)-1 , h (t+1)-1 Connect them separately and connect the output of the tth reverse LSTM unit C t , h t and the input of the t-1th reverse LSTM unit C (t-1)-1 , h (t-1)-1 connected separately; Figure 4 As shown, in this embodiment, the layer 1 combined network is composed of L1_g1, L1_g2, and L1_g3; S1033, perform inter-group connections on each layer of the combined network: for the output of each LSTM unit in the j-th group (i.e., Li_gj) in the i-th layer h t , connect it to the input of the corresponding LSTM unit in the jth group (i.e., L{i+1}_gj) network in the i+1th layer x t superior; S1034, configure the first layer combination network input: the first layer j group (ie L1_gj) network input x t is the j-th eigenvector matrix.

[0027] The present invention is based on a timing prediction method and system of a combined long short-term memory neural network, which is applied to the field of chip design and EDA technology, and uses a trained model to perform timing prediction, thereby automatically extracting timing path features and combining process angle information to perform timing prediction under multiple process angles, greatly improving the efficiency of timing analysis, and greatly enhancing the timing analysis capability of long path sequences. By grouping long timing paths by binary bodies, the shortcomings of the traditional LSTM method in processing long sequences are effectively overcome; at the same time, by grouping features, the connection features between binary bodies in the binary grouping and the implicit continuity between the features are effectively mined, improving the accuracy of timing prediction; and by introducing process angle information, accurate timing prediction can be performed under different process angles, meeting the design requirements of digital integrated circuits under multi-mode and multi-process angles, and accelerating the STA process of integrated circuit design.

[0028] The embodiment of the present invention also provides a time series prediction system based on a combined long short-term memory neural network, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the steps of the above method are executed. The prediction system of the present invention corresponds to the above prediction method and also has the advantages described in the above method.

[0029] The present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiment can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable storage media include: any entity or device that can carry computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing computer programs and / or modules stored in the memory, and calling data stored in the memory. The memory may include a high-speed random access memory and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0030] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A time series prediction method based on a combined long short-term memory neural network, characterized in that: Includes steps: Obtain each timing path in the target circuit, divide each timing path into a transmitting clock sub-path, a capturing clock sub-path and a data sub-path, obtain feature information of each binary in each sub-path and sequentially splice them into feature vectors; The feature vectors generated by each subpath of each timing path are grouped to obtain grouped feature vectors, and then the grouped feature vectors are concatenated to obtain a feature matrix; Construct a combined long short-term memory neural network; Construct the main regression network; Based on the feature matrix, the time series prediction model constructed by the combined long short-term memory neural network and the main regression network is trained to obtain a trained time series prediction model; The target circuit is predicted based on the trained timing prediction model to obtain the timing deviation value.

2. The time series prediction method based on combined long short-term memory neural network according to claim 1 is characterized in that: The specific process of sequentially concatenating the feature information of each binary in each subpath into a feature vector is as follows: for each subpath, each unit and the line it drives are considered as a binary, and then the feature information of each binary is sequentially extracted in the order from input to output; wherein the number / length of the feature information is num; Finally, the feature information of each binary in each subpath is concatenated into a feature vector in sequence; the length of the feature vector of the current subpath is N_bi, that is, the number of binary in the current subpath, and the number of feature elements in the current feature vector is N_ele = N_bi × num.

3. The time series prediction method based on combined long short-term memory neural network according to claim 2 is characterized in that: For each subpath, each unit and the line it drives are considered as a binary body, and then the specific process of extracting the feature information of each binary body in the order of input to output includes: For each subpath, each unit and the line it drives are considered as a binary entity in combination with the logical characteristics; at the beginning of the subpath, if there is no unit, a virtual unit is set, and all its characteristics are filled with the number 0; Define the characteristic information of the unit and the characteristic information of the line; The feature information of each binary is extracted in sequence from input to output; the unit feature information is in the front and the line feature information is in the back, which together constitute a feature vector of a binary, and the feature vector of each binary has the same length.

4. The time series prediction method based on combined long short-term memory neural network according to claim 3 is characterized in that: The characteristic information of the cell includes the threshold voltage Vt of the cell, the channel length Ch of the cell, the driving capability Dr of the cell, the area of ​​the cell, the load capacitance Cl of the cell and the input transition tr of the cell; the characteristic information of the line includes the line resistance, the line capacitance, the number of line deletions, the length of the line and the metal layer of the line.

5. The time series prediction method based on combined long short-term memory neural network according to any one of claims 1 to 4, characterized in that: The specific process of grouping the feature vectors generated by each subpath of each time series path to obtain the grouped feature vectors is as follows: First, the maximum value of the number of dyads N_bi in the three subpaths of each timing path is counted, denoted as N_bi_max; Secondly, according to the size of N_bi_max, set the block size, denoted as bat_size; Again, for each subpath of each timing path, bat_size grouped feature vectors are generated, and each grouped feature vector contains N_bb feature blocks; where N_bb = rounddown(N_bi_max / bat_size) + 1, and rounddown represents a rounding down function; Finally, the extracted feature vectors are normalized to eliminate the dimensional differences between different features.

6. The time series prediction method based on combined long short-term memory neural network according to claim 5 is characterized in that: For each subpath of each timing path, the specific process of generating bat_size grouped feature vectors, each of which contains N_bb feature blocks, is as follows: For each subpath of each timing path, there are N_bi binary bodies. Starting from the features of the first binary body, each bat_size binary body is divided into several blocks, and the number of blocks is N_block = roundup(N_bi / bat_size), where roundup represents the rounding up function; for the N_block block, if the number of binary bodies is less than bat_size, virtual binary bodies are added, and the features corresponding to the virtual binary bodies are all filled with 0; because N_block is not greater than N_bb, N_bb-N_block virtual binary bodies need to be added later, and the corresponding features are all filled with 0; thus, the first grouping feature vector of the subpath is produced; For each subpath of each timing path, there are N_bi binary bodies. A virtual binary body is filled before the first binary body, and its features are all filled with 0. Then, starting from the virtual binary body, it is divided into several blocks per bat_size binary bodies. The number of blocks is N_block = roundup((N_bi+1) / bat_size); where roundup represents a round-up function; for the N_block block, if there are less than bat_size, a virtual binary is added, and the features corresponding to the virtual binary are all filled with 0; since N_block is not greater than N_bb, N_bb-N_block virtual binary bodies need to be added later, and the corresponding features are all filled with 0; thus, the second grouping feature vector of the subpath is produced; if bat_size is equal to 2, end; if bat_size is greater than 2, for each subpath of each timing path, there are N_bi binary bodies, and 2 to bat_size-1 virtual binary bodies are filled before the first binary, and in accordance with this step, subsequent grouping feature vectors to the bat_sizeth are produced by analogy.

7. The time series prediction method based on combined long short-term memory neural network according to any one of claims 1 to 4, characterized in that: The specific process of constructing a combined long short-term memory neural network is: Set the number of layers of the combined network to Lc, and the number of long short-term memory units in each layer of the combined network to N_lstm = bat_size × N_bb × 2; where bat_size is the number of grouped feature vectors, and N_bb is the number of feature blocks in each grouped feature vector; Each layer of the combined network is divided into bat_size groups, and each group is connected according to the bidirectional LSTM network rules. The input of the bottom layer of the combined network corresponds to the bat_size grouped feature vectors of each timing path; Combine the first hidden state data of the top layer network h 1 and the last hidden state data h n spliced ​​together as the output of the combined long short-term memory neural network; where n=N_bb; The specific process of constructing the main regression network is as follows: using a multi-layer perceptron as the main framework of the main regression network; configuring regularization layers for the last two layers of the main regression network, and configuring activation functions for each layer; The input of the main regression network is the output of the combined long short-term memory neural network corresponding to the three sub-paths of each temporal path Ψ (cx), establish or maintain time constraint Tsh, clock period Tc of timing path check timing, and current PVT angle information, which is composed of four parts; the output of the main regression network corresponds to the timing deviation value of the timing path.

8. The time series prediction method based on combined long short-term memory neural network according to claim 7 is characterized in that: Each layer of the combined network is divided into bat_size groups, and each group is connected according to the bidirectional LSTM network rules. The specific process of the input of the bottom layer combined network corresponding to the bat_size grouped feature vectors of each timing path is: Group each layer of the combined network: divide each layer of the combined network into bat_size groups, and the group name is recorded as Li_gj, where i represents the number of layers and j represents the number of groups; Perform intra-group connections on each layer of the combined network; Perform inter-group connections for each layer of the combined network: For the output of each LSTM unit in the j-th group network in the i-th layer h t , connect it to the input of the corresponding LSTM unit in the jth group network in the i+1th layer x t superior; Configure the first layer of combined network input: the input of the first layer j group network x t is the j-th eigenvector matrix.

9. The time series prediction method based on combined long short-term memory neural network according to claim 8 is characterized in that: The specific process of intra-group connection for each layer of combined network is as follows: for the j-th group network of the i-th layer, the output of the t-th forward LSTM unit is connected to C t , h t and the input of the t+1th forward LSTM unit C (t+1)-1 , h (t+1)-1 Connect them separately and connect the output of the tth reverse LSTM unit C t , h t and the input of the t-1th reverse LSTM unit C (t-1)-1 , h (t-1)-1 connected separately; A single LSTM unit consists of a forget gate, a memory gate, and an output gate, and its input is three variables C t-1 , h t-1 , x t , the output is C t , h t ; The bidirectional LSTM unit is composed of two LSTM units, where the forward LSTM unit is used for forward propagation and the reverse LSTM unit is used for reverse propagation.

10. A time series prediction system based on a combined long short-term memory neural network, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 9.

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