OPC Correction Methods to Improve Publishing Efficiency

Abstract

This invention provides an OPC correction method to improve publishing efficiency. The method includes: providing a postOPC layout, which includes a standard graphic area and a non-standard graphic area surrounding the standard graphic area. The standard graphic area has a standard graphic and a marker graphic covering the entire standard graphic area; expanding the marker graphic outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area; extracting the standard graphic area and the visible graphic area to obtain a first sub-graphic, and the remaining other areas including only the main graphic of the non-standard graphic area; performing data layering processing on the first sub-graphic to obtain a second sub-graphic; performing OPC correction on the second sub-graphic to obtain a third sub-graphic; extracting a mask graphic from the third sub-graphic where only the standard graphic area reaches the target value after OPC correction; and merging the mask graphic with the main graphic to obtain a new complete layout. This invention solves the problem of low publishing efficiency in existing layouts.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an OPC correction method to improve publishing efficiency. Background Technology

[0002] Model-based OPC correction methods play a crucial role in resolution enhancement technology. OPC tools can reduce edge position errors by moving the edges of the layout graphics. However, in the advanced process OPC development phase, timelines are tight, tasks are heavy, processes are complex, and upper and lower layers need to work together, making it difficult to provide timely feedback on inline detection and evaluation results. OPC often faces situations where the standard pattern needs to be adjusted near the target of the final product (TO). In such cases, the full chip needs to rerun OPC. However, if the full chip rerun of OPC takes a long time, it will result in low publication efficiency. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an OPC correction method to improve publishing efficiency and solve the problem of low publishing efficiency in existing map publishing.

[0004] To achieve the above and other related objectives, the present invention provides an OPC correction method to improve publication efficiency, the method comprising:

[0005] A postOPC layout is provided, which includes a standard graphic area and a non-standard graphic area located around the standard graphic area, wherein the standard graphic area has a standard graphic and a marker graphic covering the entire standard graphic area;

[0006] The marked graphic is expanded outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area;

[0007] The standard graphic area and the visible graphic area are extracted to obtain a first sub-graphic that includes the standard graphic area and the visible graphic area, and the remaining other areas only include the main graphic that includes the non-standard graphic area;

[0008] The first sub-graphic is subjected to data layer transfer processing to obtain a second sub-graphic that includes the standard graphic and the postOPC graphic, wherein the postOPC graphic is the graphic located in the visible graphic area;

[0009] The second sub-part graphic is modified by OPC to obtain the third sub-part graphic, wherein the third sub-part graphic includes a mask graphic obtained by modifying the standard graphic;

[0010] Extract the mask pattern from the third sub-part graphic, which only reaches the target value after OPC correction of the standard graphic area;

[0011] The mask graphic is merged with the main graphic to obtain a new complete layout.

[0012] Optionally, the method of expanding the marked graphic outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area includes:

[0013] Expand the marked pattern outward by 2 μm.

[0014] Optionally, the visible graphic area is annular, and the area is defined to the OPCblock layer.

[0015] Optionally, the method for performing data layer transformation processing on the first sub-graphic to obtain a second sub-graphic including the standard graphic and the postOPC graphic includes:

[0016] Distinguish between the standard graphic area and the visible graphic area, and extract the standard graphic and the postOPC graphic respectively;

[0017] The standard graphic and the postOPC graphic are merged into the same layer to obtain the second sub-graphic.

[0018] Optionally, when performing OPC correction on the third sub-graphic, only the standard graphic is corrected.

[0019] Optionally, the method further includes the steps of performing OPC checks and layout repairs on the new complete layout.

[0020] Optionally, when repairing the new complete layout, the layout repair is performed on the mask graphic at the boundary of the marked graphic.

[0021] Optionally, the standard graphic is a simple repeating graphic.

[0022] Optionally, the standard graphics include SRAM graphics.

[0023] Optionally, applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.

[0024] As described above, the OPC correction method of the present invention for improving publishing efficiency can reduce the OPC processing area, and the standard graphic is a simple repeating graphic. Compared with rerunning the OPC globally on the complete layout, it can shorten the OPC calculation and processing time by 50% to 70% while ensuring the same quality, thereby shortening the publishing process and improving OPC publishing efficiency. Attached Figure Description

[0025] Figure 1 The flowchart shown is a process for improving OPC correction efficiency according to the present invention. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] like Figure 1 As shown, this embodiment provides an OPC correction method to improve publishing efficiency, the method comprising:

[0029] A postOPC layout is provided, which includes a standard graphic area and a non-standard graphic area located around the standard graphic area, wherein the standard graphic area has a standard graphic and a marker graphic covering the entire standard graphic area;

[0030] The marked graphic is expanded outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area;

[0031] The standard graphic area and the visible graphic area are extracted to obtain a first sub-graphic that includes the standard graphic area and the visible graphic area, and the remaining other areas only include the main graphic that includes the non-standard graphic area;

[0032] The first sub-graphic is subjected to data layer transfer processing to obtain a second sub-graphic that includes the standard graphic and the postOPC graphic, wherein the postOPC graphic is the graphic located in the visible graphic area;

[0033] The second sub-part graphic is modified by OPC to obtain the third sub-part graphic, wherein the third sub-part graphic includes a mask graphic obtained by modifying the standard graphic;

[0034] Extract the mask pattern from the third sub-part graphic, which only reaches the target value after OPC correction of the standard graphic area;

[0035] The mask graphic is merged with the main graphic to obtain a new complete layout.

[0036] Specifically, the method of expanding the marked graphic outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area includes: expanding the marked graphic outward by 2μm.

[0037] Specifically, the visible graphic area is ring-shaped and is defined to the OPCblock layer.

[0038] In this embodiment, the purpose of defining the visible graphic area to the OPCblock layer is to facilitate the viewing of the environmental structure of the visible graphic area when performing OPC processing on the standard graphic later.

[0039] Specifically, the method for performing data layer transformation processing on the first sub-graphic to obtain a second sub-graphic including the standard graphic and the postOPC graphic includes: distinguishing the standard graphic area and the visible graphic area, and extracting the standard graphic and the postOPC graphic respectively; merging the standard graphic and the postOPC graphic into the same layer to obtain the second sub-graphic.

[0040] Specifically, when performing OPC correction on the third sub-part graphic, only the standard graphic is corrected.

[0041] Specifically, the method also includes steps of performing OPC checks and layout repairs on the new complete layout.

[0042] Specifically, when repairing the new complete layout, the layout repair is performed on the mask graphic at the boundary of the marked graphic.

[0043] In this embodiment, complete and accurate layout data can be obtained by performing OPC checks on the new complete layout data and performing layout repair on the mask graphics at the boundary of the marked graphics.

[0044] Specifically, the standard graphic is a simple repeating graphic.

[0045] More specifically, the standard pattern includes an SRAM pattern. In this embodiment, the SRAM pattern is a first metal layer line SRAM pattern.

[0046] Specifically, the applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.

[0047] In summary, the OPC correction method of this invention, which improves publishing efficiency, reduces the OPC processing area. Furthermore, the standard graphic is a simple, repeating graphic. Compared to rerunning the entire OPC process globally, this method can shorten the OPC processing time by 50% to 70% while maintaining the same quality, thus shortening the publishing process and improving OPC publishing efficiency. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An OPC correction method to improve publishing efficiency, characterized in that, The method includes: A postOPC layout is provided, which includes a standard graphic area and a non-standard graphic area located around the standard graphic area, wherein the standard graphic area has a standard graphic and a marker graphic covering the entire standard graphic area; The marked graphic is expanded outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area; The standard graphic area and the visible graphic area are extracted to obtain a first sub-graphic that includes the standard graphic area and the visible graphic area, and the remaining other areas only include the main graphic that includes the non-standard graphic area; The first sub-graphic is subjected to data layer transfer processing to obtain a second sub-graphic that includes the standard graphic and the postOPC graphic, wherein the postOPC graphic is the graphic located in the visible graphic area; The second sub-part graphic is modified by OPC to obtain the third sub-part graphic, wherein the third sub-part graphic includes a mask graphic obtained by modifying the standard graphic; Extract the mask pattern from the third sub-part graphic, which only reaches the target value after OPC correction of the standard graphic area; The mask pattern that has reached the target value after OPC correction is merged with the main pattern to obtain a new complete layout.

2. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, The method of expanding the marked graphic outward by a predetermined range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area includes: Expand the marked pattern outward by 2 μm.

3. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, The visual graphic area is ring-shaped and defined to the OPCblock layer.

4. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, The method for performing data layer transformation processing on the first sub-graphic to obtain a second sub-graphic including the standard graphic and the postOPC graphic includes: Distinguish between the standard graphic area and the visible graphic area, and extract the standard graphic and the postOPC graphic respectively; The standard graphic and the postOPC graphic are merged into the same layer to obtain the second sub-graphic.

5. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, When performing OPC correction on the second sub-graphic, only the standard graphic is corrected.

6. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, The method also includes steps of performing OPC checks and layout repairs on the new complete layout.

7. The OPC correction method for improving publishing efficiency according to claim 6, characterized in that, When repairing the new complete layout, the layout repair is performed on the mask graphic at the boundary of the marked graphic.

8. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, The standard graphic is a simple, repeating graphic.

9. The OPC correction method for improving publishing efficiency according to claim 8, characterized in that, The standard graphics include SRAM graphics.

10. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that, Applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.

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