A driving circuit and a driving method, and an array substrate

Abstract

The application provides a driving circuit and a driving method, and an array substrate, and relates to the technical field of display, wherein a trigger signal generation sub-circuit is electrically connected with a first frame start signal input line, a second frame start signal input line and a shift register, is configured to generate an initial light-emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light-emitting control signal to the shift register; at least part of the shift register is configured to generate a target light-emitting control signal according to the trigger signal, and transmit the target light-emitting control signal to a pixel circuit; the initial light-emitting control signal is configured to serve as the trigger signal of the part of the shift register; and the initial light-emitting control signal is a pulse signal with different pulse widths. The driving circuit is simple in design, and the demand of the pixel circuit for the pulse signal with different pulse widths is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a driving method, and an array substrate. Background Art

[0002] With the advancement of display technology, the variety of display products has increased, and performance requirements have also steadily increased. PWM (Pulse Width Modulation) dimming technology, which precisely adjusts the brightness of display panels by adjusting the pulse width, or duty cycle, has attracted widespread attention within the industry. The constant pulse width PWM model, a related technology, offers simple control logic and is easy to implement and integrate into DICs (display driver chips), reducing chip design complexity and cost.

[0003] However, mainstream DIC cannot output VGL pulse signals of unequal widths, which limits its flexibility in achieving some special display effects or complex brightness control. Summary of the Invention

[0004] This application adopts the following technical solutions:

[0005] An embodiment of the present application provides a driving circuit, the driving circuit comprising a trigger signal generating subcircuit and a plurality of shift registers arranged in cascade;

[0006] The trigger signal generating subcircuit is electrically connected to the first frame start signal input line, the second frame start signal input line and the shift register respectively, and is configured to generate an initial light-emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light-emitting control signal to the shift register;

[0007] At least part of the shift register is electrically connected to the pixel circuit, and at least part of the shift register is configured to generate a target light emitting control signal according to a trigger signal and transmit the target light emitting control signal to the pixel circuit;

[0008] The initial light-emitting control signal is configured to be used as a trigger signal for a portion of the shift register; and the initial light-emitting control signal is a pulse signal with different pulse widths.

[0009] In the driving circuit provided in some embodiments of the present application, the pulse width of the first frame start signal is fixed, and the second frame start signal is a frame start signal with a constant pulse width and pulse width modulation information.

[0010] In the driving circuit provided in some embodiments of the present application, the plurality of shift registers include a virtual shift register and n-stage light-emitting control shift registers arranged in cascade, where n is a positive integer;

[0011] The virtual shift register is electrically connected with the trigger signal generation sub-circuit and the first-stage light-emitting control shift register respectively, and the n+1-stage light-emitting control shift register is electrically connected with the n-stage light-emitting control shift register, the n+2-stage light-emitting control shift register and the n+1-row pixel unit respectively;

[0012] The initial light-emitting control signal is configured to serve as a trigger signal of the virtual shift register, the virtual shift register is configured to receive and process the initial light-emitting control signal to obtain a waveform-stable initial light-emitting control signal, and the waveform-stable initial light-emitting control signal is configured to serve as a trigger signal of the first-stage light-emitting control shift register, and the first-stage light-emitting control shift register is configured to receive the waveform-stable initial light-emitting control signal and generate the target light-emitting control signal.

[0013] In the driving circuit provided in some embodiments of the present application, the plurality of shift registers comprises n-stage light-emitting control shift registers arranged in cascade, n being a positive integer;

[0014] The first-stage light-emitting control shift register is electrically connected with the trigger signal generation sub-circuit, the second-stage light-emitting control shift register and the first-row pixel unit respectively;

[0015] The initial light-emitting control signal is configured to serve as a trigger signal of the first-stage light-emitting control shift register, and the first-stage light-emitting control shift register is configured to generate the target light-emitting control signal according to the initial light-emitting control signal;

[0016] The target light-emitting control signal output by the n-stage light-emitting control shift register serves as a trigger signal of the n+1-stage light-emitting control shift register.

[0017] In the driving circuit provided in some embodiments of the present application, the driving circuit further comprises a first clock signal line and a second clock signal line,

[0018] The virtual shift register is electrically connected with an output end of the trigger signal generation sub-circuit, an input end of the first-stage light-emitting control shift register and the first clock signal line respectively;

[0019] The first-stage light-emitting control shift register is electrically connected with an output end of the virtual shift register, an input end of the second-stage light-emitting control shift register, the second clock signal line and the first-row pixel circuit respectively;

[0020] The second-stage light-emitting control shift register is electrically connected with the output end of the first-stage light-emitting control shift register, the input end of the third-stage light-emitting control shift register, the first clock signal line and the pixel circuit in the second row, respectively;

[0021] The m-stage light-emitting control shift register is electrically connected with the output end of the m-1-stage light-emitting control shift register, the input end of the m+1-stage light-emitting control shift register, the second clock signal line and the pixel circuit in the mth row, respectively; m is an odd number and m>1;

[0022] The m+1-stage light-emitting control shift register is electrically connected with the output end of the m-stage light-emitting control shift register, the input end of the m+2-stage light-emitting control shift register, the first clock signal line and the pixel circuit in the m+1th row, respectively.

[0023] In the driving circuit provided in some embodiments of the present application, the trigger signal generation sub-circuit comprises a first transistor and a second transistor,

[0024] The gate of the first transistor is electrically connected with the first frame start signal input line, the source of the first transistor is electrically connected with the second frame start signal input line, and the drain of the first transistor is electrically connected with the output end of the trigger signal generation sub-circuit;

[0025] The gate of the second transistor is electrically connected with the second frame start signal input line, the source of the second transistor is electrically connected with the first frame start signal input line, and the drain of the second transistor is electrically connected with the output end of the trigger signal generation sub-circuit.

[0026] In the driving circuit provided in some embodiments of the present application, the first transistor further comprises a first stable electrode, and the second transistor further comprises a second stable electrode;

[0027] The first stable electrode is electrically connected with the first frame start signal input line, and the second stable electrode is electrically connected with the second frame start signal input line.

[0028] In the driving circuit provided in some embodiments of the present application, the first frame start signal and the second frame start signal are configured to not be high-level signals at the same time.

[0029] In the driving circuit provided in some embodiments of the present application, one display frame comprises one write frame and three hold frames,

[0030] In the write frame, in the first time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the second time period, the first frame start signal is a high level signal, and the second frame start signal is a low level signal; in the third time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the fourth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

[0031] In the driving circuit provided in some embodiments of the present application, in the holding frame, in the fifth time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the sixth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

[0032] In the driving circuit provided in some embodiments of the present application, the first frame start signal and the second frame start signal are configured to be provided separately by a driving chip.

[0033] In the driving circuit provided in some embodiments of the present application, the driving circuit also includes a reset shift register, the first frame start signal is configured to be provided by the driving chip, and the reset shift register and the light-emitting control shift register share the first frame start signal; the second frame start signal is configured to be provided by the driving chip alone.

[0034] In a second aspect, an embodiment of the present application provides a driving method for driving the driving circuit according to any one of the first aspects, the method comprising:

[0035] inputting a first frame start signal and a second frame start signal into the trigger generation subcircuit;

[0036] A clock signal is input to the shift register, where the clock signal is a first clock signal or a second clock signal.

[0037] In a third aspect, an embodiment of the present application provides an array substrate, comprising the driving circuit according to any one of the first aspects, wherein the array substrate comprises:

[0038] substrate, and

[0039] a semiconductor layer, located on one side of the substrate, comprising a semiconductor pattern of a first transistor, a semiconductor pattern of a second transistor, a source and a drain of the first transistor, and a source and a drain of the second transistor in the trigger signal generating subcircuit;

[0040] a first gate layer, located on a side of the semiconductor layer away from the substrate, comprising a gate of the first transistor and a gate of the second transistor;

[0041] A source-drain conductive layer is located on the side of the first gate layer away from the substrate, and includes a first frame start signal input line and a second frame start signal input line.

[0042] In the array substrate provided in some embodiments of the present application, the drain of the first transistor and the drain of the second transistor are shared,

[0043] The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, the source and the drain of the first transistor, and the source and the drain of the second transistor are integrated structures.

[0044] In the array substrate provided in some embodiments of the present application, the gate of the first transistor and the gate of the second transistor are symmetrically distributed with the geometric center of the drain of the first transistor as the symmetric point.

[0045] In the array substrate provided in some embodiments of the present application, the first frame start signal input line partially surrounds one side of the first transistor and the second transistor, and the second frame start signal input line partially surrounds the other side of the first transistor and the second transistor.

[0046] In the array substrate provided in some embodiments of the present application, the array substrate further includes:

[0047] A second gate layer is located between the first gate layer and the source-drain conductive layer, and includes an initial light-emitting control signal output line configured to output the initial light-emitting control signal.

[0048] In the array substrate provided in some embodiments of the present application, one of the first frame start signal input line and the second frame start signal input line overlaps the orthographic projection of the initial light-emitting control signal output line on the substrate.

[0049] In the array substrate provided in some embodiments of the present application, the array substrate further includes:

[0050] A light-shielding conductive layer is located between the substrate and the semiconductor layer, and includes a first stable electrode and a second stable electrode.

[0051] The orthographic projection of the first stable electrode on the substrate covers the gate of the first transistor, and the orthographic projection of the second stable electrode on the substrate covers the gate of the second transistor; the first stable electrode is electrically connected to the first frame start signal input line, and the second stable electrode is electrically connected to the second frame start signal input line.

[0052] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] Figure 1 A schematic structural diagram of a pixel circuit in a related art provided in an embodiment of the present application;

[0055] Figure 2 for Figure 1 Timing diagram of

[0056] Figure 3 for Figure 2 Timing diagram of writing frames in one display frame;

[0057] Figure 4 for Figure 2 A timing diagram of a frame held within a display frame;

[0058] Figure 5 A schematic structural diagram of a driving circuit provided in an embodiment of the present application;

[0059] Figure 6 and Figure 7 A schematic structural diagram of two trigger signal generation sub-circuits provided in an embodiment of the present application;

[0060] Figure 8 for Figure 6 or Figure 7 The timing diagram of the trigger signal generating sub-circuit in the writing frame is shown;

[0061] Figure 9 for Figure 6 or Figure 7 The trigger signal generating sub-circuit shown is a timing diagram of the holding frame;

[0062] Figure 10 for Figure 7 The floor plan of the trigger signal generation subcircuit is shown. DETAILED DESCRIPTION

[0063] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0064] In the embodiments of the present application, the terms "first", "second", "third", "fourth" and the like are used to distinguish the same items or similar items with basically the same functions and effects, only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0065] In the embodiments of the present application, the terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, only for the purpose of facilitating the description of the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0066] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0067] In the embodiments of the present application, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise explicitly specified.

[0068] The features of "parallel", "vertical" and "same" and the like used in the embodiments of the present application include the strictly "parallel", "vertical", "same" and the like, and the "approximately parallel", "approximately vertical", "approximately same" and the like with a certain tolerance, which is determined by the person of ordinary skill in the art within the acceptable deviation range for a specific value considering the measurement and the tolerance related to the measurement of a specific quantity. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0069] Unless otherwise required by the context, the term "comprising" is interpreted to be open, inclusive, meaning "including, but not limited to" in the entire specification and claims.

[0070] The polygons in the present specification are not strictly in the sense that they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and there can be some small deformations due to tolerances.

[0071] In the present specification, "electrically connected" and "coupled" include cases where the constituent elements are connected together through an element having some electrical action.

[0072] PWM, Pulse Width Modulation, is a commonly used method of digitally encoding analog signal levels. The PWM mode mainly controls the output signal by controlling the duty cycle (the ratio of the high level duration to the total period) of the fixed frequency pulse signal. In a PWM period, the longer the high level time, the larger the duty cycle, and the higher the average voltage (for voltage type PWM) or average current (for current type PWM) output; otherwise, the smaller the duty cycle, the lower the average voltage or current. By changing the duty cycle, the brightness can be controlled without changing the data signal (Data) written into the display panel.

[0073] In the pixel circuit, Oxide TFT (oxide thin film transistor) has unique performance and has shown great potential in medium and large size low frequency products. Compared with the traditional LTPS TFT (low temperature polysilicon thin film transistor), Oxide TFT has shown significant advantages. In terms of drain current characteristics, the drain current of Oxide TFT is significantly smaller. In medium and large size low frequency products, such as some smart TVs, computer monitors, etc., when the screen is in a static display picture, the high drain current of LTPS TFT may cause the charge of the pixel point to slowly leak, thereby affecting the stability and display effect of the picture. While Oxide TFT has small drain current, it can maintain the charge state of the pixel point for a long time, so that the picture can still maintain clear and stable when displaying the same content for a long time, effectively reducing the flicker and noise of the picture. Oxide TFT also has better magnetic hysteresis performance. Hysteresis phenomenon may cause signal response delay, picture switching not smooth, etc. In medium and large size products, especially in complex application scenarios, Oxide TFT's magnetic hysteresis performance is particularly important. It can ensure that it responds quickly and accurately to the driving signal under different working conditions, realizes fast switching and stable display of the picture, and greatly improves the display quality.

[0074] The main pixel circuit currently uses source follower V TH The compensation method separates V TH Compensation and Data writing. Figure 1is a 6T2C circuit schematic diagram of an example full oxide pixel circuit. Figure 2 is Figure 1 The circuit diagram shown corresponds to a 120Hz timing diagram of a VRR (Virtual Refresh Rate). The VRR is a variable refresh rate technology that is playing an increasingly important role in the display field and is closely linked to oxide TFT technology. In Figure 2 , a display frame (1Frame) can include a write frame and three hold frames. Figure 3 The Figure 2 timing diagram of a write frame in Figure 4 The Figure 2 timing diagram of a hold frame in

[0075] As Figure 3 shown, in the write frame, the output waveform of the EM1 signal needs to be a low-level signal VGL in the reset period ① and the Data write period ③, and a high-level signal VGH in the compensation period ② between the reset period ① and the Data write period ③. As Figure 4 shown, in the hold frame, the EM1 signal outputs a VGL signal for a period of time (for example, period ⑤), and there is no as complex output waveform as in the write frame.

[0076] For the pixel circuit as Figure 1 shown, when it is combined with the PWM technology, different brightness modes can be obtained by adjusting the pulse width of the EM1 signal. However, since the current mainstream DIC (IC for controlling the input of screen Data and GOA signals) supports a PWM model with equal pulse widths, it cannot output the EM1 signal with unequal VGL widths as Figure 3 shown. Thus, the application of the pixel circuit as Figure 1 shown is limited.

[0077] Therefore, based on this, the embodiment of the present application provides a driving circuit and a driving method, and an array substrate. The driving circuit comprises a trigger signal generation sub-circuit and a plurality of shift registers which are cascaded. The trigger signal generation sub-circuit is electrically connected with a first frame start signal input line, a second frame start signal input line and the shift registers, and is configured to generate an initial light-emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light-emitting control signal to the shift registers. At least part of the shift registers are electrically connected with pixel circuits, and are configured to generate a target light-emitting control signal according to the trigger signal, and transmit the target light-emitting control signal to the pixel circuits. The initial light-emitting control signal is configured to be used as the trigger signal of part of the shift registers, and the initial light-emitting control signal is a pulse signal with unequal pulse widths.

[0078] In the present application, by using the existing DIC output pulse width and with pulse width modulation information signal (such as the second frame start signal STV2), the initial light emitting control signal is generated in the trigger signal generation sub-circuit; the initial light emitting control signal is a pulse signal with unequal pulse width. The target light emitting control signal is generated by the at least partial shift register according to the trigger signal (the initial light emitting control signal) and transmitted to the pixel circuit, so that the EM1 drive signal with PWM function required by the full oxide pixel circuit as shown in Figure 1 is obtained.

[0079] The driving circuit and driving method, and array substrate provided by the embodiments of the present application will be specifically introduced and described below in combination with the drawings.

[0080] The embodiments of the present application provide a driving circuit, as shown in Figure 5 The driving circuit includes a trigger signal generation sub-circuit 1 and a plurality of shift registers GOA arranged in cascade.

[0081] The trigger signal generation sub-circuit 1 is electrically connected with the first frame start signal input line STV1, the second frame start signal input line STV2 and the shift register GOA respectively, and is configured to generate the initial light emitting control signal EM1-STV according to the first frame start signal STV1 and the second frame start signal STV2 and transmit the initial light emitting control signal EM1-STV to the shift register GOA.

[0082] The at least partial shift register GOA is electrically connected with the pixel circuit X, and is configured to generate the target light emitting control signal according to the trigger signal and transmit the target light emitting control signal to the pixel circuit X.

[0083] The initial light emitting control signal EM1-STV is configured to be used as the trigger signal of the partial shift register GOA; the initial light emitting control signal EM1-STV is a pulse signal with unequal pulse width.

[0084] For example, the waveform of the target light emitting control signal is the same as that of the initial light emitting control signal.

[0085] In such a display driving circuit architecture, the design of the trigger signal generation sub-circuit 1 is crucial, which cooperates closely with the first frame start signal input line STV1 and the second frame start signal input line STV2 to generate the initial light-emitting control signal EM1-STV based on the two start signals. The initial light-emitting control signal EM1-STV is a pulse signal with unequal pulse widths, and its unique pulse characteristics can trigger the subsequent shift registers GOA and make the subsequent shift registers GOA(n) output the target light-emitting control signal EM(y) with the same waveform, where y and n are positive integers.

[0086] In addition, at least part of the shift registers GOA are electrically connected to the pixel circuit X, and at least part of the shift registers GOA are configured to generate the target light-emitting control signal according to the trigger signal and transmit the target light-emitting control signal to the pixel circuit X, including the following two cases:

[0087] The first case: in the multiple shift registers GOA arranged in cascade, part of the shift registers GOA are electrically connected to the pixel circuit X (the virtual shift register described later is not electrically connected to the pixel circuit X), and this part of the shift registers GOA are configured to generate the target light-emitting control signal EM(y) according to the trigger signal and transmit the target light-emitting control signal EM(y) to the pixel circuit X.

[0088] The second case: all the shift registers GOA are electrically connected to the pixel circuit X (in the case of not containing the virtual shift register described later), and each shift register GOA is configured to generate the target light-emitting control signal according to the trigger signal and transmit the target light-emitting control signal EM(y) to the pixel circuit X.

[0089] Among them, the initial light-emitting control signal EM1-STV is configured to serve as the trigger signal of part of the shift registers GOA, and it can be understood that the initial light-emitting control signal EM1-STV serves as the trigger signal of one shift register directly electrically connected to the trigger signal generation sub-circuit 1.

[0090] In this application, by using the existing DIC output signal (for example, the second frame start signal STV2) with equal pulse width and pulse width modulation information, the initial light-emitting control signal is generated in the trigger signal generation sub-circuit; the initial light-emitting control signal is a pulse signal with unequal pulse widths. At least part of the shift registers generate the target light-emitting control signal according to the trigger signal (the initial light-emitting control signal) and transmit the target light-emitting control signal to the pixel circuit, and the waveform of the target light-emitting control signal is the same as that of the initial light-emitting control signal, so that the EM1 driving signal with PWM function required by the full-oxide pixel circuit as shown in Figure 1 is obtained, which meets the signal requirements of the pixel circuit.

[0091] When applied to a display panel carrying all-oxide pixel circuits, such a driving circuit has obvious advantages. Oxide TFTs have excellent V TH uniformity, so that each pixel can emit light at the same standard when receiving the target light-emitting control signal EM(y) output by the shift register GOA. Because the pulse width of the initial light-emitting control signal EM1-STV is not equal, the shift register GOA can flexibly adjust the driving time of the pixel circuit X according to the different pulse widths, thereby more accurately controlling the display state and light-emitting brightness of each pixel. When displaying complex images or high-definition videos, such accurate control can avoid the problems of brightness unevenness and color deviation caused by driving differences between pixels, fully exerting the advantages of Oxide TFTs in improving the uniformity of display quality and presenting more delicate and realistic picture effects to users.

[0092] In the driving circuit provided in some embodiments of the present application, as shown in Figure 8 and Figure 9 , the pulse width of the first frame start signal STV1 signal is fixed, and the second frame start signal STV2 signal is a frame start signal with equal pulse width and pulse width modulation information.

[0093] Because the pulse width of the first frame start signal STV1 signal is fixed, and the second frame start signal STV2 signal is a frame start signal with equal pulse width and pulse width modulation information, when the trigger signal generation sub-circuit 1 receives these two signals, it needs to analyze the pulse width modulation information in the second frame start signal. Based on the analysis result, in combination with the fixed pulse width of the first frame start signal, the initial light-emitting control signal is generated. Due to the modulation characteristics of the second frame start signal, the pulse width of the initial light-emitting control signal EM1-STV will no longer be a simple fixed value, but will have multiple pulse signals with unequal pulse widths.

[0094] In the driving circuit provided in some embodiments of the present application, as shown in Figure 5 , the plurality of shift registers GOA includes a virtual shift register GOA(0) and n-stage light-emitting control shift registers GOA(n) arranged in cascade, n being a positive integer;

[0095] The virtual shift register GOA(0) is electrically connected with the trigger signal generation sub-circuit 1 and the first-stage light-emitting control shift register GOA(1), respectively, and the (n+1)-stage light-emitting control shift register GOA(n+1) is electrically connected with the n-stage light-emitting control shift register GOA(n), the (n+2)-stage light-emitting control shift register GOA(n+2), and the (n+1)-row pixel unit X, respectively;

[0096] The initial light-emitting control signal EM1-STV is configured to be used as a trigger signal of the virtual shift register GOA(0). The virtual shift register GOA(0) is configured to receive the initial light-emitting control signal EM1-STV and process the initial light-emitting control signal EM1-STV to obtain the initial light-emitting control signal EM1-STV with a stable waveform. The initial light-emitting control signal EM1-STV with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register GOA(1). The first-level light-emitting control shift register GOA(1) is configured to receive the initial light-emitting control signal EM1-STV with a stable waveform and generate a target light-emitting control signal EM(y), where y is a positive integer.

[0097] The virtual shift register GOA(0) has the same circuit structure and basic functions as the light-emission control shift register GOA(n). The virtual shift register GOA(0) is directly electrically connected to the trigger signal generation subcircuit 1, and the output end of the virtual shift register GOA(0) is not connected to the pixel circuits in the display area AA. The light-emission control shift registers GOA(n) are cascaded, and each level of the light-emission control shift register GOA(n) is connected to a row of pixel circuits and transmits the target light-emission control signal EM(y) to the pixel circuits.

[0098] The light-emitting control shift register GOA(n) is a key component in the display driver system. It is mainly responsible for generating and transmitting light-emitting control signals, thereby regulating the light-emitting process of the pixel circuit.

[0099] The light emitting control shift register GOA(n) (generally referred to as EM GOA) described in this application refers to a register for generating and transmitting light emitting signals such as Figure 1 The EM1 signal is shown in the shift register. Of course, as Figure 1 As shown in , in actual applications, it may also include a shift register for generating and transmitting an EM2 signal, a shift register for generating and transmitting an RST1 signal, a shift register for generating and transmitting an RST2 signal, and a shift register for generating and transmitting a Gate signal.

[0100] The main function of the virtual shift register GOA(0) is to stabilize the initial light-emitting control signal EM1-STV output by the trigger signal generation subcircuit 1, thereby obtaining a target light-emitting control signal EM(y) with the same waveform and stable waveform and low noise. This is beneficial for the subsequent light-emitting control shift register GOA(n) to transmit a more stable target light-emitting control signal EM(y) to the pixel circuit based on it.

[0101] The stable trigger signal is the basis of ensuring high-quality display, and any interference or fluctuation can destroy the synchronization of the signal, resulting in flickering, stripes and other undesirable phenomena on the screen. Since the initial light-emitting control signal EM1-STV is used as the trigger signal of the shift register directly electrically connected with the trigger signal generation sub-circuit 1, after the virtual shift register GOA(0) is used for the stabilization processing, the signal output by the virtual shift register GOA(0) can provide a more stable trigger signal to the light-emitting control shift register, thereby facilitating the improvement of the quality of the display screen.

[0102] In the driving circuit provided in some embodiments of the present application, the plurality of shift registers includes n-stage light-emitting control shift registers (not including the virtual shift register GOA(0)) arranged in cascade, where n is a positive integer;

[0103] The first-stage light-emitting control shift register GOA(1) is electrically connected with the trigger signal generation sub-circuit 1, the second-stage light-emitting control shift register GOA(2) and the first row of pixel units X, respectively;

[0104] The initial light-emitting control signal EM1-STV is configured to be used as the trigger signal of the first-stage light-emitting control shift register EM1-STV, and the first-stage light-emitting control shift register GOA(1) is configured to generate a target light-emitting control signal EM(y) according to the initial light-emitting control signal EM1-STV;

[0105] The target light-emitting control signal EM(y) output by the n-stage light-emitting control shift register GOA(n) is used as the trigger signal of the (n+1)-stage light-emitting control shift register.

[0106] In the case where the driving circuit is applied to a display product with low requirements for display quality and insufficient design space of the array substrate, the trigger signal generation sub-circuit 1 can be arranged in the driving circuit without arranging the virtual shift register GOA(0), so that, in the case where the EM1 driving signal with PWM function required by the full-oxide pixel circuit as shown in Figure 1 is provided, the design difficulty is also reduced and the cost is lowered.

[0107] In the driving circuit provided in some embodiments of the present application, as shown in Figure 5 , the driving circuit further includes a first clock signal line CB and a second clock signal line CK,

[0108] The virtual shift register GOA(0) is electrically connected with the output end of the trigger signal generation sub-circuit 1, the input end (STV) of the first-stage light-emitting control shift register GOA(1) and the first clock signal line CB, respectively;

[0109] The first-stage light-emitting control shift register GOA(1) is electrically connected with the output terminal (OUT) of the virtual shift register GOA(0), the input terminal (STV) of the second-stage light-emitting control shift register GOA(2), the second clock signal line CK and the first row of pixel circuits X, respectively;

[0110] The second-stage light-emitting control shift register GOA(2) is electrically connected with the output terminal (OUT) of the first-stage light-emitting control shift register GOA(1), the input terminal (STV) of the third-stage light-emitting control shift register, the first clock signal line CB and the second row of pixel circuits X, respectively;

[0111] The m-stage light-emitting control shift register GOA(m) is electrically connected with the output terminal (OUT) of the (m-1)-stage light-emitting control shift register GOA(m-1), the input terminal (STV) of the (m+1)-stage light-emitting control shift register GOA(m+1), the second clock signal line CK and the m-th row of pixel circuits X, respectively; m is an odd number and m>1;

[0112] The (m+1)-stage light-emitting control shift register GOA(m+1) is electrically connected with the output terminal (OUT) of the m-stage light-emitting control shift register GOA(m), the input terminal (STV) of the (m+2)-stage light-emitting control shift register GOA(m+2), the first clock signal line CB and the (m+1)-th row of pixel circuits X, respectively.

[0113] It should be noted that, in Figure 5 , only the position of the pixel circuit X is simply shown by a rectangular frame, and in actual application, each stage of light-emitting control shift register transmits the target light-emitting control signal EM(y) to the pixel circuit in the same row, and in Figure 5 , according to the different row numbers, the target light-emitting control signal EM(y) is marked as EM1<1>, EM1<2>, EM1<3>, EM1<4>, EM1<5>, EM1<6>……

[0114] In addition, the pixel circuit here can be the pixel circuit as shown in Figure 1 , and the working principle and driving process of the pixel circuit can be referred to the introduction and description in the related art, which will not be described here.

[0115] In the driving circuit provided in some embodiments of the present application, as shown in Figure 6 and Figure 7 , the trigger signal generation sub-circuit 1 includes a first transistor M1 and a second transistor M2,

[0116] The gate of the first transistor M1 is electrically connected with the first frame start signal input line STV1, the source of the first transistor M1 is electrically connected with the second frame start signal input line STV2, and the drain of the first transistor M1 is electrically connected with the output end (labeled as EM1-STV) of the trigger signal generation sub-circuit 1.

[0117] The gate of the second transistor M2 is electrically connected with the second frame start signal input line STV2, the source of the second transistor M2 is electrically connected with the first frame start signal input line STV1, and the drain of the second transistor M2 is electrically connected with the output end (labeled as EM1-STV) of the trigger signal generation sub-circuit 1.

[0118] In the exemplary embodiments, both the first transistor M1 and the second transistor M2 are P-type transistors. For the P-type transistor, when a negative voltage is applied to the gate relative to the source, the source and the drain are turned on; otherwise, the source and the drain are turned off.

[0119] In the driving circuit provided by some embodiments of the present application, as shown in FIG. 1, the first transistor M1 further includes a first stable electrode BSM1, and the second transistor M2 further includes a second stable electrode BSM2. Figure 7

[0120] The first stable electrode BSM1 is electrically connected with the first frame start signal input line STV1, and the second stable electrode BSM2 is electrically connected with the second frame start signal input line STV2.

[0121] In the exemplary embodiments, both the first stable electrode BSM1 and the second stable electrode BSM2 can be metal materials.

[0122] For example, the first stable electrode BSM1 and the second stable electrode BSM2 can also be referred to as a bottom shield metal (BSM). On the one hand, the bottom shield metal can block the electromagnetic field generated by other circuits below or the external environment from interfering with the transistor, like a shield. On the other hand, the transistor generates heat during operation, and excessive heat accumulation can cause the performance of the transistor to decrease or even damage the transistor. The bottom shield metal has good thermal conductivity, which can act as a heat dissipation channel to quickly conduct the heat generated by the transistor to the surrounding environment. On the other hand, in the substrate in which the driving circuit is arranged, there are various noise sources, such as noise generated by parasitic capacitance coupling and noise generated by substrate current fluctuation. The bottom shield metal can isolate the substrate noise from affecting the transistor, guide and shunt the noise current in the substrate when it appears, avoid the noise directly affecting the normal operation of the transistor, and thus improve the signal-to-noise ratio of the transistor and the overall performance of the circuit.

[0123] ​In the driving circuit provided in some embodiments of the present application, in combination with the timing information in Figure 8 and Figure 9 , the first frame start signal STV1 and the second frame start signal STV2 are configured to not be high signals at the same time.

[0124] Wherein, Figure 8 is the timing diagram of the first frame start signal STV1 and the second frame start signal STV2 in the write frame, Figure 9 is the timing diagram of the first frame start signal STV1 and the second frame start signal STV2 in the hold frame.

[0125] The working principle of the trigger signal generation sub-circuit 1 will be explained in combination with the circuit schematic and timing information of the trigger signal generation sub-circuit in Figure 6 or Figure 7 :

[0126] 1. When the first frame start signal STV1 is low and the second frame start signal STV2 is high, the first transistor M1 is turned on, the second transistor M2 is turned off, and the output end of the trigger signal generation sub-circuit 1 outputs the high initial light-emitting control signal EM1-STV.

[0127] 2. When the first frame start signal STV1 is high and the second frame start signal STV2 is low, the first transistor M1 is turned off, the second transistor M2 is turned on, and the output end of the trigger signal generation sub-circuit 1 outputs the high initial light-emitting control signal EM1-STV.

[0128] 3. When the first frame start signal STV1 is low and the second frame start signal STV2 is low, the first transistor M1 is turned on, the second transistor M2 is turned on, and the output end of the trigger signal generation sub-circuit 1 outputs the low initial light-emitting control signal EM1-STV.

[0129] Based on this, in actual application, since the pulse width of the first frame start signal STV1 is fixed, the second frame start signal STV2 is a frame start signal with equal pulse width and pulse width modulation information, and therefore the required initial light-emitting control signal EM1-STV can be regulated and generated according to the first frame start signal STV1 and the second frame start signal STV2.

[0130] Figure 8 and Figure 9 is the timing of the initial light-emitting control signal EM1-STV generated by the trigger generation sub-circuit based on the first frame start signal STV1 and the second frame start signal STV2, wherein, Figure 8 is the timing of the initial light-emitting control signal EM1-STV in the write frame, Figure 9It is the timing of the initial light emitting control signal EM1-STV when the frame is maintained.

[0131] In the driving circuit provided in some embodiments of the present application, a display frame includes a writing frame and three holding frames.

[0132] like Figure 8 As shown, in the write frame, in the first time period ①, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a low level signal; the initial light emitting control signal EM1-STV is a low level signal;

[0133] In the second time period ②, the first frame start signal STV1 is a high level signal, the second frame start signal STV2 is a low level signal; the initial light emitting control signal EM1-STV is a high level signal;

[0134] In the third time period ③, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a low level signal; the initial light emitting control signal EM1-STV is a low level signal;

[0135] In the fourth time period ④, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a high level signal; and the initial light emitting control signal EM1-STV is a high level signal.

[0136] In the driving circuit provided in some embodiments of the present application, Figure 9 As shown,

[0137] In the hold frame, in the fifth time period ⑤, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a low level signal, and the initial light emitting control signal EM1-STV is a low level signal;

[0138] In the sixth time period ⑥, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a high level signal, and the initial light emitting control signal EM1-STV is a high level signal.

[0139] It should be noted that the specific durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤ and the sixth time period ⑥ are not limited here.

[0140] The durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤, and the sixth time period ⑥ are not completely equal. For example, the durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤, and the sixth time period ⑥ may not all be equal. For another example, the durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤, and the sixth time period ⑥ may be partially equal and partially unequal.

[0141] like Figure 8 As shown, the width of the initial light-emitting control signal EM1-STV in the first time period ① and the third time period ③ is not limited here and can be designed according to actual needs. For example, the low-level signal width of the initial light-emitting control signal EM1-STV in the first time period ① can be greater than the low-level signal width of the initial light-emitting control signal EM1-STV in the third time period ③; or, the low-level signal width of the initial light-emitting control signal EM1-STV in the first time period ① can be less than the low-level signal width of the initial light-emitting control signal EM1-STV in the third time period ③. In particular, when the second frame start signal STV2 is determined, the low-level signal width of the initial light-emitting control signal EM1-STV in the first time period ① and the low-level signal width of the initial light-emitting control signal EM1-STV in the third time period ③ can be adjusted according to the width of the high-level signal of the first frame start signal STV1 in the second time period ② and the position of the rising edge of this high-level signal.

[0142] In addition, the waveform of the target light emitting control signal EM(y) generated by the subsequent light emitting control shift register GOA(n) is the same as that of the target light emitting control signal EM(y) when writing the frame. Figure 8 The waveform of the initial light emitting control signal EM1-STV shown in FIG is the same; the waveform of the target light emitting control signal EM(y) generated by the subsequent light emitting control shift register GOA(n) is the same as that of the target light emitting control signal EM(y) when the frame is maintained. Figure 9 The waveform of the initial light-emitting control signal EM1-STV shown in FIG. 1 is the same; in this way, the target light-emitting control signal EM(y) is input to the pixel circuit of the corresponding row, so that the pixel circuit can also be combined with the PWM mode of the current mainstream DIC (IC that controls the screen Data and GOA signal input), which satisfies the following requirements: Figure 3 The pixel circuit shown in the figure has requirements for EM1 signals of different widths, which is also compatible with the current mainstream DIC. This expands the functionality without increasing the cost of DIC and improves the flexibility of the driver circuit application.

[0143] In the driving circuit provided in some embodiments of the present application, the first frame start signal STV1 and the second frame start signal STV2 are configured to be separately provided by the driving chip (DIC). It should be understood that the driving chip (DIC) has multiple transmission channels, one of which is used to provide the first frame start signal STV1 to the driving circuit as shown in FIG. 1, and the other is used to provide the second frame start signal STV2 to the driving circuit as shown in FIG. 2. Figure 5 Figure 5 At this time, the design of the driving circuit is simple and easy to prepare.

[0144] In the driving circuit provided in some embodiments of the present application, the driving circuit further comprises a reset shift register RST GOA, the first frame start signal STV1 is configured to be provided by the driving chip (DIC), and the reset shift register RST GOA and the light-emitting control shift register EM GOA share the first frame start signal STV1; the second frame start signal STV2 is configured to be separately provided by the driving chip (DIC). It should be understood that the driving chip (DIC) has multiple transmission channels, one of which is used to provide the same first frame start signal STV1 to the driving circuit as shown in FIG. 1 and the reset shift register RST GOA of the driving circuit, and the other is used to provide the second frame start signal STV2 to the driving circuit as shown in FIG. 2. Figure 5 Figure 5 At this time, since the reset shift register RST GOA and the light-emitting control shift register EM GOA share the first frame start signal STV1, the space for designing the wire can be saved, so that the space utilization is improved, which is beneficial to the preparation of small-size products and narrow-frame products.

[0145] The above-mentioned manner of providing the first frame start signal STV1 and the second frame start signal STV2 by the driving chip (DIC) can be determined according to the actual product demand, so that the flexibility of the designed circuit is improved.

[0146] Embodiments of the present application provide a driving method for driving the driving circuit of any one of the preceding embodiments, the method comprising:

[0147] S1, inputting the first frame start signal STV1 and the second frame start signal STV2 to the trigger generation sub-circuit 1;

[0148] Specifically, in the case that the first frame start signal STV1 is at a low level and the second frame start signal STV2 is at a high level, the first transistor M1 is turned on, the second transistor M2 is turned off, and the output end of the trigger signal generation sub-circuit outputs the initial light-emitting control signal EM1-STV at a high level.

[0149] ​​In a case where the first frame start signal STV1 is at a high level and the second frame start signal STV2 is at a low level, the first transistor M1 is turned off, the second transistor M2 is turned on, and the output terminal of the trigger signal generation sub-circuit outputs the initial light emitting control signal EM1-STV at a high level.

[0150] In a case where the first frame start signal STV1 is at a low level and the second frame start signal STV2 is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, and the output terminal of the trigger signal generation sub-circuit outputs the initial light emitting control signal EM1-STV at a low level.

[0151] Based on this, in actual application, since the pulse width of the first frame start signal STV1 is fixed, the second frame start signal STV2 is a frame start signal with equal pulse width and pulse width modulation information, and thus the required initial light emitting control signal EM1-STV can be regulated and generated according to the first frame start signal STV1 and the second frame start signal STV2.

[0152] S2, input a clock signal to the shift register GOA, the clock signal being the first clock signal CB or the second clock signal CK.

[0153] At least part of the shift register GOA can generate a target light emitting control signal EM(y) and transmit it to the pixel circuit according to the initial light emitting control signal EM1-STV transmitted by the trigger generation sub-circuit 1 and the clock signal.

[0154] Specifically, the plurality of shift registers GOA includes a virtual shift register GOA(0) and n-stage light emitting control shift registers GOA(n) arranged in cascade, n being a positive integer;

[0155] The virtual shift register GOA(0) is electrically connected with the trigger signal generation sub-circuit 1 and the first-stage light emitting control shift register GOA(1) respectively, the n+1-stage light emitting control shift register GOA(n+1) is electrically connected with the n-stage light emitting control shift register GOA(n), the n+2-stage light emitting control shift register GOA(n+2) and the n+1-row pixel unit X respectively;

[0156] The initial light-emitting control signal EM1-STV is configured to be used as a trigger signal of the virtual shift register GOA(0). The virtual shift register GOA(0) is configured to receive the initial light-emitting control signal EM1-STV and process the initial light-emitting control signal EM1-STV to obtain the initial light-emitting control signal EM1-STV with a stable waveform. The initial light-emitting control signal EM1-STV with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register GOA(1). The first-level light-emitting control shift register GOA(1) is configured to receive the initial light-emitting control signal EM1-STV with a stable waveform and generate a target light-emitting control signal EM(y), where y is a positive integer.

[0157] The embodiment of the present application provides an array substrate, comprising any of the driving circuits described above, such as Figure 10 As shown, the array substrate includes:

[0158] substrate, and

[0159] a semiconductor layer (e.g., LTPS), located on one side of the substrate, including a semiconductor pattern of the first transistor M1, a semiconductor pattern of the second transistor M2, a source and a drain of the first transistor M1, and a source and a drain of the second transistor M2 in the trigger signal generating sub-circuit 1;

[0160] A first gate layer Gate1 is located on a side of the semiconductor layer (eg, LTPS) away from the substrate, and includes a gate Gate of the first transistor M1 and a gate Gate of the second transistor M2;

[0161] The source-drain conductive layer SD is located on a side of the first gate layer Gate1 away from the substrate, and includes a first frame start signal input line STV1 and a second frame start signal input line STV2.

[0162] In an exemplary embodiment, the array substrate may be applied to an OLED (Organic Light-Emitting Diode) display panel.

[0163] In an exemplary embodiment, the substrate may be a glass substrate. For example, the thickness of the glass substrate may range from 0.3 mm to 0.7 mm. Specifically, the thickness may be 0.3 mm, 0.4 mm, 0.5 mm, or 0.6 mm.

[0164] In an exemplary embodiment, the substrate may be made of one or more materials selected from the group consisting of polyimide, polycarbonate, polyacrylate, polyetherimide, and polyethersulfone, and this embodiment includes but is not limited thereto.

[0165] The semiconductor layer can be a silicon material, wherein the silicon material can be classified into single crystal silicon, polycrystalline silicon and amorphous silicon according to crystalline form. Polycrystalline silicon is a silicon material composed of many single crystal silicon particles with different orientations. LTPS is polycrystalline silicon thin film prepared at a relatively low temperature. Compared with the traditional high-temperature process, the low-temperature process can use a low-cost substrate such as glass, and the polycrystalline silicon structure gives the material better electrical properties.

[0166] In addition, as shown in FIG. 1, the semiconductor pattern of the first transistor M1, the semiconductor pattern of the second transistor M2, the source and the drain of the first transistor M1 and the source and the drain of the second transistor M2 can be an integrated structure. Figure 10

[0167] It should be noted that the specific circuit of each shift register in the driving circuit shown in FIG. 1 and the type of transistor contained in the circuit are not limited, and can be designed differently according to the type of product. In addition, since the number of transistors and other components contained in the shift register is usually greater than that of the trigger signal sub-circuit, the space occupied by the trigger signal sub-circuit in the array substrate is smaller than that occupied by a shift register. Figure 5

[0168] The material of the first gate layer Gate1 and the source-drain conductive layer SD can include metal, for example, the material of the first gate layer Gate1 and the source-drain conductive layer SD can include at least one of copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo).

[0169] In the array substrate provided by some embodiments of the present application, as shown in FIG. 1, the drain of the first transistor M1 and the drain of the second transistor M2 are shared, and the semiconductor pattern of the first transistor M1, the semiconductor pattern of the second transistor M2, the source and the drain of the first transistor M1 and the source and the drain of the second transistor M2 are an integrated structure. Figure 10

[0170] Among them, the drain of the first transistor M1 and the drain of the second transistor M2 are shared, and are electrically connected with the initial light-emitting control signal output line (labeled as EM-STV) through the connection line SD / LJ arranged on the source-drain conductive layer SD, the connection line SD / LJ is arranged in the region between the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2, and the connection line SD / LJ does not overlap with the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2.

[0171] ​​​In the present application, by setting the drain of the first transistor M1 and the drain of the second transistor M2 to be shared, on the one hand, the design space can be saved, and on the other hand, the resistance during contact and interconnection can be reduced, and the stability of signal transmission can be improved; and by setting the semiconductor pattern of the first transistor M1, the semiconductor pattern of the second transistor M2, the source and the drain of the first transistor M1, and the source and the drain of the second transistor M2 to be integrated structures; the design space of the trigger signal sub-circuit is further reduced.

[0172] In the array substrate provided in some embodiments of the present application, as shown in Figure 10 the gate of the first transistor M1 and the gate of the second transistor M2 are centrally symmetrically distributed with the geometric center of the drain of the first transistor M1 as the symmetric point.

[0173] By setting the gate of the first transistor M1 and the gate of the second transistor M2 to be centrally symmetrically distributed with the geometric center of the drain of the first transistor M1 as the symmetric point, the layout of the first transistor M1 and the second transistor M2 can be more compact, thereby facilitating the saving of design space.

[0174] In the array substrate provided in some embodiments of the present application, as shown in Figure 10 the first frame start signal input line STV1 partially surrounds one side of the first transistor M1 and the second transistor M2, and the second frame start signal input line STV2 partially surrounds the other side of the first transistor M1 and the second transistor M2.

[0175] Based on the foregoing setting that the gate of the first transistor M1 and the gate of the second transistor M2 are centrally symmetrically distributed, when the first frame start signal input line STV1 and the second frame start signal input line STV2 are subsequently set, the first frame start signal input line STV1 is set close to one side of the gate of the first transistor M1, the second frame start signal input line STV2 is set close to one side of the gate of the second transistor M2, and the first frame start signal input line STV1 partially surrounds one side of the first transistor M1 and the second transistor M2, and the second frame start signal input line STV2 partially surrounds the other side of the first transistor M1 and the second transistor M2; in this way, while meeting the input of signals of the first frame start signal input line STV1 and the second frame start signal input line STV2 to the trigger generation sub-circuit, the design space is maximally utilized, so that the space occupied by the trigger generation sub-circuit is as small as possible, leaving sufficient space for the layout of the shift register circuit.

[0176] The "partially surrounding" means that the first frame start signal input line STV1 or the second frame start signal input line STV2 surrounds a part of the peripheral region of the first transistor M1 and the second transistor M2, and the "part" can be half or less than half. The width of the first frame start signal input line STV1 and the second frame start signal input line STV2 is not limited, and can be determined according to the signal transmission requirement and the conductive property of the material.

[0177] For example, when the first frame start signal input line STV1 and the second frame start signal input line STV2 are arranged in the same layer and are made of the same material, the width of the first frame start signal input line STV1 and the second frame start signal input line STV2 can be set to be the same.

[0178] For example, the width of the initial light-emitting control signal output line (labeled as EM-STV) can be set to be less than or equal to the width of the second frame start signal input line STV2.

[0179] In some embodiments of the array substrate provided in the present application, as shown in Figure 10 The array substrate further includes a second gate layer Gate2 between the first gate layer Gate1 and the source-drain conductive layer SD, and the second gate layer Gate2 includes an initial light-emitting control signal output line (labeled as EM-STV) configured to output an initial light-emitting control signal.

[0180] The material of the second gate layer Gate2 can be the same as that of the first gate layer Gate1.

[0181] In some embodiments of the array substrate provided in the present application, one of the first frame start signal input line STV1 and the second frame start signal input line STV2 overlaps with the orthographic projection of the initial light-emitting control signal output line (labeled as EM-STV) on the substrate 1.

[0182] For example, the second frame start signal input line STV2 overlaps with the orthographic projection of the initial light-emitting control signal output line (labeled as EM-STV) on the substrate 1.

[0183] In the case that the orthogonal projection of the first frame start signal input line STV1 and the initial light-emitting control signal output line (labeled as EM-STV) on the substrate 1 overlaps, the length of the first frame start signal input line STV1 can be greater than the length of the second frame start signal input line STV2.

[0184] For example, the orthogonal projection of the first frame start signal input line STV1 and the initial light-emitting control signal output line (labeled as EM-STV) on the substrate 1 overlaps.

[0185] Of course, in the case that the orthogonal projection of the first frame start signal input line STV1 and the initial light-emitting control signal output line (labeled as EM-STV) on the substrate 1 overlaps, the length of the first frame start signal input line STV1 can be greater than the length of the second frame start signal input line STV2, and the reason is similar to the foregoing, which will not be described herein again, wherein the via via1 is used to connect the first frame start signal input line STV1 and the first stable electrode BSM1.

[0186] In the array substrate provided by some embodiments of the present application, as shown in Figure 10 The array substrate further includes a light-shielding conductive layer (for example, a bottom shield metal BSM), which is located between the substrate and the semiconductor layer (for example, an LTPS), and includes the first stable electrode BSM1 and the second stable electrode BSM2; wherein the orthogonal projection of the first stable electrode BSM1 on the substrate covers the gate of the first transistor M1, and the orthogonal projection of the second stable electrode BSM2 on the substrate covers the gate of the second transistor M2; the first stable electrode BSM1 is electrically connected with the first frame start signal input line STV1, and the second stable electrode BSM2 is electrically connected with the second frame start signal input line STV2.

[0187] For example, the material of the light-shielding conductive layer can be metal, for example, copper (Cu).

[0188] Embodiments of the present application further provide a display panel, which includes the array substrate as described in the foregoing.

[0189] The present application provides a display device, which includes: the display panel as provided in any of the embodiments; and a driving assembly connected with the display panel, configured to drive the display panel to emit light.

[0190] Those skilled in the art can understand that the display device provided in the present application has the advantages of the display panel of any one of the above-mentioned embodiments.

[0191] The display device provided in the present application can be a display module, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a vehicle-mounted display device, a smart watch, a fitness wristband, a personal digital assistant, or any product or component having a display function.

[0192] In the present application, a transistor refers to an element including at least a gate, a drain, and a source. The transistor has a channel region between the drain and the source, and current can flow through the drain, the channel region, and the source. In the present application, the channel region refers to a region through which current mainly flows.

[0193] In the present application, the transistor can be a thin film transistor or a field effect transistor. The present application is described by taking a thin film transistor as an example.

[0194] In the case of using a transistor having opposite polarity or in the case of changing the current direction in the circuit operation, the functions of the "source" and the "drain" are sometimes interchanged. Therefore, in the present application, the "source" and the "drain" can be interchanged.

[0195] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A driving circuit, wherein: The driving circuit includes a trigger signal generating subcircuit and a plurality of shift registers arranged in cascade; The trigger signal generating subcircuit is electrically connected to the first frame start signal input line, the second frame start signal input line and the shift register respectively, and is configured to generate an initial light-emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light-emitting control signal to the shift register; At least part of the shift register is electrically connected to the pixel circuit, and at least part of the shift register is configured to generate a target light emitting control signal according to a trigger signal and transmit the target light emitting control signal to the pixel circuit; The initial light-emitting control signal is configured to be used as a trigger signal for a portion of the shift register; and the initial light-emitting control signal is a pulse signal with different pulse widths.

2. The driving circuit according to claim 1, wherein: The pulse width of the first frame start signal is fixed, and the second frame start signal is a frame start signal with a constant pulse width and pulse width modulation information.

3. The driving circuit according to claim 2, wherein: The multiple shift registers include a virtual shift register and n-stage light emitting control shift registers arranged in cascade, where n is a positive integer; The virtual shift register is electrically connected to the trigger signal generating sub-circuit and the first-stage light-emitting control shift register, respectively; the (n+1)-stage light-emitting control shift register is electrically connected to the n-stage light-emitting control shift register, the (n+2)-stage light-emitting control shift register, and the (n+1)-row pixel unit, respectively; The initial light-emitting control signal is configured to be used as a trigger signal of the virtual shift register, and the virtual shift register is configured to receive the initial light-emitting control signal and process the initial light-emitting control signal to obtain the initial light-emitting control signal with a stable waveform. The initial light-emitting control signal with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register, and the first-level light-emitting control shift register is configured to receive the initial light-emitting control signal with a stable waveform and generate the target light-emitting control signal.

4. The driving circuit according to claim 2, wherein: The plurality of shift registers include n-stage light emitting control shift registers arranged in cascade, where n is a positive integer; The light emitting control shift register of the first stage is electrically connected to the trigger signal generating sub-circuit, the light emitting control shift register of the second stage and the pixel units of the first row respectively; The initial light emitting control signal is configured to be used as a trigger signal for the first-stage light emitting control shift register, and the first-stage light emitting control shift register is configured to generate the target light emitting control signal according to the initial light emitting control signal; The target light emitting control signal outputted by the light emitting control shift register at the nth stage is used as a trigger signal for the light emitting control shift register at the (n+1)th stage.

5. The driving circuit according to claim 3, wherein: The driving circuit further includes a first clock signal line and a second clock signal line, The virtual shift register is electrically connected to the output end of the trigger signal generating sub-circuit, the input end of the first-stage light emitting control shift register, and the first clock signal line respectively; The light emitting control shift register of the first stage is electrically connected to the output end of the virtual shift register, the input end of the light emitting control shift register of the second stage, the second clock signal line and the pixel circuit of the first row respectively; The second-stage light-emitting control shift register is electrically connected to the output end of the first-stage light-emitting control shift register, the input end of the third-stage light-emitting control shift register, the first clock signal line, and the pixel circuits in the second row respectively; The light emitting control shift register of the mth stage is electrically connected to the output terminal of the light emitting control shift register of the m-1th stage, the input terminal of the light emitting control shift register of the m+1th stage, the second clock signal line, and the pixel circuit of the mth row; m is an odd number, and m>1; The (m+1)th level light control shift register is electrically connected to the output end of the (m)th level light control shift register, the input end of the (m+2)th level light control shift register, the first clock signal line and the pixel circuit in the (m+1)th row.

6. The driving circuit according to claim 3 or 4, wherein: The trigger signal generating sub-circuit includes a first transistor and a second transistor, The gate of the first transistor is electrically connected to the first frame start signal input line, the source of the first transistor is electrically connected to the second frame start signal input line, and the drain of the first transistor is electrically connected to the output end of the trigger signal generation sub-circuit; The gate of the second transistor is electrically connected to the second frame start signal input line, the source of the second transistor is electrically connected to the first frame start signal input line, and the drain of the second transistor is electrically connected to the output end of the trigger signal generating sub-circuit.

7. The driving circuit according to claim 6, wherein: The first transistor further includes a first stabilizing electrode, and the second transistor further includes a second stabilizing electrode; The first stable electrode is electrically connected to the first frame start signal input line, and the second stable electrode is electrically connected to the second frame start signal input line.

8. The driving circuit according to claim 6, wherein: The first frame start signal and the second frame start signal are configured not to be high level signals at the same time.

9. The driving circuit according to claim 8, wherein: A display frame consists of a write frame and three hold frames. In the write frame, in the first time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the second time period, the first frame start signal is a high level signal, and the second frame start signal is a low level signal; in the third time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the fourth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

10. The driving circuit according to claim 9, wherein: In the holding frame, in the fifth time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal. In the sixth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

11. The driving circuit according to any one of claims 2 to 10, wherein: The first frame start signal and the second frame start signal are configured to be provided separately by a driving chip.

12. The driving circuit according to any one of claims 2 to 10, wherein: The driving circuit further includes a reset shift register, the first frame start signal is configured to be provided by the driving chip, and the reset shift register and the light emitting control shift register share the first frame start signal; the second frame start signal is configured to be provided solely by the driving chip.

13. A driving method, wherein: For driving the driving circuit according to any one of claims 1 to 12, the method comprises: inputting a first frame start signal and a second frame start signal into the trigger signal generating subcircuit; A clock signal is input to the shift register, where the clock signal is a first clock signal or a second clock signal.

14. An array substrate, wherein: The array substrate comprises a driving circuit according to any one of claims 1 to 12, wherein the array substrate comprises: substrate, and a semiconductor layer, located on one side of the substrate, comprising a semiconductor pattern of a first transistor, a semiconductor pattern of a second transistor, a source and a drain of the first transistor, and a source and a drain of the second transistor in the trigger signal generating subcircuit; a first gate layer, located on a side of the semiconductor layer away from the substrate, comprising a gate of the first transistor and a gate of the second transistor; The source-drain conductive layer is located on a side of the first gate layer away from the substrate, and includes a first frame start signal input line and a second frame start signal input line.

15. The array substrate according to claim 14, wherein: The drain of the first transistor and the drain of the second transistor are shared, The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, the source and drain of the first transistor, and the source and drain of the second transistor are an integrated structure.

16. The array substrate according to claim 15, wherein: The gate of the first transistor and the gate of the second transistor are centrally symmetrically distributed with the geometric center of the drain of the first transistor as a symmetry point.

17. The array substrate according to claim 16, wherein: The first frame start signal input line partially surrounds one side of the first transistor and the second transistor, and the second frame start signal input line partially surrounds the other side of the first transistor and the second transistor.

18. The array substrate according to claim 16, wherein: The array substrate further includes: A second gate layer is located between the first gate layer and the source-drain conductive layer, and the second gate layer includes an initial light-emitting control signal output line, and the initial light-emitting control signal output line is configured to output the initial light-emitting control signal.

19. The array substrate according to claim 18, wherein: One of the first frame start signal input line and the second frame start signal input line overlaps with an orthographic projection of the initial light emission control signal output line on the substrate.

20. The array substrate according to claim 19, wherein: The array substrate further includes: a light-shielding conductive layer, the light-shielding conductive layer being located between the substrate and the semiconductor layer and comprising a first stabilizing electrode and a second stabilizing electrode; The orthographic projection of the first stabilizing electrode on the substrate covers the gate of the first transistor, and the orthographic projection of the second stabilizing electrode on the substrate covers the gate of the second transistor; the first stabilizing electrode is electrically connected to the first frame start signal input line, and the second stabilizing electrode is electrically connected to the second frame start signal input line.

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