Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same. A packaged electronic device structure includes a substrate having a major surface. A semiconductor device is connected to the main surface of the substrate, the semiconductor device having a first main surface, a second main surface opposite the first main surface, and a side surface extending between the first main surface and the second main surface. The package encapsulates a portion of the semiconductor device, wherein a side surface of the semiconductor device is exposed through a side surface of the package. In some examples, the side surface of the semiconductor device is an active surface. In some examples, the package includes a molded structure that contacts and covers a first major surface of the semiconductor device.

Description

[0001] This case is a divisional application of the invention patent application with the application date of February 20, 2020, the priority date of February 23, 2019, the application number 202010103533.8, and the invention name of semiconductor device and method for manufacturing semiconductor device.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Patent Application No. 16 / 283,752, filed on February 23, 2019, which is incorporated herein by reference. Technical Field

[0004] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages. Background Art

[0005] Previous semiconductor packages and methods of forming semiconductor packages are inadequate, for example, resulting in excessive cost, poor thermal performance, reduced reliability, relatively low performance, or package size that is too large. More specifically, some packaged semiconductor devices include semiconductor devices such as sensors or optical devices that require one or more side surfaces of the device that are active surfaces to be exposed to the outside of the package. Such devices include, for example, laser devices that can be incorporated into light detection and ranging ("LIDAR") systems. The aforementioned methods for producing packaged semiconductor devices in which one or more side surfaces of the semiconductor device are exposed produce poor results, with problems including damage to the semiconductor device and conductive interconnects, such as wire bonds. In addition, the conductive interconnects have been exposed to the environment through open side surfaces or within the cavity of the package, resulting in reliability issues. By comparing such methods with the present disclosure and referring to the drawings, it will be apparent to those of ordinary skill in the art that other limitations and disadvantages of conventional and traditional methods.

[0006] Therefore, it is desirable to have a packaging structure and method that provides a packaged electronic device that overcomes the shortcomings of the prior art. It is also desirable to have a structure and method that is easily incorporated into a manufacturing flow, accommodates a variety of die interconnect schemes, and is cost-effective. Summary of the invention

[0007] Among other features, the present specification includes packaged electronic device structures and associated methods, which include electronic devices having active side surfaces exposed in side surfaces of a closed structure. In some instances, the closed structure includes a molded package. In other instances, the closed structure includes a cover structure. In both structures, elements such as conductive interconnect structures are protected from environmental influences to improve reliability compared to the aforementioned devices. The packaged electronic device structure can accommodate a variety of bare die interconnect solutions. The associated methods can be incorporated into standard manufacturing processes to provide cost-saving integrated solutions.

[0008] More specifically, in one example, a method for forming a packaged electronic device structure includes providing a substrate having a main surface. The method includes attaching a first device to the main surface of the substrate. The method includes forming a package that encapsulates a portion of the first device, wherein a side surface of the first device is exposed outside the package. In some examples, attaching the first device includes attaching a semiconductor device having an emitter region as a portion of the side surface of the semiconductor device exposed outside the package. In some examples, the method includes attaching a second device to a main surface spaced apart from the first device to provide a gap between the first device and the second device; and forming the package includes forming the package so that the gap does not contain the package. In some examples, forming the package includes: placing a blocking structure to surround the gap; and molding the package onto at least a portion of the first device. In some examples, placing the blocking structure includes placing a mold tool having a portion extending across the gap, the mold tool having a protective film disposed between the mold tool and the first device and the second device. In some examples, the first device includes a first semiconductor device. In some examples, the second device includes a dummy device. In some examples, the second device includes a second semiconductor device. In some instances, the substrates are separated by a gap. In some instances, the first device is electrically connected to the substrate, wherein: a side surface of the first device includes an emitter region. In some instances, the electrical connection includes attaching a conductive interconnect structure to the first device and the substrate; and forming a package includes forming a mold structure, the mold structure covering the conductive interconnect structure with the package. In some instances, forming the package includes covering at least 50% of the main surface of the first device. In some instances, forming the package includes providing a package having a package side surface, wherein the side surface of the first device is exposed; and the package side surface has an inclined shape in a cross-sectional view.

[0009] In another example, a packaged electronic device structure includes a substrate having a main surface. A semiconductor device is connected to the main surface of the substrate, the semiconductor device having a first main surface, a second main surface opposite to the first main surface, and a side surface extending between the first main surface and the second main surface. The package encapsulates a portion of the semiconductor device, wherein the side surface of the semiconductor device is exposed through the side surface of the package. In some examples, the package includes a molded structure that contacts and covers the first main surface of the semiconductor device. In other examples, the structure further includes a conductive interconnect structure that electrically connects the semiconductor device to the substrate, and the package encapsulates the conductive interconnect structure. In some examples, the package includes a molded structure that contacts and covers at least a portion of the first main surface of the semiconductor device. In some examples, the semiconductor device includes a laser device; and the side surface of the semiconductor device includes an emitter region.

[0010] In another example, a method for forming a packaged electronic device structure includes providing a substrate having a main surface. The method includes attaching a semiconductor device to the main surface of the substrate, the semiconductor device having a first main surface, a second main surface opposite to the first main surface, and a side surface extending between the first main surface and the second main surface. The method includes electrically connecting the semiconductor device to the substrate through a conductive interconnect structure. The method includes covering the conductive interconnect structure and at least a portion of the first main surface of the semiconductor device with a protective material. The method includes attaching a cover structure to the substrate, the cover structure including a side, a top, and an opening, wherein the side surface of the semiconductor device is exposed to the outside of the cover structure through the opening. In some examples, the substrate and the cover structure include similar materials. In some examples, the substrate and the cover structure include a laminated material. In other examples, attaching the cover structure includes attaching the side to the main surface of the substrate; and attaching the top to the side; and the method further includes removing a portion of the cover structure to provide an opening after the cover structure is attached to the substrate. In some examples, removing a portion of the cover structure further includes singulating the substrate. In some examples, removing a portion of the cover structure includes singulating the substrate. In some examples, attaching the lid structure includes attaching a one-piece lid structure surrounding the semiconductor device; the method further includes removing a portion of the lid structure to provide the opening after the lid structure is attached to the substrate; and removing the portion of the lid structure includes singulating the substrate.

[0011] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims, and / or the specification of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A cross-sectional view illustrating an example packaged electronic device of the present specification;

[0013] Figure 2is a flow chart of an example method of forming a packaged electronic device of the present specification;

[0014] Figures 3 to 7 Description of the various stages of manufacturing according to this specification Figure 1 A partial cross-sectional view of a packaged electronic device;

[0015] Figure 8 A partial cross-sectional view illustrating an example packaged electronic device of the present specification at an intermediate stage of manufacture;

[0016] Fig. 9 A cross-sectional view illustrating an example packaged electronic device of the present specification;

[0017] Fig.10 is a flow chart of an example method of forming a packaged electronic device of the present specification;

[0018] Figures 11 to 15 Description of the various stages of manufacturing according to this specification Fig. 9 A partial cross-sectional view of a packaged electronic device; and

[0019] Fig.16 A cross-sectional view illustrating an example packaged electronic device of the present specification.

[0020] For simplicity and clarity of illustration, the elements in the figures are not necessarily drawn to scale, and the same reference numerals represent the same elements in different figures. In addition, the description and details of well-known steps and elements are omitted for simplicity of description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the terms used herein are only for the purpose of describing specific example embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It should be further understood that the terms "comprises / comprising" and / or "includes / including" specify the presence of stated features, numbers, steps, operations, elements and / or components when used in this specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components and / or groups thereof. It should be understood that although the terms "first, second, etc." can be used in this article to describe various components, elements, regions, layers and / or sections, these components, elements, regions, layers and / or sections should not be limited by these terms. These terms are used only to distinguish one component, element, region, layer and / or section from another component, element, region, layer and / or section. Thus, for example, the first component, first element, first region, first layer and / or first section discussed below may be referred to as the second component, second element, second region, second layer and / or second section without departing from the teachings of the present disclosure. Reference to "an example" or "an example" refers to the specific features, structures or characteristics described in conjunction with the embodiment being included in at least one example of the present invention. Therefore, the phrases "in an example" or "in an example" appearing in different positions throughout this specification do not necessarily refer to the same example, but in some cases refer to the same example. In addition, as will be understood by a person of ordinary skill in the art, specific features, structures or characteristics may be combined in one or more example embodiments in any suitable manner. In addition, the term "at..." refers to a specific action occurring at least within a portion of the duration of the initiating action. The use of the words "approximately, approximately or substantially" refers to the expectation that the value of an element is close to a state value or position. However, it is well known in the art that there are always minor differences that prevent the precise statement of values ​​or positions. Unless otherwise specified, as used herein, the words "on" or "over" include orientations, placements, or relationships in which the specified elements may be in direct or indirect physical contact. It should be further understood that the examples illustrated and described below may suitably have examples and / or may be practiced in the absence of any elements not specifically disclosed herein. DETAILED DESCRIPTION

[0021] Figure 1An example packaged electronic device structure 10 according to the present description is illustrated, for example, a cross-sectional view of a packaged semiconductor device 10. The example is illustrated as a land grid array packaged semiconductor device structure, but the present description is not limited to this type of package and is applicable to other types of packages. Figure 1 In the illustrated example, packaged electronic device structure 10 includes substrate 11, electronic component 16 such as semiconductor device 16, attaching material 17, conductive interconnect structure 21, and enclosing structure such as package body 36. According to the present specification and the present example, semiconductor device 16 includes side surface 14, which may be an active surface exposed through an opening or via or through side surface 32 of enclosing structure 36.

[0022] Conductive interconnect structure 21, substrate 11, attachment material 17, and package body 36 may be referred to as semiconductor package 190, and semiconductor package 190 may provide protection for portions of semiconductor device 16 from external elements and / or environmental exposure. In addition, semiconductor package 190 may provide electrical coupling from external electrical components (not shown) to conductive interconnect structure 21 and semiconductor device 16.

[0023] The substrate 11 may be selected from common circuit boards (e.g., rigid circuit boards and flexible circuit boards), multilayer substrates, laminated substrates, core substrates with built-in layers, coreless substrates, ceramic substrates, lead frame substrates, molded lead frame substrates, or similar substrates known to those skilled in the art. In this regard, the present specification is not intended to be limited to any particular type of substrate 11. By way of example and not by limitation, the substrate 11 may include an insulating structure 114 having opposing substantially planar top and bottom surfaces. It should be understood that multiple insulating layer portions may be used to provide the insulating structure 114. The conductive pattern 112 or conductive pattern layer 112 may be disposed adjacent to the top surface of the insulating structure 114, and the conductive pad 113 may be disposed adjacent to the bottom surface of the insulating structure 114.

[0024] In some examples, the conductive pattern 112 and the conductive pad 113 are electrically interconnected with each other in a specified pattern or arrangement using a conductive interconnection path 111 defined by a portion of one or more conductive layers, the conductive interconnection path extending from the conductive pattern 112 to the conductive pad 113 through the insulating structure 114. The conductive pattern 112, the conductive pad 113, and the conductive interconnection layer 111 include conductive materials, for example, one or more metals. In some examples, the conductive pattern 112, the conductive pad 113, and the conductive interconnection layer 111 include copper. In some examples, a solder mask 115 or a protective layer 115 may be disposed adjacent to at least a portion of the conductive pattern 112 and the top surface of the insulating structure 114. In addition, in some examples, a solder mask 116 or a protective layer 116 may be disposed on at least a portion of the pad 113 and the bottom surface of the insulating structure 114. The solder mask 115 is used to protect portions of the conductive pattern 112 that are otherwise susceptible to electrical short circuit problems. The solder mask 116 serves to protect portions of the pads 113 that would otherwise be exposed to the surrounding environment.

[0025] The semiconductor device 16 includes: a first main surface 18, in which active devices and / or passive devices are generally provided; an opposite second main surface 19; and a side surface 14, which extends substantially vertically between the first main surface 18 and the second main surface 19. The main surface 19 of the semiconductor device 16 can be attached to the substrate 11 in a device active area upward (or die upward) configuration using an attachment material 17, which can include a thermally conductive and electrically conductive material, or a thermally conductive and non-conductive material. In some examples, the attachment material 17 includes an epoxy-type die attach material. In other examples, the attachment material 17 can be a welding material, such as solder paste or other materials known to those of ordinary skill in the art. The attachment material 17 is generally used to provide both mechanical fixation of the semiconductor device 16 to the substrate 11 and dissipation of heat generated by the semiconductor device 16. In some examples, the attachment material 17 can provide an electrical path from the substrate 11 to the semiconductor device 16.

[0026] In some examples, the semiconductor device 16 includes a pad 24 disposed adjacent to the main surface 18. In some examples, a conductive interconnect structure 21 electrically connects the pad 24 to a portion of the conductive pattern 112. In the present example, the conductive interconnect structure 21 includes a conductive wire and can be provided using a wire bonding technique, wherein the wire includes copper, gold, aluminum, or other conductive materials known to those of ordinary skill in the art. The conductive interconnect structure 21 is used to transmit electrical signals to and from the semiconductor device 16. In other examples, the semiconductor device 16 can be attached to a portion of the conductive pattern 112 by a different conductive interconnect structure, such as a conductive bump in a flip chip configuration, wherein the main surface 18 faces the substrate 11.

[0027] In this example, the conductive pad 113 can be configured to be directly connected or attached to a next level assembly, such as a printed circuit board. In some examples, the conductive interconnect structure can be attached to the conductive pad 113 in a ball grid array (BGA) configuration and can include a conductive material, such as a solder ball, a solder bump, a copper bump, a nickel gold bump, or a similar material known to a person of ordinary skill in the art.

[0028] In some examples, semiconductor device 16 is an optical device, such as a laser device including an emitter region 161 disposed proximate to side surface 14 of semiconductor device 16. It should be understood that emitter region 161 can be disposed completely or partially within semiconductor device 16. Examples of such laser devices can include edge emitting laser (EEL) devices. In other examples, semiconductor device 16 is an integrated circuit device, a power semiconductor device, an optical device, any type of sensor device, or other devices known to those of ordinary skill in the art, specifically, devices that require one or more side surfaces of the device to be exposed to a side surface (e.g., side surface 32) of package body 36. Those of ordinary skill in the art will appreciate that semiconductor device 16 is illustrated in simplified form and may also include multiple diffusion regions, multiple conductive layers, and multiple dielectric layers.

[0029] The packaged semiconductor device 10 further includes a sealing structure 36, for example, a package body 36 covering or encapsulating the conductive interconnect structure 21, a portion of the semiconductor die 16, the conductive pattern 112, and a portion of the substrate 11. According to the present example, the package body 36 is provided so that the side surface 14 of the semiconductor device 16 is exposed to the outside of the packaged semiconductor device 10. In some examples, the package body 36 does not extend along the side surface of the substrate 11 or along the bottom surface of the substrate 11.

[0030] In some examples, package 36 can be a polymer-based composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with appropriate filler. Package 36 includes a non-conductive and environmentally friendly material that protects conductive interconnect structure 21 and portions of semiconductor device 16 from external elements and contaminants. Package 36 can be formed using solder paste printing, compression molding, transfer molding, overmolding, liquid encapsulation molding, vacuum lamination, other suitable applicators, or other processes known to those of ordinary skill in the art. In some embodiments, package 36 is an epoxy molding compound ("EMC") and can be formed using transfer or injection molding techniques.

[0031] According to the present example, the configuration of the package 36 facilitates exposing the side surface 14 of the semiconductor device 16 including, for example, the emitter region 161 to the outside of the package 36 through the side surface 32. In some examples, the side surface 32 includes a Figure 1 1, which may provide a more efficient and reliable manufacturing process. In addition, encapsulation body 36 is used to protect conductive interconnect structure 21, portions of semiconductor device 16 including pads 24, and portions of conductive pattern 112, thereby improving reliability compared to previously packaged devices in which some or all of these features are exposed to the environment. In some examples, encapsulation body 36 contacts semiconductor device 16 and laterally covers more than 50% of major surface 18 of semiconductor device 16. In other examples, encapsulation body 36 contacts semiconductor device 16 and laterally covers more than 75% of major surface 18.

[0032] Figure 2 1 is a flow chart of an example method 100 for manufacturing a packaged electronic device, such as a packaged semiconductor device 10, according to the present specification. In block S110 of method 100, a plurality of devices and a substrate structure are provided. The plurality of devices may include one or more semiconductor devices and other devices. In block S120 of method 100, a plurality of devices including a first device and a second device are attached to a major surface of the substrate structure such that the first device and the second device are laterally spaced apart to provide a gap or cavity therebetween.

[0033] Figure 3 and 4 A partial cross-sectional view of a packaged semiconductor device 10 at a stage of manufacturing is illustrated, and an example of blocks S110 and S120 of method 100 is further illustrated. In this example, the plurality of devices provided may include one or more semiconductor devices, such as semiconductor device 16 (or variations thereof), and other devices, such as Figure 4 The dummy device 117 (or its variant) described in FIG. 1 can be similar to the substrate structure provided. Figure 1 11 (or a variant thereof or other substrate structure). In one example, the first device can be one of the semiconductor devices 16, which is attached to the surface of the substrate 11 by the attachment material 17 as part of block S120. As previously described, the attachment material 17 can be an epoxy-type die attachment material, which can be deposited on one or more predetermined portions of the substrate 11. In other examples, the attachment material 17 can include a solder material or other materials known to a person of ordinary skill in the art. In this example, the semiconductor device 16 includes a sensor device having a side surface 14, which is an active surface or active portion of the semiconductor device 16. By way of example, the semiconductor device 16 is a laser device having an emitter region 161, which is disposed on a portion of the side surface 14, disposed within a portion of the side surface 14, or disposed as a portion of the side surface 14. In some examples, the attachment material 17 can be cured after the semiconductor device 16 is placed in contact with the attachment material 17.

[0034] In this example, the second device includes Figure 4 , the dummy device 117 described in the figure may be an unprocessed chip or die including a semiconductor material. In some examples, the dummy device 117 has a thickness similar to that of the semiconductor device 16, but the dummy device 117 may have a smaller area than the semiconductor device 16 to consume less area on the substrate 11. In one example, the dummy device 117 is an unprocessed or minimally processed silicon die. In block S120, a second device such as the dummy device 117 is attached to the substrate 11. In some examples, the attachment material 17 (or other material) may be used to attach the dummy device 117 to the substrate 11. According to the present specification, the semiconductor device 16 and the dummy device 117 are disposed on the substrate 11 so as to be laterally spaced apart from each other to provide a gap 41, a cavity 41, or a lateral space 41 therebetween. In the present example, the dummy device 117 has a side surface 214 that directly faces or covers the side surface 14 of the semiconductor device 16 to define at least a portion of the gap 41.

[0035] The method 100 also includes a block S130 , which includes electrically connecting at least a first device to the substrate structure. Figure 5 A partial cross-sectional view of encapsulating a semiconductor device 10 at another stage of manufacturing is described, and an example of a frame S130 of the method 100 is further described. In some examples, the step of electrically connecting can be completed using a wire configured as a conductive interconnect structure 21, which can be provided using a wire bonding technology. In some examples, the conductive interconnect structure 21 is attached to a pad 24 and a conductive pattern 112, and the pad is arranged adjacent to the main surface 18 of the semiconductor device 16. In other examples, the semiconductor device 16 can be attached to the substrate 11 with a flip chip configuration, wherein the conductive interconnect structure includes a conductive bump structure, such as a solder bump. In this alternative configuration, it is not necessary to attach the dummy die 117 to the substrate 11 in a flip chip configuration, but according to design selection, the dummy die can be attached in a flip chip configuration. That is, when the semiconductor device is attached to the substrate 11 by the conductive bump, the dummy die 117 can still be attached to the substrate 11 by the attachment material 17. In this example, the semiconductor device 16 and the dummy die 117 are attached to the substrate 11 using different methods. When flip chip interconnects are used, the steps of attaching the first device to the substrate structure and electrically connecting the first device to the substrate structure may be combined steps.In some examples, an optical inspection step may be performed at this point in the manufacturing process to ensure that the subassembly is properly formed.

[0036] At this stage of fabrication, a subassembly 51A is provided; and it should be understood that, although only one semiconductor device 16 and one dummy device 117 are illustrated, the subassembly 51A may include multiple (i.e., more than one) semiconductor devices 16 and multiple (i.e., more than one) dummy devices 117. It should be further understood that the order in which the semiconductor devices 16 and dummy devices 117 are attached to the substrate 11 may be different from the sequence illustrated. In addition, the conductive interconnect structure 21 may be attached to the semiconductor device 16 and the conductive pattern layer 112 before the dummy device 117 is attached to the substrate 11.

[0037] The method 100 further includes a block S140, which includes surrounding or covering the gap using a barrier structure, and thereafter forming a package to encapsulate at least a portion of the first device while exposing at least one side surface of the first device to the gap and not covered by the package. In some examples, at least a portion of the second device is encapsulated by the package while at least one side surface of the second device is exposed to the gap and not covered by the package. Figure 6 A partial cross-sectional view of subassembly 51A after further processing according to block S140 of method 100 is illustrated. In some examples, subassembly 51A is placed in a molding apparatus including a support structure (not shown) for holding substrate 11 and a blocking device, such a moldchase tool 61 having a protrusion 620 configured to surround or cover gap 41 between semiconductor device 16 and dummy device 117. In some examples, a film assisted molding technique is used with block S140. For example, a protective film 63 is disposed on an outer surface 610 of moldchase tool 61. In some examples, protective film 63 includes a plastic material or a similar material known to those of ordinary skill in the art.

[0038] In some examples, portion 620 of mold tool 61 has a width that is wider than gap 41, so portion 620 extends completely across gap 41 and covers portions of major surface 18 of semiconductor device 16 and portions of dummy device 117. The amount of overlap determines where along major surface 18 of semiconductor device 16 the package 36 terminates. In some examples, portion 620 having protective film 63 contacts semiconductor device 16, dummy device 117, and portions of substrate 11 (not shown) to form a seal around gap 41. Next, package 36 is provided using a molding technique. According to the present example, package 36 is provided to encapsulate or cover portions of semiconductor device 16 and dummy device 117, while leaving side surface 14 of semiconductor device 16 and side surface 214 of dummy device 117 exposed in gap 41 and not covered by package 36. That is, at least side surface 14 of semiconductor device 16 is not covered by package 36 and is exposed through an opening or passage in side surface 32 of package 36, as shown in FIG. Figure 1 and 7 As described in .

[0039] In some examples, the portion of substrate 11 disposed within gap 41 is not covered by package 36. In some examples, the shape or contour of portion 620 defines the shape of side surface 32 of package 36. Such a shape may include, for example, Figure 1 In other examples, other blocking structures may be used, such as a masking structure that surrounds the gap 41 during the molding process.

[0040] Block S150 of method 100 includes separating the first device from the second device through the gap to provide at least one packaged semiconductor device, the side surface of the at least one packaged semiconductor device being exposed through the side surface of the package body. In some examples, a separation process (represented by arrow 71) such as a sawing process or a laser cutting process is used to singulate subassembly 51A or physically separate subassembly 51A into individual packaged semiconductor devices, such as packaged semiconductor devices 10. In some examples, the width of gap 41 is selected to provide a safe operating area 72 to accommodate methods for separating substrate 11 without damaging semiconductor device 16. In other examples, part (or all) of dummy device 117 can be removed during the singulation process to allow for a narrower safe operating area 71.

[0041] In accordance with the present description, method 100 provides a packaged semiconductor device 10 having a semiconductor device 16 partially encapsulated by a package body 36 that protects the semiconductor device 16 and portions of a conductive interconnect structure 21 while providing a side surface 14 that is an active surface of the semiconductor device 16 exposed through a side surface 32 of the package body 36 .

[0042] Figure 8 A partial cross-sectional view illustrating an example of a packaged electronic device 10 at an intermediate stage of manufacturing. In this example, a subassembly 51B has a second device that includes another semiconductor device 16B instead of a dummy device 117. In some examples, semiconductor device 16B is attached to substrate 11 so that a side surface 14B of semiconductor device 16B directly faces side surface 14 of semiconductor device 16, which may be an active surface including emitter region 161B. During the molding process, a barrier structure covers a portion of a major surface 18 of semiconductor device 16B.

[0043] Fig. 9An example packaged electronic device structure 90 according to the present specification is described, for example, a cross-sectional view of a packaged semiconductor device 90. The packaged semiconductor device 90 is another example of a semiconductor package 190 according to the present specification. The packaged semiconductor device 90 is similar to the packaged semiconductor device 10 and only the differences will be described below. The packaged semiconductor device 90 includes a different encapsulation structure compared to the packaged semiconductor device 10. More specifically, the packaged semiconductor device 90 includes a lid structure 360, which includes a side 361 or sidewall 361 and a top 363 attached to the side 361 by an attachment material 364. In some examples, the side 361 is attached to the substrate 11 using an attachment material 367. The attachment materials 364 and 367 may include an electrically conductive and thermally conductive material, an insulating and thermally conductive material, a solder material, an epoxy resin type adhesive material, a conductive paste, or other materials known to those of ordinary skill in the art.

[0044] In some examples, cover structure 360 ​​includes a laminate material and can be one or more materials similar to those used to provide substrate 11. In some examples, cover structure 360 ​​includes an insulating structure. In other examples, cover structure 360 ​​includes a conductive material or a combination of conductive and insulating materials. When cover structure 360 ​​includes a conductive material, cover structure 360 ​​can be configured as a shielding structure for semiconductor device 16, and in some examples, as is typically the case in Fig. 9 As described in the figure, the conductive pattern layer 112, the conductive interconnection path 111 and the conductive pad 113 can be electrically grounded. In some examples, the cover structure 360 ​​includes multiple parts, such as the generally Fig. 9 In other examples, the cover structure 360 ​​includes a monolithic configuration, such as is typically described in Fig.16 As described in .

[0045] In some examples, the side 361 has a height that safely places the top 363 above the conductive interconnect structure 21, which is protected or surrounded by the protective material 211 in this example. The protective material 211 can include a protective gel, such as a polymer material. In some examples, the protective material 211 includes a silicone gel. The protective material 211 is used to seal, encapsulate and protect the conductive interconnect structure 21 and portions of the semiconductor device 16, including, for example, the pad 24. This is an improvement over previous devices in which the conductive interconnect structure is exposed to the environment, which can cause reliability issues.

[0046] According to the present specification, the cap structure 360 ​​is provided with an opening 368, which exposes the active side surface 14 including the emitter region 161 of the semiconductor device 16 to the outside of the cap structure 360. In some examples, the top 363 is supported by three side surfaces 361, which are arranged around the periphery of the substrate 11. In other examples, the top 363 is supported by at least two side surfaces 361. The side surfaces 361 can be configured to follow the overall shape of the semiconductor device 16. In other examples, the side surfaces 361 can be configured to have a shape different from that of the semiconductor device 16.

[0047] Fig.10 is a flow chart illustrating an example method 200 for fabricating a packaged electronic device structure, such as packaged semiconductor device 90 , in accordance with the present description. Figures 11 to 15 Partial cross-sectional views of a packaged semiconductor device 90 are illustrated at various stages of fabrication according to method 200. In block S210, a first device is attached to a major surface of a substrate structure.

[0048] Fig.11 FIG. 1 is a partial cross-sectional view of a packaged semiconductor device 90 at an early stage of manufacturing after completing block S210. In some examples, the substrate structure may be similar to Fig. 9 11 (or a variant thereof or other type of substrate). In some examples, the first device may be a semiconductor device 16 (or a variant thereof) as well as other devices. As previously described, the first device, such as semiconductor device 16, may be attached to substrate 11 by an attachment material 17. In some examples, attachment material 17 may be cured after semiconductor device 16 is placed in contact with attachment material 17.

[0049] The method 200 also includes block S220 , which includes electrically connecting the first device to the substrate structure through the conductive interconnect structure. Fig.12 A partial cross-sectional view of packaging semiconductor device 90 after completing block S220 according to one example is illustrated. In some examples, the step of electrically connecting can be completed using wires configured as conductive interconnect structures 21, which can be provided using wire bonding technology. In some examples, conductive interconnect structures 21 are attached to pads 24 and conductive patterns 112, and the pads are disposed adjacent to the main surface 18 of semiconductor device 16. In other examples, semiconductor device 16 can be attached to substrate 11 in a flip-chip configuration, wherein the conductive interconnect structures include conductive bump structures, such as solder bumps. In the flip-chip configuration, blocks S210 and S220 can be combined into a single step.

[0050] The method 200 further includes block S230, which includes providing a protective material covering the conductive interconnect structure. The protective material may be similar to the protective material 211 (or a variation thereof). Fig.13A partial cross-sectional view of the packaged semiconductor device 90 after completing block S230 according to one example is illustrated. In some examples, a protective material 211 is provided to cover the conductive interconnect structure 21 and the protective material may include a protective gel material as previously described. A dispensing process may be used to form the protective material 211. In some examples, the protective material 211 further covers a portion of the semiconductor device 16, including the pad 24, and further covers a portion of the conductive pattern layer 112, wherein the conductive interconnect structure 21 is attached. In some examples, the protective material 211 may be cured after it is formed. In some examples, an optical inspection step may be performed at this point in the manufacturing process to ensure that the subassembly is properly formed.

[0051] The method 200 includes block S240, which includes attaching an enclosing structure to the substrate structure, the enclosing structure including the sidewall structure. The enclosing structure may be similar to the cap structure 360 ​​(or a variation thereof). Fig.14 The packaged semiconductor device 90 after completing block S240 according to one example is described. When the cap structure 360 ​​includes multiple parts, first the side 361 can be attached to the substrate 11 using the attachment material 367. In some examples, one or more sides 361 are attached to the conductive pattern layer 112. In one example, the attachment material 367 includes an epoxy type attachment material. In other examples, the attachment material 367 can be a solder material.

[0052] After attaching the side 361, the top 363 can be attached to the side 361 using an attachment material 364, which can be an epoxy resin type attachment material or a welding material. When the cover structure 360 ​​includes a single piece, the side 361 integrated with the top 363 can be attached to the substrate 11 by an attachment material 367. In other examples, before the side 361 is attached to the substrate 11 by the attachment material 367, the side 361 can be attached to the top 363 by the attachment material 364. In some examples, the attachment materials 364 and 367 are cured after attaching the side 361 and the top 363. After frame S140, the cover structure 360 ​​can completely surround the semiconductor device 16, the conductive interconnect structure 21, and the protective material 211. In some examples, after attaching the cover structure 360, the top 363 can be marked with identification information. Laser marking can be used to provide identification information on the top 363. With this configuration, the top 363 is supported on all edges by the sides 361, which can provide a more stable structure for the laser marking step.

[0053] Method 200 further includes block S250, including removing a portion of the enclosing structure including a portion of the sidewall structure to provide an opening exposing the side surface of the first device to the exterior of the enclosing structure. The removing step may remove a portion of cover structure 360 ​​(or a variation thereof), including a portion of side 361. Fig.15 A partial cross-sectional view of packaged semiconductor device 90 according to an example of block S250 is illustrated. In some examples, a separation process (indicated by arrow 71), such as a sawing process or a laser cutting process, is used to singulate or physically separate a portion of cap structure 360 ​​and substrate 11 at selected locations (indicated by vertical dashed lines 172) to expose side surfaces 14 of semiconductor device 16 through openings 368 of cap structure 360, such as generally at Fig. 9 The location of the separation process is selected so that the semiconductor device 16 is not damaged during this step.

[0054] According to the present description, method 200 provides packaged semiconductor device 90 having protective material 211 covering conductive interconnect structure 21 and semiconductor device 16 having side surface 14 (which is an active surface) exposed through opening 368 in cap structure 360. In addition, when cap structure 360 ​​and substrate 11 include similar materials, a packaged semiconductor device with reduced stress can be provided.

[0055] Fig.16 A cross-sectional view of an example packaged electronic device structure 160, such as packaged semiconductor device 160, according to the present specification is illustrated. Packaged semiconductor device 160 is another example of a semiconductor package 190 according to the present specification. Packaged semiconductor device 160 is similar to packaged semiconductor device 90 and only the differences will be described below. Fig.16 The cover structure 360 ​​illustrated in includes a single-piece structure in which the side 361 is integrated with the top 363. In addition, the protective material 211 is provided so as to cover most of the semiconductor device 16 while leaving the side surface 14 uncovered and exposed through the opening 368. In other examples, a lens structure may be provided within the opening 368. In the semiconductor device 160, the protective material 211 may be provided before or after the cover structure 360 ​​is attached to the substrate 11. In some examples, the cover structure 360 ​​physically contacts the protective material 211. In other examples, one or more spaces or gaps (e.g., a space between the top 363 and the protective material 211, and / or a space between the side 361 and the protective material 211) may be provided between the protective material 211 and the cover structure 360 ​​or a portion thereof.

[0056] In summary, packaged electronic device structures and associated methods have been described, the packaged electronic device structures including electronic devices having active side surfaces exposed in side surfaces of an enclosed structure. In some instances, the enclosed structure includes a molded package. In other instances, the enclosed structure includes a cover structure. In both structures, elements such as conductive interconnect structures are protected from environmental influences to improve reliability compared to the aforementioned devices. The packaged electronic device structures can accommodate a variety of bare die interconnect schemes. The associated methods can be incorporated into standard manufacturing processes to provide cost-effective integration.

[0057] Although the subject matter of the present invention is described by specific example steps and example embodiments, the aforementioned drawings and their descriptions only depict typical examples of the subject matter and are therefore not to be considered as limiting its scope. It is apparent that many alternatives and variations will be apparent to those skilled in the art. By way of example, a plurality of electronic devices may be attached to the pads in a side-by-side configuration, a stacked configuration, a combination thereof, or other configurations known to those skilled in the art. In addition, the cover structure for encapsulating the semiconductor device 90 may be provided with a pre-existing opening before being attached to the substrate structure.

[0058] As reflected in the following claims, aspects of the present invention lie in less than all of the features of a single previously disclosed embodiment. Therefore, the claims expressed below are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate example of the present invention. In addition, although some examples described herein include some but not all of the other features included in other examples, as will be understood by those skilled in the art, the combination of features of different examples is intended to be within the scope of the present invention and is intended to form different examples.

Claims

1. A packaged semiconductor device, characterized in that: include: a substrate having a first substrate surface; A semiconductor component connected to the first substrate surface, the semiconductor component having a first main surface, a second main surface opposite the first main surface, and a side surface extending between the first main surface and the second main surface, wherein the semiconductor component comprises an optical device and the side surface of the semiconductor component comprises an emitter region, and wherein: The side surface includes a first side and a second side, the first side being close to the first outer side surface of the substrate and the second side being away from the first outer side surface of the substrate; and said first side including said emitter region; a conductive interconnect structure electrically connecting the semiconductor component to the substrate; and an encapsulated package covering at least a portion of the first substrate surface and covering the semiconductor component, wherein the emitter region is exposed to the outside of the encapsulated package, and wherein: The encapsulated package covers and contacts the second side; and The encapsulated package contacts the first major surface of the semiconductor component, including corner edges of the semiconductor component adjacent to the first major surface and the second side.

2. The packaged semiconductor device according to claim 1, wherein: The first side is exposed to the exterior of the packaged semiconductor device; and The encapsulated package encapsulates the conductive interconnect structure.

3. The packaged semiconductor device according to claim 1, wherein: The encapsulated package covers more than 50% but less than 100% of the first major surface of the semiconductor component.

4. The packaged semiconductor device according to claim 1, wherein: The encapsulated package covers more than 75% but less than 100% of the first major surface of the semiconductor component.

5. The packaged semiconductor device according to claim 1, wherein: The second side of the side surface of the semiconductor component is an inactive side.

6. The packaged semiconductor device according to claim 1, wherein: The substrate includes a second outer side surface, the second outer side surface is opposite to the first outer side surface; The encapsulated package body includes a first package body side surface, the first package body side surface being adjacent to the first side of the semiconductor component; The first package body side surface comprises a tapered shape; The encapsulated package body comprises a second package body side surface, the second package body side surface is opposite to the first package body side surface; and The second package body side surface is substantially coplanar with the second outer side surface of the substrate.

7. The packaged semiconductor device according to claim 1, wherein: The encapsulated package includes an epoxy material.

8. The packaged semiconductor device according to claim 1, wherein: The substrate comprises: an insulating structure, the insulating structure comprising the first substrate surface and a second substrate surface opposite to the first substrate surface; a conductive pattern, the conductive pattern being adjacent to a surface of the first substrate; a conductive pad, the conductive pad being adjacent to the second substrate surface; as well as A conductive interconnection path electrically couples the conductive pattern to the conductive pad.

9. The packaged semiconductor device according to claim 1, wherein: The first outer side surface of the substrate includes a singulation surface proximate to the first side of the semiconductor component; and The first side of the semiconductor component is disposed above the first substrate surface, laterally inward from the singulation surface, such that a portion of the first substrate surface is interposed between the first side of the semiconductor component and the singulation surface.

10. A packaged electronic device, characterized in that: include: a substrate having a major surface, a first side, and a second side opposite the first side; an electronic component coupled to the substrate, the electronic component having a first major surface, a second major surface opposite the first major surface, and side surfaces extending between the first major surface and the second major surface, wherein the side surfaces include an active side surface proximate the first side of the substrate; a conductive interconnect structure electrically coupling the electronic component to the substrate; as well as a package encapsulating the conductive interconnect structure, at least a portion of the major surface of the substrate, and the electronic component, wherein: The active side surface and a portion of the first main surface of the electronic component close to the active side surface are exposed to the outside of the package body; and The electronic component is coupled to the major surface of the substrate such that the active side surface of the electronic component is laterally inward of the first side, with a portion of the major surface of the substrate interposed between the first side and the active side surface.

11. The packaged electronic device according to claim 10, characterized in that: The side surface of the electronic component includes a passive side surface, and the passive side surface is away from the active side surface; The package body contacts the passive side surface; and The electronic component includes an optical component having an emitter adjacent to the active side surface.

12. The packaged electronic device according to claim 10, characterized in that: The package body contacts the electronic component; and The encapsulation body covers more than 50% but less than 100% of the first major surface of the electronic component.

13. The packaged electronic device according to claim 10, characterized in that: The package body includes a package body side surface, the package body side surface being close to the active side surface of the electronic component; and The package body side surface includes a tapered shape.

14. The packaged electronic device according to claim 10, characterized in that: The first side of the substrate includes a singulated surface proximate to the active side surface of the electronic component.

15. The packaged electronic device according to claim 10, characterized in that: The substrate comprises: an insulating structure, the insulating structure comprising the main surface and a second main surface opposite to the main surface; a conductive pattern adjacent to the major surface; a conductive pad adjacent to the second major surface; and a conductive interconnection path electrically coupling the conductive pattern to the conductive pad; and The electronic components are attached directly to the major surface.

16. A semiconductor device, characterized in that: include: a substrate having a substrate top surface and a substrate side surface; A semiconductor component coupled to the substrate top surface via a conductive interconnect structure, the semiconductor component having a first main surface, a second main surface opposite to the first main surface, a side surface extending between the first main surface and the second main surface, and an emitter region, wherein: The side surface of the semiconductor component includes: a first side surface portion; and a second side surface portion, which is opposite to the first side surface portion; the emitter region is close to the first side surface portion; The first side surface portion is close to a first portion of the substrate side surface; and The second side surface portion is away from the first portion of the side surface of the substrate; and a sealing structure covering at least a portion of the top surface of the substrate and covering the semiconductor component, wherein: The closed structure comprises: an insulating protection member covering and contacting the second side surface portion of the semiconductor component and covering the conductive interconnect structure; and A cover structure comprising: a sidewall coupled to the substrate top surface; a top portion coupled to and perpendicular to the sidewall, separated from the conductive interconnect structure, and above the insulating protection component; and Open your mouth; and The emitter region is exposed to the outside of the closed structure through the opening.

17. The semiconductor device according to claim 16, wherein: The cover structure comprises a monolithic structure; and The top portion covers more than 50% of the first main surface of the semiconductor component.

18. The semiconductor device according to claim 16, wherein: The cover structure includes an electrically conductive material.

19. The semiconductor device according to claim 16, wherein: The insulating protection member contacts the first main surface of the semiconductor component, including a corner edge of the semiconductor component adjacent to the first main surface and the second side surface portion.

20. The semiconductor device according to claim 16, wherein: The emitter region is configured to emit laser light at least at the first side surface portion.

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