Semiconductor device

Abstract

The invention provides a semiconductor device which can be reduced in size in a structure for electrically connecting a semiconductor chip arranged on a conductive substrate and a printed circuit board. A semiconductor device is provided with: a conductive substrate (1a); a plurality of semiconductor chips provided on the conductive substrate (1a); a printed substrate having a first conductive layer (12f) provided on the conductive substrate (1a), an insulating layer (11) provided on the first conductive layer (12f), and a second conductive layer (12a) provided on the insulating layer (11) and electrically connected to the first electrodes of the plurality of semiconductor chips; and a first external terminal (4a) provided on the second conductive layer (12a) and extending above the second conductive layer (12a).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device (power semiconductor module) having a power semiconductor element mounted thereon. Background Art

[0002] Patent Documents 1 and 2 disclose the following structures: a gate layer is arranged on a main surface metal layer via an insulating layer, and a gate terminal is connected to the gate layer via a bonding wire. Patent Document 3 discloses the following structure: an insulating circuit substrate includes a ceramic substrate and a circuit layer formed on one surface of the ceramic substrate, and the circuit layer is a laminated structure having a first circuit layer bonded to one surface of the ceramic substrate and a second circuit layer bonded to the surface of the first circuit layer.

[0003] Patent document 4 discloses the following method: a bonding material is sandwiched between each of the two surfaces of a ceramic raw material and a metal plate of the same shape and thickness made of the same material, and after the laminated body thereof is pressurized and heated in the lamination direction thereof to be bonded, the laminated body is cooled to form a circuit layer and a metal layer of symmetrical shape through the ceramic raw material. Patent document 5 discloses the following structure: an insulating circuit substrate, which is formed by bonding a circuit layer having a circuit pattern to one surface of a ceramic substrate and bonding a metal layer to the other surface, wherein the circuit layer has a first circuit layer bonded to the ceramic substrate and a second circuit layer bonded to the upper surface of the first circuit layer, and the metal layer has a first metal layer bonded to the ceramic substrate and a second metal layer bonded to the upper surface of the first metal layer.

[0004] Patent document 6 discloses the following structure: a first conductor layer, a first insulating substrate, a second conductor layer, and a second insulating substrate are stacked in order, and a third conductor layer and a fourth conductor layer are stacked on the second insulating substrate. Patent document 7 discloses a wiring substrate including a heat sink, an insulating layer fixed to the heat sink, and a conductive wiring circuit portion fixed to a surface of the insulating layer opposite to the heat sink, the insulating layer including at least one resin layer, and the heat sink and the wiring circuit portion having the same thermal expansion coefficient and thickness.

[0005] Patent document 8 discloses a structure including an insulating substrate, a first heat transfer body and a second heat transfer body disposed on the insulating substrate, a first substrate and a second substrate disposed on the first heat transfer body and the second heat transfer body, and a first signal terminal and a second signal terminal disposed on the first substrate and the second substrate. Patent document 9 discloses a structure including a gate layer disposed on a conductive plate via a substrate, and a gate terminal connected to the gate layer via a bonding wire.

[0006] Patent document 10 discloses a structure in which a gate wiring layer is arranged on a wiring layer via an insulating plate, and a gate terminal is connected to the gate wiring layer via a wire. Patent document 11 discloses a structure in which a gate layer is arranged on a conductive member via an insulating substrate, and a gate terminal is connected to the gate layer via a wire.

[0007] Patent Document 12 discloses a structure in which a control signal pattern is arranged on a conductor plate via an insulating plate, and a control signal terminal is connected to the control signal pattern via a bonding wire. Patent Document 13 discloses a structure in which a gate electrode terminal extends below between a plurality of chips.

[0008] Patent document 14 discloses a structure in which an end of a gate terminal is connected to a gate relay layer by a gate wiring. Patent document 15 discloses a structure in which a control wiring substrate having a gate wiring layer and a source wiring layer is arranged between semiconductor chips, and the gate terminal is connected to the gate wiring layer by a gate wiring.

[0009] Patent document 16 discloses a structure including a substrate, a first switching element and a second switching element provided on the substrate, and a conductor line provided on the substrate and connected to a signal terminal of the first switching element. Patent document 17 discloses a structure in which a silicon nitride circuit substrate is formed by bonding metal plates to both surfaces of a silicon nitride substrate, and a warp is formed in the silicon nitride substrate.

[0010] Patent Documents 18 and 19 disclose structures in which semiconductor chips are arranged on both sides of a printed wiring board, respectively. Patent Document 20 discloses a structure in which a lead pattern is provided on an aluminum plate via an adhesive resin, and an insertion terminal having a press-fit portion is inserted into a through hole of the lead pattern.

[0011] Prior art literature

[0012] Patent Literature

[0013] Patent Document 1: International Publication No. 2021 / 079913

[0014] Patent Document 2: Japanese Patent Application Publication No. 2021-190505

[0015] Patent Document 3: Japanese Patent Application Publication No. 2019-149460

[0016] Patent Document 4: Japanese Patent Application Publication No. 2018-137396

[0017] Patent Document 5: International Publication No. 2019 / 167931

[0018] Patent Document 6: Japanese Patent Application Publication No. 2016-92283

[0019] Patent Document 7: Japanese Patent Application Publication No. 2006-269966

[0020] Patent Document 8: Japanese Patent Application Publication No. 2020-21886

[0021] Patent Document 9: International Publication No. 2019 / 098368

[0022] Patent Document 10: Japanese Patent Application Publication No. 2020-77762

[0023] Patent Document 11: International Publication No. 2019 / 235146

[0024] Patent Document 12: International Publication No. 2017 / 163612

[0025] Patent Document 13: Japanese Patent Application Publication No. 2007-281443

[0026] Patent Document 14: Japanese Patent Application Publication No. 2021-141219

[0027] Patent Document 15: Japanese Patent Application Publication No. 2021-141220

[0028] Patent Document 16: Japanese Patent Application Publication No. 2014-192976

[0029] Patent Document 17: International Publication No. 2016 / 125635

[0030] Patent Document 18: U.S. Patent No. 8981545

[0031] Patent Document 19: U.S. Patent No. 9,659,912

[0032] Patent Document 20: Japanese Patent Application Publication No. 2018-73923 Summary of the invention

[0033] Problem that the invention aims to solve

[0034] In conventional power semiconductor modules, a semiconductor chip is mounted on a conductive substrate, and the semiconductor chip is electrically connected to a printed circuit board disposed on the conductive substrate using a lead frame and bonding wires. However, if the printed circuit board and external terminals are connected using wire bonding or a lead frame, the size becomes larger.

[0035] In view of the above problems, an object of the present disclosure is to provide a semiconductor device capable of being reduced in size in a structure for electrically connecting a semiconductor chip provided on a conductive substrate and a printed circuit board.

[0036] Solutions for solving problems

[0037] The main purpose of a technical solution of the present invention is a semiconductor device, wherein the semiconductor device comprises: a conductive substrate; a plurality of semiconductor chips having a first electrode and arranged on the conductive substrate; a printed circuit board having a first conductive layer arranged on the conductive substrate, an insulating layer arranged on the first conductive layer, and a second conductive layer arranged on the insulating layer and electrically connected to the first electrodes of the plurality of semiconductor chips; and a first external terminal arranged on the second conductive layer and extending above the second conductive layer.

[0038] In the semiconductor device, the first external terminal may include: a support portion provided on the second conductive layer; and an extension portion supported by the support portion and extending upward from the second conductive layer.

[0039] In the semiconductor device, the support portion may have an opening, and the end portion of the extending portion may be press-fitted into the opening.

[0040] In the semiconductor device, the insulating layer may have a planar pattern including a first region extending in one direction between the plurality of semiconductor chips and a second region extending in a direction orthogonal to the first region.

[0041] In the semiconductor device, the second conductive layer may be provided so as to straddle the first region and the second region.

[0042] In the semiconductor device, a plurality of second conductive layers may be provided in parallel on the second region, and the first external terminals may be provided on the plurality of second conductive layers, respectively, so that the plurality of first external terminals form a row.

[0043] It may be that in the semiconductor device, the plurality of semiconductor chips further have a second electrode, and the semiconductor device further comprises: a sealing resin, which seals the plurality of semiconductor chips; and a second external terminal, which is electrically connected to the second electrodes of the plurality of semiconductor chips, wherein a portion of the first external terminal protrudes from the upper surface of the sealing resin, and a portion of the second external terminal protrudes from the side surface of the sealing resin.

[0044] In addition, the above summary of the invention does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions.

[0045] Effects of the Invention

[0046] According to the present disclosure, it is possible to provide a semiconductor device capable of being reduced in size in a structure for electrically connecting a semiconductor chip provided on a conductive substrate and a printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a perspective view of the semiconductor device according to the first embodiment.

[0048] Figure 2 is with Figure 1 The corresponding top view.

[0049] Figure 3 This is a perspective view in which a part of the semiconductor device according to the first embodiment is omitted.

[0050] Figure 4 is with Figure 3 The corresponding top view.

[0051] Figure 5 is with Figure 3 and Figure 4 Corresponding side view.

[0052] Figure 6 Yes Figure 5 Magnified side view of area A.

[0053] Figure 7 This is a perspective view in which a part of the semiconductor device according to the first embodiment is omitted.

[0054] Figure 8 is with Figure 7 The corresponding top view.

[0055] Fig. 9 It is a cross-sectional view of a part of the mounting structure of the semiconductor device according to the first embodiment.

[0056] Fig.10 It is a cross-sectional view of a control terminal of the semiconductor device according to the first embodiment.

[0057] Fig.11 It is a perspective view of the conductive member of the semiconductor device according to the first embodiment.

[0058] Fig.12 It is a perspective view of the negative electrode terminal of the semiconductor device according to the first embodiment.

[0059] Fig.13 It is a perspective view of the resin member of the semiconductor device according to the first embodiment.

[0060] Fig.14 It is a side view of the mounting structure of the semiconductor device according to the first embodiment.

[0061] Fig.15 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0062] Fig.16 This is a perspective view in which a part of the semiconductor device according to the second embodiment is omitted.

[0063] Fig.17 is with Fig.16The corresponding top view.

[0064] Fig.18 It is a perspective view of a resin member of a semiconductor device according to a second embodiment.

[0065] Fig.19 It is a side view of the laminated structure of the semiconductor device according to the second embodiment.

[0066] Fig. 20 Yes Fig.19 Magnified side view of area A.

[0067] Fig.21 Yes Description Fig.19 A side view of the assembly method of the laminate structure shown.

[0068] Fig. 22 It is a perspective view of a conductive member of a semiconductor device according to a modification of the second embodiment.

[0069] Fig.23 It is a perspective view of a resin member of a semiconductor device according to a modification of the second embodiment.

[0070] Description of Reference Numerals

[0071] 1a, 1b, conductive substrate; 2a, negative terminal; 2b, positive terminal; 2c, output terminal; 3a~3l, semiconductor chip; 4a~4g, control terminal (first external terminal); 5, temperature detection chip; 6, conductive member; 8, 9, resin member; 10, sealing resin; 11, insulating layer; 12a~12e, conductive layer (second conductive layer); 12f, conductive layer (first conductive layer); 13, insulating layer; 14a~ 14c, conductive layer (second conductive layer); 15a~15c, pad portion; 21a~21f, chip bonding portion; 22a~22c, 23, connection portion; 23a, 23b, opening portion; 24, external connection portion; 31a~31l, source electrode; 41, support portion; 42, first end portion; 43, central portion; 44, second end portion; 61a~61c, pad bonding portion; 62, connection portion; 63a~63f, chip bonding 64a-64c, connecting portion; 65, connecting portion; 65a, 65b, recessed portion; 71a-71l, 72a-72l, 73a, 73b, 74, bonding line; 80, main body; 81a, 81b, 82, 83a-83c, opening; 84, supporting portion; 85a-85e, supporting portion; 90, flat portion; 91a-91c, strip portion; 92a, 92b, convex portion; 94, 95a-95f , protrusion; 97, connecting portion; 98a~98c, bonding material; 101, semiconductor device; 102, resin layer (resin sheet); 103, cooler (base); D1, D2, body diode; G1, G2, gate control terminal; N, negative terminal (second external terminal); P, positive terminal (second external terminal); S1, S2, auxiliary source terminal; T1, T2, transistor; U, output terminal (second external terminal). DETAILED DESCRIPTION

[0072] Hereinafter, the first embodiment and the second embodiment of the present disclosure will be described with reference to the accompanying drawings. In the description of the accompanying drawings referred to in the following description, the same or similar parts are marked with the same or similar figure marks. However, it should be noted that the accompanying drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual situation. Therefore, the specific thickness and size should be determined with reference to the following description. In addition, the drawings naturally also include parts with different relationship and ratio of size.

[0073] In addition, the definitions of directions such as "up", "down", "up and down", "left", "right", and "left and right" in the following description are only for the convenience of explanation and do not limit the technical ideas of the present disclosure. For example, it is natural that if the object is rotated 90° to observe, "up and down" should be understood as "left and right", and if it is rotated 180° to observe, "up and down" should be understood in reverse. In addition, the "upper surface" and "lower surface" can also be replaced by "front" and "back", respectively. In addition, the "first main surface" and "second main surface" of each component are main surfaces opposite to each other. For example, if the "first main surface" is the upper surface, the "second main surface" is the lower surface.

[0074] (First embodiment)

[0075] <Structure of Semiconductor Device>

[0076] Figure 1 is a perspective view of a semiconductor device (power semiconductor module) according to a first embodiment. Figure 2 FIG. 1 is a top view of the semiconductor device according to the first embodiment. Figure 1 and Figure 2 As shown, the semiconductor device of the first embodiment comprises: a sealing resin 10, which seals a power semiconductor element (semiconductor chip); and a second external terminal (negative terminal) 2a, a second external terminal (positive terminal) 2b, a second external terminal (output terminal) 2c and a first external terminal (control terminal) 4a~4g respectively protruding from the sealing resin 10.

[0077] The sealing resin 10 has a substantially rectangular parallelepiped shape. The negative terminal 2a and the positive terminal 2b protrude from the side of a common surface of the sealing resin 10, which is a substantially rectangular parallelepiped shape. The output terminal 2c protrudes from the side of a surface of the sealing resin 10, which is a substantially rectangular parallelepiped shape, which is opposite to the surface from which the negative terminal 2a and the positive terminal 2b protrude. The control terminals 4a to 4g protrude from the upper surface of a surface between the surface from which the negative terminal 2a and the positive terminal 2b protrude from the substantially rectangular parallelepiped shape of the sealing resin 10 and the surface from which the output terminal 2c protrudes.

[0078] The sealing resin 10 is made of insulating resin such as epoxy resin. The output terminal 2c, the positive terminal 2b, the negative terminal 2a and the control terminals 4a to 4g are made of conductive materials such as copper (Cu), Cu alloy, aluminum (Al) or Al alloy.

[0079] Figure 3 It is omitted Figure 1 and Figure 2 A perspective view of a semiconductor device according to a first embodiment of the present invention is shown in FIG. Figure 4 is with Figure 3 The corresponding top view, Figure 5 is with Figure 3 The corresponding side view, Figure 6 Yes Figure 5 Magnified side view of area A.

[0080] like Figure 3 to Figure 6 As shown in FIG. 1 , the semiconductor device of the first embodiment includes a conductive substrate 1a and a conductive substrate 1b that are disposed separately from each other. The conductive substrate 1a and the conductive substrate 1b have a substantially rectangular planar pattern. The conductive substrate 1a and the conductive substrate 1b are made of a conductive material such as copper (Cu) or aluminum (Al). The lower surfaces of the conductive substrates 1a and 1b are Figure 1 and Figure 2 The sealing resin 10 is shown exposed.

[0081] The output terminal 2c has a flat plate shape bent in the shape of the letter L, and is joined to the conductive substrate 1a via a bonding material such as solder or sintered material or by direct bonding. The positive terminal 2b has a flat plate shape bent in the shape of the letter L, and is joined to the conductive substrate 1b via a bonding material such as solder or sintered material or by direct bonding. The negative terminal 2a is arranged in parallel with the positive terminal 2b, and has an external connection portion 24 in the shape of a flat plate bent in the shape of the letter L. The negative terminal 2a is set to extend toward the output terminal 2c side and cross the conductive substrate 1a and the conductive substrate 1b. The control terminals 4a to 4g are set to extend parallel to each other in a direction perpendicular to the upper surfaces of the conductive substrates 1a and 1b.

[0082] Although in Figure 3 and Figure 4 Although not shown in the figure, there is a Fig.11 The conductive member (also called "intermediate clip" or "lead frame") 6 is shown. The conductive member 6 is arranged in a manner opposed to and separated from a part of the negative terminal 2a. A part of the negative terminal 2a and a part of the conductive member 6 are covered by a resin member 8.

[0083] The negative terminal 2a, the conductive component 6 and the resin component 8 are integrally formed by integral molding, etc., to form an integrated structure (2a, 6, 8). A portion of the resin component 8 is sandwiched between the negative terminal 2a and the conductive component 6. By integrally forming the negative terminal 2a, the conductive component 6 and the resin component 8, and using the resin component 8 to maintain the gap between the negative terminal 2a and the conductive component 6, low inductance, insulation characteristics, and gap management (evaluation) can be achieved. In addition, by making the negative terminal 2a, the conductive component 6 and the resin component 8 into one component, the cost increase caused by the complication of the jig and the lead frame can be suppressed, and the man-hour reduction can be achieved. The structures of the negative terminal 2a, the conductive component 6 and the resin component 8 will be described later.

[0084] Figure 7 It is omitted Figure 1 and Figure 2 The sealing resin 10 of the semiconductor device of the first embodiment shown in the figure is a perspective view of an integrated structure (2a, 6, 8) composed of the negative electrode terminal 2a, the conductive member 6 and the resin member 8, which is also omitted. Figure 8 is with Figure 7 The corresponding top view.

[0085] like Figure 7 and Figure 8 As shown, the semiconductor device of the first embodiment includes: a plurality of (6) power semiconductor elements (semiconductor chips) 3a to 3f, which are arranged on the upper surface side of the conductive substrate 1a; and a plurality of (6) power semiconductor elements (semiconductor chips) 3g to 3l, which are arranged on the upper surface side of the conductive substrate 1b. The semiconductor chips 3a to 3f are bonded to the conductive substrate 1a via a bonding material such as solder or sintered material. The semiconductor chips 3a to 3f are arranged on the conductive substrate 1a in a manner of being connected in parallel to form the first column and the second column. The semiconductor chips 3g to 3l are bonded to the conductive substrate 1b via a bonding material such as solder or sintered material. The semiconductor chips 3g to 3l are arranged on the conductive substrate 1b in a manner of being connected in parallel to form the first column and the second column.

[0086] In the semiconductor device of the first embodiment, MOSFET is exemplified as the semiconductor chips 3a to 31, and a two-in-one power semiconductor module is exemplified in which MOSFET is connected in parallel in two pairs in series. The semiconductor chips 3a to 3f constitute the lower arm of the half-bridge circuit of one phase of the three-phase inverter circuit, and the semiconductor chips 3g to 31 constitute the upper arm. In addition, the semiconductor device of the first embodiment is not limited to a two-in-one semiconductor module, and may be, for example, a six-in-one semiconductor module.

[0087] The semiconductor chips 3a to 3l have a semiconductor substrate, a first main electrode (drain electrode) provided on the lower surface side of the semiconductor substrate, a second main electrode (source electrode) 31a to 31l provided on the upper surface side of the semiconductor substrate, and a control electrode (gate electrode). The drain electrodes of the semiconductor chips 3a to 3f are electrically connected to the conductive substrate 1a. The drain electrodes of the semiconductor chips 3g to 3l are electrically connected to the conductive substrate 1b.

[0088] The semiconductor substrate of the semiconductor chips 3a to 3l is composed of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), etc. The configuration position and number of the semiconductor chips 3a to 3l are not particularly limited. In addition to field effect transistors (FETs) such as MOSFETs, the semiconductor chips 3a to 3l may also be insulated gate bipolar transistors (IGBTs), reverse conducting insulated gate bipolar transistors (RC-IGBTs) formed by connecting a diode and an IGBT in reverse parallel, electrostatic induction (SI) thyristors, or gate turn-off (GTO) thyristors, etc.

[0089] A printed circuit board (11, 12a to 12f) for control wiring is arranged on the upper surface side of the conductive substrate 1a. This printed circuit board is also called a control wiring board. The printed circuit board (11, 12a to 12f) includes an insulating layer 11, conductive layers 12a to 12e arranged on the upper surface side of the insulating layer 11 in a manner separated from each other, and a conductive layer 12f located on the lower surface side of the insulating layer 11 and having a width narrower than the insulating layer 11 (see Fig. 9 ).

[0090] The insulating layer 11 has a plurality of semiconductor chips 3a to 3f extending in one direction ( Figure 8 The first region extending in the vertical direction) and the first region extending in the direction orthogonal to the first region ( Figure 8 The second area extends in the left and right directions. Figure 7 and Figure 8 In the example, the insulating layer 11 has a plane pattern in the shape of the letter T, but the present invention is not limited thereto. For example, the insulating layer 11 may also have a plane pattern in the shape of the letter L. The conductive layers 12a to 12e are arranged in a row on the second region of the insulating layer 11. The conductive layers 12a and 12b are arranged across the first region and the second region of the insulating layer 11. The control terminals 4a to 4d are arranged in a row on the conductive layers 12a to 12d.

[0091] The insulating layer 11 is composed of, for example, a ceramic plate mainly made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or a resin insulating layer made of a polymer material. The resin insulating layer may also be a layer made by impregnating glass fiber with epoxy resin. The conductive layers 12a to 12f are composed of, for example, copper (Cu), aluminum (Al), or the like.

[0092] Fig. 9 is and in Figure 7 and Figure 8A cross-sectional view of a printed circuit board (11, 12a to 12f) arranged between a semiconductor chip 3b and a semiconductor chip 3e in a mounting structure of a semiconductor device. The semiconductor chip 3b is bonded to the upper surface side of the conductive substrate 1a via a bonding material 98a. The semiconductor chip 3e is bonded to the upper surface side of the conductive substrate 1a via a bonding material 98b. The conductive layer 12f of the printed circuit board (11, 12a to 12f) is bonded to the upper surface side of the conductive substrate 1a via a bonding material 98c. Solder or sintered material can be used as the bonding materials 98a to 98c.

[0093] The width of the conductive layer 12f is narrower than the width of the insulating layer 11. Therefore, as shown by the dotted line, a long creeping insulation distance can be ensured from the end of the conductive layer 12f to the end of the conductive layers 12a and 12b via the end lower surface, side surface, and end upper surface of the insulating layer 11. That is, since the end lower surface and the end upper surface of the insulating layer 11 overlap, the distance between the semiconductor chip 3b and the semiconductor chip 3e can be shortened compared to when the insulating layer 11 is directly disposed on the upper surface of the conductive substrate 1a. Figure 7 and Figure 8 The cross section of the printed substrate (13, 14a, 14b) between the semiconductor chips 3h and 3k shown is also the same, so repeated description is omitted. In addition, although not shown, a conductive layer having a width narrower than the width of the insulating layer 13 is arranged on the lower surface side of the insulating layer 13 of the printed substrate (13, 14a, 14b), which is the same as the conductive layer 12f of the printed substrate (11, 12a to 12f).

[0094] The insulating layer 11 and the conductive layer 12a are arranged in a manner extending from the end of the conductive substrate 1a to between the semiconductor chips 3a to 3c and the semiconductor chips 3d to 3f. The wider areas of the conductive layer 12a and the conductive layer 12b are arranged alternately. The wider area of ​​the conductive layer 12a is electrically connected to the local source electrodes 31a to 31f of each of the semiconductor chips 3a to 3f via the control wiring (bonding wire) 72a to 72f. The control terminal 4a is bonded to the conductive layer 12a using a bonding material such as solder or sintering material. The control terminal 4a stands up toward the top of the conductive layer 12a and extends in a direction perpendicular to the upper surface of the conductive layer 12a. The control terminal 4a applies a control signal to the source electrodes 31a to 31f of each of the semiconductor chips 3a to 3f via the conductive layer 12a and the bonding wires 72a to 72f.

[0095] The conductive layer 12b is provided in parallel with the conductive layer 12a so as to extend from the end of the conductive substrate 1a to between the semiconductor chips 3a to 3c and the semiconductor chips 3d to 3f. The wider region of the conductive layer 12b is electrically connected to the gate electrodes (not shown) of the semiconductor chips 3a to 3f via the control wiring (bonding wires) 71a to 71f. The control terminal 4b is bonded to the conductive layer 12b using a bonding material such as solder or a sintered material. The control terminal 4b stands upward toward the conductive layer 12b and extends in a direction perpendicular to the upper surface of the conductive layer 12b. The control terminal 4b is connected to the gate electrodes of the semiconductor chips 3a to 3f via the bonding wires 71a to 71f and the conductive layer 12b. When the semiconductor chips 3a to 3f are turned on, a voltage is applied to the control terminal 4a, and a voltage obtained by adding a voltage value of the control terminal 4a to a voltage value above the threshold of the semiconductor chips 3a to 3f is applied to the control terminal 4b.

[0096] The temperature detection chip 5 having two electrodes (not shown) on the surface is bonded to the conductive layer 12e using a bonding material such as solder or a sintered material.

[0097] The control terminal 4c is bonded to the conductive layer 12c using a bonding material such as solder or sintered material. The control terminal 4c stands upward from the conductive layer 12c and extends in a direction perpendicular to the upper surface of the conductive layer 12c. The conductive layer 12c is connected to one electrode of the temperature detection chip 5 via a control wiring (bonding wire) 73a.

[0098] The control terminal 4d is bonded to the conductive layer 12d using a bonding material such as solder or sintered material. The control terminal 4d stands upward from the conductive layer 12d and extends in a direction perpendicular to the upper surface of the conductive layer 12d. The conductive layer 12d is connected to another electrode of the temperature detection chip 5 via a control wiring (bonding wire) 73b.

[0099] The control terminals 4 c and 4 d transmit the temperature detection signal from the temperature detection chip 5 to the outside via the bonding wires 73 a and 73 b and the conductive layers 12 c and 12 d.

[0100] The pads 15a to 15c are provided on the upper surface side of the conductive substrate 1a at a position adjacent to the conductive substrate 1b. The pads 15a to 15c are bonded to the upper surface of the conductive substrate 1a using a bonding material such as solder or a sintered material. The pads 15a to 15c are made of a conductive material such as copper (Cu) or aluminum (Al). The pads 15a to 15c may also be formed integrally with the conductive substrate 1a.

[0101] A printed circuit board (13, 14a to 14c) for control wiring is arranged on the upper surface side of the conductive substrate 1b. The printed circuit board (13, 14a to 14c) includes an insulating layer 13 and conductive layers 14a to 14c arranged on the upper surface side of the insulating layer 13 to be separated from each other. The insulating layer 13 can be made of the same material as the insulating layer 11, and the conductive layers 14a to 14c can be made of the same material as the conductive layers 12a to 12e.

[0102] The insulating layer 13 has a plurality of semiconductor chips 3g to 3l extending in one direction ( Figure 8 The first region extending in the vertical direction) and the first region extending in the direction orthogonal to the first region ( Figure 8 The second area extends in the left and right directions. Figure 7 and Figure 8 In the example, the insulating layer 13 has a plane pattern in the shape of the letter T, but the present invention is not limited thereto. For example, the insulating layer 13 may also have a plane pattern in the shape of the letter L. The conductive layers 14a to 14c are arranged in a row on the second region of the insulating layer 13. The conductive layers 14a and 14b are arranged across the first region and the second region of the insulating layer 13. The control terminals 4e to 4g are arranged in a row on the conductive layers 14a to 14c.

[0103] The insulating layer 13 and the conductive layer 14a are arranged so as to extend from the end of the conductive substrate 1b to between the semiconductor chips 3g to 3i and the semiconductor chips 3j to 3l. The wider areas of the conductive layer 14a and the conductive layer 14b are arranged alternately. The wider area of ​​the conductive layer 14a is electrically connected to the local source electrodes 31g to 31l of the semiconductor chips 3g to 3l via the control wiring (bonding wires) 72g to 72l. The control terminal 4e is bonded to the conductive layer 14a using a bonding material such as solder or sintered material. The control terminal 4e stands up toward the top of the conductive layer 14a and extends in a direction perpendicular to the upper surface of the conductive layer 14a. The control terminal 4e applies a control signal to the source electrodes 31g to 31l of the semiconductor chips 3g to 3l via the conductive layer 14a and the bonding wires 72g to 72l.

[0104] The conductive layer 14b is provided in parallel with the conductive layer 14a so as to extend from the end of the conductive substrate 1b to between the semiconductor chips 3g to 3i and the semiconductor chips 3j to 3l. The wider region of the conductive layer 14b is electrically connected to the gate electrodes (not shown) of the semiconductor chips 3g to 3l via the control wiring (bonding wires) 71g to 71l. The control terminal 4f is bonded to the conductive layer 14b using a bonding material such as solder or a sintered material. The control terminal 4f stands upward toward the conductive layer 14b and extends in a direction perpendicular to the upper surface of the conductive layer 14b. The control terminal 4f is connected to the gate electrodes of the semiconductor chips 3g to 3l via the bonding wires 71g to 71l and the conductive layer 14b. When the semiconductor chips 3g to 3l are turned on, a voltage is applied to the control terminal 4e, and a voltage obtained by adding a voltage value above the threshold of the semiconductor chips 3g to 3l to the voltage value of the control terminal 4e is applied to the control terminal 4f.

[0105] The conductive layer 14c is connected to the conductive substrate 1b via a control wiring (bonding wire) 74. A control terminal 4g is bonded to the conductive layer 14c using a bonding material such as solder or a sintered material. The control terminal 4g stands upward toward the conductive layer 14c and extends in a direction perpendicular to the upper surface of the conductive layer 14c. The control terminal 4g transmits the current signal flowing in the drain electrode of the semiconductor chips 3g to 3l to the outside via the bonding wire 74 and the conductive layer 14c.

[0106] Fig.10 is with Figure 7 and Figure 8 The control terminal 4a is shown in a cross-sectional view related to the control terminal 4a. The control terminal 4a is provided on the upper surface side of the conductive substrate 1a via the conductive layer 12f, the insulating layer 11 and the conductive layer 12a of the printed circuit board (11, 12a to 12f). The control terminal 4a includes a support portion 41 and an extension portion (42, 43, 44) supported by the support portion 41. The support portion 41 is composed of, for example, a cylindrical sleeve having an opening. The support portion 41 is bonded to the conductive layer 12a using a bonding material such as solder or a sintered material.

[0107] The extension portions 42, 43, 44 are constituted by, for example, press-fit pins. The extension portions (42, 43, 44) include a first end portion (lower end portion) 42 supported by the support portion 41, a central portion 43 continuous with the first end portion 42, and a second end portion (upper end portion) 44 continuous with the central portion 43. The shape of the first end portion 42 is not particularly limited, as long as it is a shape that can be pressed into and fixed to the opening portion of the support portion 41. The central portion 43 extends in a direction perpendicular to the upper surface of the conductive substrate 1a. The shape of the central portion 43 is not particularly limited, and may be a flat plate, a pin, a rod, a cylinder, a polygonal column, or the like. The second end portion 44 has a wide portion that can be pressed into a through hole of an external component. The shape of the second end portion 44 is not particularly limited, as long as it can be electrically connected to an external component. Figure 7 and Figure 8 The control terminals 4b to 4g shown also have Fig.10 The control terminal 4a shown has the same structure.

[0108] Fig.11 A perspective view showing the conductive member 6 as a constituent element of the integrated structure (2a, 6, 8). Fig.11 As shown, the conductive member 6 includes pad bonding portions 61a to 61c, connecting portions 62 connected to the pad bonding portions 61a to 61c, chip bonding portions 63a to 63c connected to the connecting portions 62, connecting portions 64a to 64c connected to the chip bonding portions 63a to 63c, and chip bonding portions 63d to 63f connected to the connecting portions 64a to 64c. The pad bonding portions 61a to 61c and the chip bonding portions 63a to 63f are bent and connected to the connecting portions 62 and the connecting portions 64a to 64c in a manner convex to the lower side. The connecting portions 64a to 64c have a planar pattern of stripes that are separated from each other and extend in parallel.

[0109] At least the lower surface of the pad bonding portions 61a to 61c is Figure 3 to Figure 6 The resin member 8 is exposed. The pad bonding portions 61a to 61c are bonded to the substrate using a bonding material such as solder or sintered material. Figure 7 and Figure 8 The pads 15a to 15c are formed on the upper surface of the conductive substrate 1a. The connection portion 62 and the connection portions 64a to 64c are Figure 3 to Figure 6 The die bonding portions 63a to 63f are covered with the resin member 8 shown. Figure 3 to Figure 6 The resin member 8 is exposed. The die bonding portions 63a to 63f are bonded to the die using a bonding material such as solder or sintered material. Figure 7 and Figure 8 The semiconductor chips 3g to 31 are shown with source electrodes 31g to 311.

[0110] Fig.12 A perspective view showing the negative electrode terminal 2a as a constituent element of the integrated structure (2a, 6, 8). Fig.12 As shown, the negative terminal 2a includes chip bonding parts 21a to 21c, connecting parts 22a to 22c connected to the chip bonding parts 21a to 21c, chip bonding parts 21d to 21f connected to the connecting parts 22a to 22c, a connecting part 23 connected to the chip bonding parts 21d to 21f, and an external connecting part 24 connected to the connecting part 23. The chip bonding parts 21a to 21f, the connecting parts 22a to 22c, and the external connecting part 24 are connected to the connecting parts 23. Figure 3 to Figure 6 The resin member 8 is shown exposed. A portion of the connecting portion 23 is Figure 3 to Figure 6 The resin member 8 shown is exposed, and another part of the connection portion 23 is covered by the resin member 8 .

[0111] Fig.12 The die bonding portions 21a to 21f shown are bent so as to protrude downward and connected to the connection portions 22a to 22c. The die bonding portions 21a to 21f are bonded to the connection portions 22a to 22c using a bonding material such as solder or sintered material. Figure 7 and Figure 8 The source electrodes 31a to 31f of the semiconductor chips 3a to 3f shown in the figure and the connection portions 22a to 22c have a planar pattern of stripes extending in parallel and spaced apart from each other.

[0112] The connecting portion 23 has a substantially rectangular planar pattern. Fig.11 The pad bonding portions 61a to 61c, the connecting portion 62, the chip bonding portions 63a to 63f, and the connecting portions 64a to 64c of the conductive member 6 are arranged opposite to each other. The connecting portion 23 is provided with openings 23a and 23b that penetrate from the upper surface to the lower surface of the connecting portion 23. The openings 23a and 23b have a substantially rectangular planar pattern. The opening 23a is shaped similar to the Fig.11 The opening 23b is arranged so as to overlap with the space between the connecting parts 64a and 64b. Fig.11 The connection portions 64b and 64c are arranged so that the spaces between them overlap.

[0113] In a plan view, the opening 23a is Figure 7 and Figure 8 The control wiring regions including the bonding wires 71h, 71k, 72h, and 72k connected to the semiconductor chips 3h and 3k are arranged so as to overlap. Figure 7 and Figure 8 The control wiring regions shown, including bonding wires 71i, 71l, 72i, and 72l connected to the semiconductor chips 3i and 3l, are arranged in an overlapping manner.

[0114] In addition, the portion of the external connection part 24 in the negative terminal 2a can also be defined as a "negative terminal", and the portion other than the external connection part 24, namely the chip bonding parts 21a~21c, the connecting parts 22a~22c, the chip bonding parts 21d~21f and the connecting part 23 can be defined as a "lead frame" integrated with the "negative terminal".

[0115] Fig.13 A perspective view showing a resin member 8 as a constituent element of the integrated structure (2a, 6, 8). Fig.13As shown, the resin member 8 has a main body 80 having a substantially rectangular parallelepiped shape. An opening 82 and openings 83a to 83c are provided on the side of the main body 80. A portion of the connection portion 23 of the negative terminal 2a is exposed from the opening 82. The pad bonding portions 61a to 61c of the conductive member 6 are exposed from the openings 83a to 83c. The main body 80 is provided with openings 81a and 81b extending from the upper surface of the main body 80 to the lower surface. The openings 81a and 81b are provided so as to be aligned with the conductive member 6. Fig.12 The negative electrode terminal 2a shown is provided so that the openings 23a and 23b overlap with each other.

[0116] like Figure 3 and Figure 4 As shown in FIG. 1 , when the integrated structure (2a, 6, 8) is arranged on the upper surface side of the conductive substrates 1a and 1b, the opening 81a of the resin member 8 is located at a position overlapping with the control wiring area including the bonding wires 71h, 71k, 72h, and 72k connected to the semiconductor chips 3h and 3k in a plan view. The opening 81b is arranged so as to overlap with the control wiring area including the bonding wires 71i, 71l, 72i, and 72l connected to the semiconductor chips 3i and 3l.

[0117] like Figures 4 to 6 As shown in FIG. 1 , a support portion 84 and support portions 85a to 85e are provided on the lower surface side of the main body portion 80. Figure 4 , the support portions 85a to 85e hidden under the main body 80 are schematically shown by dotted lines. The support portion 84 and the support portions 85a to 85e are formed integrally with the main body 80. The support portion 84 is arranged on the upper surface side of the conductive substrate 1a. The support portions 85a to 85e are arranged on the upper surface side of the conductive substrate 1b. The shape of the support portions 85a to 85e is, for example, cylindrical, but is not particularly limited. The configuration position and number of the support portions 85a to 85e are not particularly limited.

[0118] By providing a support portion 84 and support portions 85a to 85e on the lower surface side of the main body 80, when the chip bonding portions 21a to 21f of the negative terminal 2a and the chip bonding portions 63a to 63f of the conductive component 6 are welded to the source electrodes of the semiconductor chips 3a to 3l, the inclination of the integrated structure (2a, 6, 8) including the chip bonding portions 21a to 21f and the chip bonding portions 63a to 63f can be suppressed, thereby controlling the height of the integrated structure (2a, 6, 8).

[0119] The surface of the resin member 8 may also be roughened by performing a process such as pleating to roughen the surface. By roughening the surface of the resin member 8, it is possible to prevent the resin member 8 from peeling off from the sealing resin 10 and improve the adhesion. The surface of the resin member 8 may be roughened as a whole or a part of the surface of the resin member 8 may be roughened locally.

[0120] Fig.14 1 is a schematic side view of the mounting structure of the semiconductor device 101 according to the first embodiment. The semiconductor device 101 corresponds to Figure 1 and Figure 2 In the semiconductor device shown, the lower surfaces of the conductive substrates 1a and 1b are exposed on the lower surface side of the semiconductor device 101. On the lower surface side of the semiconductor device 101, a cooler (base) 103 is arranged via a sheet-like resin layer (resin sheet) 102.

[0121] The resin sheet 102 ensures heat dissipation from the semiconductor device 101 to the cooler 103 and has the function of insulating and bonding the semiconductor device 101 and the cooler 103. As the material of the resin sheet 102, for example, epoxy resin can be used. As the material of the cooler 103, for example, copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), a composite material of magnesium (Mg) and silicon carbide (MgSiC), etc. can be used.

[0122] According to the mounting structure of the semiconductor device 101 , compared with the case where an insulating circuit substrate and a cooler are joined by solder, the functions of insulation, bonding, and heat dissipation can be concentrated on the resin sheet 102 , thereby reducing costs.

[0123] Fig.15 : is an equivalent circuit of the semiconductor device according to the first embodiment. Fig.15 As shown, the semiconductor device of the first embodiment constitutes a part of a three-phase bridge circuit. The drain electrode of the transistor T1 on the upper arm side is connected to the positive terminal P, and the source electrode of the transistor T2 on the lower arm side is connected to the negative terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1. The auxiliary source terminal S2 is connected to the source electrode of the transistor T2. The gate control terminals G1 and G2 are connected to the gate electrodes of the transistors T1 and T2. Body diodes D1 and D2, which serve as freewheeling diodes (FWD), are built-in in the transistors T1 and T2 and are connected in reverse parallel.

[0124] Fig.15 The output terminal U, the positive terminal P and the negative terminal N shown correspond to Figure 7 and Figure 8 The output terminal 2c, the positive terminal 2b and the negative terminal 2a are shown. Fig.15 The transistor T1 and body diode D1 shown correspond to Figure 7 and Figure 8 The semiconductor chips 3g to 31 are shown. Fig.15 The transistor T2 and body diode D2 shown correspond to Figure 7 and Figure 8The semiconductor chips 3a to 3f are shown. Fig.15 The gate control terminals G1 and G2 shown correspond to Figure 7 and Figure 8 Control terminals 4b, 4f are shown. Fig.15 The auxiliary source terminals S1, S2 shown correspond to Figure 7 and Figure 8 Control terminals 4a, 4e are shown.

[0125] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment is described. Figure 7 and Figure 8 As shown, on the upper surface of the conductive substrate 1a, the output terminal 2c, the semiconductor chips 3a to 3f, the printed circuit board (11, 12a to 12e) and the pads 15a to 15c are bonded using a bonding material such as solder or sintered material. Furthermore, on the upper surface of the printed circuit board (11, 12a to 12e), the control terminals 4a to 4d and the temperature detection chip 5 are bonded using a bonding material such as solder or sintered material. At this time, as shown in FIG. Fig.10 As shown, the support portion 41 is bonded to the upper surface of the conductive layer 12a via a bonding material such as solder or sintered material. Then, the first end portion 42 of the extension portion (42, 43, 44) is pressed into the support portion 41, so that the control terminal 4a is set to stand in a direction perpendicular to the upper surface of the conductive layer 12a. The control terminals 4b to 4d are also provided in the same manner as the control terminal 4a. Furthermore, the gate electrodes (not shown) of the semiconductor chips 3a to 3f are connected to the conductive layer 12b of the printed substrate 11 by bonding wires 71a to 71f for gate signals, the source electrodes (not shown) of the semiconductor chips 3a to 3f are connected to the conductive layer 12a of the printed substrate 11 by bonding wires 72a to 72f for auxiliary sources, and then one electrode of the temperature detection chip 5 is connected to the conductive layer 12c of the printed substrate 11 by bonding wires 73a for temperature signals, and the other electrode of the temperature detection chip 5 is connected to the conductive layer 12d of the printed substrate 11 by bonding wires 73b for temperature signals.

[0126] In addition, if Figure 7 and Figure 8As shown, the positive terminal 2b, the semiconductor chips 3g to 31, and the printed circuit board (13, 14a to 14c) are bonded to the upper surface of the conductive substrate 1b using a bonding material such as solder or sintered material. Furthermore, the control terminals 4e to 4g are bonded to the upper surface of the printed circuit board (13, 14a to 14c) using a bonding material such as solder or sintered material. The control terminals 4e to 4g are also provided to stand in a direction perpendicular to the upper surface of the conductive layer 14a to 14c, similarly to the control terminal 4a. Furthermore, the gate electrodes (not shown) of the semiconductor chips 3g to 31 and the conductive layer 14b of the printed circuit board 13 are connected to each other using bonding wires 71g to 71l for gate signals, and the source electrodes (not shown) of the semiconductor chips 3g to 31 and the conductive layer 14a of the printed circuit board 13 are connected to each other using bonding wires 72g to 72l for auxiliary sources. Then, the conductive substrate 1b and the conductive layer 14c of the printed circuit board 13 are connected to each other using bonding wires 74.

[0127] In addition, the mold will Fig.11 The conductive member 6 shown, Fig.12 The negative terminal 2a and Fig.13 The resin member 8 shown is integrally molded to produce an integrated structure (2a, 6, 8).

[0128] Then, if Figure 3 to Figure 6 As shown, the conductive substrate 1a to which the semiconductor chips 3a to 3f and the like are bonded and the conductive substrate 1b to which the semiconductor chips 3g to 31 and the like are bonded are placed opposite to the integrated structure (2a, 6, 8). Then, the chip bonding portions 21a to 21f of the negative electrode terminal 2a of the constituent element of the integrated structure (2a, 6, 8) are bonded to the source electrodes 31a to 31f of the semiconductor chips 3a to 3f using a bonding material such as solder or a sintered material. In addition, the chip bonding portions 63a to 63f of the conductive member 6 of the constituent element of the integrated structure (2a, 6, 8) are bonded to the source electrodes 31g to 31l of the semiconductor chips 3g to 31 using a bonding material such as solder or a sintered material. In addition, the pad bonding portions 61a to 61c of the conductive member 6 are bonded to the pad portions 15a to 15c on the upper surface side of the conductive substrate 1a using a bonding material such as solder or a sintered material.

[0129] Next, using transfer molding, such as Figure 1 As shown, the semiconductor chips 3a to 31 and the like are sealed with the sealing resin 10. Thus, the semiconductor device of the first embodiment is completed.

[0130] According to the semiconductor device of the first embodiment, the negative terminal 2a, the conductive component 6 and the resin component 8 are integrally formed to form an integrated structure (2a, 6, 8), the main wiring circuit is three-dimensionally wired, and the control wiring circuit is made into an independent substrate using a printed substrate (11, 12a~12e) for control wiring and a printed substrate (13, 14a~14c).

[0131] Therefore, compared with the previous semiconductor device, that is, a semiconductor chip is mounted on the circuit pattern of an insulating circuit substrate, and the semiconductor chip and the circuit pattern of the insulating circuit substrate are electrically connected by a lead frame and bonding wires, etc., the wiring area can be reduced, thereby reducing the chip size and cost increase, and achieving low inductance characteristics.

[0132] Furthermore, control terminals 4a to 4g are directly provided on printed substrates (11, 12a to 12e) and printed substrates (13, 14a to 14c) provided on conductive substrates 1a and 1b, and the control terminals 4a to 4g are extended upward from the printed substrates (11, 12a to 12e) and printed substrates (13, 14a to 14c). Thus, the size of the semiconductor device can be reduced, and the control terminals 4a to 4g can be firmly bonded to the printed substrates (11, 12a to 12e) and printed substrates (13, 14a to 14c), compared with a case where the control terminals 4a to 4g are connected to the printed substrates (11, 12a to 12e) and printed substrates (13, 14a to 14c) via bonding wires or lead frames.

[0133] In addition, compared with the conventional semiconductor device, that is, a printed circuit board is arranged above a semiconductor chip mounted on an insulating circuit board, and the semiconductor chip and the printed circuit board are electrically connected using pin terminals, the reliability of the connection part can be ensured, and inspection is easy, and low cost can be achieved. In addition, there is no problem of warping and thermal deformation of the printed circuit board, and the mounting performance and reliability can be ensured, and it is easy to handle.

[0134] Furthermore, compared with a conventional semiconductor device in which an insulating circuit substrate is surrounded by a case and sealed by injecting a resin through potting, a case is not required, thereby reducing space, man-hours, and costs.

[0135] Thus, according to the semiconductor device of the first embodiment, a wiring technology that is low-cost and easy to manufacture can be realized without using a complicated component position accuracy control technology, and a low inductance characteristic that maximizes the switching characteristics of a semiconductor chip composed of silicon carbide (SiC) etc. can be realized while maintaining the heat dissipation characteristics. For example, when using a semiconductor chip composed of SiC, in order to reduce costs, a plurality of small chips are sometimes connected in parallel, and in the case of mounting a plurality of semiconductor chips in this way, the effect of reducing the wiring area is large, which is particularly effective.

[0136] (Second embodiment)

[0137] The semiconductor device structure of the second embodiment Figure 1 and Figure 2 The semiconductor device of the first embodiment shown has the same appearance. Fig.16 It is omitted Figure 1 and Figure 2 A perspective view of a semiconductor device according to a second embodiment of the present invention is shown in FIG. Fig.17 is with Fig.16 Corresponding plan view The semiconductor device according to the second embodiment includes a printed circuit board similar to the printed circuit board of the semiconductor device according to the first embodiment.

[0138] like Fig.16 and Fig.17 As shown in FIG. 1 , the semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that the semiconductor device includes a resin member 9 arranged in a manner sandwiched between the negative electrode terminal 2a and the conductive member 6. In the semiconductor device of the second embodiment, a laminated structure (2a, 6, 9) is formed by laminating the negative electrode terminal 2a, the conductive member 6, and the resin member 9. The negative electrode terminal 2a and the conductive member 6, which are components of the laminated structure (2a, 6, 9), are respectively Fig.12 The negative terminal 2a and Fig.11 The conductive member 6 shown is constructed in the same manner.

[0139] Fig.18 A perspective view showing a resin member 9 as a constituent element of the laminated structure (2a, 6, 9). Fig.18 As shown in FIG. 1 , the resin member 9 includes a flat portion 90 and strip portions 91a to 91c connected to the flat portion 90. The flat portion 90 is disposed at Fig.11 The connecting portion 62 of the conductive member 6 is shown Fig.12 The flat portion 90 is provided with a protrusion 94 on the lower surface side. The protrusion 94 is embedded in the Fig.11 The pad bonding portions 61a to 61c shown are bent downwardly of the conductive member 6. In addition, the protruding portion 94 may not be provided.

[0140] The strip portion 91a is arranged on Fig.11 The die bonding portion 63a, the connecting portion 64a and the die bonding portion 63d of the conductive member 6 are shown in FIG. Fig.12 The connecting portion 23 of the negative terminal 2a shown in the figure is between the strip-shaped portions on the end side of the opening 23a. The strip-shaped portion 91a is provided with protrusions 95a and 95d on the lower surface side. The protrusions 95a and 95d are embedded in Fig.11 The conductive member 6 shown has die bonding portions 63 a and 63 d bent downward.

[0141] The strip portion 91b is arranged on Fig.11 The die bonding portion 63b, the connecting portion 64b and the die bonding portion 63e of the conductive member 6 are shown. Fig.12 The strip-shaped portion 91b is provided between the openings 23a and 23b of the connecting portion 23 of the negative electrode terminal 2a. The protrusions 95b and 95e are provided on the lower surface side of the strip-shaped portion 91b. The protrusions 95b and 95e are embedded in Fig.11 The conductive member 6 shown has die bonding portions 63 b and 63 e bent downward.

[0142] The strip portion 91c is arranged on Fig.11 The die bonding portion 63c, the connecting portion 64c and the die bonding portion 63f of the conductive member 6 are shown in FIG. Fig.12 The connecting portion 23 of the negative terminal 2a shown in the figure is between the strip-shaped portions on the end side of the opening 23b. The strip-shaped portion 91c is provided with protrusions 95c and 95f on the lower surface side. The protrusions 95c and 95f are embedded in Fig.11 The conductive member 6 shown has die bonding portions 63c and 63f bent downward.

[0143] The space between the strips 91a and 91b is set to Fig.11 The space between the connecting portions 64a, 64b of the conductive member 6 shown and Fig.12 The opening 23a of the connecting portion 23 of the negative terminal 2a shown in the figure overlaps. The space between the strip portions 91b and 91c is set to Fig.11 The space between the connecting portions 64b, 64c of the conductive member 6 shown and Fig.12 The opening 23b of the connection portion 23 of the negative electrode terminal 2a shown overlaps.

[0144] Fig.19 2a, 6, 9 are side views of the laminated structures. Fig.19As shown, the upper surface side of the chip bonding parts 63c and 63f of the conductive member 6 is in contact with the protrusions 95c and 95f of the resin member 9. Similarly, the upper surface side of the chip bonding parts 63a, 63b, 63d, and 63e of the conductive member 6 is in contact with the protrusions 95a, 95b, 95d, and 95e of the resin member 9. Fig.19 As shown, the upper surfaces of the flat portion 90 and the strip portion 91c of the resin member 9 are in contact with the lower surface of the connection portion 23 of the negative terminal 2a. Similarly, the upper surfaces of the strip portions 91a and 91b of the resin member 9 are in contact with the lower surface of the connection portion 23 of the negative terminal 2a.

[0145] Fig. 20 Indicates that the Fig.19 FIG. 6 is a side view of an area A surrounded by dotted lines around a protruding portion 95c of a resin member 9. Engaging portions (convex portions) 92a, 92b are provided on the side of the protruding portion 95c of the resin member 9. Engaging portions (concave portions) 65a, 65b are provided on the curved portion of the chip bonding portion 63c of the conductive member 6. The conductive member 6 can be fixed to the resin member 9 by engaging (fitting) the convex portions 92a, 92b of the resin member 9 with the concave portions 65a, 65b of the conductive member 6.

[0146] Fig.21 express Fig.19 An example of a method for assembling the laminated structure (2a, 6, 9) shown in FIG. 2 is provided with a negative electrode terminal 2a, a resin member 9 and a conductive member 6, as shown in FIG. Fig.21 As shown, the upper surface of the resin member 9 is joined (fixed) to the lower surface of the negative terminal 2a by crimping or the like. Next, the upper surface side of the conductive member 6 is made to face the lower surface side of the resin member 9 fixed to the negative terminal 2a, and the upper surface of the conductive member 6 is fixed to the lower surface of the resin member 9 by crimping or the like. At this time, the convex portions 92a, 92b of the resin member 9 are engaged (fitted) with the concave portions 65a, 65b of the conductive member 6, so that the upper surface of the conductive member 6 can be firmly fixed to the lower surface of the resin member 9.

[0147] The other structures of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, duplicate descriptions are omitted.

[0148] According to the semiconductor device of the second embodiment, the negative electrode terminal 2a, the conductive member 6 and the resin member 9 constitute a laminated structure (2a, 6, 9), the main wiring circuit is three-dimensionally wired, and the control wiring circuit is made into a separate substrate using a printed substrate (11, 12a to 12e) for control wiring and a printed substrate (13, 14a to 14c). As a result, the wiring area can be reduced, so the increase in chip size and cost can be reduced, and low inductance characteristics can be achieved.

[0149] Fig. 22 This is a perspective view of another example of the conductive member 6 which is a constituent element of the laminated structure (2a, 6, 9). Fig. 22 The conductive member 6 shown in the figure further includes a connection portion 65 connected to the chip bonding portions 63d to 63f. Fig.11 The conductive members 6 shown are different. Fig.23 It is a perspective view of another example of the resin member 9 which is a constituent element of the laminated structure (2a, 6, 9). Fig.23 The resin member 9 shown in the figure further includes a connection portion 97 connected to the strip-shaped portions 91a to 91c. Fig.18 In the semiconductor device of the second embodiment, the resin member 9 shown in FIG. Fig. 22 The conductive member 6 shown, Fig.23 The resin member 9 shown and Fig.12 The negative electrode terminal 2a shown constitutes a laminated structure (2a, 6, 9).

[0150] (Other embodiments)

[0151] As described above, the present disclosure is described through the first embodiment and the second embodiment, but it should not be understood that the discussion and drawings constituting part of the disclosure are used to limit the present disclosure. Based on the present disclosure, those skilled in the art can clearly understand various alternative embodiments, examples, and application technologies.

[0152] For example, in the first and second embodiments, the case where the conductive substrate 1a and the conductive substrate 1b are provided is exemplified, but the conductive substrate 1a and the conductive substrate 1b may be formed by a circuit pattern on the upper surface side of an insulating circuit substrate such as a direct copper bonded (DCB) substrate. In the case where the insulating circuit substrate is formed, the insulating circuit substrate may include an insulating substrate such as a ceramic board, the conductive substrate 1a and the conductive substrate 1b provided on the upper surface side of the insulating substrate, and a heat sink provided on the lower surface side of the insulating substrate.

[0153] In addition, the structures disclosed in the first embodiment and the second embodiment can be appropriately combined within the scope that does not cause contradiction. In this way, the present disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of the present disclosure is determined only by the invention-specific matters of the claims properly understood based on the above description.

Claims

1. A semiconductor device, wherein: The semiconductor device comprises: Conductive substrate; a plurality of semiconductor chips having a first electrode and disposed on the conductive substrate; a printed circuit board having a first conductive layer provided on the conductive substrate, an insulating layer provided on the first conductive layer, and a second conductive layer provided on the insulating layer and electrically connected to the first electrodes of the plurality of semiconductor chips; as well as The first external terminal is provided on the second conductive layer and extends upward from the second conductive layer.

2. The semiconductor device according to claim 1, wherein The first external terminal comprises: a supporting portion provided on the second conductive layer; and An extension portion is supported by the support portion and extends upward from the second conductive layer.

3. The semiconductor device according to claim 2, wherein: The support portion has an opening, An end portion of the extending portion is pressed into the opening portion.

4. The semiconductor device according to claim 1 or 2, wherein: The insulating layer has a planar pattern, The flat pattern has: a first region extending in a direction between the plurality of semiconductor chips; and The second region extends in a direction perpendicular to the first region.

5. The semiconductor device according to claim 4, wherein: The second conductive layer is provided across the first region and the second region.

6. The semiconductor device according to claim 4, wherein: The second conductive layer is provided in plurality in an array on the second region, The first external terminals are provided on the plurality of second conductive layers, respectively, and the plurality of first external terminals form a column.

7. The semiconductor device according to claim 1 or 2, wherein: The plurality of semiconductor chips further include a second electrode, The semiconductor device further comprises: a sealing resin that seals the plurality of semiconductor chips; and a second external terminal electrically connected to the second electrodes of the plurality of semiconductor chips, Part of the first external terminal protrudes from the upper surface of the sealing resin, and part of the second external terminal protrudes from the side surface of the sealing resin.

Images