Preparation method of semiconductor element comprising cutting structure

Abstract

A method of fabricating a semiconductor device is provided, including forming an isolation layer in a substrate to define a pre-cut region, forming a lower pattern layer on the substrate, and forming an intermediate pattern layer on the lower pattern layer; patterning the lower pattern layer and the intermediate pattern layer using a main mask layer to form a first lower pattern layer and a first intermediate pattern layer which expose the pre-cut region; forming an upper pattern layer to cover the main lower pattern layer, the main middle pattern layer and the pre-cut area; patterning the upper pattern layer by using the secondary mask layer to obtain a main upper pattern layer which comprises at least two first-type spaces and a second-type space; and deepening the first-type space to form at least two first-type recesses in the pre-cutting area, and forming at least two cutting structures in the first-type recesses. The first tilt direction intersects the second tilt direction, and an active region is defined within the pre-cut region by an adjacent pair of cut structures.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2024101568612, filed on February 4, 2024, with the invention name of “Cutting structure, semiconductor element containing the cutting structure and preparation method thereof”. Application No. 2024101568612 claims priority and benefits of U.S. formal application No. 18 / 508,568 filed on November 14, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a cutting structure, a semiconductor element and a method for preparing the semiconductor element, and more particularly to a semiconductor element comprising the cutting structure and a method for preparing the semiconductor element. Background Art

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor components is gradually getting smaller to meet the increasing demand for computing power. However, during the process of decreasing size, different problems are added, and such problems continue to increase. Therefore, there is still a constant challenge to achieve improved quality, yield, performance and reliability, as well as reduced complexity.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] An embodiment of the present disclosure provides a cutting structure, including two main cutting insulation layers, which are located at both ends of a secondary cutting insulation layer and extend upward, wherein the two main cutting insulation layers and the secondary cutting insulation layer together constitute a U-shaped cross-sectional profile; a conductive portion, which is located on the cutting insulation layer and is laterally surrounded by the two main cutting insulation layers; and a covering portion, which is located on the conductive portion and is laterally surrounded by the two main cutting insulation layers.

[0006] Another embodiment of the present disclosure provides a semiconductor element, including an isolation layer, located in a substrate, to define a pre-cut area along a first inclined direction in a top view; at least two cutting structures, located in the pre-cut area, respectively including: two main cutting insulation layers, located at both ends of a secondary cutting insulation layer and extending upward; a conductive portion, located on the secondary cutting insulation layer and laterally surrounded by the two main cutting insulation layers; and a covering portion, located on the conductive portion and laterally surrounded by the two main cutting insulation layers. The two main cutting insulation layers and the secondary cutting insulation layer together form a U-shaped cross-sectional profile. An active area is defined in the pre-cut area by a pair of adjacent cutting structures.

[0007] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including forming an isolation layer in a substrate to define a pre-cut area, the pre-cut area extends along a first inclined direction in a top view, forming a lower pattern layer on the substrate, and forming an intermediate pattern layer on the lower pattern layer; using a main mask layer to pattern the lower pattern layer and the intermediate pattern layer, the main mask layer extends along a second inclined direction in a top view, forming a first lower pattern layer and a first intermediate pattern layer, which expose the pre-cut area; forming an upper pattern layer to cover the main lower pattern layer, the main intermediate pattern layer and the pre-cut area; using a secondary mask layer to pattern the upper pattern layer, the secondary mask layer extends along a first direction intersecting the first inclined direction and the second inclined direction to obtain a main upper pattern layer, which includes at least two first type spaces exposing the pre-cut area and a second type space exposing the main intermediate pattern layer; and deepening the first type space to form at least two first type recesses in the pre-cut area, and forming at least two cutting structures in the first type recesses. The first inclined direction intersects with the second inclined direction, and an active area is defined in the pre-cutting region by a pair of adjacent cutting structures.

[0008] Due to the design of the semiconductor device disclosed herein, the formation of the cutting structure and the active region can be integrated with the formation of the word line structure. This integration reduces the complexity and cost of manufacturing the semiconductor device. In addition, by carefully controlling the process parameters of the primary cutting insulation layers and the secondary cutting insulation layers, a well-controlled insulation capability of the cutting structure can be achieved.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0011] Figure 1 1 is a flow chart illustrating a method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0013] Figure 3 and Figure 4 is a cross-sectional schematic diagram, illustrating Figure 2 Sections along the midline A-A', B-B', and C-C'.

[0014] Figure 5 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0015] Figures 6 to 8 is a cross-sectional schematic diagram, illustrating Figure 5 Sections along the midline A-A', B-B', and C-C'.

[0016] Fig. 9 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0017] Fig.10 and Fig.11 is a cross-sectional schematic diagram, illustrating Fig. 9 Sections along the midline A-A', B-B', and C-C'.

[0018] Fig.12 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0019] Fig.13 is a cross-sectional schematic diagram, illustrating Fig.12Sections along the midline A-A', B-B', and C-C'.

[0020] Fig.14 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0021] Fig.15 is a cross-sectional schematic diagram, illustrating Fig.12 Sections along the midline A-A', B-B', and C-C'.

[0022] Fig.16 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0023] Fig.17 is a cross-sectional schematic diagram, illustrating Fig.16 Sections along the midline A-A', B-B', and C-C'.

[0024] Fig.18 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure.

[0025] Figure 19 to Figure 21 is a cross-sectional schematic diagram, illustrating Fig.18 Sections along the midline A-A', B-B', and C-C'.

[0026] Fig. 22 is a schematic close-up cross-sectional view, illustrating Fig.21 Cross-sections of regions A1, A2 and A3 in FIG.

[0027] Fig.23 and Fig.24 is a schematic close-up cross-sectional view illustrating various semiconductor components of some embodiments of the present disclosure.

[0028] The reference numerals are described as follows:

[0029] 10: Preparation method

[0030] 1A: Semiconductor components

[0031] 1B: Semiconductor components

[0032] 1C: Semiconductor components

[0033] 101: Base

[0034] 101TS: Top surface

[0035] 103: Isolation layer

[0036] 103BS: Lower surface

[0037] 211: Lower pattern layer

[0038] 213: Main lower pattern layer

[0039] 215: Secondary lower pattern layer

[0040] 221: Middle pattern layer

[0041] 223: Main middle pattern layer

[0042] 225: Secondary intermediate pattern layer

[0043] 231: Upper pattern layer

[0044] 233: Main upper pattern layer

[0045] 311: Main mask layer

[0046] 321: Secondary mask layer

[0047] 331: Space

[0048] 341: The first type of space

[0049] 343: Second Type Space

[0050] 345: The third type of space

[0051] 347: The fourth type of space

[0052] 351: Type I depression

[0053] 351BS: Lower surface

[0054] 353: Second type of depression

[0055] 353BS: Lower surface

[0056] 355: The third type of depression

[0057] 355BS: Lower surface

[0058] 400: Cutting structure

[0059] 410: Mainly cut the insulation layer

[0060] 410BS: Lower surface

[0061] 410TS: Top surface

[0062] 411: Side

[0063] 413: Bottom

[0064] 420: Secondary cutting insulation layer

[0065] 420BS: Lower surface

[0066] 420E: End

[0067] 421: Side

[0068] 423: Bottom

[0069] 430: Conductive part

[0070] 431: Bottom segment

[0071] 433: Top segment

[0072] 440: Covering

[0073] 440TS: Top surface

[0074] 500: First word line structure

[0075] 510: First word line dielectric layer

[0076] 510BS: Bottom surface

[0077] 520: first word line conductive layer

[0078] 521: Bottom

[0079] 523: Top

[0080] 530: First word line covering layer

[0081] 600: Second word line structure

[0082] 610: Second word line dielectric layer

[0083] 610BSl: bottom surface

[0084] 620: Second word line conductive layer

[0085] 621: Bottom

[0086] 623: Top

[0087] 630: Second word line covering layer

[0088] A1~A3:Area

[0089] AA: Active Area

[0090] D1: First tilt direction

[0091] D2: Second tilt direction

[0092] PCA: Pre-cut area

[0093] R1~R7: Area

[0094] S11: Steps

[0095] S13: Steps

[0096] S15: Steps

[0097] S17: Steps

[0098] S19: Steps

[0099] T1: Thickness

[0100] T2: Thickness

[0101] VL1: Vertical plane

[0102] VL2: Vertical plane

[0103] VL3: Vertical plane

[0104] VL4: Vertical plane

[0105] VL5: Vertical plane

[0106] VL6: Vertical plane

[0107] X: Second direction

[0108] Y: First direction DETAILED DESCRIPTION

[0109] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0110] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0111] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0112] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0113] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, is exactly the same, equal, or planar, or it may be the same, equal, or planar within an acceptable variance, and for example, the acceptable variance may occur due to the manufacturing process.

[0114] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor devices.

[0115] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0116] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 3 and Figure 4 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Figure 2 Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG.

[0117] Please refer to Figures 1 to 4 In step S11 , a substrate 101 may be provided, an isolation layer 103 may be formed in the substrate 101 to define a plurality of pre-cut areas PCA, a lower pattern layer 211 may be formed on the substrate 101 , and an intermediate pattern layer 221 may be formed on the lower pattern layer 211 .

[0118] Please refer to Figure 2 and Figure 3 The substrate 101 may include a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include an element semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon rhodium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, etc., a III-V compound semiconductor or a II-VI compound semiconductor; or a combination thereof.

[0119] Please refer to Figure 2 and Figure 3, an isolation layer 103 may be formed in the substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A lithography process and a subsequent etching process, such as an anisotropic dry etching process, may be performed to form a plurality of trenches penetrating the pad oxide layer, the pad nitride layer and extending to the substrate 101. An insulating material may be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, may be subsequently performed until the upper surface of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the isolation layer 103. For example, the insulating material may be silicon oxide or other suitable insulating materials.

[0120] The isolation layer 103 may define a plurality of pre-cut areas PCA of the substrate 101. In some embodiments, each of the plurality of pre-cut areas PCA may be a linear cross-sectional profile and may extend along a first oblique direction D1 in a top view. That is, in a top view, the plurality of pre-cut areas PCA may present a series of linear cross-sectional profiles, each of which extends along the first oblique direction D1 and is spaced apart from each other. The first oblique direction D1 may intersect the Y direction (also referred to as the first direction) and the X direction (also referred to as the second direction).

[0121] In subsequent processes, each region may exhibit different film composition or characteristics. Therefore, regions R1, R2, R3, R4, R5, R6, and R7 are described in detail to illustrate the different film compositions or characteristics observed in the following stages.

[0122] Please refer to Figure 2 and Figure 3 , a plurality of pre-cut areas PCA may be exposed in areas R1, R2, R4, and R5. The isolation layer 103 may be exposed in areas R3, R6, and R7.

[0123] Please refer to Figure 4 , the lower pattern layer 211 can be blanket-formed on the substrate 101 to cover the plurality of pre-cut areas PCA and the isolation layer 103. In some embodiments, the lower pattern layer 211 may include a material having etching selectivity to the substrate 101 and the isolation layer 103. In some embodiments, for example, the lower pattern layer 211 may include silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, silicon boron carbonitride, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof. In some embodiments, for example, the manufacturing technology of the lower pattern layer 211 may include chemical vapor deposition, physical vapor deposition, or other applicable deposition processes.

[0124] Please refer to Figure 4 , the middle pattern layer 221 can be blanket formed on the lower pattern layer 211. In some embodiments, the middle pattern layer 221 may include a material having an etching selectivity relative to the lower pattern layer 211. In some embodiments, the middle pattern layer 221 may include a material having an etching selectivity to the lower pattern layer 211, the substrate 101, and the isolation layer 103. In some embodiments, for example, the middle pattern layer 221 may include silicon nitride, boron nitride, silicon boron nitride, boron nitride, silicon boron carbonitride, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof. In some embodiments, for example, the manufacturing technology of the middle pattern layer 221 may include chemical vapor deposition, physical vapor deposition, or other applicable deposition processes. The middle pattern layer 221 may be exposed by regions R1, R2, R3, R4, R5, R6, and R7. It should be understood that for the sake of clarity, Figure 2 The lower pattern layer 211 and the middle pattern layer 221 are not shown.

[0125] Figure 5 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figures 6 to 8 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Figure 5 Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG.

[0126] Please refer to Figure 1 and Figures 5 to 8 In step S13, the lower pattern layer 211 and the middle pattern layer 221 can be patterned by multiple main mask layers 311 to form a main lower pattern layer 213 and a main middle pattern layer 223, and an upper pattern layer 231 can be formed to cover the main lower pattern layer 213 and the main middle pattern layer 223.

[0127] Please refer to Figure 5 and Figure 6 , a plurality of main mask layers 311 may be formed on the intermediate pattern layer 221. In some embodiments, each of the plurality of main mask layers 311 may be a linear cross-sectional profile and may extend along a second oblique direction D2 in a top view. That is, in a top view, the plurality of main mask layers 311 may present a series of linear cross-sectional profiles, each of which extends along the second oblique direction D2 and is spaced apart from each other. These depicted profiles of the main mask layers 311 may be collectively identified as a first pattern. The second oblique direction D2 may intersect with the first oblique direction D1. The first oblique direction D1 may intersect with the Y direction and the X direction.

[0128] In some embodiments, the plurality of main mask layers 311 may be a photoresist layer. The manufacturing technique of the first pattern of the plurality of main mask layers 311 may include performing a lithography process. The unpatterned main mask layer ( Figure 5 and Figure 6 (not shown) can be based on the mask ( Figure 5 and Figure 6 The main mask layer 311 is exposed to the processing light (not shown). A wavelength of the processing light can be associated with the critical dimension of the pattern. In some embodiments, the processing light can be a deep ultraviolet (DUV). In some embodiments, the processing light can be an extreme ultraviolet (EUV) light, and the lithography process can be an EUV lithography. After exposure to the processing light, the pattern on the mask is converted into an unpatterned main mask layer. The unpatterned main mask layer can then be etched according to the converted pattern to form a first pattern of multiple main mask layers 311. In some embodiments, the manufacturing technology of the multiple main mask layers 311 can include a multiple lithography-etching (LE) patterning process, a self-aligned double patterning (SADP) process, a self-aligned quadruple patterning (SAQP) process, a self-aligned octal patterning (SAOP) process, or other applicable lithography processes.

[0129] Please refer to Figure 5 , Figure 6 , regions R1, R4, R7 may not be shielded by the plurality of primary mask layers 311. In other words, the intermediate pattern layer 221 in regions R1, R4, R7 may be exposed through the space between adjacent pairs of the plurality of primary mask layers 311. Conversely, regions R2, R3, R5, R6 may be shielded by the plurality of primary mask layers 311. It should be understood that for the sake of clarity, Figure 5 The lower pattern layer 211 and the middle pattern layer 221 are not shown.

[0130] Please refer to Figure 7 , an etching process (also referred to as a first etching process) can be performed using multiple main mask layers 311 as masks to remove some portions of the lower pattern layer 211 and the intermediate pattern layer 221. After the first etching process, the lower pattern layer 211 can become the main lower pattern layer 213 and the intermediate pattern layer 221 can become the main intermediate pattern layer 223. Spaces 331 can be formed in the main lower pattern layer 213 and the main intermediate pattern layer 223 to expose multiple pre-cut areas PCA and the isolation layer 103. In some embodiments, the first etching process can be a multi-stage etching process. For example, the first etching process can be a two-stage anisotropic dry etching process. The etching chemicals in each stage can be different to provide different etching selectivities.

[0131] Please refer to Figure 5 and Figure 7In regions R1 and R4, the pre-cut region PCA may be exposed through the space 331. In region R7, the isolation layer 103 may be exposed through the space 331. In contrast, regions R2, R3, R5, and R6 are shielded by the plurality of primary mask layers 311; therefore, these regions do not expose the pre-cut region PCA or the isolation layer 103. It should be understood that for the sake of clarity, Figure 5 The main lower pattern layer 213 and the main middle pattern layer 223 are not shown.

[0132] After the first etching process, the plurality of main mask layers 311 may be removed.

[0133] Please refer to Figure 8 , an upper pattern layer 231 may be formed to cover the main lower pattern layer 213 and the main intermediate pattern layer 223. The space 331 may be completely filled by the upper pattern layer 231. In some embodiments, the upper pattern layer 231 may include a material having an etching selectivity to the substrate 101 and the isolation layer 103. In some embodiments, the upper pattern layer 231 may include a material having an etching selectivity to the substrate 101, the isolation layer 103, and the main intermediate pattern layer 223. In some embodiments, the upper pattern layer 231 may include a material having an etching selectivity to the substrate 101, the isolation layer 103, the main intermediate pattern layer 223, and the main lower pattern layer 213. In some embodiments, for example, the upper pattern layer 231 may include silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, silicon boron nitride, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. In some embodiments, for example, the fabrication technique of the upper pattern layer 231 may include chemical vapor deposition, physical vapor deposition or other applicable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps.

[0134] It should be understood that for the sake of clarity, Figure 5 The upper pattern layer 231 is not shown.

[0135] Fig. 9 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.10 and Fig.11 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Fig. 9 Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG. Fig.12 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.13 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Fig.12Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG.

[0136] Please refer to Figure 1 and Figures 9 to 13 In step S15, the upper pattern layer 231 can be patterned by means of multiple secondary mask layers 321 to form a main upper pattern layer 233, the main upper pattern layer 233 includes multiple first type spaces 341 exposing multiple pre-cut areas PCA and multiple second type spaces 343 exposing the main intermediate pattern layer 223, and the multiple first type spaces 341 can be deepened to form multiple first type recesses 351 in the multiple pre-cut areas PCA.

[0137] Please refer to Fig. 9 and Fig.10 , a plurality of secondary mask layers 321 may be formed on the upper pattern layer 231. In some embodiments, each of the plurality of secondary mask layers 321 may be a linear cross-sectional profile and may extend along direction Y in the top view. That is, in the top view, the plurality of secondary mask layers 321 may present a series of linear cross-sectional profiles, each of which extends along direction Y and is spaced apart from each other. These depicted profiles of the secondary mask layers 321 may be collectively identified as a second pattern. In some embodiments, the second pattern may also serve as a pattern of a word line structure.

[0138] In some embodiments, the plurality of secondary mask layers 321 may be a photoresist layer. The manufacturing technique of the second pattern of the plurality of secondary mask layers 321 may include performing a lithography process. Fig. 9 and Fig.10 (not shown) can be based on the mask ( Fig. 9 and Fig.10 The secondary mask layer 321 is exposed to the processing light (not shown). A wavelength of the processing light can be associated with the critical dimension of the pattern. In some embodiments, the processing light can be a DUV. In some embodiments, the processing light can be an EUV, and the lithography process can be an EUV lithography. After exposure to the processing light, the pattern on the mask is converted into an unpatterned secondary mask layer. The unpatterned secondary mask layer can then be etched according to the converted pattern to form a second pattern of multiple secondary mask layers 321. In some embodiments, the manufacturing technology of the multiple secondary mask layers 321 can include multiple LE patterning processes, SADP processes, SAQP processes, SAOP processes or other applicable lithography processes.

[0139] Please refer to Fig. 9 and Fig.10, regions R1, R2, and R3 may not be shielded by the plurality of secondary mask layers 321. In other words, the upper pattern layer 231 in regions R1, R2, and R3 may be exposed through the spaces between adjacent pairs of the plurality of secondary mask layers 321. Conversely, regions R4, R5, R6, and R7 may be shielded by the plurality of secondary mask layers 321. It should be understood that for the sake of clarity, Fig. 9 The upper pattern layer 231 is not shown.

[0140] Please refer to Fig.11 , an etching process (also referred to as a second etching process) may be performed using the plurality of secondary mask layers 321 as masks to remove portions of the upper pattern layer 231. After the second etching process, the upper pattern layer 231 may be transformed into a main upper pattern layer 233. A plurality of first type spaces 341 may be formed in the main upper pattern layer 233 to expose a plurality of pre-cut areas PCA. A plurality of second type spaces 343 may be formed in the main upper pattern layer 233 to expose the main intermediate pattern layer 223.

[0141] In region R1, the pre-cut area PCA may be exposed through the first type space 341. In regions R2 and R3, the main intermediate pattern layer 223 may be exposed through a plurality of second type spaces 343. In regions R4, R5, R6, and R7, the main upper pattern layer 233 may be shielded by a plurality of secondary mask layers 321. In some embodiments, the second etching process may be an anisotropic dry etching process.

[0142] After the second etching process, the plurality of secondary mask layers 321 may be removed.

[0143] Please refer to Fig.12 and Fig.13 , the plurality of first type spaces 341 may be deepened toward the substrate 101 to form a plurality of first type recesses 351 in the plurality of pre-cut areas PCA. In some embodiments, the sidewalls of the plurality of first type recesses 351 may be tapered. In some embodiments, the bottom surfaces 351BS of the plurality of first type recesses 351 may be at a vertical plane VL1, which is higher than the vertical plane VL2 of the bottom surface 103BS of the isolation layer 103.

[0144] In some embodiments, the formation of the plurality of first type recesses 351 may be achieved by an etching process (also referred to as a third etching process). In some embodiments, the main intermediate pattern layer 223 exposed through the plurality of second type spaces 343 may also be removed during the third etching process. After the third etching process, the plurality of second type spaces 343 may penetrate the main intermediate pattern layer 223 and transform the main intermediate pattern layer 223 into a secondary intermediate pattern layer 225. In some embodiments, the main lower pattern layer 213 may be used as an etching stop layer or an end point of the third etching process.

[0145] Please refer to Fig.12 and Fig.13 In the region R1, the first type recess 351 may be exposed through the first type space 341. In the regions R2 and R3, the main lower pattern layer 213 may be exposed through the second type space 343. In the regions R4, R5, R6, and R7, the lower layer (i.e., the secondary intermediate pattern layer 225, the main lower pattern layer 213, the pre-cut area PCA, or the isolation layer 103) may be covered by the main upper pattern layer 233.

[0146] Fig.14 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.15 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Fig.14 Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG. Fig.16 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Fig.17 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Fig.16 Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG.

[0147] Please refer to Figure 1 and Figures 14 to 17 In step S17 , a plurality of main cutting insulation layers 410 may be formed along the plurality of first type recesses 351 to define a plurality of active areas AA, and a plurality of second type spaces 343 may be deepened to expose a plurality of pre-cut areas PCA and the isolation layer 103 .

[0148] Please refer to Fig.14 and Fig.15, an oxidation process may be performed to oxidize each sidewall and each lower surface 351BS of the plurality of first type recesses 351. In some embodiments, the oxidation process may be a wet oxidation process. After the oxidation process, the plurality of oxidized portions of the substrate 101 may be referred to as a plurality of main cutting insulating layers 410. Each of the plurality of main cutting insulating layers 410 may include a bottom 413 and two side portions 411. The side portions 411 may be formed along the sidewalls of the first type recesses 351. The bottom 413 may be formed along the lower surface 351BS of the first type recesses 351. In some embodiments, the plurality of main cutting insulating layers 410 may include silicon oxide.

[0149] For a plurality of main cutting insulation layers 410 formed in the same pre-cut area PCA, each pair of adjacent main cutting insulation layers 410 defines an active area AA.

[0150] Please refer to Fig.14 and Fig.15 , in region R1, a portion of the bottom 413 and the side 411 may be exposed via the first type space 341. In region R2, the main lower pattern layer 213 may be exposed via the second type space 343, and the pre-cut area PCA may be covered by the main lower pattern layer 213. In region R3, the main lower pattern layer 213 may be exposed via the second type space 343, and the isolation layer 103 may be covered by the main lower pattern layer 213. In region R4, the pre-cut area PCA may be covered by the main upper pattern layer 233. In region R5, the main upper pattern layer 233 may be formed above the secondary intermediate pattern layer 225, the main lower pattern layer 213, and the pre-cut area PCA. In region R6, the main upper pattern layer 233 may be formed above the secondary intermediate pattern layer 225, the main lower pattern layer 213, and the isolation layer 103. In region R7, the isolation layer 103 may be covered by the main upper pattern layer 233.

[0151] Please refer to Fig.16 and Fig.17 , the plurality of second type spaces 343 may be deepened by removing some portions of the main lower pattern layer 213. The deepening of the plurality of second type spaces 343 may be achieved by an etching process (also referred to as a fourth etching process) such as an anisotropic dry etching process. After the fourth etching process, the main lower pattern layer 213 may be transformed into the secondary lower pattern layer 215. The plurality of second type spaces 343 may become a plurality of third type spaces 345 exposing a plurality of pre-cut areas PCA and a plurality of fourth type spaces 347 exposing the isolation layer 103.

[0152] Please refer to Fig.16 and Fig.17In region R1, the main cutting insulating layer 410 may be exposed through the first type space 341. In region R2, the pre-cutting area PCA may be exposed through the third type space 345. In region R3, the isolation layer 103 may be exposed through the fourth type space 347. The film composition of regions R5, R6, and R7 is similar to Fig.14 and Fig.15 The membrane components shown are the same and will not be described again here.

[0153] Fig.18 FIG. 4 is a top view schematically illustrating a middle semiconductor element according to an embodiment of the present disclosure. Figure 19 to Figure 21 is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure along Fig.18 Partial process of manufacturing semiconductor element 1A along the sections AA', BB' and CC' in FIG. Fig. 22 is a schematic close-up cross-sectional view, illustrating Fig.21 Cross-sections of regions A1, A2 and A3 in FIG.

[0154] Please refer to Figure 1 and Figures 18 to 22 In step S19, a plurality of second type recesses 353 may be formed in a plurality of pre-cut areas PCA, a plurality of third type recesses 355 may be formed in the isolation layer 103, a plurality of first word line (WL) structures 500 may be formed in the plurality of second type recesses 353, a plurality of second word line (WL) structures 600 may be formed in the plurality of third type recesses 355, and a plurality of cutting structures 400 may be formed in the plurality of first type recesses 351.

[0155] Please refer to Fig.18 and Fig.19 , an etching process (also referred to as the fifth etching process) may be performed to deepen the plurality of third type spaces 345 and the plurality of fourth type spaces 347. After the fifth etching process, the plurality of third type spaces 345 may be deepened to form a plurality of second type recesses 353 in the plurality of active regions AA. The plurality of fourth type spaces 347 may be deepened to form a plurality of third type recesses 355 in the isolation layer 103. In some embodiments, the fifth etching process may be an anisotropic dry etching process. In some embodiments, each lower surface 353BS of the plurality of second type recesses 353 may be in a vertical plane VL3, which is higher than the vertical plane VL4 of each lower surface 355BS of the plurality of third type recesses 355.

[0156] In some embodiments, the bottom 413 of the main cutting insulating layer 410 may be consumed during the fourth etching process. That is, after the fifth etching process, the main cutting insulating layer 410 may include only the side 411. After the fourth etching process, each lower surface 351BS of the plurality of first type recesses 351 may be exposed. In some embodiments, each lower surface 351BS of the plurality of first type recesses 351 may be at a vertical plane VL1, which is lower than the vertical plane VL3 of each lower surface 353BS of the plurality of second type recesses 353 and the vertical plane VL4 of the lower surface 355BS of the plurality of third type recesses 355.

[0157] Please refer to Fig.18 and Fig.19 In region R1, the lower surface 351BS of the first type recess 351 and the main cutting insulating layer 410 may be exposed through the first type space 341. In region R2, the lower surface 353BS of the second type recess 353 may be exposed through the third type space 345. In region R3, the lower surface 355BS of the third type recess 355 may be exposed through the fourth type space 347. The film composition of regions R4, R5, R6, and R7 is similar to that of regions R5, R6, and R7. Fig.16 and Fig.17 The membrane components shown are the same and will not be described again here.

[0158] Please refer to Fig. 20 , a plurality of secondary cut insulating layers 420 may be conformally formed in the plurality of first type recesses 351, a plurality of first word line dielectric layers 510 may be conformally formed in the plurality of second type recesses 353, and a plurality of second word line dielectric layers 610 may be conformally formed in the plurality of third type recesses 355. In some embodiments, the secondary cut insulating layer 420, the first word line dielectric layer 510, and the second word line dielectric layer 610 may have a U-shaped cross-sectional profile.

[0159] In some embodiments, the secondary cut insulating layer 420, the first word line dielectric layer 510, and the second word line dielectric layer 610 may be formed simultaneously. In some embodiments, for example, the secondary cut insulating layer 420, the first word line dielectric layer 510, and the second word line dielectric layer 610 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, for example, the manufacturing technology of the secondary cut insulating layer 420, the first word line dielectric layer 510, and the second word line dielectric layer 610 may include atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0160] In some embodiments, the high-k dielectric material may include a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0161] In some embodiments, the secondary cutting insulation layer 420, the first word line dielectric layer 510, and the second word line dielectric layer 610 can be formed before the primary upper pattern layer 233 and the secondary middle pattern layer 225, and the secondary lower pattern layer 215 is removed. In some embodiments, the secondary cutting insulation layer 420, the first word line dielectric layer 510, and the second word line dielectric layer 610 can be formed after the primary upper pattern layer 233 and the secondary middle pattern layer 225, and the secondary lower pattern layer 215 is removed. Fig. 20 (not shown).

[0162] Please refer to Fig. 20 In region R1, the secondary cutting insulating layer 420 may be exposed through the first type space 341. In region R2, the first word line dielectric layer 510 may be exposed through the third type space 345. In region R3, the second word line dielectric layer 610 may be exposed through the fourth type space 347. The film composition of regions R4, R5, R6, and R7 is similar to that of regions R5, R6, and R7. Fig.16 and Fig.17 The membrane components shown are the same and will not be described again here.

[0163] For the sake of brevity, clarity and convenience, only a first word line structure 500, a second word line structure 600 and a cutting structure 400 are described. The cutting structure 400 may include a primary cutting insulating layer 410, a secondary cutting insulating layer 420, a conductive portion 430 and a covering portion 440. The first word line structure 500 may include a first word line dielectric layer 510, a first word line conductive layer 520 and a first word line covering layer 530. The second word line structure 600 may include a second word line dielectric layer 610, a second word line conductive layer 620 and a second word line covering layer 630.

[0164] Please refer to Fig.21 and Fig. 22, in some embodiments, the primary upper pattern layer 233, the secondary middle pattern layer 225, and the secondary lower pattern layer 215 may be removed. The conductive portion 430 may be formed in the first type recess 351 and on the secondary cutting insulating layer 420. In some embodiments, the conductive portion 430 may include a bottom segment 431 and a top segment 433. The bottom segment 431 may be disposed on the bottom 423 of the secondary cutting insulating layer 420 and surrounded by the side 421 of the secondary cutting insulating layer 420. In some embodiments, for example, the bottom segment 431 may include tungsten, cobalt, zirconium, tantalum, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), transition metal aluminide, or a combination thereof. The top segment 433 may be disposed on the bottom segment 431 and surrounded by the side 421 of the secondary cutting insulating layer 420. In some embodiments, the top segment 433 may include polysilicon, polygermanium, polysilicon germanium, doped polysilicon, doped polygermanium, doped polysilicon germanium, or combinations thereof, for example.

[0165] In some embodiments, the first word line conductive layer 520 may include a bottom portion 521 and a top portion 523. The bottom portion 521 may be formed on the first word line dielectric layer 510 and in the second type recess 353. The top portion 523 may be formed on the bottom portion 521. Sidewalls of the bottom portion 521 and the top portion 523 may be surrounded by the first word line dielectric layer 510.

[0166] In some embodiments, the second word line conductive layer 620 may include a bottom portion 621 and a top portion 623. The bottom portion 621 may be formed on the second word line dielectric layer 610 and in the third type recess 355. The top portion 623 may be formed on the bottom portion 621. Sidewalls of the bottom portion 621 and the top portion 623 may be surrounded by the second word line dielectric layer 610.

[0167] In some embodiments, the conductive portion 430 , the first word line conductive layer 520 , and the first word line capping layer 530 may be formed simultaneously and may include the same material.

[0168] Please refer to Fig.21 and Fig. 22 In some embodiments, the cover portion 440 may be formed on the conductive portion 430 and within the first type recess 351. In some embodiments, the upper surface 440TS of the cover portion 440, the upper surface 410TS of the main cutting insulation layer 410, and the upper surface 101TS of the substrate 101 (i.e., the upper surface of the pre-cut area PCA or the active area AA) may be substantially coplanar. In some embodiments, for example, the cover portion 440 may include silicon nitride or other applicable dielectric materials.

[0169] In some embodiments, a first word line capping layer 530 may be formed on the first word line conductive layer 520 and within the second type recess 353. A sidewall of the first word line capping layer 530 may be surrounded by the first word line dielectric layer 510. In some embodiments, a second word line capping layer 630 may be formed on the second word line conductive layer 620 and within the third type recess 355. A sidewall of the second word line capping layer 630 may be surrounded by the second word line dielectric layer 610. In some embodiments, the capping portion 440, the first word line capping layer 530, and the second word line capping layer 630 may be formed simultaneously and may include the same material.

[0170] In some embodiments, after the covering part 440 is formed, the primary upper pattern layer 233 , the secondary middle pattern layer 225 , and the secondary lower pattern layer 215 may be removed.

[0171] Fig.23 and Fig.24 1 is a schematic close-up cross-sectional view illustrating various semiconductor elements 1B and 1C of some embodiments of the present disclosure.

[0172] Please refer to Fig.23 , the semiconductor element 1B may have Fig. 22 A structure similar to the structure shown. Fig.23 Zhongyu Fig. 22 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0173] In the semiconductor element 1B, since the deposition rates at the bottom and the sidewall of the first type recess 351 are different during the formation of the secondary cutting insulating layer 420, the secondary cutting insulating layer 420 can be disposed only on the bottom of the first type recess 351. Two main cutting insulating layers 410 can be disposed on both ends 420E of the secondary cutting insulating layer 420 and extend upward. The two main cutting insulating layers 410 and the secondary cutting insulating layer 420 together form a U-shaped cross-sectional profile. The lower surfaces 410BS of the two main cutting insulating layers and the lower surface 420BS of the secondary cutting insulating layer 420 can be substantially coplanar.

[0174] In some embodiments, the thickness T1 of the primary cutting insulation layer 410 and the thickness T2 of the secondary cutting insulation layer 420 may be substantially the same. In some embodiments, the thickness T1 of the primary cutting insulation layer 410 and the thickness T2 of the secondary cutting insulation layer 420 may be different. The thicknesses T1 and T2 of the primary cutting insulation layer 410 and the secondary cutting insulation layer 420 may determine the insulation capability of the cutting structure 400.

[0175] In some embodiments, the bottom surface 510BS of the first word line dielectric layer 510 may be at a vertical plane VL3, which is higher than a vertical plane VL4 of the bottom surface 610BS of the second word line dielectric layer 610. In some embodiments, the bottom surface 420BS of the secondary cutting insulation layer 420 may be at a vertical plane VL1, which is lower than the vertical plane VL3 of the bottom surface 510BS of the first word line dielectric layer 510 and the vertical plane VL4 of the bottom surface 610BS of the second word line dielectric layer 610.

[0176] The conductive portion 430 may be disposed on the secondary cutting insulating layer 420 and laterally surrounded by the two primary cutting insulating layers 410. Specifically, the bottom segment 431 may be disposed on the secondary cutting insulating layer 420 and laterally surrounded by the two primary cutting insulating layers 410. The top segment 433 may be disposed on the bottom segment 431 and laterally surrounded by the two primary cutting insulating layers 410. The covering portion 440 may be disposed on the conductive portion 430 and laterally surrounded by the two primary cutting insulating layers 410.

[0177] Please refer to Fig.24 , the semiconductor element 1C may have Fig.23 A structure similar to the structure shown. Fig.24 Zhongyu Fig.23 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0178] In the semiconductor element 1C, as Fig.18 and Fig.19 As shown, some of the substrate 101 adjacent to the bottom of the first type recess 351 may also be removed during the etching process. Fig.23 In comparison, the secondary cutting insulation layer 420 may be formed at a lower position. For example, the lower surface 420BS of the secondary cutting insulation layer 420 may be at a vertical plane VL5 that is lower than the vertical plane VL6 of the lower surface 410BS of the primary cutting insulation layer 410 .

[0179] An embodiment of the present disclosure provides a cutting structure, including two main cutting insulation layers, which are located at both ends of a secondary cutting insulation layer and extend upward, wherein the two main cutting insulation layers and the secondary cutting insulation layer together constitute a U-shaped cross-sectional profile; a conductive portion, which is located on the cutting insulation layer and is laterally surrounded by the two main cutting insulation layers; and a covering portion, which is located on the conductive portion and is laterally surrounded by the two main cutting insulation layers.

[0180] Another embodiment of the present disclosure provides a semiconductor element, including an isolation layer, located in a substrate, to define a pre-cut area along a first inclined direction in a top view; at least two cutting structures, located in the pre-cut area, respectively including: two main cutting insulation layers, located at both ends of a secondary cutting insulation layer and extending upward; a conductive portion, located on the secondary cutting insulation layer and laterally surrounded by the two main cutting insulation layers; and a covering portion, located on the conductive portion and laterally surrounded by the two main cutting insulation layers. The two main cutting insulation layers and the secondary cutting insulation layer together form a U-shaped cross-sectional profile. An active area is defined in the pre-cut area by a pair of adjacent cutting structures.

[0181] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including forming an isolation layer in a substrate to define a pre-cut area, the pre-cut area extends along a first inclined direction in a top view, forming a lower pattern layer on the substrate, and forming an intermediate pattern layer on the lower pattern layer; using a main mask layer to pattern the lower pattern layer and the intermediate pattern layer, the main mask layer extends along a second inclined direction in a top view, forming a first lower pattern layer and a first intermediate pattern layer, which expose the pre-cut area; forming an upper pattern layer to cover the main lower pattern layer, the main intermediate pattern layer and the pre-cut area; using a secondary mask layer to pattern the upper pattern layer, the secondary mask layer extends along a first direction intersecting the first inclined direction and the second inclined direction to obtain a main upper pattern layer, which includes at least two first type spaces exposing the pre-cut area and a second type space exposing the main intermediate pattern layer; and deepening the first type space to form at least two first type recesses in the pre-cut area, and forming at least two cutting structures in the first type recesses. The first inclined direction intersects with the second inclined direction, and an active area is defined in the pre-cutting region by a pair of adjacent cutting structures.

[0182] Due to the design of the semiconductor device disclosed herein, the formation of the cutting structure 400 and the active area AA can be integrated with the formation of the word line structures 500, 600. This integration reduces the complexity and cost of manufacturing the semiconductor devices 1A, 1B, 1C. In addition, by carefully controlling the process parameters of the primary cutting insulation layers 410 and the secondary cutting insulation layers 420, a well-controlled insulation capability of the cutting structure 400 can be achieved.

[0183] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0184] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, comprising: forming an isolation layer in a substrate to define a pre-cut region, the pre-cut region extending along a first oblique direction in a top view, forming a lower pattern layer on the substrate, and forming an intermediate pattern layer on the lower pattern layer; Patterning the lower pattern layer and the middle pattern layer using a main mask layer, the main mask layer extending along a second oblique direction in a top view to form a first lower pattern layer and a first middle pattern layer, which expose the pre-cut area; forming an upper pattern layer to cover the lower pattern layer, the middle pattern layer and the pre-cut area; Patterning the upper pattern layer using a secondary mask layer, the secondary mask layer extending along a first direction intersecting the first oblique direction and the second oblique direction, to obtain a primary upper pattern layer including at least two first type spaces exposing the pre-cut area and a second type space exposing the primary intermediate pattern layer; and deepening the first type space to form at least two first type recesses in the pre-cutting area, and forming at least two cutting structures in the first type recesses, The first inclined direction intersects with the second inclined direction, and an active area is defined in the pre-cutting region by a pair of adjacent cutting structures.

2. The method of claim 1, wherein forming the at least two cut structures comprises: Conformally forming at least two main cutting insulation layers along the at least two first type recesses; When removing the bottom portions of the at least two main cutting insulating layers along the first type recess to expose the pre-cut region and retaining the side portions of the at least two main cutting insulating layers, deepening the second type space to form a second type recess in the active region and a third type recess in the isolation layer; Forming at least two pre-cut insulating layers in the first type recess and covering the pre-cut area; forming at least two conductive portions on the at least two secondary to-cut insulating layers and in the first type recess and laterally surrounded by the side portion; as well as forming at least two covering portions on the conductive portion and in the first type recess and laterally surrounded by the side portion, The at least two main cutting insulating layers, the at least two secondary cutting insulating layers, the at least two conductive parts and the at least two covering parts cooperate to form the at least two cutting structures.

3. The method of claim 2, further comprising forming a first word line structure in the second type recess. 4 . The method of claim 3 , further comprising forming a second word line structure in the third type recess.

5. The method of claim 4 , wherein forming the first word line structure in the second type recess comprises: When forming the at least two sub-cut insulating layers, conformally forming a first word line dielectric layer in the second type recess; When forming the at least two conductive portions, forming a first word line conductive layer on the first word line dielectric layer and in the second type recess; and When the at least two covering portions are formed, a first word line covering layer is formed on the first word line conductive layer and in the second type recess.

6. The method of claim 4 , wherein forming the second word line structure in the third type recess comprises: When forming the at least two sub-cut insulating layers, conformally forming a second word line dielectric layer in the third type recess; When forming the at least two conductive portions, forming a second word line conductive layer on the second word line dielectric layer and in the third type recess; and When the at least two covering portions are formed, a second word line covering layer is formed on the second word line conductive layer and in the third type recess. 7 . The manufacturing method according to claim 2 , wherein the at least two main cutting insulation layers and the at least two sub-cutting insulation layers comprise the same material. 8 . The manufacturing method according to claim 2 , wherein the at least two main cutting insulation layers and the at least two secondary cutting insulation layers comprise different materials. 9 . The method of claim 5 , wherein the first word line conductive layer comprises a bottom portion on the first word line dielectric layer and a top portion on the bottom portion. 10 . The method of claim 6 , wherein the second word line conductive layer comprises a bottom portion on the second word line dielectric layer and a top portion on the bottom portion. The manufacturing method as claimed in claim 2 , wherein the second type of recess is narrower than the third type of recess. 12 . The manufacturing method as claimed in claim 2 , wherein the third type of recess is narrower than the first type of recess.

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