A fan-out type dual-polarized packaged antenna array integrating a heterogeneous chipset

Abstract

The present invention relates to the field of packaged antenna arrays, and specifically discloses a fan-out type dual-polarized packaged antenna array integrating a heterogeneous chipset. The packaged antenna array includes three packages arranged from top to bottom, internally integrating a dual-polarized antenna array, a feeding network, and a heterogeneous chipset embedded inside the packages. The present invention realizes the high-density fan-out integration of the dual-polarized antenna array and the heterogeneous radio frequency front-end chipset, has lower transmission loss and higher integration, can not only effectively reduce the system volume and cost, but also has the characteristics of simple assembly process, high consistency, and easy realization of arbitrary expansion of the array scale, and can be applied as a standard module to large-scale phased array systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of packaged antenna arrays, and specifically discloses a fan-out dual-polarized packaged antenna array integrating a heterogeneous chipset. Background Art

[0002] At present, there are mainly two ways to implement a packaged antenna array: one is to directly fabricate antenna elements on one side of a substrate, and attach the packaged chips to the other side of the substrate. In this implementation, the antenna feed path is relatively long, resulting in large signal losses. Moreover, since the processing accuracy of the substrate is less than that of the wafer manufacturing process, the consistency of the array elements is poor, and it is difficult to obtain excellent performance; the other way is through the wafer fan-out method, where signals are led out from the chip through the redistribution technology and directly connected to the antenna element structure around the chip, and then encapsulated and protected with encapsulation materials. Although this method can achieve lower path losses, the area utilization rate is low, it is difficult to effectively expand the antenna structure and the number of channels, and the antenna performance / area efficiency is reduced.

[0003] In view of this, the present invention provides an integrated solution for chip-packaging-antenna array to improve the integration degree of the packaged antenna array and the overall performance. Summary of the Invention

[0004] To solve the above problems existing in the prior art, the present invention provides a fan-out dual-polarized packaged antenna array integrating a heterogeneous chipset.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A fan-out dual-polarized packaged antenna array integrating a heterogeneous chipset, comprising a first package, a second package, a third package and a solder ball array arranged from top to bottom;

[0007] One side of the first package and the second package are abutted and connected by an adhesive material;

[0008] The other side of the second package and one side of the third package are abutted and connected by an adhesive material;

[0009] The other side of the third package is provided with a solder ball array for transmitting radio frequency signals, control signals and power supply.

[0010] Further, the first package is composed of a first wiring layer and a first dielectric layer; the first wiring layer is located on the upper surface of the first dielectric layer;

[0011] The first wiring layer is provided with N antenna radiation patches arranged at array intervals, and N is 2×2 or 4×4.

[0012] Further, the second encapsulation body is composed of a second wiring layer and a second dielectric layer; the second wiring layer is located between the second dielectric layer and the first encapsulation body;

[0013] The second wiring layer is provided with a plurality of parasitic radiation patches arranged at array intervals; the parasitic radiation patches correspond to the antenna radiation patches one by one, and the parasitic radiation patches are respectively located directly below the corresponding antenna radiation patches.

[0014] Further, the third encapsulation body is composed of a third wiring layer, a third dielectric layer and a fourth wiring layer; the third dielectric layer is located between the third wiring layer and the fourth wiring layer, wherein the third wiring layer is in contact with the second encapsulation body, and the fourth wiring layer is in contact with the solder ball array;

[0015] The third wiring layer is provided with 2N slotted structures serving as antenna coupling slots;

[0016] The fourth wiring layer is provided with 2N antenna feeders;

[0017] A heterogeneous chip group composed of a silicon-based CMOS chip, 2N compound chips and several TMV chips is encapsulated inside the third dielectric layer.

[0018] Further, N antenna radiation patches of the first encapsulation body, N parasitic radiation patches of the second encapsulation body, and 2N slotted structures and 2N antenna feeders of the third encapsulation body form an N-element dual-polarized antenna unit array structure.

[0019] Further, one end of the 2N compound chips is connected to a plurality of corresponding ports of the silicon-based CMOS chip through the first connecting lines on the fourth wiring layer, and the lengths of each first connecting line are the same;

[0020] The other end of the 2N compound chips is connected to the corresponding antenna feeders through the second connecting lines on the fourth wiring layer, and the lengths of each second connecting line are the same;

[0021] The TMV chips penetrate through the third dielectric layer and realize the electrical connection between the third wiring layer and the fourth wiring layer through metallized vias.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] (1) It realizes the miniaturization, integration and three-dimensional fan-out integration of the array antenna unit and the heterogeneous chip group, and improves the integration degree of the antenna array; (2) Adopting the wafer-level packaging process, the antenna feeder path is shorter and the loss is lower, thus improving the overall performance; (3) It has scalability, and the expansion of any array scale can be realized by splicing. Brief Description of the Drawings

[0024] Figure 1 It is a schematic cross-sectional structure diagram of a fan-out type dual-polarization packaged antenna array integrating a heterogeneous chipset in an embodiment of the present invention;

[0025] Figure 2 It is a schematic layered structure diagram of a fan-out type dual-polarization packaged antenna array integrating a heterogeneous chipset in an embodiment of the present invention. Specific embodiments

[0026] In order to further illustrate the advantages of the present invention and the specific technical means adopted, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, those skilled in the art should fall within the scope of protection of the claims of this application for various equivalent modifications of the present invention.

[0027] The following is a further detailed description of the present invention with reference to the accompanying drawings.

[0028] As Figure 1 shown, an embodiment of the present invention provides a fan-out type dual-polarization packaged antenna array integrating a heterogeneous chipset, including a first package body 1, a second package body 2, a third package body 3, and a solder ball array 4 arranged from top to bottom;

[0029] One side of the first package body 1 and the second package body 2 are abutted and connected by an adhesive material;

[0030] The other side of the second package body 2 and one side of the third package body 3 are abutted and connected by an adhesive material;

[0031] The other side of the third package body 3 is provided with a solder ball array 4 for transmitting radio frequency signals, control signals, and power supply.

[0032] Specifically, the first package body 1 is composed of a first wiring layer 11 and a first dielectric layer 12;

[0033] The first wiring layer 11 is provided with N (N = 2×2 or 4×4) antenna radiation patches 101 arranged at intervals in an array;

[0034] Specifically, the second package body 2 is composed of a second wiring layer 21 and a second dielectric layer 22;

[0035] The second wiring layer 21 is provided with N parasitic radiation patches 201 arranged at intervals in an array, and the N parasitic radiation patches 201 are located directly below the antenna radiation patches 101;

[0036] Specifically, the third package body 3 is composed of a third wiring layer 31, a third dielectric layer 32, and a fourth wiring layer 33;

[0037] The third wiring layer 31 is provided with 2N slotted structures 301 serving as antenna coupling slots;

[0038] The fourth wiring layer 33 is provided with 2N antenna feeders 401;

[0039] The third dielectric layer 32 encapsulates a heterogeneous chip group composed of a silicon-based CMOS chip 501, 2N compound chips 502, and several molded vias TMV chips 503 inside.

[0040] Specifically, the N antenna radiation patches 101, the N parasitic radiation patches 201, the 2N slotted structures 301, and the 2N antenna feeders 401 form an N-element dual-polarized antenna unit array structure. The antenna radiation patches 101 and the parasitic radiation patches 201 are in one-to-one correspondence, and the parasitic radiation patches 201 are located below the corresponding antenna radiation patches 101; the 2N slotted structures 301 are divided into N groups, with two slotted structures 301 in each group. In this embodiment, the slotted structure is in the shape of a "work" character. The two slotted structures 301 in the same group are perpendicular to each other and are located below the corresponding parasitic radiation patches 201; the antenna feeders 401 are divided into N groups, with two antenna feeders in each group. The two antenna feeders 401 in the same group are both located below the slotted structures 301 in the corresponding group.

[0041] Specifically, one end of the 2N compound chips 502 is connected to multiple corresponding ports of the silicon-based CMOS chip 501 through the fourth wiring layer 33, and the length of each connection line is the same;

[0042] The other end of the 2N compound chips 502 is connected to the corresponding antenna feeders 401 through the fourth wiring layer 33, and the length of each connection line is the same;

[0043] The TMV chips 503 penetrate the third dielectric layer 32 to realize the electrical connection between the third wiring layer 31 and the fourth wiring layer 33 through metallized vias.

[0044] Figure 2 It is a schematic diagram of a hierarchical structure of a fan-out type dual-polarized packaged antenna array integrating a heterogeneous chip group according to a specific embodiment of the present invention. More specifically, when N takes 2×2.

[0045] The working principle of signal transmission implemented in this specific embodiment is as follows: The transmitted signal is processed by the silicon-based CMOS chip 501 and then transmitted to the compound chip 502. After amplification, it is output to the antenna feeder 401. The antenna feeder 401 transfers the energy to the antenna radiation patch 101 and the parasitic radiation patch 201 through the slotted structure 301. The antenna radiation patch 101 and the parasitic radiation patch 201 convert the received energy into radio waves propagating in an unbounded medium (usually free space), and the radio waves radiate into the surrounding space, thereby realizing the signal transmission.

[0046] The working principle of signal reception implemented in this specific embodiment is as follows: The antenna radiation patch 101 and the parasitic radiation patch 201 receive radio waves in space and convert them into energy. The energy is sequentially transmitted to the compound chip 502 through the slotted structure 301 and the antenna feeder 401. Multiple compound chips 502 transmit the received signals to the silicon-based CMOS chip 501, and the silicon-based CMOS chip 501 processes the multiplexed received signals, thereby realizing the signal reception.

Claims

1. A fan-out type dual-polarized packaged antenna array integrating a heterogeneous chipset, characterized in that It includes arranging a first package body (1), a second package body (2), a third package body (3) and a solder ball array (4) from top to bottom; One side of the first package body (1) and the second package body (2) are in contact and connected by an adhesive material; The other side of the second package body (2) and one side of the third package body (3) are in contact and connected by an adhesive material; The other side of the third package body (3) is provided with a solder ball array (4) for transmitting radio frequency signals, control signals and power supply; The first package body (1) is composed of a first wiring layer (11) and a first dielectric layer (12); the first wiring layer (11) is located on the upper surface of the first dielectric layer (12); The first wiring layer (11) is provided with N antenna radiation patches (101) arranged at array intervals, and N is 2×2 or 4×4; The second package body (2) is composed of a second wiring layer (21) and a second dielectric layer (22); the second wiring layer (21) is located between the second dielectric layer (22) and the first package body (1); The second wiring layer (21) is provided with a plurality of parasitic radiation patches (201) arranged at array intervals; the parasitic radiation patches (201) correspond to the antenna radiation patches (101) one by one, and the parasitic radiation patches (201) are respectively located directly below the corresponding antenna radiation patches (101); The third package body (3) is composed of a third wiring layer (31), a third dielectric layer (32) and a fourth wiring layer (33); the third dielectric layer (32) is located between the third wiring layer (31) and the fourth wiring layer (33), wherein the third wiring layer (31) is in contact with the second package body (2), and the fourth wiring layer (33) is in contact with the solder ball array (4); The third wiring layer (31) is provided with 2N slotted structures (301) serving as antenna coupling slots; The fourth wiring layer (33) is provided with 2N antenna feeders (401); Inside the third dielectric layer (32), a heterogeneous chip group composed of a silicon-based CMOS chip (501), 2N compound chips (502) and several TMV chips (503) is encapsulated.

2. The fan-out type dual-polarized packaged antenna array integrating a heterogeneous chip group according to claim 1, characterized in that The N antenna radiation patches (101) of the first package body (1), the N parasitic radiation patches (201) of the second package body (2), and the 2N slotted structures (301) and 2N antenna feeders (401) of the third package body (3) constitute an N-element dual-polarized antenna unit array structure.

3. The fan-out type dual-polarized packaged antenna array integrating a heterogeneous chip group according to claim 1, characterized in that One end of the 2N compound chips (502) is connected to a plurality of corresponding ports of the silicon-based CMOS chip (501) through the first connecting lines on the fourth wiring layer (33), and the lengths of each first connecting line are the same; The other ends of the 2N compound chips (502) are connected to corresponding antenna feeders (401) through second connection lines on the fourth wiring layer (33), and the lengths of each second connection line are the same; The TMV chip (503) penetrates through the third dielectric layer (32), and realizes electrical connection between the third wiring layer (31) and the fourth wiring layer (33) through metallized vias.

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