Silicon-based hybrid integrated light-emitting device and preparation method thereof

Abstract

According to the silicon-based hybrid integrated light-emitting device and the preparation method thereof, a buried heterojunction structure is adopted in a light-emitting gain region, transverse diffusion of injection current is effectively restrained, the current injection efficiency is remarkably improved, and therefore the working temperature of the light-emitting gain region is reduced, a deep mesa etching process is adopted, an active region is not directly etched, and the light-emitting efficiency is improved. The reliability problem caused by etching of the active region is avoided; the first mode field conversion region has no electrode and does not participate in light emitting, etching of an active region interface is avoided, the reliability of the device is further improved, the dilution waveguide layer realizes efficient coupling with the function lamination layer, meanwhile, coupling with the SOI waveguide below is avoided, and effective transmission and mode matching of a light field are ensured; and in the second mode field conversion region, the effective refractive index of the diluted waveguide layer is controlled by removing the active waveguide region on the diluted waveguide layer and adjusting the thickness and the width of the diluted waveguide layer, so that a higher degree of freedom is provided for compatibility with different types of SOI wafers and waveguide structure design.

Description

Technical Field

[0001] The invention belongs to the technical field of lasers, and in particular relates to a silicon-based hybrid integrated light-emitting device and a preparation method thereof. Background Art

[0002] With the rapid development of optical communication and optoelectronic integration technology, silicon-based hybrid integrated light-emitting devices have gradually become a research hotspot due to their advantages in integration, cost-effectiveness and manufacturing process compatibility. The combination of silicon-based photonics platform and III-V semiconductor materials can realize high-performance light source devices, thereby promoting the development of optoelectronic integrated chips. However, existing silicon-based hybrid integrated light-emitting devices still face many challenges in structural design and preparation process, especially in terms of current injection efficiency, light field limitation factor, threshold current density and device reliability.

[0003] At present, common silicon-based hybrid integrated light-emitting devices mainly include two structures: Ridge Waveguide Laser (RW Laser) and Buried Heterostructure Laser (BH Laser). Among them, the advantage of the ridge waveguide laser is that its preparation process is simple, it can be completed with only one epitaxy, and the requirements for ridge stage etching and line width are relatively low. However, the disadvantage of the ridge waveguide laser is that lateral leakage is prone to occur during current injection, resulting in a decrease in internal quantum efficiency, which in turn affects key performance indicators such as junction temperature and threshold current. The buried heterojunction laser can effectively improve the current injection efficiency and reduce the threshold current density and junction temperature by suppressing the lateral diffusion of current, but its preparation process is complicated and usually requires three epitaxies, which increases the manufacturing cost and process difficulty.

[0004] In addition, Intel proposed a technical solution for direct coupling of III-V semiconductors with silicon on insulator (SOI). This solution adopts a coplanar NP electrode structure and establishes a lateral current diffusion blocking region (Blocking Region) by ion implantation to suppress the lateral diffusion of current. The AlGaInAs active region and SOI waveguide together form a cavity waveguide to achieve lasing. However, the disadvantage of this solution is that the light field limitation factor is small, resulting in a high threshold current, which is difficult to meet the needs of low-power applications. In another solution, the III-V semiconductor and the SOI waveguide work independently of each other, achieve optical coupling through a tapered coupler (Taper Coupler), and adopt a coplanar NP electrode structure. This solution suppresses the lateral diffusion of current by etching through the active region with a ridge terrace, but its disadvantage is that the active waveguide has high loss, and the damage to the active region during the etching process may cause device reliability problems.

[0005] In summary, the existing silicon-based hybrid integrated light-emitting devices still have significant deficiencies in current injection efficiency, light field confinement factor, threshold current density and device reliability. Therefore, a new silicon-based hybrid integrated light-emitting device structure and its preparation method are urgently needed to solve the above problems. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a silicon-based hybrid integrated light-emitting device and a preparation method thereof, so as to solve the problem that the silicon-based hybrid integrated light-emitting devices in the prior art still have significant deficiencies in current injection efficiency, threshold current density and device reliability.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a silicon-based hybrid integrated light-emitting device, comprising the following steps:

[0008] Providing a semiconductor substrate, forming a buried oxide layer and a first waveguide layer in sequence on the semiconductor substrate, and forming a bonding layer on the first waveguide layer;

[0009] forming a dilution waveguide layer on the bonding layer, wherein the dilution waveguide layer includes at least three InP layers and at least two InGaAsP layers or AlGaInAs layers;

[0010] Forming a first InGaAsP layer on the diluted waveguide layer, etching the first InGaAsP layer and the diluted waveguide layer to form a first etched groove, a second etched groove, a third etched groove, a fourth etched groove, a fifth etched groove and a sixth etched groove, respectively, wherein the first etched groove and the sixth etched groove are symmetrically distributed about the central axis of the semiconductor substrate;

[0011] forming an electron injection layer on the first InGaAsP layer, and etching the electron injection layer between the second etching groove and the fifth etching groove to remove a portion of the electron injection layer;

[0012] Performing an epitaxial process on the electron injection layer between the second etched groove and the fifth etched groove to form a light-emitting device functional stack, and performing side ion implantation on the light-emitting device functional stack between the third etched groove and the fourth etched groove to form an electron injection blocking region;

[0013] A first metal electrode with ohmic contact and an InGaAs epitaxial layer are formed on the light emitting device functional stack between the third etched groove and the fourth etched groove, and a second metal electrode is formed on the electron injection layer between the third etched groove and the fourth etched groove.

[0014] Optionally, the dilute waveguide layer includes three InP layers and two InGaAsP layers or AlGaInAs layers, wherein the InGaAsP layers or AlGaInAs layers serve as spacer layers to separate the three InP layers from each other.

[0015] Optionally, the central axis of the dilution waveguide layer, the electron injection layer, and the light-emitting device functional stack coincides with the central axis of the semiconductor substrate.

[0016] Optionally, the light-emitting device functional stack includes an energy band transition layer, a hole injection layer, an upper waveguide limiting layer, a multi-quantum well layer and a lower waveguide limiting layer stacked in sequence from bottom to top, wherein the material of the energy band transition layer includes InGaAsP, the material of the hole injection layer includes InP, the material of the upper waveguide limiting layer includes InGaAsP or AlGaInAs, the material of the multi-quantum well layer includes InGaAs, and the material of the lower waveguide limiting layer includes InGaAsP or AlGaInAs.

[0017] Optionally, the width of the dilution waveguide layer between the second etched groove and the fifth etched groove is greater than the width of the electron injection layer and the light emitting device functional stack between the second etched groove and the fifth etched groove.

[0018] Optionally, the width of the electron injection layer and the light-emitting device functional stack located between the third etching groove and the fourth etching groove is greater than the width of the electron injection layer and the light-emitting device functional stack located between the second etching groove and the third etching groove and between the fourth etching groove and the fifth etching groove.

[0019] Optionally, the width of the diluted waveguide layer between the first etched groove and the second etched groove and between the fifth etched groove and the sixth etched groove is smaller than the width of the diluted waveguide layer between the second etched groove and the third etched groove and between the fourth etched groove and the fifth etched groove.

[0020] The present invention also provides a silicon-based hybrid integrated light-emitting device, the silicon-based hybrid integrated light-emitting device comprising:

[0021] A semiconductor substrate, and a buried oxide layer, a first waveguide layer and a bonding layer located on the semiconductor substrate;

[0022] A diluted waveguide layer, located above the bonding layer, the diluted waveguide layer comprising at least three InP layers and at least two InGaAsP layers or AlGaInAs layers;

[0023] a first InGaAsP layer, the first InGaAsP layer being located on the dilute waveguide layer;

[0024] The first to sixth etched grooves are arranged at intervals, the first waveguide layer is exposed at the bottom of the first to sixth etched grooves, the area between the first etched groove and the second etched groove and the area between the fifth etched groove and the sixth etched groove are used as the second mode field conversion area, the area between the second etched groove and the third etched groove and the area between the fourth etched groove and the fifth etched groove are used as the first mode field conversion area, and the area between the third etched groove and the fourth etched groove is used as the light emitting gain area;

[0025] An electron injection layer, located on the first InGaAsP layer;

[0026] A light emitting device functional stack is located on the electron injection layer between the second etched groove and the fifth etched groove;

[0027] An electron injection blocking region, located at a side opposite to the light emitting device functional stack between the third etched groove and the fourth etched groove;

[0028] A first metal electrode and an InGaAs epitaxial layer are located on the light emitting device functional stack between the third etched groove and the fourth etched groove, and an ohmic contact is formed between the first metal electrode and the InGaAs epitaxial layer;

[0029] The second metal electrode is located on the electron injection layer between the third etched groove and the fourth etched groove.

[0030] Optionally, the light-emitting device functional stack includes an energy band transition layer, a hole injection layer, an upper waveguide limiting layer, a multi-quantum well layer and a lower waveguide limiting layer stacked in sequence from bottom to top, wherein the material of the energy band transition layer includes InGaAsP, the material of the hole injection layer includes an InP layer, the material of the upper waveguide limiting layer includes InGaAsP or AlGaInAs, the material of the multi-quantum well layer includes InGaAs, and the material of the lower waveguide limiting layer includes InGaAsP or AlGaInAs.

[0031] Optionally, the first waveguide layer is a strip waveguide or a rib waveguide.

[0032] As described above, the present invention provides a silicon-based hybrid integrated light-emitting device and a preparation method thereof, and the beneficial effects are as follows: the light-emitting device functional stack in the light-emitting gain region adopts a buried heterojunction (BH) structure, thereby effectively suppressing the lateral diffusion of the injected current, significantly improving the current injection efficiency, thereby reducing the operating temperature of the light-emitting gain region, and also playing a role in tightly binding the mode field of the quantum well light-emitting region. The light-emitting device functional stack adopts a deep mesa etching process, and the etching process does not directly etch through the active region, thereby avoiding the reliability problem caused by the etching of the side wall of the active region; no metal electrode is set in the first mode field conversion region, so no injection current is generated, and since it does not participate in the light emission, it is avoided. The reliability problem caused by the etching interface of the active area is avoided, and the reliability of the device is further improved. In addition, the diluted waveguide layer in the first mode field conversion zone realizes efficient coupling with the functional stack of the light-emitting device, while avoiding coupling with the SOI waveguide below, ensuring the effective transmission and mode matching of the light field; in the second mode field conversion zone, by removing the active waveguide area on the diluted waveguide layer and adjusting the thickness of the InGaAsP layer or AlGaInAs layer sandwiched by the InP layer in the diluted waveguide layer, the thickness and width of the diluted waveguide layer and the effective refractive index of the diluted waveguide layer can be controlled, thereby providing a higher degree of freedom for compatibility with different types of SOI wafers and waveguide structure design. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a process flow chart of a method for preparing a silicon-based hybrid integrated light-emitting device in an embodiment of the present invention.

[0034] Figure 2 Shown is a schematic structural diagram of a substrate provided in the method for preparing a silicon-based hybrid integrated light-emitting device of the present invention.

[0035] Figure 3 It is a schematic diagram of the structure after forming a buried oxide layer, a first waveguide layer and a bonding layer in the method for preparing a silicon-based hybrid integrated light-emitting device of the present invention.

[0036] Figure 4 It is a schematic diagram of the structure after forming a diluted waveguide layer in the method for preparing a silicon-based hybrid integrated light-emitting device of the present invention.

[0037] Figure 5 It is a schematic diagram of the structure after forming a first InGaAsP layer and a plurality of etching grooves in the method for preparing a silicon-based hybrid integrated light-emitting device of the present invention.

[0038] Figure 6 It is a schematic diagram of the structure after the electron injection layer is formed in the preparation method of the silicon-based hybrid integrated light-emitting device of the present invention.

[0039] Figure 7It is a schematic diagram of the structure after forming the functional stack of the light-emitting device in the method for preparing the silicon-based hybrid integrated light-emitting device of the present invention.

[0040] Figure 8 It is a schematic diagram of the structure after the electron injection blocking region is formed in the method for preparing the silicon-based hybrid integrated light-emitting device of the present invention.

[0041] Fig. 9 It is a schematic diagram of the structure after forming the first electrode and the second electrode in the method for preparing the silicon-based hybrid integrated light-emitting device of the present invention.

[0042] Component number description

[0043] 10. semiconductor substrate; 11. buried oxide layer; 12. first waveguide layer; 13. bonding layer; 14. diluted waveguide layer; 141. InP layer; 142. InGaAsP layer or AlGaInAs layer; 15. first InGaAsP layer; 161. first etched groove; 162. second etched groove; 163. third etched groove; 164. fourth etched groove; 165. fifth etched groove; 166. sixth etched groove Groove; 171, second mode field conversion region; 172, first mode field conversion region; 173, light-emitting gain region; 18, electron injection layer; 191, lower waveguide confinement region; 192, multi-quantum well layer; 193, upper waveguide confinement region; 194, hole injection layer; 195, band transition layer; 20, electron injection blocking region; 21, InGaAs epitaxial layer; 221, first metal electrode; 222, second metal electrode; S1~S6: steps. DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0046] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0047] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] like Figure 1 As shown, this embodiment provides a method for preparing a silicon-based hybrid integrated light-emitting device, and the preparation method comprises the following steps:

[0050] S1: providing a semiconductor substrate 10, sequentially forming a buried oxide layer 11 and a first waveguide layer 12 on the semiconductor substrate 10, and forming a bonding layer 13 on the first waveguide layer 12;

[0051] S2: forming a dilution waveguide layer 14 on the bonding layer 13, wherein the dilution waveguide layer 14 includes at least three InP layers 141 and at least two InGaAsP layers or AlGaInAs layers 142;

[0052] S3: forming a first InGaAsP layer 15 on the diluted waveguide layer 14, etching the first InGaAsP layer 15 and the diluted waveguide layer 14 to form a first etching groove 161, a second etching groove 162, a third etching groove 163, a fourth etching groove 164, a fifth etching groove 165 and a sixth etching groove 166, respectively, wherein the first etching groove 161 and the sixth etching groove 166 are symmetrically distributed about the central axis of the semiconductor substrate 10;

[0053] S4: forming an electron injection layer 18 on the first InGaAsP layer 15, and etching the electron injection layer 18 between the second etching groove 162 and the fifth etching groove 165 to remove a portion of the electron injection layer 18;

[0054] S5: performing an epitaxial process on the electron injection layer 18 between the second etching groove 162 and the fifth etching groove 165 to form a light-emitting device functional stack, and performing side ion implantation on the light-emitting device functional stack between the third etching groove 163 and the fourth etching groove to form an electron injection blocking region 20;

[0055] S6: forming a first metal electrode 221 and an InGaAs epitaxial layer 21 with ohmic contact on the light-emitting device functional stack between the third etching groove 163 and the fourth etching groove, and forming a second metal electrode 222 on the electron injection layer 18 between the third etching groove 163 and the fourth etching groove.

[0056] It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the silicon-based hybrid integrated light-emitting device protected by the present invention, and those skilled in the art may change it according to the actual preparation steps. The following is a further introduction to the method for preparing the silicon-based hybrid integrated light-emitting device in conjunction with the accompanying drawings, as follows:

[0057] In step S1, see Figure 1 , Figure 2 and Figure 3 , a semiconductor substrate 10 is provided, a buried oxide layer 11 and a first waveguide layer 12 are sequentially formed on the semiconductor substrate 10 , and a bonding layer 13 is formed on the first waveguide layer 12 .

[0058] As an example, the substrate may be a silicon substrate of a single crystal, polycrystalline or amorphous structure, or a silicon-on-insulator (SOI), or may include other types, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe). The substrate may also include a compound semiconductor and / or an alloy semiconductor, such as gallium nitride, gallium arsenide, etc. In this embodiment, Figure 2 As shown, the substrate is a common single crystal silicon substrate.

[0059] In this embodiment, if Figure 3As shown, a buried oxide layer 11 is formed on the substrate by thermal oxidation or chemical vapor deposition (CVD) process, a first waveguide layer 12 (for example, a Si or SiN waveguide layer) is formed on the buried oxide layer 11 by epitaxial growth or deposition process, and a bonding layer 13 (for example, a SiO2 or SiN bonding layer 13) is formed on the first waveguide layer 12. The first waveguide layer 12 can be a strip waveguide formed by completely etching the top silicon layer, or a rib waveguide formed by partially etching the top silicon layer, wherein the thickness of the top silicon layer is at least 220nm, and the waveguide width of the formed first waveguide layer 12 is greater than 400nm. Furthermore, a chemical mechanical polishing process is performed on the bonding layer 13, which is conducive to obtaining a flat bonding layer 13, thereby improving the performance of the silicon-based hybrid integrated light-emitting device.

[0060] In step S2, see Figure 1 and Figure 4 , a dilution waveguide layer 14 is formed on the bonding layer 13 , wherein the dilution waveguide layer 14 includes at least three InP layers 141 and at least two InGaAsP layers or AlGaInAs layers 142 .

[0061] As an example, a dilution waveguide layer 14 is formed on the bonding layer 13 by a multi-layer epitaxial growth process, and the dilution waveguide layer 14 includes at least three InP layers 141 and at least two InGaAsP layers or AlGaInAs layers 142. For example, the dilution waveguide layer 14 may be an InP layer 141, an InGaAsP layer, an InP layer 141, an InGaAsP layer, and an InP layer 141 in sequence. In a specific embodiment, the dilution waveguide layer 14 includes three InP layers 141 and two InGaAsP layers or the dilution waveguide layer 14 includes three InP layers 141 and two AlGaInAs layers, that is, the number of InGaAsP layers or AlGaInAs layers 142 is one layer less than the number of InP layers 141, so that the InGaAsP layer or AlGaInAs layer 142 can be used as a separation layer to separate adjacent InP layers 141 from each other, and the dilution waveguide layer 14 is subsequently divided into different regions by grooves formed by an etching process.

[0062] In step S3, see Figure 1 and Figure 5 , a first InGaAsP layer 15 is formed on the diluted waveguide layer 14, and the first InGaAsP layer 15 and the diluted waveguide layer 14 are etched to form a first etched groove 161, a second etched groove 162, a third etched groove 163, a fourth etched groove 164, a fifth etched groove 165 and a sixth etched groove 166, respectively, wherein the first etched groove 161 and the sixth etched groove 166 are symmetrically distributed about the central axis of the semiconductor substrate 10.

[0063] Specifically, in this embodiment, the first InGaAsP layer 15 is formed on the uppermost InP layer 141 in the diluted waveguide layer 14 by a PECVD process, the first InGaAsP layer 15 is used as a buffer layer, a photoresist mask layer is formed on the first InGaAsP layer 15, the photoresist mask layer is exposed and developed, and the diluted waveguide layer 14 and the first InGaAsP layer 15 are dry-etched based on the photoresist mask layer to form a plurality of etched grooves, and the plurality of etched grooves divide the substrate into different functional areas, specifically as follows: the first etched groove 161 and the sixth etched groove 166 are symmetrically distributed about the central axis of the semiconductor substrate 10, and the first etched groove 161 and the sixth etched groove 166 expose the first waveguide layer 12 and are used as the SOI waveguide transmission area, the area between the first etched groove 161 and the second etched groove 162 and the area between the fifth etched groove 165 and the sixth etched groove 166 are symmetrically distributed about the central axis of the semiconductor substrate 10, and the first etched groove 161 and the sixth etched groove 166 expose the first waveguide layer 12 and are used as the SOI waveguide transmission area, and the area between the first etched groove 161 and the second etched groove 162 and the area between the fifth etched groove 165 and the sixth etched groove 166 are symmetrically distributed about the central axis of the semiconductor substrate 10. The area between the grooves 166 is used as the second mode field conversion zone 171, the area between the second etched groove 162 and the third etched groove 163 and the area between the fourth etched groove 164 and the fifth etched groove 165 are used as the first mode field conversion zone 172, and the area between the third etched groove 163 and the fourth etched groove 164 is used as the light-emitting gain zone 173, wherein the light-emitting gain zone 173 is used to generate stimulated amplified light radiation and transmit it in the active waveguide formed by the III-V semiconductor material; the first mode field conversion zone 172 is used to couple the light transmitted in the active waveguide downward to the adjacent passive waveguide zone formed by the III-V semiconductor material; the second mode field conversion zone 171 is used to further couple the light transmitted in the passive waveguide formed by the III-V semiconductor material downward to the adjacent SOI passive waveguide zone; the SOI waveguide transmission zone is used to transmit the light in the second mode field conversion zone 171 downward to the SOI waveguide zone.

[0064] As an example, the width of the dilution waveguide layer 14 between the first etched groove 161 and the second etched groove and between the fifth etched groove 165 and the sixth etched groove 166 is smaller than the width of the dilution waveguide layer 14 between the second etched groove 162 and the third etched groove 163 and between the fourth etched groove 164 and the fifth etched groove 165. In order to further optimize the mode matching of the light field, reduce the loss, and improve the conversion efficiency, the width of the dilution waveguide layer 14 of the second mode field conversion region 171 is designed to be smaller than the width of the dilution waveguide layer 14 of the first mode field conversion region 172.

[0065] As an example, the width of the dilution waveguide layer 14 between the second etched groove 162 and the fifth etched groove 165 is greater than the width of the electron injection layer 18 and the light emitting device functional stack between the second etched groove 162 and the fifth etched groove 165. That is, the width of the dilution waveguide layer 14 of the light emitting gain region 173 is greater than the width of the light emitting device functional stack of the light emitting gain region 173, and the width of the dilution waveguide layer 14 of the first mode field conversion region 172 is greater than the width of the light emitting device functional stack of the first mode field conversion region 172.

[0066] In step S4, see Figure 1 and Figure 6 , an electron injection layer 18 is formed on the first InGaAsP layer 15 , and the electron injection layer 18 located between the second etching groove 162 and the fifth etching groove 165 is etched to remove a portion of the electron injection layer 18 .

[0067] As an example, an electron injection layer 18 is formed on the first InGaAsP layer 15. In this embodiment, the material of the first InGaAsP layer 15 is n-InGaAsP, the material of the electron injection layer 18 is n-InP, and the process for forming the electron injection layer 18 can be selected as a chemical vapor deposition (CVD) process. It should be noted that when the chemical vapor deposition (CVD) process is used, part of the electron injection layer 18 may be formed in the first etching groove 161, the second etching groove 162, the third etching groove 163, the fourth etching groove 164, the fifth etching groove 165 and the sixth etching groove 166, and needs to be removed by an etching process. In addition, since the widths of the electron injection layer 18 in the light-emitting gain region 173 and the first mode field conversion region 172 are different, it is also necessary to etch the electron injection layer 18 between the second etching groove 162 and the fifth etching groove 165 to remove part of the electron injection layer 18, so as to form a layer as shown in FIG. Figure 6 The structure shown.

[0068] In step S5, refer to Figure 1 , Figure 7 and Figure 8 , an epitaxial process is performed on the electron injection layer 18 located between the second etching groove 162 and the fifth etching groove 165 to form a light-emitting device functional stack, and side ion implantation is performed on the light-emitting device functional stack located between the third etching groove 163 and the fourth etching groove to form an electron injection blocking area 20.

[0069] As an example, Figure 7As shown, the light-emitting device functional stack includes an energy band transition layer 195, a hole injection layer 194, an upper waveguide limiting layer, a multi-quantum well layer 192 and a lower waveguide limiting layer stacked in sequence from bottom to top, wherein the material of the energy band transition layer 195 includes InGaAsP, the material of the hole injection layer 194 includes InP, the material of the upper waveguide limiting layer includes InGaAsP or AlGaInAs, the material of the multi-quantum well layer 192 includes InGaAs, and the material of the lower waveguide limiting layer includes InGaAsP or AlGaInAs. For example: in a specific embodiment, the material of the energy band transition layer 195 is a p-InGaAsP layer, the material of the hole injection layer 194 is a p-InP layer, the materials of the upper waveguide limiting layer and the lower waveguide limiting layer are both InGaAsP, and the material of the multi-quantum well layer 192 is InGaAs.

[0070] As an example, the strain of other layers in the light emitting device functional stack except the multi-quantum well layer 192 relative to the first InGaAsP layer 15 is less than ±0.1%. Under the effect of quantum confinement, the emission wavelength of photoluminescence (PL) is 2.1 μm to 2.3 μm.

[0071] As an example, the upper waveguide limiting layer and the lower waveguide limiting layer are used to provide an energy barrier, limit carriers and light fields, and improve the efficiency and gain of the light-emitting device.

[0072] As an example, the hole injection layer 194 and the electron injection layer 18 are used to guide and confine the light field, thereby improving the optical gain and mode stability of the light-emitting device.

[0073] As an example, the width of the electron injection layer 18 and the light-emitting device functional stack between the third etched groove 163 and the fourth etched groove is greater than the width of the electron injection layer 18 and the light-emitting device functional stack between the second etched groove 162 and the third etched groove 163 and between the fourth etched groove 164 and the fifth etched groove 165. That is, the width of the light-emitting device functional stack of the light-emitting gain region 173 is greater than the width of the light-emitting device functional stack of the first mode field conversion region 172.

[0074] As an example, Figure 8 As shown, side ion implantation is performed on the light-emitting device functional stack of the light-emitting gain region 173 to form an electron injection blocking region 20 on the side of the light-emitting device functional stack. The electron injection blocking region 20 is arranged in contact with the hole injection layer 194, the upper waveguide confinement layer, the multi-quantum well layer 192, the lower waveguide confinement layer and the electron injection layer 18, wherein the material of the electron injection blocking region 20 is selected to be semi-insulating InP.

[0075] As an example, the central axis of the dilution waveguide layer 14 , the electron injection layer 18 , and the light-emitting device functional stack coincides with the central axis of the semiconductor substrate 10 .

[0076] In step S6, refer to Figure 1 and Fig. 9 A first metal electrode 221 and an InGaAs epitaxial layer 21 with ohmic contact are formed on the light-emitting device functional stack located between the third etching groove 163 and the fourth etching groove, and a second metal electrode 222 is formed on the electron injection layer 18 located between the third etching groove 163 and the fourth etching groove.

[0077] As an example, it also includes forming an InGaAs epitaxial layer 21 and a first metal electrode 221, wherein the InGaAs epitaxial layer 21 is located above the band transition layer 195 as an ohmic contact layer, the first metal electrode 221 is located above the InGaAs epitaxial layer 21 and is electrically connected to the InGaAs epitaxial layer 21, the material of the first metal electrode 221 is a p-metal electrode, the InGaAs epitaxial layer 21 is p-InGaAs, and a P-type ohmic contact is formed between the first metal electrode 221 and the InGaAs epitaxial layer 21 to reduce the contact resistance between the electrode and the device.

[0078] As an example, the step of forming a second metal electrode 222 is also included. The material of the second metal electrode 222 is an n-metal electrode. The second metal electrode 222 is located on the electron injection layer 18 and forms an electrical connection with the electron injection layer 18. The first metal electrode 221 and the second metal electrode 222 are used to electrically connect the light-emitting device to a power source and / or an external device.

[0079] Thus, a silicon-based hybrid integrated light-emitting device is obtained. Fig. 9 The silicon-based hybrid integrated light-emitting device includes a semiconductor substrate 10, and a buried oxide layer 11, a first waveguide layer 12 and a bonding layer 13 located on the semiconductor substrate 10;

[0080] A diluted waveguide layer 14, located above the bonding layer 13, wherein the diluted waveguide layer 14 includes at least three InP layers 141 and at least two InGaAsP layers or AlGaInAs layers 142;

[0081] A first InGaAsP layer 15, wherein the first InGaAsP layer 15 is located on the dilution waveguide layer 14;

[0082] First to sixth etched grooves 166 are arranged at intervals, the bottoms of the first to sixth etched grooves 166 expose the first waveguide layer 12, and isolate the diluted waveguide layer 14 and the first InGaAsP layer 15 into regions with different functions;

[0083] An electron injection layer 18, located on the first InGaAsP layer 15;

[0084] A light emitting device functional stack is located on the electron injection layer 18 between the second etching groove 162 and the fifth etching groove 165;

[0085] An electron injection blocking region 20 is located at a side opposite to the light emitting device functional stack between the third etched groove 163 and the fourth etched groove;

[0086] A first metal electrode 221 and an InGaAs epitaxial layer 21 are located on the light emitting device functional stack between the third etched groove 163 and the fourth etched groove, and an ohmic contact is formed between the first metal electrode 221 and the InGaAs epitaxial layer 21;

[0087] The second metal electrode 222 is located on the electron injection layer 18 between the third etched groove 163 and the fourth etched groove.

[0088] Specifically, the first etched groove 161 and the sixth etched groove 166 expose the first waveguide layer 12 and are used as the SOI waveguide transmission area, the area between the first etched groove 161 and the second etched groove 162 and the area between the fifth etched groove 165 and the sixth etched groove 166 are used as the second mode field conversion area 171, the area between the second etched groove 162 and the third etched groove 163 and the area between the fourth etched groove 164 and the fifth etched groove 165 are used as the first mode field conversion area 172, and the area between the third etched groove 163 and the fourth etched groove 164 is used as the emission area. The light gain region 173 is used to generate stimulated amplified light radiation and transmit it in the active waveguide formed by the III-V semiconductor material; the first mode field conversion region 172 is used to couple the light transmitted in the active waveguide downward to the adjacent passive waveguide region formed by the III-V semiconductor material; the second mode field conversion region 171 is used to further couple the light transmitted in the passive waveguide formed by the III-V semiconductor material downward to the adjacent SOI passive waveguide region; the SOI waveguide transmission region is used to transmit the light in the second mode field conversion region 171 downward to the SOI waveguide region.

[0089] As an example, the functional stack of the light-emitting device includes a band transition layer 195, a hole injection layer 194, an upper waveguide limiting layer, a multi-quantum well layer 192 and a lower waveguide limiting layer stacked in sequence from bottom to top, wherein the material of the band transition layer 195 includes InGaAsP, the material of the hole injection layer 194 includes an InP layer, the material of the upper waveguide limiting layer includes InGaAsP or AlGaInAs, the material of the multi-quantum well layer 192 includes InGaAs, and the material of the lower waveguide limiting layer includes InGaAsP or AlGaInAs.

[0090] As an example, the first waveguide layer 12 may be a strip waveguide or a rib waveguide.

[0091] In summary, in the silicon-based hybrid integrated light-emitting device and the preparation method thereof of the present invention, by adopting a buried heterojunction (BH) structure in the light-emitting device functional stack in the light-emitting gain region, the lateral diffusion of the injected current can be effectively suppressed, the current injection efficiency can be significantly improved, and the operating temperature of the light-emitting gain region can be reduced, and the mode field of the quantum well light-emitting region can be tightly bound. The light-emitting device functional stack adopts a deep table etching process, and the etching process does not directly etch through the active region, thereby avoiding the reliability problem caused by the etching of the side wall of the active region; no metal electrode is set in the first mode field conversion region, so no injected current is generated, and since it does not participate in the light emission, the active region is avoided. The reliability problem caused by the etching interface in the first mode field conversion zone is solved, and the reliability of the device is further improved. In addition, the diluted waveguide layer in the first mode field conversion zone realizes efficient coupling with the functional stack of the light-emitting device, while avoiding coupling with the SOI waveguide below, ensuring the effective transmission and mode matching of the light field; in the second mode field conversion zone, by removing the active waveguide area on the diluted waveguide layer and adjusting the thickness of the InGaAsP layer or AlGaInAs layer sandwiched by the InP layer in the diluted waveguide layer, the thickness and width of the diluted waveguide layer and the effective refractive index of the diluted waveguide layer are controlled, thereby providing a higher degree of freedom for designing compatible SOI wafers and waveguide structures of different types. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a silicon-based hybrid integrated light-emitting device, characterized in that: The following steps are involved: Providing a semiconductor substrate, forming a buried oxide layer and a first waveguide layer in sequence on the semiconductor substrate, and forming a bonding layer on the first waveguide layer; forming a dilution waveguide layer on the bonding layer, wherein the dilution waveguide layer includes at least three InP layers and at least two InGaAsP layers or AlGaInAs layers; Forming a first InGaAsP layer on the diluted waveguide layer, etching the first InGaAsP layer and the diluted waveguide layer to form a first etched groove, a second etched groove, a third etched groove, a fourth etched groove, a fifth etched groove and a sixth etched groove, respectively, wherein the first etched groove and the sixth etched groove are symmetrically distributed about the central axis of the semiconductor substrate; forming an electron injection layer on the first InGaAsP layer, and etching the electron injection layer between the second etching groove and the fifth etching groove to remove a portion of the electron injection layer; Performing an epitaxial process on the electron injection layer between the second etched groove and the fifth etched groove to form a light-emitting device functional stack, and performing side ion implantation on the light-emitting device functional stack between the third etched groove and the fourth etched groove to form an electron injection blocking region; A first metal electrode with ohmic contact and an InGaAs epitaxial layer are formed on the light emitting device functional stack between the third etched groove and the fourth etched groove, and a second metal electrode is formed on the electron injection layer between the third etched groove and the fourth etched groove.

2. The method for preparing a silicon-based hybrid integrated light-emitting device according to claim 1, characterized in that: The dilute waveguide layer includes three InP layers and two InGaAsP layers or AlGaInAs layers, wherein the InGaAsP layers or AlGaInAs layers serve as separation layers to separate the three InP layers from each other.

3. The method for preparing a silicon-based hybrid integrated light-emitting device according to claim 1, characterized in that: The central axis of the dilution waveguide layer, the electron injection layer, and the light-emitting device functional stack coincides with the central axis of the semiconductor substrate.

4. The method for preparing a silicon-based hybrid integrated light-emitting device according to claim 1, characterized in that: The light-emitting device functional stack includes an energy band transition layer, a hole injection layer, an upper waveguide limiting layer, a multi-quantum well layer and a lower waveguide limiting layer stacked in sequence from bottom to top, wherein the material of the energy band transition layer includes InGaAsP, the material of the hole injection layer includes InP, the material of the upper waveguide limiting layer includes InGaAsP or AlGaInAs, the material of the multi-quantum well layer includes InGaAs, and the material of the lower waveguide limiting layer includes InGaAsP or AlGaInAs.

5. The method for preparing a silicon-based hybrid integrated light-emitting device according to claim 1, characterized in that: The width of the dilution waveguide layer between the second etched groove and the fifth etched groove is greater than the width of the electron injection layer and the light emitting device functional stack between the second etched groove and the fifth etched groove.

6. The method for preparing a silicon-based hybrid integrated light-emitting device according to claim 1, characterized in that: The width of the electron injection layer and the light-emitting device functional stack between the third etching groove and the fourth etching groove is greater than the width of the electron injection layer and the light-emitting device functional stack between the second etching groove and the third etching groove and between the fourth etching groove and the fifth etching groove.

7. The method for preparing a silicon-based hybrid integrated light-emitting device according to claim 1, characterized in that: The width of the diluted waveguide layer between the first etched groove and the second etched groove and between the fifth etched groove and the sixth etched groove is smaller than the width of the diluted waveguide layer between the second etched groove and the third etched groove and between the fourth etched groove and the fifth etched groove.

8. A silicon-based hybrid integrated light-emitting device, characterized in that: The silicon-based hybrid integrated light-emitting device comprises: A semiconductor substrate, and a buried oxide layer, a first waveguide layer and a bonding layer located on the semiconductor substrate; A diluted waveguide layer, located above the bonding layer, the diluted waveguide layer comprising at least three InP layers and at least two InGaAsP layers or AlGaInAs layers; a first InGaAsP layer, the first InGaAsP layer being located on the dilute waveguide layer; The first to sixth etched grooves are arranged at intervals, the first waveguide layer is exposed at the bottom of the first to sixth etched grooves, the area between the first etched groove and the second etched groove and the area between the fifth etched groove and the sixth etched groove are used as the second mode field conversion area, the area between the second etched groove and the third etched groove and the area between the fourth etched groove and the fifth etched groove are used as the first mode field conversion area, and the area between the third etched groove and the fourth etched groove is used as the light emitting gain area; An electron injection layer, located on the first InGaAsP layer; A light emitting device functional stack is located on the electron injection layer between the second etched groove and the fifth etched groove; An electron injection blocking region, located at a side opposite to the light emitting device functional stack between the third etched groove and the fourth etched groove; A first metal electrode and an InGaAs epitaxial layer are located on the light emitting device functional stack between the third etched groove and the fourth etched groove, and an ohmic contact is formed between the first metal electrode and the InGaAs epitaxial layer; The second metal electrode is located on the electron injection layer between the third etched groove and the fourth etched groove.

9. The silicon-based hybrid integrated light-emitting device according to claim 8, characterized in that: The light-emitting device functional stack includes an energy band transition layer, a hole injection layer, an upper waveguide limiting layer, a multi-quantum well layer and a lower waveguide limiting layer stacked in sequence from bottom to top, wherein the material of the energy band transition layer includes InGaAsP, the material of the hole injection layer includes an InP layer, the material of the upper waveguide limiting layer includes InGaAsP or AlGaInAs, the material of the multi-quantum well layer includes InGaAs, and the material of the lower waveguide limiting layer includes InGaAsP or AlGaInAs.

10. The silicon-based hybrid integrated light-emitting device according to claim 8, characterized in that: The first waveguide layer is a strip waveguide or a rib waveguide.

Images