Frequency converter, drive signal processing method thereof, and computer readable storage medium

Abstract

The present application discloses a frequency converter and its drive signal processing method, as well as a computer-readable storage medium. The method includes: receiving a modulated wave, a first triangular carrier corresponding to the upper left tube in an H-bridge, and a second triangular carrier corresponding to the upper right tube in the H-bridge; obtaining a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube based on the modulated wave, the first triangular carrier, and the second triangular carrier; encoding the first drive signal and the second drive signal to obtain a coded signal; and sending the coded signal to a driver board according to the interval point of the interrupt frequency, so that the driver board decodes the coded signal to obtain the first drive signal and the second drive signal. In this way, the drive signal is ensured to be characterized without distinction, thereby driving the motor to operate.

Description

Technical Field

[0001] The present application relates to the technical field of frequency converters, and in particular to a frequency converter, a drive signal processing method thereof, and a computer-readable storage medium. Background Art

[0002] In the inverter system, the driving signal needs to be sent to multiple units synchronously through the main control board, and the wave analysis is performed by the units, and the driving module in the driving power circuit board is driven to perform wave processing. When the time when each cascade unit receives the driving instruction is inconsistent and exceeds the tolerance range, it will cause damage to the power unit, and even worse, the machine will explode.

[0003] In order to ensure the synchronization of the driving signal, the usual solution is to connect the left and right upper tubes in the H-bridge directly to the corresponding optical fiber that generates the driving signal in the main control board through two optical fibers, so as to control the power board driving signal to generate the wave, thereby driving the motor to run. Summary of the Invention

[0004] The frequency converter and its drive signal processing method, as well as the computer-readable storage medium provided in this application, can ensure that the drive signal is portrayed without distinction, thereby driving the motor to operate.

[0005] In a first aspect, the present application provides a drive signal processing method for an inverter, the drive signal processing method comprising: receiving a modulated wave, a first triangular carrier corresponding to the upper left tube in an H-bridge, and a second triangular carrier corresponding to the upper right tube in the H-bridge; obtaining a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulated wave, the first triangular carrier, and the second triangular carrier; encoding the first drive signal and the second drive signal to obtain a coded signal; and sending the coded signal to a driver board according to an interval point of an interrupt frequency, so that the driver board decodes the coded signal to obtain the first drive signal and the second drive signal.

[0006] Among them, according to the modulation wave, the first triangular carrier and the second triangular carrier, the first drive signal corresponding to the upper left tube and the second drive signal corresponding to the upper right tube are obtained, including: within each interrupt frequency, according to the modulation wave, the first triangular carrier and the second triangular carrier, the first drive signal corresponding to the upper left tube and the second drive signal corresponding to the upper right tube are obtained, as well as the first signal switching duration corresponding to the first drive signal and the second signal switching duration corresponding to the second drive signal.

[0007] Among them, sending the coded signal to the driver board according to the interval points of the interruption frequency so that the driver board decodes the coded signal to obtain the first drive signal and the second drive signal, including: sending the coded signal, the first signal switching duration, and the second signal switching duration to the driver board according to the interval points of the interruption frequency so that the driver board decodes the coded signal according to the first signal switching duration and the second signal switching duration to obtain the first drive signal and the second drive signal.

[0008] The first drive signal and the second drive signal are encoded to obtain a coded signal, including: using the first signal value in the first drive signal as the first bit in the coded signal; using the first signal value in the second drive signal as the second bit in the coded signal; using the second signal value in the first drive signal as the third bit in the coded signal; and using the second signal value in the second drive signal as the fourth bit in the coded signal, thereby obtaining a 4-bit coded signal.

[0009] The driving board decodes the coded signal, including: using the first bit in the coded signal as the first signal value in the first driving signal; using the third bit in the coded signal as the second signal value in the first driving signal to obtain the first driving signal; using the second bit in the coded signal as the first signal value in the second driving signal; using the fourth bit in the coded signal as the second signal value in the second driving signal to obtain the second driving signal.

[0010] After receiving the modulated wave, the method includes latching the modulated wave.

[0011] In a second aspect, the present application provides a frequency converter, which includes: a signal processing chip that generates a modulation wave; a main control chip that is coupled to the signal processing chip, receives the modulation wave, and generates a first triangular carrier corresponding to the upper left tube in the H-bridge and a second triangular carrier corresponding to the upper right tube in the H-bridge; and obtains a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube based on the modulation wave, the first triangular carrier and the second triangular carrier; and encodes the first drive signal and the second drive signal to obtain a coded signal; sends the coded signal to a drive board according to the interval point of the interrupt frequency; the drive board is coupled to the main control chip, receives the coded signal, decodes the coded signal, and obtains the first drive signal and the second drive signal.

[0012] Among them, the driver board and the main control chip are connected through optical fiber.

[0013] Among them, within each interrupt frequency, the main control chip obtains the first drive signal corresponding to the upper left tube, the second drive signal corresponding to the upper right tube, the first signal switching duration corresponding to the first drive signal, and the second signal switching duration corresponding to the second drive signal according to the modulation wave, the first triangular carrier and the second triangular carrier.

[0014] In a third aspect, the present application provides a computer-readable storage medium for storing a computer program. When the computer program is executed by a processor, it is used to implement the driving signal processing method provided in the first aspect.

[0015] The beneficial effects of the present application are as follows: different from the prior art, the frequency converter and its drive signal processing method, and computer-readable storage medium provided by the present application receive a modulation wave, a first triangular carrier corresponding to the upper left tube in the H-bridge, and a second triangular carrier corresponding to the upper right tube in the H-bridge; obtain a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulation wave, the first triangular carrier, and the second triangular carrier; encode the first drive signal and the second drive signal to obtain an encoded signal; and send the encoded signal to the driver board according to the interval point of the interruption frequency so that the driver board decodes the encoded signal to obtain the first drive signal and the second drive signal. Cycle-by-cycle encoding of the drive signal can not only ensure the protection of the frequency converter in a short time, but also accurately send the drive signal, thereby ensuring use on low-speed optical fiber, and ensuring the realization of synchronous wave transmission, thereby ensuring that the drive signal is characterized without distinction, thereby driving the motor to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0017] Figure 1 This is a flow chart of an embodiment of a method for processing a drive signal of a frequency converter provided by the present application;

[0018] Figure 2 Schematic diagram of the waveform of the drive signal of the frequency converter provided by this application;

[0019] Figure 3 1 is a waveform diagram of an embodiment of a driving signal provided by the present application;

[0020] Figure 4 is a waveform diagram of another embodiment of the driving signal provided by the present application;

[0021] Figure 5 is a waveform diagram of another embodiment of the driving signal provided by the present application;

[0022] Figure 6 is a waveform diagram of another embodiment of the driving signal provided by the present application;

[0023] Figure 7is a waveform diagram of another embodiment of the driving signal provided by the present application;

[0024] Figure 8 This is a structural diagram of an embodiment of a frequency converter provided by the present application;

[0025] Figure 9 It is a structural diagram of an embodiment of a computer-readable storage medium provided by this application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the inverter system, the driving signal needs to be sent to multiple units synchronously through the main control board, and the wave analysis is performed by the units, and the driving module in the driving power circuit board is driven to perform wave processing. When the time when each cascade unit receives the driving instruction is inconsistent and exceeds the tolerance range, it will cause damage to the power unit, and even worse, the machine will explode.

[0029] In order to ensure the synchronization of the driving signal, the usual solution is to connect the left and right upper tubes in the H-bridge directly to the corresponding optical fiber that generates the driving signal in the main control board through two optical fibers, so as to control the power board driving signal to generate the wave, thereby driving the motor to run.

[0030] Based on this, the present application proposes receiving a modulation wave, a first triangular carrier wave corresponding to the upper left tube in an H-bridge, and a second triangular carrier wave corresponding to the upper right tube in the H-bridge; obtaining a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulation wave, the first triangular carrier wave, and the second triangular carrier wave; encoding the first drive signal and the second drive signal to obtain a coded signal; and sending the coded signal to a driver board according to the interval points of the interruption frequency so that the driver board decodes the coded signal to obtain the first drive signal and the second drive signal. Cycle-by-cycle encoding of the drive signal can not only ensure the protection of the frequency converter in a short time, but also accurately send the drive signal, thereby ensuring its use on low-speed optical fibers and ensuring the realization of synchronous wave transmission, thereby ensuring that the drive signal is portrayed without distinction, thereby driving the motor to operate. For details, please refer to the technical solution of any of the following embodiments.

[0031] See Figure 1 , Figure 1 1 is a flow chart of an embodiment of a method for processing a drive signal of a frequency converter provided by the present application. The drive signal processing method includes:

[0032] Step 11: Receive the modulated wave, the first triangular carrier wave corresponding to the upper left tube in the H-bridge, and the second triangular carrier wave corresponding to the upper right tube in the H-bridge.

[0033] In some embodiments, after receiving the modulated wave, the modulated wave is latched to facilitate execution of step 12 .

[0034] Step 12: Obtain a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulated wave, the first triangular carrier wave and the second triangular carrier wave.

[0035] In some embodiments, within each interrupt frequency, based on the modulation wave, the first triangular carrier and the second triangular carrier, a first drive signal corresponding to the upper left tube, a second drive signal corresponding to the upper right tube, a first signal switching duration corresponding to the first drive signal, and a second signal switching duration corresponding to the second drive signal are obtained.

[0036] In some embodiments, combined Figure 2 To explain:

[0037] like Figure 2 As mentioned above, the portion of the triangular carrier wave corresponding to the upper left transistor in the H-bridge above the modulation wave is a low level 0, and the portion of the triangular carrier wave corresponding to the upper left transistor in the H-bridge below the modulation wave is a high level 1. The triangular carrier wave corresponding to the upper left transistor in the H-bridge intersects with the modulation wave at the signal switching moment. The triangular carrier wave corresponding to the upper right transistor in the H-bridge above the modulation wave is a low level 0, and the portion of the triangular carrier wave corresponding to the upper left transistor in the H-bridge below the modulation wave is a high level 1. The triangular carrier wave corresponding to the upper left transistor in the H-bridge intersects with the modulation wave at the signal switching moment.

[0038] Step 13: Encode the first driving signal and the second driving signal to obtain an encoded signal.

[0039] In some embodiments, the first signal value in the first drive signal is used as the first bit in the encoded signal; the first signal value in the second drive signal is used as the second bit in the encoded signal; the second signal value in the first drive signal is used as the third bit in the encoded signal; and the second signal value in the second drive signal is used as the fourth bit in the encoded signal, thereby obtaining a 4-bit encoded signal.

[0040] For example, in an interrupt period, in response to the first drive signal being 10 and the second drive signal being 10, the first drive signal and the second drive signal are encoded, and the resulting encoded signal is 1100. The first 1 in the encoded signal 1100 represents the first 1 in the first drive signal, the second 1 in the encoded signal 1100 represents the first 1 in the second drive signal, the third 0 in the encoded signal 1100 represents the second 0 in the first drive signal, and the fourth 0 in the encoded signal 1100 represents the second 0 in the second drive signal. Figure 3 As shown, Figure 3 AH and BH represent the drive signals of the left and right upper tubes in the H-bridge circuit respectively. Subsequent decoding can be done according to this logic.

[0041] like Figure 3 As shown in the figure, there are two driving signals that are changing. The driving signal needs to be sent down once at a fixed interruption time T. By using two time scale standards to characterize the switching moment, the driving signal can be accurately characterized. The driving instruction can be represented by 4-bit data, such as Figure 3 In the left figure, CMD=1100, time1, and time2 need to be sent to accurately characterize the drive signal. Figure 3 In the figure on the right, only the command is modified to CMD=1100, where time1 and time2 represent the drive AH and BH signals, respectively. After sending this signal to the unit control board, the drive signal is analyzed to ensure synchronization and accurately depict the drive waveform.

[0042] In the interruption period, in response to the first drive signal being 1 and the second drive signal being 1, it means that in the interruption period, the first drive signal and the second drive signal are both at a high level of 1. In order to ensure the logical consistency of the encoding, the first drive signal and the second drive signal are encoded, and the obtained encoded signal is 1111. Among them, the first drive signal represented by the first 1 in the encoded signal 1111 is 1, the second drive signal represented by the second 1 in the encoded signal 1111 is 1, the first drive signal represented by the third 1 in the encoded signal 1111 is 1, and the second drive signal represented by the fourth 1 in the encoded signal 1111 is 1, as shown in FIG. Figure 4 Subsequent decoding can be done according to this logic.

[0043] In the interruption period, in response to the first drive signal being 0 and the second drive signal being 0, it means that in the interruption period, the first drive signal and the second drive signal are both at a low level of 0. In order to ensure the logical consistency of the encoding, the first drive signal and the second drive signal are encoded, and the obtained encoded signal is 0000. Among them, the first drive signal is represented by the first 0 in the encoded signal 0000, the second drive signal is represented by the second 0 in the encoded signal 0000, the first drive signal is represented by the third 0 in the encoded signal 0000, and the second drive signal is represented by the fourth 0 in the encoded signal 0000. Figure 5 Subsequent decoding can be done according to this logic.

[0044] like Figure 4 and Figure 5 As shown, for the case of sending the same level, it is only necessary to Figure 4 Send CMD=4'b1111, time1=time2=T or 0, and according to Figure 5 Send CMD=4'b0000, time1=time2=T or 0. Figure 4 and Figure 5 The driving signal in the CMOS is accurately characterized.

[0045] In the interruption period, in response to the first drive signal being 01 and the second drive signal being 10, the first drive signal and the second drive signal are encoded, and the obtained encoded signal is 0110. The first 0 in the encoded signal 0110 represents the first 0 in the first drive signal, the second 1 in the encoded signal 0110 represents the first 1 in the second drive signal, the third 1 in the encoded signal 0110 represents the second 1 in the first drive signal, and the fourth 0 in the encoded signal 0110 represents the second 0 in the second drive signal, as shown in FIG. Figure 6 As shown. Subsequent decoding can be done according to this logic. Figure 6As shown, for the inconsistent sending level, Figure 6 , respectively encode the driving signal as follows: CMD=4'b0110, time1, time2, and then send it to the unit for driving analysis and wave generation.

[0046] In the interruption period, in response to the first drive signal being 10 and the second drive signal being 01, the first drive signal and the second drive signal are encoded, and the obtained encoded signal is 1001. The first 1 in the first drive signal represented by the first 1 in the encoded signal 1001, the first 0 in the second drive signal represented by the second 0 in the encoded signal 1001, the second 0 in the first drive signal represented by the third 0 in the encoded signal 1001, and the second 1 in the second drive signal represented by the fourth 1 in the encoded signal 1001, as shown in FIG. Figure 7 As shown. Subsequent decoding can be done according to this logic. Figure 7 As shown, for the inconsistent sending level, Figure 7 , encode the driving signal as follows: CMD=4'b1001, time1, time2, and then send it to the unit for driving analysis and wave generation.

[0047] During the interruption period, in response to the first drive signal being 1 and the second drive signal being 01, it indicates that during the interruption period, the first drive signal is at a high level 1. The first drive signal and the second drive signal are encoded to obtain an encoded signal of 1011. The first 1 in the encoded signal 1011 represents a 1 in the first drive signal, the second 0 in the encoded signal 1011 represents the first 0 in the second drive signal, the third 1 in the encoded signal 1011 represents a 1 in the first drive signal, and the fourth 1 in the encoded signal 1011 represents the second 1 in the second drive signal. Subsequent decoding can be performed according to this logic.

[0048] During the interrupt period, in response to the first drive signal being 01 and the second drive signal being 01, the first drive signal and the second drive signal are encoded, resulting in an encoded signal of 0011. The first 0 in the encoded signal 0011 represents the first 0 in the first drive signal, the second 0 in the encoded signal 0011 represents the first 0 in the second drive signal, the third 1 in the encoded signal 0011 represents the second 1 in the first drive signal, and the fourth 1 in the encoded signal 0011 represents the second 1 in the second drive signal. Subsequent decoding can be performed according to this logic.

[0049] During the interruption period, in response to the first drive signal being 01 and the second drive signal being 11, it indicates that during the interruption period, the second drive signal is at a high level 1. The first drive signal and the second drive signal are encoded to obtain a coded signal of 0111. The first 0 in the coded signal 0111 represents the first 0 in the first drive signal, the second 1 in the coded signal 0111 represents the 1 in the second drive signal, the third 1 in the coded signal 0111 represents the second 1 in the first drive signal, and the fourth 1 in the coded signal 0111 represents the 1 in the second drive signal. Subsequent decoding can be performed according to this logic.

[0050] During the interruption period, in response to the first drive signal being 11 and the second drive signal being 10, it indicates that during the interruption period, the first drive signal is at a high level of 1. The first drive signal and the second drive signal are encoded to obtain an encoded signal of 1110. The first 1 in the encoded signal 1110 represents a 1 in the first drive signal, the second 1 in the encoded signal 1110 represents the first 1 in the second drive signal, the third 1 in the encoded signal 1110 represents a 1 in the first drive signal, and the fourth 0 in the encoded signal 1110 represents the second 0 in the second drive signal. Subsequent decoding can be performed according to this logic.

[0051] Step 14: Send the coded signal to the driving board according to the interval points of the interruption frequency, so that the driving board decodes the coded signal to obtain the first driving signal and the second driving signal.

[0052] The coded signal, the first signal switching duration (the above-mentioned time1), and the second signal switching duration (the above-mentioned time2) are sent to the driver board according to the interval points of the interruption frequency, so that the driver board decodes the coded signal according to the first signal switching duration and the second signal switching duration to obtain the first drive signal and the second drive signal.

[0053] Among them, the driving board uses the first bit in the coding signal as the first signal value in the first driving signal; uses the third bit in the coding signal as the second signal value in the first driving signal to obtain the first driving signal; uses the second bit in the coding signal as the first signal value in the second driving signal; uses the fourth bit in the coding signal as the second signal value in the second driving signal to obtain the second driving signal.

[0054] For example, in response to the coded signal being 1100, the first drive signal being 10, and the second drive signal being 10, the driver board determines the duration of the signal "1" in the first drive signal based on the first signal switching duration, and determines the duration of the signal "1" in the second drive signal based on the second signal switching duration. That is, when the duration of "1" in the first drive signal reaches the first signal switching duration, it switches to "0" at the next moment. When the duration of "1" in the second drive signal reaches the second signal switching duration, it switches to "0" at the next moment.

[0055] In this case, the driver board responds to the coding signal of 1111, the first drive signal is 1, and the second drive signal is 1. That is, the first drive signal is at a high level of 1 during the first signal switching duration. The second drive signal is at a high level of 1 during the second signal switching duration. At this time, the first signal switching duration and the second signal switching duration are equal to the duration of the interruption period.

[0056] In the case where the driver board responds to the coding signal being 0000, the first drive signal is 0 and the second drive signal is 0. That is, the first drive signal is at a low level of 0 during the first signal switching duration. The second drive signal is at a high level of 0 during the second signal switching duration. At this time, the first signal switching duration and the second signal switching duration are equal to the duration of the interruption period.

[0057] In response to the coding signal being 0110, the first drive signal being 01 and the second drive signal being 10, the driver board determines the duration of the 0 in the first drive signal based on the first signal switching duration, and determines the duration of the 1 in the second drive signal based on the second signal switching duration. That is, when the duration of the 0 in the first drive signal reaches the first signal switching duration, the signal is switched to 1 at the next moment. When the duration of the 1 in the second drive signal reaches the second signal switching duration, the signal is switched to 0 at the next moment.

[0058] In response to the coding signal being 1001, the first drive signal being 10, and the second drive signal being 01, the driver board determines the duration of the 1 in the first drive signal based on the first signal switching duration, and determines the duration of the 0 in the second drive signal based on the second signal switching duration. That is, when the duration of 1 in the first drive signal reaches the first signal switching duration, the signal is switched to 0 at the next moment. When the duration of 0 in the second drive signal reaches the second signal switching duration, the signal is switched to 1 at the next moment.

[0059] In response to the coded signal being 1011, the driver board sets the first drive signal to 1 and the second drive signal to 01, and determines the duration of the 0 in the second drive signal based on the second signal switching duration. That is, the first drive signal remains at a high level of 1 during the first signal switching duration. When the duration of the 0 in the second drive signal reaches the second signal switching duration, the signal switches to 1 at the next instant. At this point, the first signal switching duration equals the duration of the interruption period.

[0060] In response to the coding signal being 0011, the first drive signal being 01 and the second drive signal being 01, the driver board determines the duration of the 0 in the first drive signal based on the first signal switching duration, and determines the duration of the 0 in the second drive signal based on the second signal switching duration. That is, when the duration of the 0 in the first drive signal reaches the first signal switching duration, the signal is switched to 1 at the next moment. When the duration of the 0 in the second drive signal reaches the second signal switching duration, the signal is switched to 1 at the next moment.

[0061] In response to the coded signal being 0111, the driver board generates a first drive signal of 01 and a second drive signal of 11, and determines the duration of the 0 in the first drive signal based on the first signal switching duration. That is, when the duration of the 0 in the first drive signal reaches the first signal switching duration, the signal is switched to 1 at the next moment. The second drive signal remains at a high level of 1 during the first signal switching duration. At this point, the second signal switching duration equals the duration of the interruption period.

[0062] In response to the coded signal being 1110, the first drive signal being 11, and the second drive signal being 10, the driver board determines the duration of the signal 1 in the second drive signal based on the second signal switching duration. That is, the first drive signal remains at a high level of 1 during the first signal switching duration. When the duration of the 1 in the second drive signal reaches the second signal switching duration, it switches to 0 at the next instant. At this point, the first signal switching duration equals the duration of the interruption period.

[0063] In this embodiment, a modulation wave, a first triangular carrier wave corresponding to the upper left tube in the H-bridge, and a second triangular carrier wave corresponding to the upper right tube in the H-bridge are received; a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube are obtained according to the modulation wave, the first triangular carrier wave, and the second triangular carrier wave; the first drive signal and the second drive signal are encoded to obtain an encoded signal; and the encoded signal is sent to the driver board at intervals of the interruption frequency so that the driver board decodes the encoded signal to obtain the first drive signal and the second drive signal. Cycle-by-cycle encoding of the drive signal can not only ensure short-term protection of the frequency converter, but also accurately transmit the drive signal, thereby ensuring use on low-speed optical fibers and ensuring the realization of synchronous wave transmission, thereby ensuring that the drive signal is uniformly characterized, thereby driving the motor to operate.

[0064] See Figure 8 , Figure 8 FIG1 is a schematic diagram of the structure of an embodiment of a frequency converter provided by the present application. The frequency converter 100 includes: a signal processing chip 10 , a main control chip 20 and a driver board 30 .

[0065] The signal processing chip 10 generates a modulated wave. In some embodiments, the signal processing chip 10 may be a DSP chip or a related chip based on FPGA.

[0066] The main control chip 20 is coupled to the signal processing chip 10, receives the modulation wave, and generates a first triangular carrier wave corresponding to the upper left tube of the H-bridge and a second triangular carrier wave corresponding to the upper right tube of the H-bridge. The main control chip 20 obtains a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube based on the modulation wave, the first triangular carrier wave, and the second triangular carrier wave. The main control chip 20 encodes the first drive signal and the second drive signal to obtain a coded signal. The coded signal is sent to the driver board 30 at intervals of the interrupt frequency.

[0067] The driving board 30 is coupled to the main control chip 20 , receives the coded signal, decodes the coded signal, and obtains a first driving signal and a second driving signal.

[0068] In some embodiments, the driving board 30 and the main control chip 20 are connected via an optical fiber.

[0069] In some embodiments, the main control chip 20 obtains the first drive signal corresponding to the upper left tube, the second drive signal corresponding to the upper right tube, the first signal switching duration corresponding to the first drive signal, and the second signal switching duration corresponding to the second drive signal within each interrupt frequency according to the modulation wave, the first triangular carrier and the second triangular carrier.

[0070] In some embodiments, the signal processing chip 10, the main control chip 20, and the driver board 30 cooperate with each other to implement the method of any of the above embodiments. That is, the main control chip 20 can implement the above encoding-related technologies, and the driver board 30 can implement the above decoding-related technologies.

[0071] The frequency converter mentioned above can be a high-frequency transformer or a low-frequency transformer or any other known type of transformer.

[0072] In one application scenario, the three-way modulated wave signal processed by the algorithm is sent to the main control FPGA (main control chip 20) through the main control board DSP (signal processing chip 10). After receiving the modulated wave data, the main control FPGA performs subsequent processing.

[0073] In the main controller, the modulation wave sent by the DSP is latched and compared with the triangular carrier in the main controller. The switching state of the drive signal is encoded, and the drive opening time is characterized by two time scales TIME1 and TIME2, and then sent down through synchronous communication.

[0074] The encoded driving signal is sent to the unit through a synchronous communication mechanism, and then latched and analyzed in time, and the driving signal is sent to the power driving board (driving board 30) for wave processing.

[0075] During this process, a relatively low-speed optical fiber can be used to connect the driver board 30 and the main control chip 20 to reduce hardware costs.

[0076] In summary, after receiving the modulated wave and comparing it with the dualized triangular carrier wave, the main control chip 20 performs calculations using an internal fixed algorithm, encodes the drive signal, and then transmits it at intervals of the interrupt frequency. This is also the key to the synchronization strategy, as it is equivalent to aligning the drive once every interrupt cycle, greatly eliminating errors caused by clock drift. At the same time, after encoding the 4-bit data sampled by the drive signal, the drive analysis module (driver board 30) can theoretically restore the drive signal without error. In addition, as the number of encoding bits increases, it can be easily expanded to the transmission of three-level drives. This strategy has strong universal applicability.

[0077] See Figure 9 , Figure 9 1 is a schematic diagram of the structure of an embodiment of a computer-readable storage medium provided by the present application. The computer-readable storage medium 90 is used to store a computer program 91. When the computer program 91 is executed by a processor, it is used to implement the following method:

[0078] Receive a modulated wave, a first triangular carrier wave corresponding to the upper left tube in the H-bridge, and a second triangular carrier wave corresponding to the upper right tube in the H-bridge; obtain a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulated wave, the first triangular carrier wave, and the second triangular carrier wave; encode the first drive signal and the second drive signal to obtain a coded signal; and send the coded signal to a driver board according to interval points of the interrupt frequency, so that the driver board decodes the coded signal to obtain the first drive signal and the second drive signal.

[0079] In some embodiments, when the computer program 91 is executed by a processor, it is also used to implement the method of any of the above embodiments.

[0080] The processor of this embodiment is equivalent to the main control chip 20 mentioned above.

[0081] In summary, the frequency converter 100 and its drive signal processing method, and computer-readable storage medium 90 provided in the present application receive a modulated wave, a first triangular carrier corresponding to the upper left tube in the H-bridge, and a second triangular carrier corresponding to the upper right tube in the H-bridge; obtain a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulated wave, the first triangular carrier, and the second triangular carrier; encode the first drive signal and the second drive signal to obtain a coded signal; and send the coded signal to the driver board 30 according to the interval point of the interruption frequency so that the driver board 30 decodes the coded signal to obtain the first drive signal and the second drive signal. The cycle-by-cycle encoding of the drive signal can not only ensure the protection of the frequency converter in a short time, but also accurately send the drive signal, thereby ensuring its use on low-speed optical fiber, and ensuring the realization of synchronous wave transmission, thereby ensuring that the drive signal is characterized without distinction, thereby driving the motor to operate.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0083] If the integrated units in the other embodiments described above are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processing circuit component (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code.

[0084] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for processing a drive signal of a frequency converter, characterized in that: The driving signal processing method includes: Receive the modulated wave, the first triangular carrier wave corresponding to the upper left tube in the H-bridge, and the second triangular carrier wave corresponding to the upper right tube in the H-bridge; Obtaining a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube according to the modulated wave, the first triangular carrier wave, and the second triangular carrier wave; encoding the first drive signal and the second drive signal to obtain a coded signal; sending the coded signal to the driving board at intervals of the interruption frequency, so that the driving board decodes the coded signal to obtain the first driving signal and the second driving signal; The encoding of the first drive signal and the second drive signal to obtain a coded signal includes: using the first signal value in the first driving signal as the first bit in the coded signal; using a first signal value in the second drive signal as a second bit in the coded signal; using the second signal value in the first drive signal as the third bit in the coded signal; The second signal value in the second driving signal is used as the fourth bit in the coded signal, thereby obtaining a 4-bit coded signal.

2. The driving signal processing method according to claim 1, wherein: The obtaining, according to the modulated wave, the first triangular carrier wave, and the second triangular carrier wave, of a first driving signal corresponding to the upper left tube and a second driving signal corresponding to the upper right tube includes: Within each of the interrupt frequencies, a first drive signal corresponding to the upper left tube, a second drive signal corresponding to the upper right tube, a first signal switching duration corresponding to the first drive signal, and a second signal switching duration corresponding to the second drive signal are obtained based on the modulated wave, the first triangular carrier, and the second triangular carrier.

3. The driving signal processing method according to claim 2, wherein: The method of sending the coded signal to the driver board at intervals of the interruption frequency so that the driver board decodes the coded signal to obtain the first drive signal and the second drive signal comprises: The coded signal, the first signal switching duration, and the second signal switching duration are sent to the driving board according to the interval points of the interruption frequency, so that the driving board decodes the coded signal according to the first signal switching duration and the second signal switching duration to obtain the first driving signal and the second driving signal.

4. The driving signal processing method according to claim 1, wherein: The driving board decodes the coded signal, including: using the first bit of the coded signal as the first signal value of the first drive signal; and using the third bit of the coded signal as the second signal value of the first drive signal to obtain the first drive signal; The second bit of the coded signal is used as the first signal value of the second drive signal; the fourth bit of the coded signal is used as the second signal value of the second drive signal, to obtain the second drive signal.

5. The driving signal processing method according to claim 1, wherein: After receiving the modulated wave, the method includes: latching the modulated wave.

6. A frequency converter, characterized in that: The frequency converter comprises: Signal processing chip, generating modulation wave; A main control chip is coupled to the signal processing chip, receives the modulated wave, and generates a first triangular carrier wave corresponding to the upper left tube in the H-bridge and a second triangular carrier wave corresponding to the upper right tube in the H-bridge; obtains a first drive signal corresponding to the upper left tube and a second drive signal corresponding to the upper right tube based on the modulated wave, the first triangular carrier wave, and the second triangular carrier wave; encodes the first drive signal and the second drive signal to obtain a coded signal; and transmits the coded signal to the driver board at intervals of the interrupt frequency; a driving board, coupled to the main control chip, receiving the coded signal, decoding the coded signal, and obtaining the first driving signal and the second driving signal; The main control chip encodes the first drive signal and the second drive signal to obtain an encoded signal, including: using the first signal value in the first driving signal as the first bit in the coded signal; using a first signal value in the second drive signal as a second bit in the coded signal; using the second signal value in the first drive signal as the third bit in the coded signal; The second signal value in the second driving signal is used as the fourth bit in the coded signal, thereby obtaining a 4-bit coded signal.

7. The frequency converter according to claim 6, characterized in that: The driving board and the main control chip are connected via optical fibers.

8. The frequency converter according to claim 6, characterized in that: The main control chip obtains, within each of the interrupt frequencies, a first drive signal corresponding to the upper left tube, a second drive signal corresponding to the upper right tube, a first signal switching duration corresponding to the first drive signal, and a second signal switching duration corresponding to the second drive signal according to the modulated wave, the first triangular carrier, and the second triangular carrier.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, it is used to implement the method according to any one of claims 1 to 5.

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