Pre-amplifier circuit applied to sensor chip

Abstract

The invention discloses a pre-amplifier circuit applied to a sensor chip, and the pre-amplifier circuit comprises an amplifier main body circuit which is of a differential symmetric design structure and is used for realizing low offset voltage by using an NPN type triode as an input tube of the pre-amplifier circuit, meanwhile, stable gain output of the pre-amplifier circuit is realized through a feedback loop arranged in the circuit; and the common-mode feedback circuit is used for raising the output common-mode level of the amplifier main body circuit by utilizing an emitter follower structure of the NPN type triode and eliminating the influence of the base current of the NPN type triode on the output common-mode level by utilizing the base compensation current. According to the invention, an NPN type triode is used as an input tube of the amplifier to realize low offset voltage, relatively few circuit devices are adopted to further realize low noise performance, a feedback loop is arranged in the circuit to realize gain stability of the pre-amplifier, and a common-mode feedback circuit is used to stably output common-mode level.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design in sensors, and in particular to a pre-amplifier circuit applied to a sensor chip. Background Art

[0002] In sensor chip applications, the physical quantity obtained by the sensing device needs to be amplified by a pre-amplifier circuit before it can be further applied to subsequent signal processing. The gain stability, offset and noise of the pre-amplifier will directly affect the signal quality of the subsequent transmission of the sensor.

[0003] The prior art preamplifier circuit generally adopts a low-gain, high-linearity open-loop differential output amplifier. However, the prior art preamplifier circuit has problems such as unstable gain, large gain error, and failure to ensure the stability of the amplifier differential output common-mode level.

[0004] In view of this, this application is hereby filed. Summary of the invention

[0005] The technical problem to be solved by the present invention is that the pre-amplifier circuit of the prior art has unstable gain, large gain error, and cannot ensure the stability of the common-mode level of the amplifier differential output. The purpose of the present invention is to provide a pre-amplifier circuit applied to a sensor chip. The present invention combines the amplifier main circuit and the common-mode feedback circuit to achieve stable gain output, and the output gain error is small; specifically, an NPN-type triode is used as the input tube of the amplifier to achieve low offset voltage, and relatively few circuit components are used to further achieve low noise performance. At the same time, a feedback loop is provided inside the circuit to achieve the gain stability of the pre-amplifier and stabilize the output common-mode level through the common-mode feedback circuit.

[0006] The present invention is achieved through the following technical solutions:

[0007] A pre-amplifier circuit applied to a sensor chip, the pre-amplifier circuit comprising:

[0008] The amplifier main circuit is a differential symmetrical design structure, which is used to use an NPN transistor as an input tube of the pre-amplifier circuit to achieve a low offset voltage, and at the same time achieve a gain-stable output of the pre-amplifier circuit through a feedback loop provided inside the circuit;

[0009] The common-mode feedback circuit is used to raise the output common-mode level of the amplifier main circuit by using the emitter follower structure of the NPN transistor, and to eliminate the influence of the base current of the NPN transistor on the output common-mode level by using the base compensation current.

[0010] Further, the main circuit of the amplifier includes a transistor Q1, a transistor Q2, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and three current sources;

[0011] The base of the transistor Q1 is connected to the amplifier non-inverting input terminal inp, the collector of the transistor Q1 is connected to the gate of the MOS tube M1, the emitter of the transistor Q1 is connected to the resistor R1, the emitter of the transistor Q1 is also connected to the resistor R2, the resistor R2 is connected to the drain of the MOS tube M1, and the source of the MOS tube M1 is connected to the power supply VDD;

[0012] The base of the transistor Q2 is connected to the inverting input terminal inn of the amplifier, the collector of the transistor Q2 is connected to the gate of the MOS tube M2, the emitter of the transistor Q2 is connected to the resistor R3, the emitter of the transistor Q2 is also connected to the resistor R4, the resistor R4 is connected to the drain of the MOS tube M2, and the source of the MOS tube M2 is connected to the power supply VDD;

[0013] The drain of the MOS tube M1 and the common end of the resistor R2 are connected to the resistor R5, the resistor R5 is connected to the resistor R6, the resistor R6 is connected to the drain of the MOS tube M2 and the common end of the resistor R4, and the difference between the voltage at the common end of the drain of the MOS tube M1 and the resistor R2 and the voltage at the common end of the drain of the MOS tube M2 and the resistor R4 is used as the differential output of the pre-amplifier circuit; the common end of the resistor R5 and the resistor R6 is recorded as the node VCM2;

[0014] The drain of the MOS tube M3 is connected to the common end of the resistor R1 and the resistor R3, the source of the MOS tube M3 is grounded, and the gate of the MOS tube M3 is recorded as a node VFB;

[0015] The current source I1 is connected to the collector of the transistor Q1 and the gate of the MOS transistor M1, the current source I2 is connected to the collector of the transistor Q2 and the gate of the MOS transistor M2, and the current source I1 and the current source I2 are connected to the power supply VDD; the current source I3 is connected to the source of the MOS transistor M3, and the resistors R1, R3, the current source I3 and the drain of the MOS transistor M3 are connected to the node VS.

[0016] Furthermore, transistor Q1 and transistor Q2 are both NPN transistors;

[0017] The MOS tube M1 and the MOS tube M2 are both PMOS tubes; the MOS tube M3 is an NMOS tube.

[0018] Furthermore, the transistor Q1 and the transistor Q2 have the same size and are both used as input transistors of the pre-amplifier circuit;

[0019] The current sources I1 and I2 have the same magnitude.

[0020] Furthermore, the resistance values ​​of the resistor R1 and the resistor R3 are equal, and the resistance values ​​of the resistor R2 and the resistor R4 are equal.

[0021] Furthermore, the gain expression of the pre-amplifier circuit is:

[0022] Av=1+R2 / R1

[0023] Wherein, Av is the gain of the entire pre-amplifier circuit, R2 is the resistance value of resistor R2, and R1 is the resistance value of resistor R1.

[0024] Furthermore, the common-mode feedback circuit includes an operational amplifier OP, a transistor Q3, a transistor Q4, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a capacitor C1 and two current sources;

[0025] The base of the transistor Q3 is connected to the node VCM2 of the amplifier main circuit, the base of the transistor Q3 is also connected to the drain of the MOS transistor M4, the collector of the transistor Q3 is connected to the power supply VDD, and the emitter of the transistor Q3 is connected to the inverting input terminal of the operational amplifier OP; the source of the MOS transistor M4 is connected to the power supply VDD, the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M5, the source of the MOS transistor M5 is connected to the power supply VDD, the drain of the MOS transistor M5 is connected to the drain of the MOS transistor M6, and the drain of the MOS transistor M5 is also connected to the gate of the MOS transistor M5; the gate of the MOS transistor M6 is connected to the collector of the transistor Q4, the source of the MOS transistor M6 is connected to the base of the transistor Q4, and the emitter of the transistor Q4 is grounded;

[0026] The non-inverting input terminal of the operational amplifier OP is connected to an external voltage signal as a reference; the output terminal of the operational amplifier OP is connected to a capacitor C1, the capacitor C1 is grounded, and the output terminal of the operational amplifier OP is recorded as a node VFB;

[0027] The emitter of the transistor Q3 and the current source I4 are connected to the inverting input terminal of the operational amplifier OP, and the emitter of the transistor Q4 and the current source I4 are connected to the ground; the gate of the MOS tube M6 and the current source I5 are connected to the collector of the transistor Q4, and the collector of the transistor Q3, the source terminal of the MOS tube M4, the source terminal of the MOS tube M5 and the current source I5 are all connected to the power supply VDD.

[0028] Furthermore, transistor Q3 and transistor Q4 are both NPN transistors;

[0029] The MOS tube M4 and the MOS tube M5 are both PMOS tubes; the MOS tube M6 is an NMOS tube.

[0030] Furthermore, the current ratio of the current source I4 to the current source I5 is consistent with the width-to-length ratio of the MOS transistor M4 to the MOS transistor M5.

[0031] Furthermore, the expression of the output common-mode level of the pre-amplifier circuit is:

[0032] VCM2=(Voutp+Voutn) / 2=VCM1+VBE3

[0033] Wherein, VCM2 is the output common-mode level of the entire pre-amplifier circuit, Voutp is the in-phase output voltage of the pre-amplifier circuit, Voutn is the inverting output voltage of the pre-amplifier circuit, VCM1 is the external reference voltage, and VBE3 is the voltage difference between the base and emitter of transistor Q3.

[0034] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0035] 1. The present invention discloses a pre-amplifier circuit for a sensor chip. The present invention combines an amplifier main circuit and a common-mode feedback circuit to achieve a stable gain output, and the output gain error is small. Specifically, an NPN transistor is used as an input tube of the amplifier to achieve a low offset voltage, and relatively few circuit components are used to further achieve low noise performance. At the same time, a feedback loop is provided inside the circuit to achieve the gain stability of the pre-amplifier and to stabilize the output common-mode level through a common-mode feedback circuit.

[0036] 2. The gain of the preamplifier in the present invention is only related to the resistance ratio (the ratio of the resistance value of resistor R2 to the resistance value of resistor R1), and the gain is stable and the error is small;

[0037] 3. The present invention adopts NPN tube as input tube, the internal feedback loop gain is high and uses fewer devices, and the circuit has low offset and low noise performance;

[0038] 4. The pre-amplifier circuit of the present invention contains common-mode feedback to ensure the stability of the common-mode level of the amplifier differential output, and to ensure the working conditions of the subsequent circuit using NPN as the input tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0040] Figure 1 The present invention is a schematic diagram of a pre-amplifier circuit applied to a sensor chip. DETAILED DESCRIPTION

[0041] Hereinafter, the term "include" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present invention, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0042] In various embodiments of the present invention, the expression "or" or "at least one of A or / and B" includes any combination or all combinations of the words listed at the same time. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0043] The expressions (such as "first", "second", etc.) used in various embodiments of the present invention may modify the various constituent elements in various embodiments, but may not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used for the purpose of distinguishing an element from other elements. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, without departing from the scope of various embodiments of the present invention, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0044] It should be noted that if it is described that one component element is “connected” to another component element, the first component element may be directly connected to the second component element, and a third component element may be “connected” between the first component element and the second component element. Conversely, when one component element is “directly connected” to another component element, it can be understood that there is no third component element between the first component element and the second component element.

[0045] The terms used in various embodiments of the present invention are only used for the purpose of describing specific embodiments and are not intended to limit various embodiments of the present invention. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise limited, all terms used here (including technical terms and scientific terms) have the same meaning as the meaning generally understood by those of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as the terms defined in the dictionary generally used) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in various embodiments of the present invention.

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0047] In sensor chip applications, the physical signal output by the sensing device is relatively weak and needs to be amplified and processed by the analog front-end circuit before it can be used. The pre-amplifier circuit is the first amplifier circuit that contacts the sensing device.

[0048] In high-precision sensor chip applications, the pre-amplifier circuit in the analog front-end module needs to meet design requirements such as low gain error, low offset and low noise to ensure the overall performance of the system.

[0049] Therefore, the present invention combines the amplifier main circuit and the common-mode feedback circuit to achieve gain-stable output with a small output gain error; specifically, an NPN-type triode is used as the input tube of the amplifier to achieve low offset voltage, and relatively few circuit components are used to further achieve low noise performance. At the same time, a feedback loop is provided inside the circuit to achieve gain stability of the pre-amplifier and stabilize the output common-mode level through the common-mode feedback circuit.

[0050] Example 1

[0051] like Figure 1 As shown, Figure 1 The schematic diagram of the pre-amplifier circuit of the present invention is as follows; the pre-amplifier circuit of the present invention is applied to a sensor chip, and the pre-amplifier circuit includes an amplifier main circuit and a common-mode feedback circuit:

[0052] The main circuit of the amplifier is a differential symmetrical design structure, which is used to use NPN transistors as input tubes of the pre-amplifier circuit to achieve low offset voltage, and at the same time, the gain stable output of the pre-amplifier circuit is achieved through the feedback loop provided inside the circuit;

[0053] The common-mode feedback circuit is used to raise the output common-mode level of the amplifier main circuit by using the emitter follower structure of the NPN transistor, and to eliminate the influence of the base current of the NPN transistor on the output common-mode level by using the base compensation current.

[0054] The main amplifier circuit includes transistors Q1, Q2, MOS tubes M1, M2, MOS tube M3, current sources I1, I2, I3, and resistors R1-R6; the common-mode feedback circuit includes an operational amplifier OP, transistors Q3, Q4, MOS tubes M4, M5, MOS tube M6, current sources I4, I5, and capacitor C1. The main amplifier circuit and the common-mode feedback circuit are connected through nodes VCM2 and VFB.

[0055] In a specific implementation, transistors Q1 and Q2 are both NPN transistors; MOS transistors M1 and M2 are both PMOS transistors; MOS transistor M3 is an NMOS transistor; transistors Q3 and Q4 are both NPN transistors; MOS transistors M4 and M5 are both PMOS transistors; and MOS transistor M6 is an NMOS transistor.

[0056] In this embodiment, the main circuit of the amplifier includes a transistor Q1, a transistor Q2, a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and three current sources;

[0057] The base of the transistor Q1 is connected to the amplifier non-inverting input terminal inp, the collector of the transistor Q1 is connected to the gate of the MOS tube M1, the emitter of the transistor Q1 is connected to the resistor R1, the emitter of the transistor Q1 is also connected to the resistor R2, the resistor R2 is connected to the drain of the MOS tube M1, and the source of the MOS tube M1 is connected to the power supply VDD;

[0058] The base of the transistor Q2 is connected to the inverting input terminal inn of the amplifier, the collector of the transistor Q2 is connected to the gate of the MOS tube M2, the emitter of the transistor Q2 is connected to the resistor R3, the emitter of the transistor Q2 is also connected to the resistor R4, the resistor R4 is connected to the drain of the MOS tube M2, and the source of the MOS tube M2 is connected to the power supply VDD;

[0059] The drain of the MOS tube M1 and the common end of the resistor R2 are connected to the resistor R5, the resistor R5 is connected to the resistor R6, the resistor R6 is connected to the drain of the MOS tube M2 and the common end of the resistor R4, and the difference between the voltage at the common end of the drain of the MOS tube M1 and the resistor R2 and the voltage at the common end of the drain of the MOS tube M2 and the resistor R4 is used as the differential output of the pre-amplifier circuit; the common end of the resistor R5 and the resistor R6 is recorded as the node VCM2;

[0060] The drain of the MOS tube M3 is connected to the common end of the resistor R1 and the resistor R3, the source of the MOS tube M3 is grounded, and the gate of the MOS tube M3 is recorded as a node VFB;

[0061] The current source I1 is connected to the collector of the transistor Q1 and the gate of the MOS transistor M1, the current source I2 is connected to the collector of the transistor Q2 and the gate of the MOS transistor M2, and the current source I1 and the current source I2 are connected to the power supply VDD; the current source I3 is connected to the source of the MOS transistor M3, and the resistors R1, R3, the current source I3 and the drain of the MOS transistor M3 are connected to the node VS.

[0062] In summary, for the main circuit of the amplifier, the base of the transistor Q1 is connected to the amplifier's in-phase input terminal inp, and the base of the transistor Q2 is connected to the amplifier's inverting input terminal inn; the emitter of the transistor Q1 is connected to the resistors R1 and R2 at the node VE1, the collector of the transistor Q1 is connected to the current source I1 and the gate of the MOS tube M1 at the node VC1, the emitter of the transistor Q2 is connected to the resistors R3 and R4 at the node VE2, and the collector of the transistor Q2 is connected to the current source I2 and the gate of the MOS tube M2 at the node VC 2; resistors R1, R3 and current source I3, the drain of MOS tube M3 is connected to node VS; the drain of MOS tube M1 and resistors R2, R5 are connected to the amplifier in-phase output end outp, the drain of MOS tube M2 and resistors R4, R6 are connected to the amplifier inverting output end outn; resistor R5 and resistor R6 are connected to node VCM2; the source of MOS tube M1 and the source of MOS tube M2, current source I1 and current source I2 are connected to VDD; the source of MOS tube M3 and current source I3 are connected to GND.

[0063] Specifically, the transistor Q1 and the transistor Q2 have the same size and are input transistors of the pre-amplifier circuit. Compared with the MOS input transistor, they can provide a smaller offset voltage; the current source I1 and the current source I2 have the same size, so the VBE voltages of the transistor Q1 and the transistor Q2 remain consistent, and the change in the in-phase input terminal inp can be equivalently reflected on the node VE1, and the change in the inverting input terminal inn can be equivalently reflected on the node VE2; the level change of the nodes VE1 and VE2 causes the current flowing through the resistor R1 and the resistor R3 to change, and the changed current can only be provided by the MOS tube M1 and the MOS tube M2, and the currents on both sides flow through the resistor R2 and the resistor R4 respectively, and the voltage changes generated by them affect the voltages of the nodes outp and outn.

[0064] In the main circuit of the amplifier, the resistance values ​​of resistors R1 and R3 are equal, and the resistance values ​​of resistors R2 and R4 are equal. The above change process can be expressed as:

[0065] [(Voutp-Voutn)-(Vinp-Vinn)] / R2=(Vinp-Vinn) / R1 (1)

[0066] In the formula, the voltage difference between Voutp and Voutn is the output voltage, the voltage difference between Vinp and Vinn is the input voltage, R2 is the resistance value of the resistor R2, and R1 is the resistance value of the resistor R1.

[0067] The present invention outputs a differential amplified signal through an amplifier main circuit, so that (Voutp-Voutn) and (Vinp-Vinn) are in a linear amplification relationship, and the output gain is stable.

[0068] The gain expression of the preamplifier circuit is:

[0069] Av=1+R2 / R1 (2)

[0070] Wherein, Av is the gain of the entire pre-amplifier circuit, R2 is the resistance value of resistor R2, and R1 is the resistance value of resistor R1.

[0071] In the above technical solution, two groups of feedback loops consisting of transistor Q1, resistor R2, MOS tube M1 and transistor Q2, resistor R4, MOS tube M2 enable the currents of MOS tube M1 and MOS tube M2 to be quickly adjusted through their gate voltages, and a higher loop gain is achieved with a minimum of devices, thereby reducing the noise source and ensuring the accuracy of the pre-amplifier gain. Since the gain size is mainly related to the ratio of the two resistors, the pre-amplifier gain also has high stability, and the calculated gain error is small.

[0072] It should be noted that the resistor R5 and the resistor R6 are related to the common-mode feedback of the subsequent common-mode feedback circuit.

[0073] In this embodiment, the common-mode feedback circuit includes an operational amplifier OP, a transistor Q3, a transistor Q4, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a capacitor C1 and two current sources;

[0074] The base of the transistor Q3 is connected to the node VCM2 of the amplifier main circuit, the base of the transistor Q3 is also connected to the drain of the MOS transistor M4, the collector of the transistor Q3 is connected to the power supply VDD, and the emitter of the transistor Q3 is connected to the inverting input terminal of the operational amplifier OP; the source of the MOS transistor M4 is connected to the power supply VDD, the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M5, the source of the MOS transistor M5 is connected to the power supply VDD, the drain of the MOS transistor M5 is connected to the drain of the MOS transistor M6, and the drain of the MOS transistor M5 is also connected to the gate of the MOS transistor M5; the gate of the MOS transistor M6 is connected to the collector of the transistor Q4, the source of the MOS transistor M6 is connected to the base of the transistor Q4, and the emitter of the transistor Q4 is grounded;

[0075] The non-inverting input terminal of the operational amplifier OP is connected to an external voltage signal as a reference; the output terminal of the operational amplifier OP is connected to a capacitor C1, the capacitor C1 is grounded, and the output terminal of the operational amplifier OP is recorded as a node VFB;

[0076] The emitter of the transistor Q3 and the current source I4 are connected to the inverting input terminal of the operational amplifier OP, and the emitter of the transistor Q4 and the current source I4 are connected to the ground; the gate of the MOS tube M6 and the current source I5 are connected to the collector of the transistor Q4, and the collector of the transistor Q3, the source terminal of the MOS tube M4, the source terminal of the MOS tube M5 and the current source I5 are all connected to the power supply VDD.

[0077] In summary, for the common-mode feedback circuit, the base of transistor Q3 and the drain of MOS transistor M4 are connected to the node VCM2, the emitter of transistor Q3 and the current source I4 are connected to the inverting input of operational amplifier OP; the gate of MOS transistor M4 and the gate and drain of MOS transistor M5 are connected to the drain of MOS transistor M6, the source of MOS transistor M6 is connected to the base of transistor Q4, the gate of MOS transistor M6 and the current source I5 are connected to the collector of transistor Q4; the collector of transistor Q3 and the source of MOS transistor M4, the source of M5, and the current source I5 are connected to VDD, and the emitter of transistor Q4 and the current source I4 are connected to GND; the non-inverting input of operational amplifier OP is connected to the node VCM1, the output is connected to the node VFB, and the capacitor C1 is connected across the node VFB and GND.

[0078] Specifically, in the common-mode feedback circuit, the current ratio of the current source I4 to the current source I5 is consistent with the width-to-length ratio of the MOS tube M4 and the MOS tube M5. Since the current of the MOS tube M5 is equal to the base current of the transistor Q4, the current of the MOS tube M4 is also equal to the base current of the transistor Q3, and the base current compensation of the transistor Q3 is achieved, so that the transistor Q3 is prevented from drawing current from the outp and outn terminals, and generating a voltage difference through the resistor R5 and the resistor R6, thereby affecting the output common-mode level. Under the base compensation current technology, the node VCM2 is the output common-mode level detection point, and the gate voltage of the MOS tube M3 is adjusted through the transistor Q3 and the operational amplifier OP to adjust the tail current source of the amplifier main circuit, thereby achieving the maintenance of the output common-mode level.

[0079] The insertion of capacitor C1 ensures the stability of common-mode feedback. The expression of the output common-mode level of the pre-amplifier circuit is:

[0080] VCM2= (Voutp+Voutn) / 2=VCM1+VBE3 (3)

[0081] Wherein, VCM2 is the output common-mode level of the entire pre-amplifier circuit, Voutp is the in-phase output voltage of the pre-amplifier circuit, Voutn is the inverting output voltage of the pre-amplifier circuit, VCM1 is the external reference voltage, and VBE3 is the voltage difference between the base and emitter of transistor Q3.

[0082] In the above technical solution, the pre-amplifier circuit in the present invention includes the base-emitter voltage component of the NPN tube, which can be used to ensure that the emitter voltage of the NPN tube in the subsequent circuit using the NPN tube as input is VCM1.

[0083] The advantages of the present invention are as follows:

[0084] (1) The gain of the preamplifier in the present invention is only related to the resistance ratio (the ratio of the resistance value of resistor R2 to the resistance value of resistor R1), and the gain is stable and the error is small;

[0085] (2) Using NPN tube as input tube, the internal feedback loop gain is high and uses fewer components, and the circuit has low offset and low noise performance;

[0086] (3) The pre-amplifier circuit contains common-mode feedback to ensure the stability of the common-mode level of the amplifier differential output, which can ensure the working conditions of the subsequent circuit using NPN as the input tube.

[0087] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A pre-amplifier circuit applied to a sensor chip, characterized in that: The pre-amplifier circuit includes: The amplifier main circuit is a differential symmetrical design structure, which is used to use an NPN transistor as an input tube of the pre-amplifier circuit to achieve a low offset voltage, and at the same time achieve a gain-stabilized output of the pre-amplifier circuit through a feedback loop provided inside the circuit; The common mode feedback circuit is used to raise the output common mode level of the amplifier main circuit by using the emitter follower structure of the NPN transistor, and to eliminate the influence of the base current of the NPN transistor on the output common mode level by using the base compensation current.

2. A pre-amplifier circuit for a sensor chip according to claim 1, characterized in that: The amplifier main circuit includes a triode Q1, a triode Q2, a MOS tube M1, a MOS tube M2, a MOS tube M3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and three current sources; The base of the transistor Q1 is connected to the non-inverting input terminal of the amplifier, the collector of the transistor Q1 is connected to the gate of the MOS tube M1, the emitter of the transistor Q1 is connected to the resistor R1, the emitter of the transistor Q1 is also connected to the resistor R2, the resistor R2 is connected to the drain of the MOS tube M1, and the source of the MOS tube M1 is connected to the power supply VDD; The base of the transistor Q2 is connected to the inverting input terminal of the amplifier, the collector of the transistor Q2 is connected to the gate of the MOS tube M2, the emitter of the transistor Q2 is connected to the resistor R3, the emitter of the transistor Q2 is also connected to the resistor R4, the resistor R4 is connected to the drain of the MOS tube M2, and the source of the MOS tube M2 is connected to the power supply VDD; The common end of the drain of the MOS tube M1 and the resistor R2 is connected to the resistor R5, the resistor R5 is connected to the resistor R6, the resistor R6 is connected to the common end of the drain of the MOS tube M2 and the resistor R4, and the difference between the voltage at the common end of the drain of the MOS tube M1 and the resistor R2 and the voltage at the common end of the drain of the MOS tube M2 and the resistor R4 is used as the differential output of the pre-amplifier circuit; the common end of the resistor R5 and the resistor R6 is recorded as the node VCM2; The drain of the MOS tube M3 is connected to the common end of the resistor R1 and the resistor R3, the source of the MOS tube M3 is grounded, and the gate of the MOS tube M3 is recorded as a node VFB; The current source I1 is connected to the collector of the transistor Q1 and the gate of the MOS transistor M1, the current source I2 is connected to the collector of the transistor Q2 and the gate of the MOS transistor M2, and the current source I1 and the current source I2 are connected to the power supply VDD; the current source I3 is connected to the source of the MOS transistor M3, and the resistors R1, R3, the current source I3 and the drain of the MOS transistor M3 are connected to the node VS.

3. The pre-amplifier circuit for a sensor chip according to claim 2, characterized in that: The transistor Q1 and the transistor Q2 are both NPN transistors; The MOS tube M1 and the MOS tube M2 are both PMOS tubes; the MOS tube M3 is an NMOS tube.

4. The pre-amplifier circuit for a sensor chip according to claim 2, characterized in that: The transistor Q1 and the transistor Q2 have the same size and are both used as input tubes of the pre-amplifier circuit; The current sources I1 and I2 have the same magnitude.

5. The pre-amplifier circuit for a sensor chip according to claim 2, characterized in that: The resistance values ​​of the resistor R1 and the resistor R3 are equal, and the resistance values ​​of the resistor R2 and the resistor R4 are equal.

6. The pre-amplifier circuit for a sensor chip according to claim 5, characterized in that: The gain expression of the preamplifier circuit is: Av=1+R2 / R1 Wherein, Av is the gain of the entire pre-amplifier circuit, R2 is the resistance value of resistor R2, and R1 is the resistance value of resistor R1.

7. The pre-amplifier circuit for a sensor chip according to claim 1, characterized in that: The common-mode feedback circuit includes an operational amplifier OP, a transistor Q3, a transistor Q4, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a capacitor C1 and two current sources; The base of the transistor Q3 is connected to the node VCM2 of the amplifier main circuit, the base of the transistor Q3 is also connected to the drain of the MOS transistor M4, the collector of the transistor Q3 is connected to the power supply VDD, and the emitter of the transistor Q3 is connected to the inverting input terminal of the operational amplifier OP; the source of the MOS transistor M4 is connected to the power supply VDD, the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M5, the source of the MOS transistor M5 is connected to the power supply VDD, the drain of the MOS transistor M5 is connected to the drain of the MOS transistor M6, and the drain of the MOS transistor M5 is also connected to the gate of the MOS transistor M5; the gate of the MOS transistor M6 is connected to the collector of the transistor Q4, the source of the MOS transistor M6 is connected to the base of the transistor Q4, and the emitter of the transistor Q4 is grounded; The non-inverting input terminal of the operational amplifier OP is connected to an external voltage signal as a reference; the output terminal of the operational amplifier OP is connected to a capacitor C1, the capacitor C1 is grounded, and the output terminal of the operational amplifier OP is recorded as a node VFB; The emitter of the transistor Q3 and the current source I4 are connected to the reverse input terminal of the operational amplifier OP, and the emitter of the transistor Q4 and the current source I4 are connected to the ground; the gate of the MOS transistor M6 and the current source I5 are connected to the collector of the transistor Q4, and the collector of the transistor Q3, the source terminal of the MOS transistor M4, the source terminal of the MOS transistor M5 and the current source I5 are all connected to the power supply VDD.

8. The pre-amplifier circuit for a sensor chip according to claim 7, characterized in that: The transistor Q3 and the transistor Q4 are both NPN transistors; The MOS tube M4 and the MOS tube M5 are both PMOS tubes; the MOS tube M6 is an NMOS tube.

9. The pre-amplifier circuit for a sensor chip according to claim 7, characterized in that: The current ratio of the current source I4 to the current source I5 is consistent with the width-to-length ratio of the MOS transistor M4 to the MOS transistor M5.

10. The pre-amplifier circuit for a sensor chip according to claim 7, characterized in that: The expression of the output common-mode level of the preamplifier circuit is: VCM2=(Voutp+Voutn) / 2=VCM1+VBE3 Wherein, VCM2 is the output common-mode level of the entire pre-amplifier circuit, Voutp is the in-phase output voltage of the pre-amplifier circuit, Voutn is the inverting output voltage of the pre-amplifier circuit, VCM1 is the external reference voltage, and VBE3 is the voltage difference between the base and emitter of transistor Q3.

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