RST / EN circuit

Abstract

The invention belongs to the technical field of analog integrated circuits, and relates to an RST / EN circuit which comprises a hysteresis comparator and a pulse width detection circuit. The input end of the hysteresis comparator is connected with an RST / EN signal, the output end of the hysteresis comparator is connected with the input end of the pulse width detection circuit, and the output end of the pulse width detection circuit outputs the RST / ENOUT signal; wherein the RST / EN is reset / enable, and the RST / ENOUT is reset / enable output; the hysteresis comparator is high in anti-interference capability, the pulse width detection circuit can filter burrs, and the hysteresis comparator and the pulse width detection circuit are combined, so that RST / ENOUT signals output by the RST / EN circuit are good in integrity and high in quality, errors caused by noise or distortion are avoided, and the reliability of the RST / ENOUT signals is improved. Therefore, the anti-noise capability of the driving chip can be effectively improved, the influence of external interference is reduced, and the stability of the driving chip in a complex environment is enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits and relates to a RST / EN circuit. Background Art

[0002] When most driver chips detect overcurrent and short-circuit faults, they keep the output at a low level and report the fault signal to the DSP (digital signal processor) / MCU (microcontroller unit); after receiving the fault signal, the DSP / MCU sends a RST / EN signal to the driver chip; the driver chip can only be re-enabled after receiving the RST / EN signal sent from outside the chip, otherwise the driver chip is disabled by default.

[0003] The driver chip and DSP / MCU are generally arranged on a PCB board, but due to parasitic effects, the PCB board will generate high-frequency noise, so that the RST / EN signal is affected by the noise. Summary of the invention

[0004] In order to solve the above-mentioned problems in the prior art, the present invention adopts an RST / EN circuit, including: a hysteresis comparator and a pulse width detection circuit; the input end of the hysteresis comparator is connected to the RST / EN signal, and the output end is connected to the input end of the pulse width detection circuit, and the output end of the pulse width detection circuit outputs the RST / EN_OUT signal; wherein, RST / EN is reset / enable, and RST / EN_OUT is reset / enable output.

[0005] The RST / EN circuit also includes: a first resistor and a second resistor; the RST / EN signal is connected to the input end of the hysteresis comparator, including: the RST / EN signal is connected to one end of the first resistor, one end of the second resistor is grounded, and the other ends of the first resistor and the second resistor are connected to the input end of the hysteresis comparator.

[0006] The hysteresis comparator includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third resistor, a fourth resistor, a first Schmidt inverter, a first inverter, a second inverter and a bias circuit;

[0007] One end of the bias circuit is connected to the power supply VCC, and the other end is connected to the gates of the first PMOS tube and the eighth PMOS tube; the source of the first PMOS tube is connected to VCC through a third resistor, and the drain is connected to the source of the second PMOS tube and the third PMOS tube; the gate of the second PMOS tube is connected to the voltage of VCC after resistor voltage division, and the drain is connected to the source of the fourth PMOS tube and the sixth PMOS tube; the gate of the third PMOS tube is connected to the voltage of VCC after resistor voltage division, and the drain is connected to the source of the fifth PMOS tube and the seventh PMOS tube; the gate of the fourth PMOS tube is connected to the gate of the seventh PMOS tube, and is connected to the output end of the second inverter; the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, and is connected to the output end of the first inverter;

[0008] The drain of the fourth PMOS tube, the drain of the fifth PMOS tube, the drain of the tenth PMOS tube, the gate and drain of the first NMOS tube, the drain of the second NMOS tube, the gate of the third NMOS tube and the gate of the fifth NMOS tube are connected; the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, the drain of the ninth PMOS tube, the gate and drain of the fourth NMOS tube, the drain of the third NMOS tube, the gate of the second NMOS tube and the gate of the sixth NMOS tube are connected;

[0009] The source of the eighth PMOS tube is connected to VCC through the fourth resistor, and the drain is connected to the source of the ninth PMOS tube and the source of the tenth PMOS tube; the gate of the ninth PMOS tube is connected to the voltage of VCC after resistor voltage division, and the gate of the tenth PMOS tube is connected to the voltage of the RST / EN signal after resistor voltage division;

[0010] The source of the first NMOS tube, the source of the second NMOS tube, the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube, and the source of the sixth NMOS tube are grounded;

[0011] The drain and gate of the eleventh PMOS tube are connected to the gate of the twelfth PMOS tube, the drain of the eleventh PMOS tube is connected to the drain of the fifth NMOS tube; the source of the eleventh PMOS tube and the source of the twelfth PMOS tube are connected to VDD;

[0012] The drain of the twelfth PMOS tube and the drain of the sixth NMOS tube are connected to the input end of the first Schmitt inverter; the output end of the first Schmitt inverter is connected to the input end of the first inverter, and the output end of the first inverter is connected to the input end of the second inverter.

[0013] The pulse width detection circuit includes: a high-level and low-level pulse width detection circuit, a high-level pulse width detection circuit, a low-level pulse width detection circuit and an RS trigger; the input end of the high-level and low-level pulse width detection circuit is connected to the output end of the hysteresis comparator, the output end of the high-level and low-level pulse width detection circuit is connected to the input end of the high-level pulse width detection circuit and the low-level pulse width detection circuit, and the output end of the high-level pulse width detection circuit and the low-level pulse width detection circuit is connected to the input end of the RS trigger.

[0014] The high and low level pulse width detection circuit comprises: a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter;

[0015] The input end of the third inverter is connected to the output end of the second inverter, the output end of the third inverter is connected to the input end of the fourth inverter and the input end of the fifth inverter; the output end of the fourth inverter is connected to the input end of the sixth inverter; the output ends of the fourth inverter and the sixth inverter are connected to the low level pulse width detection circuit;

[0016] The output end of the third inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the seventh inverter, the output end of the seventh inverter is connected to the input end of the eighth inverter, and the output ends of the seventh inverter and the eighth inverter are connected to the low level pulse width detection circuit.

[0017] The high-level pulse width detection circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, a seventh NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first capacitor and a second Schmidt inverter;

[0018] One end of the fifth resistor is connected to the output end of the sixth inverter, and the other end is connected to one end of the sixth resistor, the drain of the tenth NMOS tube and the drain of the fourteenth PMOS tube; the other end of the sixth resistor is connected to the source of the tenth NMOS tube, the source of the fourteenth PMOS tube, the drain of the ninth NMOS tube, the drain of the thirteenth PMOS tube and one end of the seventh resistor; the other end of the seventh resistor is connected to the source of the ninth NMOS tube, the source of the thirteenth PMOS tube, the drain of the seventh NMOS tube, the upper plate of the first capacitor and the input end of the second Schmidt inverter; the gate of the seventh NMOS tube is connected to the output end of the fourth inverter, the source of the seventh NMOS tube is connected to the lower plate of the first capacitor, and is grounded; the output end of the second Schmidt inverter is connected to the input end of the RS trigger.

[0019] The low-level pulse width detection circuit includes: an eighth resistor, a ninth resistor, a tenth resistor, a second capacitor, a third Schmidt inverter, an eighth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube;

[0020] One end of the eighth resistor is connected to the output end of the eighth inverter, and the other end of the eighth resistor is connected to one end of the ninth resistor, the drain of the eleventh NMOS tube and the drain of the fifteenth PMOS tube; the other end of the ninth resistor is connected to the source of the eleventh NMOS tube, the source of the fifteenth PMOS tube, the drain of the twelfth NMOS tube, the drain of the sixteenth PMOS tube and one end of the tenth resistor; the other end of the tenth resistor is connected to the source of the twelfth NMOS tube, the source of the sixteenth PMOS tube, the drain of the eighth NMOS tube, the upper plate of the second capacitor and the input end of the third Schmidt inverter; the gate of the eighth NMOS tube is connected to the output end of the seventh inverter, the source of the eighth NMOS tube is connected to the lower plate of the second capacitor, and is grounded; the output end of the third Schmidt inverter is connected to the input end of the RS trigger.

[0021] The RS trigger includes: a first NAND gate and a second NAND gate; the input end of the first NAND gate is connected to the output end of the second NAND gate and the output end of the third Schmitt inverter, and the input end of the second NAND gate is connected to the output end of the first NAND gate and the output end of the second Schmitt inverter.

[0022] The pulse width detection circuit also includes a ninth inverter; the input end of the ninth inverter is connected to the output end of the second NAND gate, and the output end of the ninth inverter outputs a RST / EN_OUT signal.

[0023] Beneficial effects:

[0024] 1. The hysteresis comparator of the present invention has strong anti-interference ability, and the pulse width detection circuit can filter out burrs. Combining the hysteresis comparator and the pulse width detection circuit, the RST / EN_OUT signal output by the RST / EN circuit has good integrity and high quality, avoiding errors caused by noise or distortion, thereby effectively improving the anti-noise ability of the driver chip and reducing the influence of external interference; 2. The hysteresis comparator of the present invention adds a switch structure composed of a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, and a seventh PMOS tube, as well as a first inverter and a second inverter, and the second PMOS tube is connected to the hysteresis comparator. The gates of the MOS tube and the third PMOS tube are connected to the reference voltage, the gates of the fifth PMOS tube and the sixth PMOS tube are connected to the output of the first inverter, and the gates of the fourth PMOS tube and the seventh PMOS tube are connected to the output of the second inverter; the two currents I1 and I2 outputted from the drains of the second PMOS tube and the third PMOS tube and the currents I4 and I3 of the drains of the ninth PMOS tube and the tenth PMOS tube flow into a load of a cross-coupling structure composed of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube. The hysteresis amount of the hysteresis comparator is kept stable through the above structure, and has strong stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A top-level diagram of the RST / EN circuit provided by an embodiment of the present invention;

[0026] Figure 2 A circuit diagram of a hysteresis comparator provided by an embodiment of the present invention;

[0027] Figure 3 A pulse width detection circuit diagram provided by an embodiment of the present invention;

[0028] Figure 4 A schematic diagram of simulation results of a hysteresis comparator provided in an embodiment of the present invention;

[0029] Figure 5 A pulse width detection waveform diagram provided by an embodiment of the present invention;

[0030] Figure 6 This is a pulse width detection simulation diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] like Figure 1 As shown, this embodiment adopts a RST / EN circuit for a SiC MOSFET (silicon carbide metal oxide field effect transistor) drive circuit, which is mainly divided into two parts: a hysteresis comparator and a pulse width detection circuit; the RST / EN signal is connected to the input end of the hysteresis comparator after being divided by the first resistor and the second resistor, the output end of the hysteresis comparator is connected to the input end of the pulse width detection circuit, and the output end of the pulse width detection circuit outputs RST / EN_OUT; wherein, RST / EN is a reset / enable, and RST / EN_OUT is a reset / enable output signal.

[0033] The RST / EN signal is connected to the input end of the hysteresis comparator after being divided by a first resistor (R1) and a second resistor (R2), including: the RST / EN signal is connected to one end of the first resistor, one end of the second resistor is grounded, and the other ends of the first resistor and the second resistor are connected to the input end of the hysteresis comparator.

[0034] like Figure 2As shown, the hysteresis comparator includes: a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), an eighth PMOS tube (MP8), a ninth PMOS tube (MP9), a tenth PMOS tube (MP10), an eleventh PMOS tube (MP11), a twelfth PMOS tube (MP12), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3), a fourth NMOS tube (MN4), a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a third resistor (R2), a fourth resistor (R4), a first Schmidt inverter (SMTT1), a first inverter (INV1), a second inverter (INV2), and a bias circuit;

[0035] In one embodiment, the number of first PMOS tubes is 4, the number of eighth PMOS tubes is 8, the ratio of the number of fourth PMOS tubes to the number of fifth PMOS tubes is 1:1, the ratio of the number of sixth PMOS tubes to the number of seventh PMOS tubes is 1:1, the ratio of the number of eleventh PMOS tubes to the number of twelfth PMOS tubes is 1:2, and the ratio of the number of fifth NMOS tubes to the number of sixth NMOS tubes is 1:2.

[0036] One end of the bias circuit is connected to a power source VCC, and the other end is connected to the gates of the first PMOS tube and the eighth PMOS tube; the source of the first PMOS tube is connected to VCC through a third resistor, and the drain is connected to the source of the second PMOS tube and the third PMOS tube; the gate of the second PMOS tube is connected to the voltage of VCC after resistor voltage division, and the drain is connected to the source of the fourth PMOS tube and the sixth PMOS tube; the gate of the third PMOS tube is connected to the voltage of VCC after resistor voltage division, and the drain is connected to the source of the fifth PMOS tube and the seventh PMOS tube; the gate of the fourth PMOS tube is connected to the gate of the seventh PMOS tube, and connected to the output end (LB1) of the second inverter; the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, and connected to the output end (LD1) of the first inverter;

[0037] The drain of the fourth PMOS tube, the drain of the fifth PMOS tube, the drain of the tenth PMOS tube, the gate and drain of the first NMOS tube, the drain of the second NMOS tube, the gate of the third NMOS tube and the gate of the fifth NMOS tube are connected; the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, the drain of the ninth PMOS tube, the gate and drain of the fourth NMOS tube, the drain of the third NMOS tube, the gate of the second NMOS tube and the gate of the sixth NMOS tube are connected;

[0038] The source of the eighth PMOS tube is connected to VCC through the fourth resistor, and the drain is connected to the source of the ninth PMOS tube and the source of the tenth PMOS tube; the gate of the ninth PMOS tube is connected to the voltage of VCC after resistor voltage division, and the gate of the tenth PMOS tube is connected to the voltage of the RST / EN signal after resistor voltage division;

[0039] The source of the first NMOS tube, the source of the second NMOS tube, the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube, and the source of the sixth NMOS tube are grounded;

[0040] The drain and gate of the eleventh PMOS tube are connected to the gate of the twelfth PMOS tube, the drain of the eleventh PMOS tube is connected to the drain of the fifth NMOS tube; the source of the eleventh PMOS tube and the source of the twelfth PMOS tube are connected to the power supply VDD;

[0041] The drain of the twelfth PMOS tube and the drain of the sixth NMOS tube are connected to the input end of the first Schmitt inverter; the output end of the first Schmitt inverter is connected to the input end of the first inverter, and the output end of the first inverter is connected to the input end of the second inverter.

[0042] The voltages connected to the gates of the second PMOS tube, the third PMOS tube, and the ninth PMOS tube must ensure that the input common mode range of the hysteresis comparator is met when the input high level critical condition and the input low level critical condition are met.

[0043] Optimally, the gate of the second PMOS tube is connected to the voltage of VCC divided by resistors by 4 / 39, the gate of the third PMOS tube is connected to the voltage of VCC divided by resistors by 5 / 39, and the gate of the ninth PMOS tube is connected to the voltage of VCC divided by resistors by 4.5 / 39.

[0044] like Figure 3 As shown, the pulse width detection circuit includes: a high and low level pulse width detection circuit, a high level pulse width detection circuit, a low level pulse width detection circuit, an RS trigger and a ninth inverter;

[0045] The high and low level pulse width detection circuit comprises: a third inverter (INV3), a fourth inverter (INV4), a fifth inverter (INV5), a sixth inverter (INV6), a seventh inverter (INV7) and an eighth inverter (INV8); the high level pulse width detection circuit comprises: a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), a seventh NMOS tube (NM7), a ninth NMOS tube (NM9), a tenth NMOS tube (NM10), a thirteenth PMOS tube (PM13), a fourteenth PMOS tube (PM14), a The invention relates to a low-level pulse width detection circuit comprising: an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), a second capacitor (C2), a third Schmitt inverter (SMTT3), an eighth NMOS transistor (MN8), an eleventh NMOS transistor (MN11), a twelfth NMOS transistor (MN12), a fifteenth PMOS transistor (PM15) and a sixteenth PMOS transistor (PM16); and an RS trigger comprising: a first NAND gate (NAND1) and a second NAND gate (NAND2).

[0046] The input end of the third inverter is connected to the output end of the second inverter, and the output end of the third inverter is connected to the input end of the fourth inverter and the input end of the fifth inverter; the output end (LB2) of the fourth inverter is connected to the gate of the seventh NMOS tube and the input end of the sixth inverter; the output end (LB3) of the sixth inverter is connected to one end of the fifth resistor, which is the input of the high-level pulse width detection circuit; the output end of the third inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the seventh inverter, the output end (LB4) of the seventh inverter is connected to the gate of the eighth NMOS tube and the input end of the eighth inverter, and the output end (LB5) of the eighth inverter is connected to one end of the eighth resistor, which is the input of the low-level pulse width detection circuit.

[0047] One end of the fifth resistor is connected to the output end of the sixth inverter, and the other end is connected to one end of the sixth resistor, the drain of the tenth NMOS tube and the drain of the fourteenth PMOS tube; the other end of the sixth resistor is connected to the source of the tenth NMOS tube, the source of the fourteenth PMOS tube, the drain of the ninth NMOS tube, the drain of the thirteenth PMOS tube and one end of the seventh resistor; the other end of the seventh resistor is connected to the source of the ninth NMOS tube, the source of the thirteenth PMOS tube, the drain of the seventh NMOS tube, the upper plate of the first capacitor and the input end of the second Schmidt inverter; the gate of the seventh NMOS tube is connected to the output end of the fourth inverter, the source of the seventh NMOS tube is connected to the lower plate of the first capacitor, and is grounded; the output end of the second Schmidt inverter is connected to an input end of the second NAND gate of the RS trigger.

[0048] One end of the eighth resistor is connected to the output end of the eighth inverter, and the other end of the eighth resistor is connected to one end of the ninth resistor, the drain of the eleventh NMOS tube and the drain of the fifteenth PMOS tube; the other end of the ninth resistor is connected to the source of the eleventh NMOS tube, the source of the fifteenth PMOS tube, the drain of the twelfth NMOS tube, the drain of the sixteenth PMOS tube and one end of the tenth resistor; the other end of the tenth resistor is connected to the source of the twelfth NMOS tube, the source of the sixteenth PMOS tube, the drain of the eighth NMOS tube, the upper plate of the second capacitor and the input end of the third Schmidt inverter; the source of the eighth NMOS tube is connected to the lower plate of the second capacitor and is grounded; the output end of the third Schmidt inverter is connected to an input end of the first NAND gate of the RS trigger.

[0049] The gates of the ninth NMOS tube, the twelfth NMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are connected to VDD, and the gates of the tenth NMOS tube, the eleventh NMOS tube, the thirteenth PMOS tube and the sixteenth PMOS tube are connected to GND.

[0050] The output end of the first NAND gate is connected to the other input end of the second NAND gate, and the output end of the second NAND gate is connected to the other input end of the first NAND gate;

[0051] The output end of the RS trigger is connected to the input end of the ninth inverter, and the output end of the ninth inverter outputs the RST / EN_OUT signal.

[0052] When the RST / EN voltage signal, that is, the gate of the tenth PMOS changes from GND to VCC, the critical condition for the high level input of the hysteresis comparator is: the corresponding RST / EN voltage signal when the currents on the two branches a and b are equal (that is, I4-I3=I1-I2), at this time, the gate of the fifth PMOS, the gate of the sixth PMOS, and the output of the first inverter are flipped from a low level to a high level, the gate of the fourth PMOS, the gate of the seventh PMOS, and the output of the second inverter are flipped from a high level to a low level, that is, the fifth PMOS and the sixth PMOS are turned off, the fourth PMOS and the seventh PMOS are turned on, and the output of the hysteresis comparator is flipped from a high level to a low level.

[0053] When the RST / EN voltage signal, that is, the gate of the tenth PMOS changes from VCC to GND, the critical condition of the low level input of the hysteresis comparator is: the corresponding RST / EN voltage signal when the currents on the two branches a and b are equal (that is, I4-I3=I2-I1), at this time, the gate of the fifth PMOS, the gate of the sixth PMOS, and the output of the first inverter are flipped from high level to low level, the gate of the fourth PMOS, the gate of the seventh PMOS and the output of the second inverter are flipped from low level to high level, that is, the fifth PMOS and the sixth PMOS are turned on, the fourth PMOS and the seventh PMOS are turned off, and the output of the hysteresis comparator is flipped from low level to high level.

[0054] When the RST / EN voltage signal oscillates between the input high level critical condition and the input low level critical condition, the output of the hysteresis comparator will not change. The output will only change when the RST / EN voltage signal completely exceeds one of these two conditions. The difference between the voltages of the above input high level critical condition and the input low high level critical condition is the hysteresis voltage difference.

[0055] The traditional hysteresis comparator has only two inputs, including an input signal to be compared and a reference voltage. The hysteresis comparator of the present invention uses four inputs, including an RST / EN voltage signal to be compared and three reference voltages, and the input high level critical condition and the input low level critical condition are whether the currents on branches a and b are equal. Therefore, compared with the traditional hysteresis comparator, the hysteresis comparator of the present invention has better stability.

[0056] The theoretical derivation of the voltages for the input high level critical condition and the input low high level critical condition is as follows:

[0057]

[0058]

[0059] According to the above two formulas, V gs3 Solve the problem, and the values ​​after solving are the upper threshold voltage V INH and the lower threshold voltage V INL :

[0060]

[0061] V INHYS =V INH -V INL =340mV

[0062] Among them, I1, I2, and I4 are the currents of the second PMOS tube, the third PMOS tube, and the ninth PMOS tube respectively. 3(INH) ,I 3(INL)are the upper and lower threshold currents of the tenth PMOS tube, respectively. gs1 、V gs2 、V gs3 、V gs4 are the gate-source voltages of the second PMOS tube, the third PMOS tube, the tenth PMOS tube, and the ninth PMOS tube, respectively. B is the bias current, K1 and K4 are the process parameters of the second PMOS tube and the ninth PMOS tube respectively. μ p is the carrier mobility, C ox is the capacitance per unit area, is the aspect ratio, I SS is the tail current source, VCC 3.3V is the power supply voltage, V INHYS is the upper threshold voltage V INH and the lower threshold voltage V INL The difference is the hysteresis.

[0063] It can be known from the above theoretical derivation that the hysteresis amount of the hysteresis comparator of the present invention is theoretically 340mV.

[0064] like Figure 4 As shown, under five process corners and three temperatures, the upper threshold voltage V INH The lower threshold voltage V INL is 1.431V, and the hysteresis V INHYS It is 340mV~350mV, so the hysteresis comparator structure can remain stable within 10mV when the process corner and temperature change; among them, the five process corners include: typical corner (Typical, TT), fast NMOS / fast PMOS corner (Fast NMOS / Fast PMOS, FF), slow NMOS / slow PMOS corner (Slow NMOS / Slow PMOS, SS), slow NMOS / fast PMOS corner (SF), fast NMOS / slow PMOS corner (FS).

[0065] The pulse width detection circuit is mainly composed of a high- and low-level pulse width detection circuit, a high-level pulse width detection circuit, a low-level pulse width detection circuit and an RS trigger, and its filter pulse width TINFIL=ReqC; wherein, the seventh resistor of the high-level pulse width detection circuit is short-circuited by the transmission gate composed of the ninth NMOS and the thirteenth PMOS, then the equivalent resistance Req=R5+R6, and the size of the capacitor C is the first capacitance value; the tenth resistor of the low-level pulse width detection circuit is short-circuited by the transmission gate composed of the twelfth NMOS and the sixteenth PMOS, then the equivalent resistance Req=R8+R9, and the size of the capacitor C is the second capacitance value; the high-level pulse width detection signal LB6 and the low-level pulse width detection signal LB7 are respectively shaped by the second Schmidt inverter and the third Schmidt inverter, and then input into the SR trigger composed of the first NAND gate and the second NAND gate; the first input of the first NAND gate is set to be the R signal, the first input of the second NAND gate is set to be the S signal, and the output of the ninth inverter is set to be the Q signal, that is, RST / EN_OUT. According to the above analysis, four situations are obtained, such as Figure 5 As shown, S=0, R=1, Q=0 (high level is relatively wide), S=1, R=0, Q=1 (low level is relatively wide), 00 is indeterminate state (high and low level widths are both large), and 11 is maintained (initial state or high and low level widths are very small).

[0066] like Figure 6 As shown, the filter pulse width TINFIL=ReqC=50ns is set, tl is a pulse with a level width of 35ns, and tm is a pulse with a level width of 60ns; when the width of the low level of LB1 is lower than TINFIL, the Q signal is a high level; when the width of the high level of LB1 is lower than TINFIL, the Q signal is a low level; when the width of the high and low levels of LB1 are both lower than TINFIL, the state of the Q signal is maintained, and when the width of the high and low levels are both higher than TINFIL, the Q signal is in an indeterminate state.

[0067] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A RST / EN circuit, characterized in that: include: A hysteresis comparator and a pulse width detection circuit; the input end of the hysteresis comparator is connected to the RST / EN signal, and the output end is connected to the input end of the pulse width detection circuit, and the output end of the pulse width detection circuit outputs the RST / EN_OUT signal; wherein, RST / EN is reset / enable, and RST / EN_OUT is reset / enable output.

2. A RST / EN circuit according to claim 1, characterized in that: Also includes: a first resistor and a second resistor; The RST / EN signal is connected to the input end of the hysteresis comparator, including: the RST / EN signal is connected to one end of the first resistor, one end of the second resistor is grounded, and the other ends of the first resistor and the second resistor are connected to the input end of the hysteresis comparator.

3. The RST / EN circuit according to claim 1, characterized in that: The hysteresis comparator includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third resistor, a fourth resistor, a first Schmidt inverter, a first inverter, a second inverter and a bias circuit; One end of the bias circuit is connected to the power supply VCC, and the other end is connected to the gates of the first PMOS tube and the eighth PMOS tube; the source of the first PMOS tube is connected to VCC through a third resistor, and the drain is connected to the source of the second PMOS tube and the third PMOS tube; the gate of the second PMOS tube is connected to the voltage of VCC after resistor voltage division, and the drain is connected to the source of the fourth PMOS tube and the sixth PMOS tube; the gate of the third PMOS tube is connected to the voltage of VCC after resistor voltage division, and the drain is connected to the source of the fifth PMOS tube and the seventh PMOS tube; the gate of the fourth PMOS tube is connected to the gate of the seventh PMOS tube, and is connected to the output end of the second inverter; the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, and is connected to the output end of the first inverter; The drain of the fourth PMOS tube, the drain of the fifth PMOS tube, the drain of the tenth PMOS tube, the gate and drain of the first NMOS tube, the drain of the second NMOS tube, the gate of the third NMOS tube and the gate of the fifth NMOS tube are connected; the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, the drain of the ninth PMOS tube, the gate and drain of the fourth NMOS tube, the drain of the third NMOS tube, the gate of the second NMOS tube and the gate of the sixth NMOS tube are connected; The source of the eighth PMOS tube is connected to VCC through the fourth resistor, and the drain is connected to the source of the ninth PMOS tube and the source of the tenth PMOS tube; the gate of the ninth PMOS tube is connected to the voltage of VCC after resistor voltage division, and the gate of the tenth PMOS tube is connected to the voltage of the RST / EN signal after resistor voltage division; The source of the first NMOS tube, the source of the second NMOS tube, the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube, and the source of the sixth NMOS tube are grounded; The drain and gate of the eleventh PMOS tube are connected to the gate of the twelfth PMOS tube, the drain of the eleventh PMOS tube is connected to the drain of the fifth NMOS tube; the source of the eleventh PMOS tube and the source of the twelfth PMOS tube are connected to the power supply VDD; The drain of the twelfth PMOS tube and the drain of the sixth NMOS tube are connected to the input end of the first Schmitt inverter; the output end of the first Schmitt inverter is connected to the input end of the first inverter, and the output end of the first inverter is connected to the input end of the second inverter.

4. The RST / EN circuit according to claim 1, characterized in that: The pulse width detection circuit includes: a high-level and low-level pulse width detection circuit, a high-level pulse width detection circuit, a low-level pulse width detection circuit and an RS trigger; the input end of the high-level and low-level pulse width detection circuit is connected to the output end of the hysteresis comparator, the output end of the high-level and low-level pulse width detection circuit is connected to the input end of the high-level pulse width detection circuit and the low-level pulse width detection circuit, and the output end of the high-level pulse width detection circuit and the low-level pulse width detection circuit is connected to the input end of the RS trigger.

5. A RST / EN circuit according to claim 4, characterized in that: The high and low level pulse width detection circuit comprises: a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter; The input end of the third inverter is connected to the output end of the second inverter, the output end of the third inverter is connected to the input end of the fourth inverter and the input end of the fifth inverter; the output end of the fourth inverter is connected to the input end of the sixth inverter; the output ends of the fourth inverter and the sixth inverter are connected to the low level pulse width detection circuit; The output end of the third inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the seventh inverter, the output end of the seventh inverter is connected to the input end of the eighth inverter, and the output ends of the seventh inverter and the eighth inverter are connected to the low level pulse width detection circuit.

6. A RST / EN circuit according to claim 5, characterized in that: The high-level pulse width detection circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, a seventh NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first capacitor and a second Schmidt inverter; One end of the fifth resistor is connected to the output end of the sixth inverter, and the other end is connected to one end of the sixth resistor, the drain of the tenth NMOS tube and the drain of the fourteenth PMOS tube; the other end of the sixth resistor is connected to the source of the tenth NMOS tube, the source of the fourteenth PMOS tube, the drain of the ninth NMOS tube, the drain of the thirteenth PMOS tube and one end of the seventh resistor; the other end of the seventh resistor is connected to the source of the ninth NMOS tube, the source of the thirteenth PMOS tube, the drain of the seventh NMOS tube, the upper plate of the first capacitor and the input end of the second Schmidt inverter; the gate of the seventh NMOS tube is connected to the output end of the fourth inverter, the source of the seventh NMOS tube is connected to the lower plate of the first capacitor, and is grounded; the output end of the second Schmidt inverter is connected to the input end of the RS trigger.

7. A RST / EN circuit according to claim 6, characterized in that: The low-level pulse width detection circuit includes: an eighth resistor, a ninth resistor, a tenth resistor, a second capacitor, a third Schmidt inverter, an eighth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube; One end of the eighth resistor is connected to the output end of the eighth inverter, and the other end of the eighth resistor is connected to one end of the ninth resistor, the drain of the eleventh NMOS tube and the drain of the fifteenth PMOS tube; the other end of the ninth resistor is connected to the source of the eleventh NMOS tube, the source of the fifteenth PMOS tube, the drain of the twelfth NMOS tube, the drain of the sixteenth PMOS tube and one end of the tenth resistor; the other end of the tenth resistor is connected to the source of the twelfth NMOS tube, the source of the sixteenth PMOS tube, the drain of the eighth NMOS tube, the upper plate of the second capacitor and the input end of the third Schmidt inverter; the gate of the eighth NMOS tube is connected to the output end of the seventh inverter, the source of the eighth NMOS tube is connected to the lower plate of the second capacitor, and is grounded; the output end of the third Schmidt inverter is connected to the input end of the RS trigger.

8. A RST / EN circuit according to claim 7, characterized in that: The RS trigger includes: a first NAND gate and a second NAND gate; the input end of the first NAND gate is connected to the output end of the second NAND gate and the output end of the third Schmitt inverter, and the input end of the second NAND gate is connected to the output end of the first NAND gate and the output end of the second Schmitt inverter.

9. A RST / EN circuit according to claim 8, characterized in that: The pulse width detection circuit also includes a ninth inverter; the input end of the ninth inverter is connected to the output end of the second NAND gate, and the output end of the ninth inverter outputs a RST / EN_OUT signal.

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