Segmented broken line nonlinear calibration device of analog-to-digital converter, driving chip and electronic equipment

Abstract

The present disclosure relates to a piecewise broken line non-linear calibration device of an analog-to-digital converter, a driving chip and an electronic device. The device comprises: a first adjusting unit configured to select a target slope from a slope storage unit according to high n bits of an analog-to-digital conversion result, and adjust low bit quantization values corresponding to N-n bits of the analog-to-digital conversion result by using the target slope to obtain adjusted low bit quantization values, wherein an output range of the analog-to-digital converter is divided into a plurality of continuous interval segments, and each interval segment corresponds to a slope; and a second adjusting unit configured to adjust high bit quantization values corresponding to high n bits of the analog-to-digital conversion result according to slopes of a plurality of interval segments before an interval segment corresponding to the target slope to obtain adjusted high bit quantization values, and obtain a calibrated analog-to-digital conversion result by using a sum of the adjusted high bit quantization values and the adjusted low bit quantization values. The embodiments of the present disclosure can greatly reduce the calculation complexity, save the area overhead, improve the energy efficiency, and have a higher analog-to-digital conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a segmented broken line nonlinearity calibration device of an analog-to-digital converter, a driving chip and an electronic device. BACKGROUND

[0002] An analog-to-digital converter is a typical analog and mixed-signal integrated circuit, which converts an analog signal into a digital signal through quantization, and is a bridge connecting the real world and the digital system. With the progress of integrated circuit technology, the size of transistors is continuously reduced, and the power supply voltage is gradually lowered. Lower transistor output impedance and more limited voltage swing bring severe nonlinearity challenges to the design of analog-to-digital converters.

[0003] In the conversion process of the signal, the non-ideal characteristics in the circuit will introduce nonlinearity, thereby reducing the performance of the analog-to-digital converter.

[0004] At the same time, the progress of technology also brings lower area and higher energy efficiency of digital computing capability. Therefore, calibrating the nonlinearity introduced by the analog circuit in the digital domain has become a very important method. It can use the advantages of digital computing under advanced technology to deal with the non-rational characteristics of the analog circuit, and has a wide application prospect.

[0005] The polynomial-based nonlinearity calibration algorithm is a commonly used method. Through a polynomial function, the nonlinearity effect in the circuit can be modeled, and the nonlinearity error can be extracted and corrected on this basis. The polynomial function can accurately describe the nonlinearity characteristics of the actual circuit, and only a few parameters are needed to realize the extraction of the error, which is the mainstream nonlinearity calibration algorithm at present. There are many mature background error extraction schemes on the market, which can realize the extraction of the error at a low cost. However, the polynomial calculation needs to perform power operation on the signal, thereby introducing large delay, power consumption and area overhead. This brings great challenges to the practical application of the algorithm.

[0006] Another solution is to model and extract nonlinearity error through segmented broken lines. By using a linear function to approximate a non-linear function, the calibration of nonlinearity can be realized only through linear multiplication and addition operations, thereby avoiding complex power operations and greatly reducing the overall complexity of the system. However, compared with the polynomial-based nonlinearity calibration algorithm, the calibration method based on segmented broken lines needs more parameters, and the extraction is more difficult. For a cubic polynomial y = a1x + a3x 3 , only two parameters a1 and a3 are needed to realize accurate error extraction. Assuming that the modeling is performed through 4 segmented broken lines, each segmented broken line needs a slope k i and an intercept b iTwo parameters are determined, and a total of 8 parameters are required. If higher calibration accuracy is required, a larger number of parameters is required. How to extract these parameters is a very challenging problem.

[0007] Figure 1a 、 Figure 1b The existing segmented broken line coefficient extraction scheme is shown, which extracts the segmented broken line parameters by a foreground test method. The basic idea is to generate a pre-set test voltage by a digital-to-analog converter and input it into an analog-to-digital converter, to determine the non-linear characteristics according to the output result of the analog-to-digital converter, and then to realize the extraction of the segmented broken line coefficient. This scheme requires a large hardware overhead (additional digital-to-analog converter), and can only realize foreground extraction, which needs to interrupt the normal conversion of the analog-to-digital converter. These shortcomings greatly limit its range of use.

[0008] It can be seen that the traditional polynomial non-linear error calibration algorithm has high computational complexity, can introduce a large amount of speed and area cost, and the existing non-linear calibration method based on segmented broken line has large hardware overhead and low calibration efficiency, which has many limitations in actual application. SUMMARY

[0009] According to an aspect of the present disclosure, a segmented broken line non-linear calibration device of an analog-to-digital converter is provided, the analog-to-digital converter being configured to perform analog-to-digital conversion on an input analog input signal and output an analog-to-digital conversion result, wherein the device comprises:

[0010] A first adjustment unit connected to the output end of the analog-to-digital converter, the first adjustment unit being configured to: select a target slope from a slope storage unit according to the high n bits of the analog-to-digital conversion result, and adjust the low bit quantization value corresponding to the N-n bits of the analog-to-digital conversion result by using the target slope to obtain an adjusted low bit quantization value, wherein N>n and both are positive integers, N is the conversion precision of the analog-to-digital converter, and the output range of the analog-to-digital converter is divided into a plurality of continuous interval segments, each interval segment corresponding to a slope;

[0011] A second adjustment unit connected to the output end of the analog-to-digital converter and the output end of the first adjustment unit, the second adjustment unit being configured to: adjust the high bit quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of the plurality of interval segments before the interval segment corresponding to the target slope to obtain an adjusted high bit quantization value, and obtain a calibrated analog-to-digital conversion result by using the sum of the adjusted high bit quantization value and the adjusted low bit quantization value.

[0012] In a possible implementation, the slope storage unit comprises a plurality of slope registers, each of which stores a corresponding slope, and the first adjustment unit comprises a first multiplexer and a first multiplier, wherein the plurality of inputs of the first multiplexer are connected to the slope registers of the slope storage unit respectively, the control end of the first multiplexer is configured to receive the high n bits of the analog-to-digital conversion result, the output of the first multiplexer is connected to the first input of the first multiplier, and the output of the first multiplexer is configured to output the target slope.

[0013] The plurality of inputs of the first multiplexer are connected to the slope registers of the slope storage unit respectively, the control end of the first multiplexer is configured to receive the high n bits of the analog-to-digital conversion result, the output of the first multiplexer is connected to the first input of the first multiplier, and the output of the first multiplexer is configured to output the target slope.

[0014] The second input of the first multiplier is configured to receive the low-bit quantization value corresponding to the N-n bits of the analog-to-digital conversion result, the first multiplier is configured to implement multiplication operation of the low-bit quantization value corresponding to the N-n bits of the analog-to-digital conversion result and the target slope, and the output of the first multiplier is configured to output the adjusted low-bit quantization value.

[0015] In a possible implementation, the second adjustment unit comprises a second multiplexer, an accumulator, a second multiplier, and a first adder, wherein the second multiplexer is configured to select the slopes of a plurality of interval segments before the interval segment corresponding to the target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and input the slopes into the accumulator, the accumulator is configured to output a slope accumulation result, the second multiplier is configured to implement multiplication operation of the high-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result and the slope accumulation result, and obtain the adjusted high-bit quantization value, and the first adder is connected to the output of the accumulator and the output of the first adjustment unit, and configured to sum the adjusted high-bit quantization value and the adjusted low-bit quantization value, and obtain the calibrated analog-to-digital conversion result.

[0016] The second multiplexer is configured to select the slopes of a plurality of interval segments before the interval segment corresponding to the target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and input the slopes into the accumulator, and the accumulator is configured to output a slope accumulation result.

[0017] The second multiplier is configured to implement multiplication operation of the high-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result and the slope accumulation result, and obtain the adjusted high-bit quantization value.

[0018] The first adder is connected to the output of the accumulator and the output of the first adjustment unit, and configured to sum the adjusted high-bit quantization value and the adjusted low-bit quantization value, and obtain the calibrated analog-to-digital conversion result.

[0019] In a possible implementation, the target slope is a ratio of an ideal slope of the analog-to-digital converter and an actual slope corresponding to the interval segment to which the high-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result belongs.

[0020] In a possible implementation, 2 n is the total number of the divided interval segments,

[0021] wherein in an initial case, the endpoints of each interval segment include the origin 0 and i×b0, b0=A / 2 n , 1≤i≤2 n i is an integer, and A=2 Nrepresents a maximum output value of the analog-to-digital converter,

[0022] After the device performs calibration once, the end points of each interval segment include 0 and b i ,

[0023] wherein, k i represents a slope corresponding to the i-th interval segment, and j is a positive integer.

[0024] In a possible implementation, the device further comprises a parameter updating module configured to update the slopes in the slope register and the end points of each interval segment by using the calibrated analog-to-digital conversion result.

[0025] In a possible implementation, the parameter updating module comprises an end point updating unit and a plurality of slope updating units, the slope updating units are configured to perform slope updating operations, and the end point updating unit is configured to perform end point updating operations according to the updated slopes,

[0026] wherein each slope updating unit comprises an absolute value determinator, a third multiplier, and a least mean square filter, and for any one slope updating unit:

[0027] The absolute value determinator is configured to determine the size of the absolute value of an input sample and the value of a corresponding end point, and output a determination result to the third multiplier, wherein the input sample is the difference between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal, and the input sample is used as the final analog-to-digital conversion result, wherein in the case where the absolute value of the input sample is greater than the value of the corresponding end point, the determination result is 1; in the case where the absolute value of the input sample is less than or equal to the value of the corresponding end point, the determination result is 0,

[0028] The third multiplier is configured to perform multiplication operation of the determination result and the sample, and input the operation result to the least mean square filter,

[0029] The least mean square filter is configured to receive a preset updating parameter and the operation result, and output an updated slope,

[0030] wherein the preset updating parameter is related to the digital code.

[0031] In a possible implementation, the least mean square filter comprises a fourth multiplier, a second adder, and a delay device, wherein:

[0032] The fourth multiplier is configured to receive the operation result output by the third multiplier and the preset update parameter, and an output end of the fourth multiplier is connected to a first input end of the second adder, and the output end of the fourth multiplier is configured to output a product of the operation result output by the third multiplier and the preset update parameter,

[0033] A second input end of the second adder is connected to an output end of the delay device,

[0034] An input end of the delay device is connected to an output end of the second adder, and the output end of the delay device is configured as an output end of the least mean square filter,

[0035] The preset update parameter is μ·sign(D d ), μ represents a preset value, sign() represents a sign function, and D d represents the digital code.

[0036] According to an aspect of the present disclosure, a driving chip is provided, which comprises the segmented broken-line non-linear calibration device of the analog-to-digital converter.

[0037] According to an aspect of the present disclosure, an electronic device is provided, which comprises the driving chip.

[0038] The first adjustment unit selects a target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and adjusts the low-bit quantization value corresponding to the N-n bits of the analog-to-digital conversion result by using the target slope, to obtain an adjusted low-bit quantization value. The second adjustment unit adjusts the high-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result by using the slopes of a plurality of interval segments before the interval segment corresponding to the target slope, to obtain an adjusted high-bit quantization value. The sum of the adjusted high-bit quantization value and the adjusted low-bit quantization value is used to obtain the calibrated analog-to-digital conversion result. Compared with the traditional polynomial calibration, the calculation complexity can be greatly reduced, the area overhead can be saved, and the energy efficiency can be improved. Compared with the existing segmented calibration method, the present embodiment does not need to set an additional digital-to-analog converter, can reduce the hardware overhead, reduce the cost, and does not need to interrupt the conversion process in the conversion process, and has high analog-to-digital conversion efficiency.

[0039] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0040] The drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure.

[0041] Figure 1a An error curve schematic diagram of the existing segmented calibration is shown, Figure 1b A block diagram of the existing segmented calibration is shown.

[0042] Figure 2 A schematic diagram of a segmented piecewise nonlinear calibration device of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0043] Figure 3a A schematic diagram of a segmented piecewise nonlinear calibration device of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0044] Figure 3b A segmented schematic diagram in an initial case is shown, Figure 3c A segmented schematic diagram after calibration is shown.

[0045] Figure 4 A schematic diagram of a segmented piecewise nonlinear calibration device of an analog-to-digital converter according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in different drawings represent the same or similar elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0047] In the description of the present disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0048] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0049] In the present disclosure, unless specifically defined and limited otherwise, the terms "mounting", "connecting", "connecting", "fixing" and the like should be broadly interpreted, for example, can be fixed connection, can also be detachable connection, or integrated; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship of two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0050] The term "exemplary" herein is used to mean "serving as an example, instance, or illustration." Any embodiment described as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0051] The term "and / or" herein is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of the plurality or any combination of at least two of the plurality, for example, including at least one of A, B and C can mean including any one or more elements selected from the set consisting of A, B and C.

[0052] In addition, in order to better illustrate the present disclosure, a large number of specific details are given in the specific embodiments below. Those skilled in the art should understand that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail, in order to highlight the main idea of the present disclosure.

[0053] Please refer to Figure 2 , Figure 2 A schematic diagram of a piecewise broken line non-linear calibration device of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0054] The analog-to-digital converter 10 is used to convert an input analog input signal (Vi) into a digital signal and output the conversion result, wherein, as shown in Figure 2 The device comprises:

[0055] A first adjustment unit 20 is connected to the output end of the analog-to-digital converter 10, and the first adjustment unit 20 is used to: select a target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and adjust the low bit quantization value corresponding to the N-n bits of the analog-to-digital conversion result using the target slope to obtain an adjusted low bit quantization value, wherein N>n and both are positive integers, N is the conversion precision of the analog-to-digital converter 10, and the output range of the analog-to-digital converter 10 is divided into a plurality of continuous interval segments, each interval segment corresponds to a slope.

[0056] The second adjustment unit 30 is connected to the output end of the analog-to-digital converter 10 and the output end of the first adjustment unit 20, and is configured to: according to the slopes of the plurality of interval segments before the interval segment corresponding to the target slope, adjust the high-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result to obtain an adjusted high-bit quantization value, and obtain the calibrated analog-to-digital conversion result (Dout) by using the sum of the adjusted high-bit quantization value and the adjusted low-bit quantization value.

[0057] The first adjustment unit 20 is configured to: according to the high n bits of the analog-to-digital conversion result, select a target slope from the slope storage unit 40, and adjust the low-bit quantization value corresponding to the N-n bits of the analog-to-digital conversion result by using the target slope to obtain an adjusted low-bit quantization value; and the second adjustment unit 30 is configured to: according to the slopes of the plurality of interval segments before the interval segment corresponding to the target slope, adjust the high-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result to obtain an adjusted high-bit quantization value, and obtain the calibrated analog-to-digital conversion result by using the sum of the adjusted high-bit quantization value and the adjusted low-bit quantization value. Compared with the traditional polynomial calibration, the calculation complexity can be greatly reduced, the area cost can be saved, the energy efficiency can be improved, compared with the existing segmented calibration method, the disclosed embodiment does not need to set an additional digital-to-analog converter, the hardware cost can be reduced, the cost can be reduced, and the conversion process does not need to be interrupted during the conversion process, and the analog-to-digital conversion efficiency is high.

[0058] The specific implementation of the first adjustment unit 20 and the second adjustment unit 30 is not limited in the disclosed embodiment, and a person skilled in the art can use a suitable technical solution to achieve the actual situation and needs, as long as the corresponding function can be achieved.

[0059] In a possible implementation, the slope storage unit 40 can include a plurality of slope registers, and each slope register stores a corresponding slope. The number and type of the slope registers are not limited in the disclosed embodiment, and a person skilled in the art can set them according to the actual situation and needs. For example, the corresponding slope register can be set according to the number of segments, and the number of slope registers can be greater than or equal to the specific number of segments. In a possible implementation, the number of slope registers is greater than or equal to 2 n The total number of the divided interval segments, and therefore, the number of slope registers can be greater than or equal to 2 n, i.e. each interval segment corresponds to a slope, for example, if n = 2, the input signal can be divided into 4 interval segments, the slope storage unit 40 can include at least 4 slope registers for storing the corresponding slopes of the 4 interval segments, for example, the interval segments can be arranged in ascending order, and the slopes corresponding to the interval segments can be numbered in sequence, in this example, the slopes of the first interval segment to the fourth interval segment correspond to k1 to k4.

[0060] The specific size of the slope of each interval segment is not limited in the embodiments of the present disclosure, and can be set by the person skilled in the art according to the actual situation and needs, for example, a plurality of tests can be performed in advance to obtain a simulation curve of the input and output of the analog-to-digital converter 10, and the slopes of the interval segments can be set according to the number of segments and the simulation curve and stored in the corresponding slope registers. Of course, the specific implementation of obtaining the initial slope is not limited in the embodiments of the present disclosure, and the person skilled in the art can realize it by referring to the related technology according to the actual situation and needs.

[0061] The possible implementation of the first adjustment unit 20 and the second adjustment unit 30 will be exemplarily introduced below.

[0062] Please refer to Figure 3a , Figure 3a A schematic diagram of the segmented broken line nonlinear calibration device of the analog-to-digital converter 10 according to the embodiments of the present disclosure is shown.

[0063] In a possible implementation, as Figure 3a shown, the first adjustment unit 20 can include a first multiplexer MUX1 and a first multiplier MUL1, wherein,

[0064] The plurality of input terminals of the first multiplexer MUX1 are respectively connected to the slope registers of the slope storage unit 40, the control terminal of the first multiplexer MUX1 is used to receive the high n bits (MSB) of the analog-to-digital conversion result, the output terminal of the first multiplexer MUX1 is connected to the first input terminal of the first multiplier MUL1, and the output terminal of the first multiplexer MUX1 is used to output the target slope,

[0065] The second input terminal of the first multiplier MUL1 is used to receive the low bit quantization value (LSB) corresponding to the N-n bits of the analog-to-digital conversion result, the first multiplier MUL1 is used to implement the multiplication operation of the low bit quantization value (LSB) corresponding to the N-n bits of the analog-to-digital conversion result and the target slope, and the output terminal of the first multiplier MUL1 is used to output the adjusted low bit quantization value (LSB cal ).

[0066] In a possible implementation, as Figure 3aAs shown, the second adjusting unit 30 can include a second multiplexer MUX2, an accumulator AND0, a second multiplier MUL2 and a first adder AND1, wherein,

[0067] The second multiplexer MUX2 is configured to select the slopes of the multiple interval segments before the target interval segment corresponding to the target slope according to the high n bits of the analog-to-digital conversion result from the slope storage unit 40 and input into the accumulator AND0, and the accumulator AND0 is configured to output a slope accumulation result.

[0068] The second multiplier MUL2 is configured to implement a multiplication operation of the high n-bit quantization value corresponding to the high n bits of the analog-to-digital conversion result and the slope accumulation result, to obtain the adjusted high n-bit quantization value.

[0069] The first adder AND1 is connected to the output end of the accumulator AND0 and the output end of the first adjusting unit 20, and is configured to sum the adjusted high n-bit quantization value and the adjusted low n-bit quantization value to obtain the calibrated analog-to-digital conversion result.

[0070] For example, if the high n bits MSB of the analog-to-digital conversion result is located in the third interval segment, the target slope is k3, and the slopes of the multiple interval segments before the target interval segment corresponding to the target slope include the slope k1 of the first interval segment and the slope k2 of the second interval segment, the accumulator AND0 outputs the slope accumulation result (k1+k2), and the adjusted high n-bit quantization value MSB_cal=(k1+k2)×MSB.

[0071] Of course, the above description of the first adjusting unit 20 and the second adjusting unit 30 is exemplary and should not be considered as a limitation of the embodiments of the present disclosure. Those skilled in the art can implement other ways according to actual conditions and needs, for example, the mapping relationship between each interval segment and the slope can be established in advance, the target interval segment where the high n bits of the analog-to-digital conversion result is located is queried by using a controller, and then the target slope is obtained through the target interval segment and the mapping relationship established in advance.

[0072] In a possible implementation, the target slope is the ratio of the ideal slope of the analog-to-digital converter to the actual slope of the interval segment to which the quantization value corresponding to the high n bits of the analog-to-digital conversion result belongs. In this way, the embodiments of the present disclosure can ensure that the slope of each segment of the output result after multiplication is equal to the ideal slope, thereby realizing nonlinear calibration. The ideal slope of the analog-to-digital converter can be obtained by referring to the technical manual.

[0073] Please refer to Figure 3b and Figure 3c , Figure 3b shows a segmented schematic diagram in the initial state, Figure 3c shows a segmented schematic diagram after calibration.

[0074] For simplicity, Figure 3b and Figure 3c Only the case of input signal greater than 0 is shown in the figure, for input less than 0, the absolute value can be taken and the same correction operation can be performed. Of course, the reference value "0" here can also be other values of the minimum input of the ADC, for example, for a differential circuit, the reference value can be a negative value. In addition, the high 2 bits (n = 2) shown in the figure are selected (corresponding to a 4-segment piecewise approximation), which is only a special case, and the number of segments can be increased or decreased according to the calibration accuracy requirement.

[0075] In one possible implementation, as previously described, 2 n is the total number of divided interval segments, in this example, n = 2, which can be divided into 4 interval segments, as Figure 3b shown, in the initial case, the endpoints of each interval segment include the origin 0 and i x b0, b0 = A / 2 n , 1≤i≤2 n and i is an integer, A = 2 N represents the maximum output value of the analog-to-digital converter 10, i.e. the endpoints include 0, b0, 2b0, 3b0, 4b0 (not shown), i.e. including 0~b0, b0~2b0, 2b0~3b0, 3b0~4b0 four interval segments, the slopes corresponding to 0~b0, b0~2b0, 2b0~3b0, 3b0~4b0 four interval segments are k1, k2, k3, k4 respectively.

[0076] For example, after the device performs calibration once, the endpoints of each interval segment include 0 and b i ,

[0077] wherein, k i represents the slope corresponding to the i-th interval segment, and j is a positive integer.

[0078] For example, the analog input signal will usually introduce nonlinearity due to non-ideal characteristics in the circuit, for example, as Figure 3a shown, the input signal passes through a non-linear unit (such as a non-linear amplifier, a non-linear sampling circuit, or any circuit module that will cause non-linearity) and introduces non-linearity, which will reduce the performance of the analog-to-digital converter 10, in each embodiment of the present disclosure, the analog input signal input into the analog-to-digital converter 10 can be considered to include non-linearity, and the analog input signal input into the analog-to-digital converter 10 is quantized by the analog-to-digital converter 10 to obtain a quantization result of N-bit output.

[0079] For example, the quantization result is sent to the piecewise linear non-linear calibration device. The correction behavior of the piecewise linear non-linear calibration device is determined by the number of piecewise linear segments pre-set. For example,Figure 3a As shown, taking a 4-segment broken line as an example, assuming the full swing is 0 to A, it can be divided into four segments based on the quantization result: 0 to A / 4, A / 4 to A / 2, A / 2 to 3A / 4, and 3A / 4 to A. The width of each segment is defined as b0 (here, b0 = A / 4). The signal is quantized in steps of b0 to obtain the MSB (quantization result, high n bits) and LSB (quantization residual, Nn bits). In this embodiment, the MSB reflects which segment the signal is in. For a segment with 2 segments... n In the case of powers of n, the first n bits can be used as the MSB, and the remaining (Nn) bits as the LSB (e.g., ...). Figure 3a and Figure 3b The four broken lines in the middle correspond to n=2).

[0080] For example, such as Figure 3b , Figure 3c The graph shown illustrates the distribution of MSB and LSB with input when the number of segments is set to 4. After the above division, each LSB segment can be approximated as a straight line. To achieve non-linear calibration, it is only necessary to adjust the slope of all LSBs to be consistent and then splice them together.

[0081] Therefore, in this embodiment of the present disclosure, the slope of the LSB can be changed by selecting the corresponding correction coefficients (k1 to k4) through the MSB, so that the slopes of each part of the curve are equal, such as... Figure 3b As shown by the red curve. For example, as... Figure 3b As shown, for the overall curves of the input and output of the analog-to-digital converter 10, after correction, the slopes of each LSB curve segment change from unequal (red dashed line) to equal (red solid line). This operation corresponds to the principle that the first adjustment unit 20 selects a target slope from the slope storage unit 40 based on the high n bits of the analog-to-digital conversion result, and uses the target slope to adjust the low-order quantization values ​​corresponding to the Nn bits of the analog-to-digital conversion result to obtain the adjusted low-order quantization values.

[0082] Meanwhile, during the splicing process, considering that the slopes of each part have changed, it is also necessary to select an appropriate offset to ensure the continuity after splicing. For example, as... Figure 3b As shown, the first LSB segment has a range of 0 to b0 before correction. After multiplying by the correction factor k1, as shown... Figure 3c As shown, its corresponding range becomes 0 to k1b0, so the starting point of the second LSB becomes k1b0, denoted as b1. At the same time, the width of the coverage area of ​​the second LSB also changes from b0 to k2b0, so the corresponding coverage area after correction is k1b0 to (k1+k2)b0, denoted as b1 to b2.

[0083] The embodiment of the present disclosure can efficiently and accurately realize the segmented broken line calibration of nonlinearity by adjusting the high-bit quantization value corresponding to the high n-bit of the analog-to-digital conversion result according to the slope of the multiple interval segments before the interval segment corresponding to the target slope by the second adjusting unit 30 to reselect the correct offset. Figure 3a The operation corresponds to the second multiplexer MUX2, the accumulator AND0, the second multiplier MUL2 and the first adder AND1 as shown in the figure, the slope of the multiple interval segments before the interval segment corresponding to the target slope is selected by the MSB, the accumulator AND0 is used for accumulation, the high-bit quantization value is corrected, and the LSB cal summed to obtain the final output.

[0084] In the above operation, the slope (ki) and the offset (bi) are needed, wherein the offset can be determined by the slope and the predefined step (b0). Taking a 4-segment broken line as an example, each endpoint is: 0;

[0086] b1=k1b0;

[0087] b2=(k1+k2)b0;

[0088] b3=(k1+k2+k3)b0.

[0089] In summary, for the general case of M-segment broken line, the general formula can be obtained as follows:

[0090] Please refer to Figure 4 , Figure 4 FIG. 1 shows a schematic diagram of a segmented broken line nonlinearity calibration device of an analog-to-digital converter 10 according to an embodiment of the present disclosure.

[0091] In a possible implementation, as shown in Figure 4 , the device can further include a parameter updating module 60 configured to update the slope in the slope register and the endpoints of each interval segment by using the calibrated analog-to-digital conversion result.

[0092] The embodiment of the present disclosure does not limit the specific implementation of the parameter updating module 60, and those skilled in the art can use related technologies to achieve the actual situation and needs as long as the corresponding parameter updating function can be realized. The preferred implementation is exemplarily introduced as follows.

[0093] In a possible implementation, as shown in Figure 4As shown, the parameter updating module 60 can include an endpoint updating unit 620 and a plurality of slope updating units 610 for performing updating operations of slopes, and the endpoint updating unit 620 is configured to perform updating operations of endpoints according to the updated slopes,

[0094] Each slope updating unit 610 can include an absolute value determinator 6110, a third multiplier MUL3, and a least mean square filter, and for any one slope updating unit 610:

[0095] The absolute value determinator 6110 is configured to determine the absolute value of an input sample and the value of a corresponding endpoint, and output a determination result to the third multiplier MUL3, wherein the input sample is the difference (D out,cal -D d ) between the calibrated digital-to-analog conversion result and the digital code of the random signal added to the analog input signal, and the input sample is taken as the final digital-to-analog conversion result (Dout), wherein the determination result is 1 when the absolute value of the input sample is greater than the value of the corresponding endpoint, and the determination result is 0 when the absolute value of the input sample is less than or equal to the value of the corresponding endpoint,

[0096] The third multiplier MUL3 is configured to perform multiplication operations of the determination result and the sample, and input an operation result to the least mean square filter,

[0097] The least mean square filter is configured to receive a preset updating parameter and the operation result, and output an updated slope,

[0098] Wherein the preset updating parameter is related to the digital code.

[0099] It is worth noting that, Figure 4 Although the difference between the calibrated digital-to-analog conversion result and the digital code of the random signal added to the analog input signal is shown as being implemented by the third adder in the above embodiment, the present disclosure is not limited thereto, for example, the digital code of the random signal of the analog input signal can also be input to the first adder AND1 in the above embodiment, and the input sample is obtained by using the first adder AND1, thereby saving hardware overhead. Figure 3a

[0100] Exemplarily, as shown in Figure 4 , the random signal Vd can be added to the input signal Vin in advance by using an adder, and the input signal Vin after adding the random signal Vd is input to the analog-to-digital converter 10 as the analog input signal after passing through the nonlinear unit.

[0101] ​The absolute value determiner 6110 can include a first comparator, an inverter, and a second comparator. The first comparator is configured to compare the input sample with 0. If the input sample is less than 0, the input sample is inverted by the inverter to obtain the absolute value of the input sample. If the input sample is greater than 0, the input sample does not need to be inverted by the inverter. The second comparator is configured to compare the absolute value of the input sample with the value of the corresponding endpoint. If the absolute value of the input sample is greater than the value of the corresponding endpoint, the determination result is 1 (the second comparator outputs a high-level signal). If the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the determination result is 0 (the second comparator outputs a low-level signal).

[0102] Of course, the absolute value of the input sample can also be determined in other ways, for example, using a built-in function. Many hardware platforms provide built-in functions for calculating absolute values. For example, in C language, the absolute value of an integer can be calculated using the abs function, and the absolute value of a floating-point number can be calculated using the fabs function. Binary complement operation: for signed integers, the absolute value can be calculated by using the properties of binary complements. In the complement representation, the complement of a negative number is the binary representation of its absolute value after inversion plus one. Through this operation, the absolute value of a negative number can be directly obtained.

[0103] The endpoint updating unit 620 can be implemented in various ways. For example, the endpoint updating unit 620 can be implemented by a processing component. The processing component can include, but is not limited to, a separate processor, a discrete component, or a combination of a processor and a discrete component. The processor can include a controller having an execution instruction function in an electronic device. The processor can be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0104] For example, after receiving the updated slope, the endpoint updating unit 620 can update the endpoints according to the endpoint formula .

[0105] The specific implementation of the least mean square filter is not limited in the embodiments of the present disclosure, and a person skilled in the art can adopt related technologies according to actual conditions and needs to implement the corresponding parameter updating function, and the preferred implementation is exemplarily introduced below.

[0106] In a possible implementation, as shown in Figure 4 The least mean square filter can include a fourth multiplier MUL4, a second adder AND2 and a delay unit Delay1, wherein

[0107] The fourth multiplier MUL4 is configured to receive the operation result output by the third multiplier MUL3 and the preset update parameter, and the output end of the fourth multiplier MUL4 is connected to the first input end of the second adder AND2, and the output end of the fourth multiplier MUL4 is configured to output the product of the operation result output by the third multiplier MUL3 and the preset update parameter,

[0108] The second input end of the second adder AND2 is connected to the output end of the delay unit Delay1,

[0109] The input end of the delay unit Delay1 is connected to the output end of the second adder AND2, and the output end of the delay unit Delay1 serves as the output end of the least mean square filter,

[0110] The preset update parameter is μ·sign(D d ), μ represents a preset value, sign() represents a sign function, and D d represents the digital code.

[0111] The specific parameter setting of the delay unit Delay1 is not limited in the embodiments of the present disclosure, and the delay size can be flexibly set according to actual conditions and needs.

[0112] Exemplarily, as shown in Figure 4 , a voltage signal Vd modulated by a pseudo-random code is added to the input signal Vin, the random code is irrelevant to the input signal, and the input signal Vin is input to an analog-to-digital converter 10 as an input analog signal after passing through a nonlinear unit for quantization, and the quantization result is input to the nonlinear segmented broken line nonlinear calibration device (the first adjustment unit 20 and the second adjustment unit 30) mentioned in Figure 2 , the code word D d corresponding to the random code is subtracted (D out,cal -D d ) from the digital domain. Assuming that the segmented broken line nonlinear calibration device can completely correct all nonlinear errors, the output Dout obtained after subtraction is equal to the random code D dcompletely irrelevant. Conversely, if the non-linearity is not completely eliminated, Dout and D d are still correlated. With this property, embodiments of the present disclosure update the slope (ki) by a least mean square filter such that Dout and D d are de-correlated.

[0113] Since different calibration coefficients involve different samples, embodiments of the present disclosure creatively use a gated least mean square filter with adaptive threshold to update the calibration coefficients.

[0114] For example, in the calibration device (first adjustment unit 20, second adjustment unit 30) shown in Figure 2 , the coefficient k1 directly affects the samples with absolute value of 0~b0, and this part of the samples corresponds to the range of 0~b1 after correction. At the same time, k1 also affects the samples with absolute value >b0, and the corresponding range after correction is >b1. Because the calculation of this part of the samples involves b1, b2, b3, and k1 participates in the calculation of b1, b2, b3. That is, k1 will affect all samples, and all samples will be used to update k1. In contrast, k4 only affects the samples with absolute value >b3 after correction, so only this part of the samples will be used to update k4.

[0115] Based on this observation, embodiments of the present disclosure insert an absolute value judge 6110 and a third multiplier MUL3 as a range selector before each least mean square filter, which is used to judge the range of the input sample. Only when the input sample is within the corresponding range, it will be sent to the least mean square filter to update the corresponding correction coefficient.

[0116] For example, as shown in Figure 4 , the threshold of the range selector is the offset (bi), and bi is not a fixed value but determined by ki (the specific calculation formula is given in the foregoing ). That is, bi is used to select the samples for updating ki, and after the update of k1~k4 is completed, b1~b3 will be recalculated and used as new thresholds to select the update samples. This is the adaptive threshold gated least mean square filter proposed by embodiments of the present disclosure. In short, the meaning of "adaptive threshold" is that the threshold (bi) determines whether to update the coefficient (ki), and the coefficient is updated and the threshold is adjusted, so it is called "adaptive threshold" (different from "fixed threshold").

[0117] Through the above method, the background extraction of the piecewise broken line calibration coefficient can be realized.

[0118] The non-linear calibration algorithm of embodiments of the present disclosure has the following advantages:

[0119] 1. The segmented broken line nonlinear calibration can greatly reduce the calculation complexity, save the area overhead and improve the energy efficiency compared with the traditional polynomial calibration.

[0120] 2. The adaptive threshold gated least mean square filter can realize the background extraction of the segmented broken line coefficients at a very low digital cost, thereby greatly expanding the application scenarios of the algorithm.

[0121] The segmented broken line nonlinear calibration technology based on the jitter injection and the adaptive threshold gated least mean square filter can realize the background extraction of the segmented broken line coefficients at a low hardware complexity, thereby greatly expanding the application range of the segmented broken line nonlinear calibration technology. The application can be applied to all application scenarios requiring nonlinear error calibration, such as high-speed high-precision pipeline analog-to-digital converters 10 and high-linearity sample-and-hold front ends.

[0122] According to an aspect of the present disclosure, a driving chip is provided, which comprises the segmented broken line nonlinear calibration device of the analog-to-digital converter 10.

[0123] According to an aspect of the present disclosure, an electronic device is provided, which comprises the driving chip.

[0124] The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, a vehicle-mounted device, or the like. For example, the terminal device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a wireless terminal in Internet of Vehicles, or the like. The server can be a local server or a cloud server.

[0125] Having described above several embodiments of the disclosure, any modifications and variations that fall within the scope of the described embodiments are also intended to be within the scope of the disclosure. As will be apparent to those skilled in the art, some modifications and variations to the embodiments described above can be practiced while staying within the scope and spirit of the described embodiments. The foregoing description of the described embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the described embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the disclosed embodiments be limited only by the claims.

Claims

1. A piecewise broken-line nonlinearity calibration apparatus for an analog-to-digital converter, characterized by, The analog-to-digital converter is used for analog-to-digital conversion of an input analog input signal and outputs an analog-to-digital conversion result, wherein the device comprises: A first adjustment unit connected to an output end of the analog-to-digital converter, the first adjustment unit being configured to: select a target slope from a slope storage unit according to high n bits of the analog-to-digital conversion result, and adjust low bit quantization values corresponding to N-n bits of the analog-to-digital conversion result by using the target slope to obtain adjusted low bit quantization values, wherein the adjustment of the low bit quantization values by using the target slope comprises multiplication of the low bit quantization values and the target slope, N>n and both are positive integers, N is conversion precision of the analog-to-digital converter, and an output range of the analog-to-digital converter is divided into multiple continuous interval segments, each interval segment corresponding to a slope; A second adjustment unit connected to the output end of the analog-to-digital converter and the output end of the first adjustment unit, the second adjustment unit being configured to: adjust high bit quantization values corresponding to the high n bits of the analog-to-digital conversion result according to slopes of multiple interval segments before a interval segment corresponding to the target slope to obtain adjusted high bit quantization values, and obtain a calibrated analog-to-digital conversion result by using a sum of the adjusted high bit quantization values and the adjusted low bit quantization values, wherein the second adjustment unit comprises a second multiplexer, an accumulator and a second multiplier, the second multiplexer is configured to select the slopes of the multiple interval segments before the interval segment corresponding to the target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result and input into the accumulator, the accumulator is configured to output a slope accumulation result, and the second multiplier is configured to implement multiplication of the high bit quantization values corresponding to the high n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high bit quantization values.

2. The apparatus of claim 1, wherein, The slope storage unit comprises multiple slope registers, each slope register storing a corresponding slope, and the first adjustment unit comprises a first multiplexer and a first multiplier, a plurality of input ends of the first multiplexer are respectively connected to the slope registers of the slope storage unit, a control end of the first multiplexer is configured to receive the high n bits of the analog-to-digital conversion result, an output end of the first multiplexer is connected to a first input end of the first multiplier, and the output end of the first multiplexer is configured to output the target slope, a second input end of the first multiplier is configured to receive the low bit quantization values corresponding to the N-n bits of the analog-to-digital conversion result, the first multiplier is configured to implement multiplication of the low bit quantization values corresponding to the N-n bits of the analog-to-digital conversion result and the target slope, and an output end of the first multiplier is configured to output the adjusted low bit quantization values.

3. The apparatus of claim 1 or 2, wherein, The second adjustment unit comprises a first adder, the first adder is connected to the output end of the accumulator and the output end of the first adjustment unit, and is configured to sum the adjusted high bit quantization values and the adjusted low bit quantization values to obtain the calibrated analog-to-digital conversion result.

4. The apparatus of claim 1, wherein, The target slope is a ratio of an ideal slope of the analog-to-digital converter to an actual slope corresponding to an interval segment to which a quantization value corresponding to high n bits of the analog-to-digital conversion result belongs.

5. The apparatus of claim 1, wherein, 2 n is the total number of divided interval segments, wherein, in the initial case, the end points of the individual interval segments comprise the origin 0 and is an integer, denotes the maximum output value of the analog-digital converter, After the device performs one calibration, the end points of each interval segment include 0 and , wherein , denotes the slope corresponding to the i-th interval segment, is a positive integer.

6. The apparatus of claim 5, wherein, The device further comprises a parameter updating module configured to update the slope in the slope register and the endpoints of the interval segments by using the calibrated analog-to-digital conversion result.

7. The apparatus of claim 6, wherein, The parameter updating module comprises an endpoint updating unit and a plurality of slope updating units, the slope updating units are configured to perform a slope updating operation, and the endpoint updating unit is configured to perform an endpoint updating operation according to the updated slope, Each slope updating unit comprises an absolute value determinator, a third multiplier and a least mean square filter, and for any one slope updating unit: The absolute value determinator is configured to determine a size of an absolute value of an input sample and a value of a corresponding endpoint and output a determination result to the third multiplier, wherein the input sample is a difference between the calibrated analog-to-digital conversion result and a digital code of a random signal added to the analog input signal, the input sample is used as a final analog-to-digital conversion result, and in a case where the absolute value of the input sample is greater than the value of the corresponding endpoint, the determination result is 1; in a case where the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the determination result is 0, The third multiplier is configured to perform a multiplication operation of the determination result and the sample and input an operation result into the least mean square filter, The least mean square filter is configured to receive a preset updating parameter and the operation result and output an updated slope, The preset updating parameter is related to the digital code.

8. The apparatus of claim 7, wherein, The least mean square filter comprises a fourth multiplier, a second adder and a delay device, wherein The fourth multiplier is configured to receive the operation result output by the third multiplier and the preset updating parameter, an output end of the fourth multiplier is connected to a first input end of the second adder, and the output end of the fourth multiplier is configured to output a product of the operation result output by the third multiplier and the preset updating parameter, a second input end of the second adder is connected to an output end of the delay device, an input end of the delay device is connected to an output end of the second adder, serving as an output end of the least mean square filter, Wherein, the preset update parameter is μ·sign(D d ), μ represents a preset value, sign() represents a sign function, and D d represents the digital code.

9. A driver chip, characterized by comprising: The driving chip comprises the segmented broken line nonlinear calibration device of the analog-to-digital converter according to any one of claims 1 to 8.

10. An electronic device, comprising: The electronic device comprises the driving chip according to claim 9.

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