ADC control circuit
By designing an ADC control circuit containing conventional and occasional group signal channels, the problem of inability to process occasional analog signals in the prior art is solved, timely conversion of occasional analog signals and priority processing of normal analog signals are realized, and the response capability and use efficiency of electronic equipment are improved.
Patent Information
- Application Number
- CN202411947200.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-05-16
AI Technical Summary
When processing analog signals, existing ADC converters are unable to deal with occasional conversion needs in a timely manner, resulting in the inability to process occasional analog signals in a timely manner, affecting the use of electronic equipment.
An ADC control circuit is designed to receive normal and occasional analog signals by setting up a conventional group signal channel and an occasional group signal channel. When an occasional analog signal is received, the circuit can immediately terminate the conversion process of the normal analog signal, convert the occasional analog signal, and reconvert the unfinished normal analog signal after completion.
Timely conversion of occasional analog signals is realized, avoiding the problem of inability to deal with occasional needs due to failure to deal with timely processing, ensuring that electronic equipment can process digital signals in a timely manner, and improving the efficiency of equipment use.
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Figure CN120017060A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic equipment, and in particular to an ADC control circuit. Background Art
[0002] ADC converter (Analog-to-Digital Converter) is used to convert analog signals into digital signals, and it plays a vital role in electronic devices.
[0003] Various analog signals are generated during the operation of electronic devices, which need to be converted into digital signals through ADC converters to control electronic devices. However, the current triggering method is mainly used to start the conversion sequence. When it works, it can only wait for the current sequence conversion to be completed before subsequent operations can be performed, and it cannot cope with occasional conversion needs. Summary of the invention
[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present application provides an ADC control circuit.
[0005] In a first aspect, the present application provides an ADC control circuit, comprising:
[0006] A signal conversion unit, used for converting an analog signal into a digital signal, wherein the analog signal includes a normal analog signal and an occasional analog signal;
[0007] A regular group signal channel and an occasional group signal channel, each of which includes a plurality of signal channels, the regular group signal channel is used to receive the normal analog signal, and the occasional group signal channel is used to receive the occasional analog signal;
[0008] A sequence conversion unit is electrically connected between the signal conversion unit and the regular group signal channel, and is electrically connected between the signal conversion unit and the sporadic group signal channel. The sequence conversion unit is used to control the signal conversion unit to terminate the conversion process of the normal analog signal, convert the sporadic analog signal, and reconvert the unconverted normal analog signal after the conversion of the sporadic analog signal is completed, or the signal conversion unit is also used to control the signal conversion unit to convert the sporadic analog signal after all the normal analog signals are converted, when the sporadic analog signal is received.
[0009] Optionally, it also includes:
[0010] A mode conversion unit, electrically connected to the sequence conversion unit, the mode conversion unit being used to convert a conversion mode of the analog signal converted by the signal conversion unit;
[0011] Among them, different conversion modes correspond to different conversion sequences.
[0012] Optionally, the conversion mode includes an occasional group continuous trigger mode;
[0013] In the occasional group continuous trigger mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the received occasional group trigger signal, and converts the occasional analog signals of all the signal channels in the received occasional group signal channel.
[0014] Optionally, the switching mode includes an occasional group interval trigger mode;
[0015] In the occasional group interval trigger mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the received occasional group trigger signal, and converts the occasional analog signal of a single signal channel in the received occasional group signal channel.
[0016] Optionally, the conversion mode further includes an occasional group continuous cycle mode;
[0017] In the sporadic group continuous cycle mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the preset sporadic analog signal generation cycle, and converts the sporadic analog signals of all the signal channels in the received sporadic group signal channels.
[0018] Optionally, the conversion mode further includes an occasional group interval periodic mode;
[0019] In the occasional group interval period mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the preset occasional analog signal generation period, and converts the occasional analog signal of a single signal channel in the received occasional group signal channel.
[0020] Optionally, the conversion mode also includes a conventional group priority mode;
[0021] In the normal group priority mode, the sequence conversion unit controls the signal conversion unit to convert the sporadic analog signal after all the normal analog signals are converted based on the received sporadic group trigger signal or based on the preset sporadic analog signal generation cycle.
[0022] Optionally, the conventional group signal channel includes a plurality of groups of conventional sub-group signal channels, and each group of the conventional sub-group signal channels includes at least one of the signal channels;
[0023] The conversion mode also includes a conventional subgroup scan mode:
[0024] In the normal sub-group scanning mode, after the signal conversion unit completes the conversion of the normal analog signal of the normal sub-group signal channel of the current group, it enters an idle state until receiving the normal analog signal of the normal sub-group signal channel of the next group.
[0025] Optionally, the sporadic group signal channel includes a plurality of groups of sporadic sub-group signal channels, and each group of the sporadic sub-group signal channels includes at least one of the signal channels;
[0026] The conversion mode also includes an occasional subgroup scan mode:
[0027] In the occasional subgroup scanning mode, after the signal conversion unit completes the conversion of the normal analog signal of the occasional subgroup signal channel of the current group, it enters an idle state until receiving the normal analog signal of the occasional subgroup signal channel of the next group.
[0028] Optionally, a synchronous trigger unit is further included; the signal conversion unit includes at least a first subunit and a second subunit; the first subunit and the second subunit are both used to convert the analog signal into the digital signal; the synchronous trigger unit is electrically connected to the first subunit and the second subunit;
[0029] The synchronous trigger unit is used to control the first subunit and the second subunit to convert the same analog signal simultaneously.
[0030] The present application provides an ADC control circuit, which includes: a signal conversion unit, which is used to convert an analog signal into a digital signal, the analog signal includes a normal analog signal and an occasional analog signal; a regular group signal channel and an occasional group signal channel, the regular group signal channel and the occasional group signal channel each include multiple signal channels, the regular group signal channel is used to receive the normal analog signal, and the occasional group signal channel is used to receive the occasional analog signal; a sequence conversion unit, which is electrically connected between the signal conversion unit and the regular group signal channel, and between the signal conversion unit and the occasional group signal channel, the sequence conversion unit is used to control the signal conversion unit to terminate the conversion process of the normal analog signal, convert the occasional analog signal, and re-convert the unconverted normal analog signal after the conversion of the occasional analog signal is completed, or the signal conversion unit is also used to control the signal conversion unit to convert the occasional analog signal after all the normal analog signals are converted, when receiving the occasional analog signal. Based on the above scheme, the present application sets an occasional group signal channel and a regular group signal channel to receive occasional analog signals and normal analog signals respectively. After receiving the occasional analog signal, the signal conversion unit can immediately terminate the conversion process of the normal analog signal and convert the occasional analog signal. Then, the generated occasional analog signal can be converted into a digital signal in time, which is conducive to the electronic device composed of the ADC control circuit to process the digital signal in time, avoiding the inability to cope with occasional needs due to untimely processing, which affects the use of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A schematic diagram of an ADC control circuit structure provided in an embodiment of the present application;
[0032] Figure 2 A schematic diagram of an analog signal conversion sequence provided in an embodiment of the present application;
[0033] Figure 3 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0034] Figure 4 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0035] Figure 5 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0036] Figure 6 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0037] Figure 7 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0038] Figure 8 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0039] Fig. 9 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0040] Fig.10 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0041] Fig.11 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0042] Fig.12 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application;
[0043] Fig.13 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
[0045] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.
[0046] An ADC control circuit provided in an embodiment of the present application is exemplarily described below with reference to the accompanying drawings.
[0047] Figure 1 A schematic diagram of an ADC control circuit structure provided in an embodiment of the present application, the ADC control circuit includes:
[0048] The signal conversion unit 100 is used to convert an analog signal into a digital signal, where the analog signal includes a normal analog signal and an occasional analog signal.
[0049] The regular group signal channel 200 and the occasional group signal channel 300 each include a plurality of signal channels 201 . The regular group signal channel 200 is used to receive normal analog signals, and the occasional group signal channel 300 is used to receive occasional analog signals.
[0050] The sequence conversion unit 400 is electrically connected between the signal conversion unit 100 and the regular group signal channel 200, and is electrically connected between the signal conversion unit 100 and the occasional group signal channel 300. The sequence conversion unit 400 is also used to control the signal conversion unit 100 to terminate the conversion process of the normal analog signal, convert the occasional analog signal, and re-convert the unconverted normal analog signal after the conversion of the occasional analog signal is completed, or the signal conversion unit 100 is also used to control the signal conversion unit 100 to convert the occasional analog signal after all the normal analog signals are converted, when receiving the occasional analog signal.
[0051] like Figure 1 As shown, the signal conversion unit 100 in the embodiment of the present application represents a functional unit capable of converting an analog signal into a digital signal, which may be a circuit structure or an existing component. The signal conversion unit 100 may include multiple signal channels 201, and each signal channel 201 is used to receive different analog signals.
[0052] Normal analog signals refer to analog signals that are generated at all times, and sporadic analog signals refer to analog signals that are generated sporadically. The sporadic analog signals may be generated regularly at a certain frequency, or may be generated irregularly. Specifically, in an electronic device composed of an ADC control circuit, a variety of analog signals may be generated, some of which are generated at all times, namely the normal analog signals in the embodiment of the present application, and some analog signals are generated at a fixed frequency or at a non-fixed frequency, namely the sporadic analog signals in the embodiment of the present application. However, in some scenarios, the importance of these sporadic analog signals is higher than that of normal analog signals. For example, a sporadic analog signal corresponds to the temperature detection result of a component in an electronic device. If it is not processed in time and the sporadic analog signal reflects that the temperature of the component is too high, the electronic device cannot respond to the result in time, which will cause the component to be damaged, thereby affecting the use of the electronic device.
[0053] In traditional solutions, the ADC converter (i.e., the signal conversion unit 100) can generally only convert analog signals in a fixed sequence. Even if an occasional analog signal is generated, the ADC converter can only convert it in sequence according to the set order until it rotates to the order of the occasional analog signal. This will result in the inability to process the signal in time and the inability to respond to unexpected situations in time.
[0054] In order to solve this problem, the embodiment of the present application divides the multiple signal channels 201 of the signal conversion unit 100 into regular group signal channels 200 and occasional group signal channels 300. When no occasional analog signals are received, the sequence conversion unit 400 controls the signal conversion unit 100 to convert the regular analog signals in the regular group signal channels 200 according to a specific conversion sequence (i.e., the order of converting the analog signals of different signal channels 201) to complete the regular signal conversion process. When an occasional analog signal is received, the sequence conversion unit 400 will control the signal conversion unit 100 to immediately convert the occasional analog signal in the occasional group signal channel 300. This process can be divided into two situations, namely: ① When an occasional analog signal is received, the signal conversion unit 100 is converting a regular analog signal, then the conversion process is terminated immediately, and the occasional analog signal is converted. After the conversion of the occasional analog signal is completed, the unfinished regular analog signal is reconverted; ② When an occasional analog signal is received, the signal conversion unit 100 has just completed a regular analog signal conversion process, then regardless of whether there are other regular analog signals to be converted later, the occasional analog signal is immediately converted, and after the conversion of the occasional analog signal is completed, if there is a regular analog signal to be converted, the regular analog signal is converted.
[0055] In some other implementations, the occasional analog signal may be converted after all conventional analog signals have been converted. For example, this solution is used when the urgency of the occasional analog signal is low. It should be noted that this is only a principle explanation, and does not limit how to determine the urgency of the occasional analog signal. The scenario in which this solution is used is not limited to this one, and this solution can also be used in other scenarios.
[0056] In summary, the embodiment of the present application sets an occasional group signal channel 300 and a regular group signal channel 200 to receive occasional analog signals and normal analog signals respectively. After receiving the occasional analog signal, the signal conversion unit 100 can immediately terminate the conversion process of the normal analog signal and convert the occasional analog signal. Then, the generated occasional analog signal can be converted into a digital signal in time, which is conducive to the electronic device composed of the ADC control circuit to process the digital signal in time, avoiding the inability to cope with occasional needs due to untimely processing, which affects the use of the electronic device.
[0057] In some embodiments, it further comprises:
[0058] The mode conversion unit is electrically connected to the sequence conversion unit, and the mode conversion unit is used to convert the conversion mode of the analog signal converted by the signal conversion unit.
[0059] Different conversion modes correspond to different conversion sequences.
[0060] Specifically, the embodiment of the present application further provides a mode conversion unit, which is used to change the conversion mode of the signal conversion unit converting the analog signal. In the above embodiment, the conventional group signal channel and the sporadic group signal channel both include multiple signal channels, so the sequence (order) in which the analog signal is converted can be selected. For example, the analog signals of m conventional group signal channels are first converted, then the analog signals of n sporadic group signal channels are converted, and then the analog signals of p conventional group signal channels are converted, and so on. Different conversion modes correspond to different conversion sequences.
[0061] Thus, the embodiment of the present application can be applied to various application scenarios. In the embodiment of the present application, the mode conversion unit can pre-set a specific conversion mode, or can automatically convert the conversion mode of the signal conversion unit in some cases. The conversion mode is exemplarily described below in conjunction with specific implementation methods.
[0062] In some implementations, the switching mode includes an infrequent group continuous triggering mode.
[0063] In the occasional group continuous trigger mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the received occasional group trigger signal, and converts the occasional analog signals of all signal channels in the received occasional group signal channel.
[0064] Figure 2 A schematic diagram of an analog signal conversion sequence provided in an embodiment of the present application. Figure 2 As shown, the embodiment of the present application illustrates the signal channel as "ch", and "ch3", "ch1", etc. in the figure represent different signal channels, and the sporadic group signal channel and the regular group signal channel may partially overlap. The regular group signal channel may include "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7", and the sporadic group signal channel may include "ch13", "ch5" and "ch7". Figure 2 The horizontal axis T in represents time. Figure 2 Different filling patterns are used to illustrate different processes, which are described in detail in Figure 2 In all the following embodiments, unless otherwise specified, all schematic diagrams of analog signal conversion sequences are based on this and will not be described in detail.
[0065] pass Figure 2It can be seen from the analog signal conversion sequence diagram shown in the figure that the analog signal conversion process can be divided into two steps, which are sampling and conversion in chronological order. After the analog signal of the current signal channel is sampled, the analog signal of the current signal channel is converted, and then the analog signal of the next signal channel is sampled, and then the analog signal of the next signal channel is converted.
[0066] In the occasional group continuous trigger mode, multiple occasional analog signals can be generated each time. After the signal conversion unit terminates the conversion process of the regular analog signal each time, it needs to continuously convert the occasional analog signals of multiple occasional group signal channels, and then continue to convert the unconverted regular analog signals.
[0067] For example, Figure 2 In the process, after receiving the conventional group trigger signal, the sequence conversion unit starts to poll and convert the conventional analog signals of the conventional group signal channels of "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7" in order. However, in the process of converting the conventional analog signals of the conventional group signal channel of "ch9", the occasional group trigger signal is received, and the sequence conversion unit immediately controls the signal conversion unit to stop the conversion process of the conventional group signal channel of "ch9", and polls and converts the occasional analog signals of the occasional group signal channel of "ch13", and then continues to poll and convert the occasional analog signals of the occasional group signal channels of "ch5" and "ch7" until the conversion is completed, and then reconverts the conventional analog signals of the conventional group signal channel of "ch9" that have not been converted, and then the conventional analog signals of the conventional group signal channels of "ch2", "ch5" and "ch7" in order. In this way, the timely processing of the occasional signals suddenly generated by the occasional group signal channel can be completed.
[0068] In some implementations, the switching mode includes an infrequent group interval triggering mode.
[0069] In the occasional group interval trigger mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the received occasional group trigger signal, and converts the occasional analog signal of a single signal channel in the received occasional group signal channel.
[0070] Figure 3 Another analog signal conversion sequence schematic diagram provided for an embodiment of the present application. In some scenarios, although multiple sporadic signals are generated and transmitted to the sequence conversion unit by multiple different sporadic group signal channels, they are not generated at the same time, but there is a time difference. In this case, if the signal conversion unit is still controlled to poll all sporadic group signal channels at one time, a lot of time will be wasted. In this case, this mode can be adopted.
[0071] For example, Figure 3 In the process, after receiving the regular group trigger signal, the sequence conversion unit starts to poll and convert the regular analog signals of the regular group signal channels of "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7" in sequence. However, in the process of converting the regular analog signal in the "ch6" regular group signal channel, the occasional group trigger signal is received, and the sequence conversion unit immediately controls the signal conversion unit to stop the conversion process of the regular analog signal in the "ch6" regular group signal channel, and instead polls and converts the occasional analog signal in the "ch13" occasional group signal channel. After the conversion is completed, the regular analog signal in the "ch6" regular group signal channel is reconverted again. After the conversion of the regular analog signal in the "ch9" regular group signal channel is completed, the occasional group trigger signal is received again, and the occasional analog signal in the "ch5" occasional group signal channel continues to be polled and converted, and then the regular analog signal in the "ch2" regular group signal channel continues to be converted. During the process of converting the regular analog signal in the "ch5" regular group signal channel, the occasional group trigger signal is received again, the conversion process is immediately stopped, and the occasional analog signal in the "ch7" occasional group signal channel is polled and converted. After the conversion is completed, the regular analog signal in the "ch5" regular group signal channel is converted again until the conversion of multiple regular analog signals in the "ch7" regular group signal channel is completed. In this way, the timing processing of occasional analog signals generated at different times can be completed.
[0072] In some scenarios, sporadic signals are not generated absolutely by chance, but are generated at a fixed period. For example, in an electronic device, the temperature of a component needs to be detected at a fixed period. The analog signal corresponding to the temperature is generated periodically and is also classified as a sporadic analog signal. In this case, the conversion process is not triggered by the sporadic group trigger signal, but the control signal conversion unit automatically jumps to the process of converting the sporadic analog signal in the sporadic group signal channel at a specific period. In this case, the following conversion mode can be used.
[0073] In some implementations, the switching pattern further includes an occasional group of continuous cycle patterns.
[0074] In the sporadic group continuous cycle mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the preset sporadic analog signal generation cycle, and converts the sporadic analog signals of all signal channels in the received sporadic group signal channel.
[0075] Figure 4Another analog signal conversion sequence diagram provided in the embodiment of the present application. In some scenarios, these sporadic analog signals generated at a fixed period are generated together at the same time, and this mode can be used. Specifically, for example, Figure 4 In the embodiment, after receiving the regular group trigger signal, the sequence conversion unit starts to poll and convert the regular analog signals in the regular group signal channels "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7" in sequence. After reaching a specific time node, regardless of whether the regular analog signal of the current regular group signal channel has been processed, the sequence conversion unit immediately controls the signal conversion unit to poll and convert the sporadic analog signals in all sporadic group signal channels. When all the sporadic analog signals in the sporadic group signal channels have been converted and processed, they are reconverted into the regular analog signals in the regular group signal channels that have been converted. Based on the above scheme, the embodiment of the present application can convert sporadic analog signals in a timely manner at a fixed period, and no sporadic group trigger signal is required, further simplifying the process.
[0076] In some implementations, the switching pattern further includes an occasional group interval periodic pattern.
[0077] In the sporadic group interval period mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the preset sporadic analog signal generation period, and converts the sporadic analog signal of a single signal channel in the received sporadic group signal channel.
[0078] Figure 5 Another analog signal conversion sequence diagram provided for an embodiment of the present application. In some scenarios, these sporadic analog signals generated at a fixed period are not generated at the same time. If all sporadic signal channels are polled every time a fixed period is reached, a lot of time will be wasted. In this case, this mode can be used. Specifically, for example, Figure 5In the process, after receiving the trigger signal of the regular group, the sequence conversion unit starts to find the sequence to poll and convert the regular analog signals in the regular group signal channels "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7" in sequence. After reaching the first specific time node, regardless of whether the regular analog signal of the current regular group signal channel has been processed, the sequence conversion unit immediately controls the signal conversion unit to poll and convert the sporadic analog signal in the sporadic group signal channel "ch13". When the conversion of the sporadic analog signal in the sporadic group signal channel "ch13" is completed, the regular analog signal in the regular group signal channel that has not been converted is reconverted. After reaching the second specific time node, regardless of whether the regular analog signal of the current regular group signal channel has been processed, the sequence conversion unit immediately controls the signal conversion unit to poll and convert the sporadic analog signal in the sporadic group signal channel "ch5". When the conversion of the sporadic analog signal in the sporadic group signal channel "ch5" is completed, the regular analog signal in the regular group signal channel that has not been converted is reconverted. After reaching the third specific time node, regardless of whether the conventional analog signal of the current conventional group signal channel has been processed, the sequence conversion unit immediately controls the signal conversion unit to poll and convert the sporadic analog signal in the "ch7" sporadic group signal channel. When the sporadic analog signal in the "ch7" sporadic group signal channel is converted, the conventional analog signal in the unconverted conventional group signal channel is reconverted.
[0079] Based on the above scheme, the embodiment of the present application can convert sporadic analog signals in a timely manner at a fixed period, and no longer requires sporadic group trigger signals. In addition, it is not necessary to poll all sporadic group signal channels during each conversion process, thereby avoiding wasting time.
[0080] In some implementations, the transition mode also includes a regular group priority mode.
[0081] In the normal group priority mode, the sequence conversion unit generates a cycle based on the received occasional group trigger signal or based on a preset occasional analog signal, and the control signal conversion unit converts the occasional analog signal after completing the conversion of all normal analog signals.
[0082] Figure 6 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application. Figure 7 Another analog signal conversion sequence diagram provided in an embodiment of the present application. Specifically, Figure 6 and Figure 7 The difference is that Figure 6 In the example, the sporadic analog signal is converted based on the sporadic group trigger signal received. Figure 7Generate a periodic conversion sporadic analog signal based on a preset sporadic analog signal. In some scenarios, the sporadic analog signal may be of low importance and not time-sensitive, so the regular analog signal in the regular group signal channel can be polled and converted first. After all signal channels in the regular group signal channel are polled and converted, the sporadic analog signal in the sporadic group signal channel can be polled and converted. For example, Figure 6 and Figure 7 In the process, when the occasional group trigger signal is received at any time point, the regular analog signals in the regular group signal channels "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7" can be polled and converted in sequence. When all the regular group signal channels are polled and converted, the occasional analog signals in the occasional group signal channels "ch13", "ch5" and "ch7" can be polled and converted in sequence.
[0083] In some embodiments, the regular group of signal channels includes a plurality of regular sub-group signal channels, each regular sub-group signal channel including at least one signal channel.
[0084] The conversion mode also includes the regular subgroup scanning mode:
[0085] In the normal sub-group scanning mode, after the signal conversion unit completes the conversion of the normal analog signal of the normal sub-group signal channel of the current group, it enters the idle state until it receives the normal analog signal of the normal sub-group signal channel of the next group.
[0086] Figure 8 Another analog signal conversion sequence diagram provided for an embodiment of the present application. In some scenarios, the conventional analog signals in multiple conventional group signal channels are not generated at the same time, or are not generated immediately, but may be timed apart. In this scenario, this mode can be used. Specifically, for example Figure 8The conventional group signal channels "ch3", "ch1", "ch6", "ch9", "ch2", "ch5" and "ch7" are divided into four groups, that is, "ch3" and "ch1" are a conventional sub-group, "ch6" and "ch9" are a conventional sub-group, "ch2" and "ch5" are a conventional sub-group, and "ch7" is a conventional sub-group. After the sequence conversion unit receives the conventional group trigger signal, the control signal conversion unit sequentially polls and converts the conventional group signal channels "ch3" and "ch1", and then enters the idle state. After receiving the conventional group trigger signal again, the control signal conversion unit sequentially polls and converts the conventional group signal channels "ch6" and "ch9", and then enters the idle state again. After receiving the conventional group trigger signal again, the control signal conversion unit sequentially polls and converts the conventional group signal channels "ch2" and "ch5", and then enters the idle state again. After receiving the conventional group trigger signal again, the control signal conversion unit sequentially polls and converts the conventional group signal channel "ch7", and then enters the idle state again.
[0087] This avoids wasting time polling all regular group signal channels.
[0088] In some embodiments, the sporadic group of signal channels includes multiple groups of sporadic sub-groups of signal channels, each group of sporadic sub-groups of signal channels includes at least one signal channel.
[0089] The conversion mode also includes an occasional subgroup scan mode:
[0090] In the occasional subgroup scanning mode, after the signal conversion unit completes the conversion of the normal analog signal of the occasional subgroup signal channel of the current group, it enters the idle state until receiving the normal analog signal of the occasional subgroup signal channel of the next group.
[0091] Fig. 9 Another analog signal conversion sequence diagram provided for an embodiment of the present application. In some scenarios, the embodiment of the present application may also poll and convert only the sporadic analog signals in the sporadic group signal channel, without polling and converting the regular analog signals in the regular group signal channel. In this case, the multiple signal channels in the sporadic group signal channel can be divided into multiple sporadic groups, for example Fig. 9 In the example, each sporadic subgroup includes only one signal channel. After the sequence conversion unit receives the sporadic group trigger signal, the control signal conversion unit polls and converts the sporadic group signal channel "ch13", and then enters the idle state. After receiving the sporadic group trigger signal again, the control signal conversion unit sequentially polls and converts the sporadic group signal channel "ch5", and then enters the idle state again. After receiving the sporadic group trigger signal again, the control signal conversion unit sequentially polls and converts the sporadic group signal channel "ch7", and then enters the idle state again.
[0092] In the above Figures 2 to 7 In the figure, only the process of polling and converting all signal channels once is illustrated. However, in actual scenarios, the signal conversion unit often needs to poll and convert again after the process of polling and converting all signal channels once. Fig.10 A schematic diagram of another analog signal conversion sequence provided in an embodiment of the present application. Fig.11 Another analog signal conversion sequence diagram provided in an embodiment of the present application. Specifically, after all signal channels are polled and converted, the signal conversion unit can enter an idle state, and re-polls all signal channels again after maintaining the idle state for a period of time. Alternatively, it is possible not to enter the idle state and re-polls all signal channels immediately. Fig.10 and Fig.11 All Figure 2 Based on Fig.10 In the example, after polling and converting the regular group signal channel "ch7", the signal conversion unit enters the idle state, remains in the idle state for a period of time, and then re-polls the group signal channel "ch3" in sequence. Fig.11 In the example, after polling and converting the regular group signal channel "ch7", the signal conversion unit does not enter the idle state, but directly re-polls the group signal channel "ch3" according to the sequence.
[0093] Fig.12 Another analog signal conversion sequence diagram provided in the embodiment of the present application. In some scenarios, occasional analog signals may not be generated, and regular analog signals are not generated all the time. Fig.12 That is, only one fixed regular group signal channel is polled and converted each time. Fig.12 After the polling and conversion are completed, the signal conversion unit enters the idle state, and after receiving the normal group trigger signal again, it polls the normal group signal channel "ch3" again.
[0094] Fig.13 Another analog signal conversion sequence diagram provided in the embodiment of the present application. In some scenarios, sporadic analog signals may not be generated, but regular analog signals are generated all the time. However, it is still possible to adopt a solution of polling only a single fixed regular group signal channel. Fig.13 After the polling and conversion are completed, the signal conversion unit does not enter the idle state, but directly re-polls the regular group signal channel "ch3".
[0095] In some embodiments, a synchronous trigger unit is further included. The signal conversion unit includes at least a first subunit and a second subunit. The first subunit and the second subunit are both used to convert analog signals into digital signals. The synchronous trigger unit is electrically connected to the first subunit and the second subunit.
[0096] The synchronous trigger unit is used to control the first subunit and the second subunit to convert the same analog signal simultaneously.
[0097] Specifically, the first subunit and the second subunit can both be an ADC conversion circuit, that is, the first subunit and the second subunit can both convert analog signals into digital signals. In some scenarios, some ADC conversion circuits may be damaged but cannot be discovered immediately, for example, the first subunit confirms that there is no fault, but the second subunit cannot confirm whether there is a fault. In the embodiment of the present application, the first subunit and the second subunit can be triggered by the synchronization trigger unit to receive and convert the same analog signal at the same time node. By comparing the results, it can be determined whether the second subunit has a fault. If the conversion results of the first subunit and the second subunit are the same, the second subunit has no fault, otherwise it has a fault. In some embodiments, the first subunit and the second subunit can be connected to the same signal channel through a conversion switch, and correspondingly, the first subunit and the second subunit can also be connected to different signal channels through a conversion switch to achieve receiving and converting different analog signals.
[0098] In some embodiments, the signal conversion can also perform resolution conversion, for example, converting the digital signal according to a resolution of 12, 10, 8, 6, etc. Alternatively, the digital signal can be converted in a left-aligned or right-aligned manner. Alternatively, a signed digital signal can be converted into an unsigned digital signal and the sign bit can be retained, or an unsigned digital signal can be converted into a signed digital signal. Alternatively, the signal can be biased, for example, the signal can be increased or decreased by a data bias value to obtain a standard signal. Alternatively, the conversion results (i.e., digital signals) obtained multiple times can be averaged to obtain averaged data to improve the accuracy of the data.
[0099] Correspondingly, the ADC control circuit in the embodiment of the present application may further include a trigger control unit, which may be electrically connected to the sequence conversion unit, and the trigger control unit may be used to generate the occasional group trigger signal or the regular group trigger signal in the above embodiment. The trigger control unit may be electrically connected to each signal channel, and generate a regular group trigger signal or an occasional group trigger signal based on the analog signal of each signal channel.
[0100] In some embodiments, the ADC control circuit may further include a data monitoring unit, which may be electrically connected to the signal conversion unit. Specifically, the data monitoring unit may analyze the digital signal obtained after the conversion, and take a certain level signal as an example, if the level value of the level signal exceeds the normal level threshold range, it may be considered that there is an abnormality, otherwise it may be considered that there is no abnormality.
[0101] Alternatively, a numerical offset may be added based on a specific scenario. Still taking a certain level signal as an example, during the operation of the electronic device, the level signal of the electronic device is within a certain threshold range, but it is also possible to exceed the threshold range without an abnormality. For example, the normal level threshold range of a certain level signal is 2V to 3V, but it is also possible to generate a level of 1.9V or 3.1V without an abnormality. However, as long as the level range remains between 1.8V and 3.2V, it can still be considered that there is no abnormality, that is, the numerical offset can be 0.2V. In some embodiments, the value of the numerical offset can be set based on actual needs.
[0102] In some embodiments, the ADC control circuit may further include a register unit, which may be electrically connected to the signal conversion unit. The register unit may implement register configuration functions through the AXI4-Lite bus, send configuration information to each unit, receive information such as status, data (such as digital signals) fed back by each unit, and generate and process interrupt functions and DMA (Direct Memory Access) functions. Among them, the interrupt function enables the controller (such as a CPU) connected thereto to respond to the digital signal converted by the signal conversion unit in a timely manner when necessary, while the DMA function can directly write the data converted by the signal conversion unit into the memory without the intervention of the CPU. The combination of these two functions further improves the performance and efficiency of the system, so that the present invention has significant advantages in application scenarios with high multi-tasking and real-time requirements.
[0103] Among them, the register unit may include multiple registers, as follows:
[0104] Status register: This register group mainly includes the signal conversion unit idle state flag, data monitoring exception flag, trigger conflict flag, etc.
[0105] Control register: This register group mainly includes signal conversion unit work enable, signal conversion unit working mode configuration, data monitoring working mode configuration, signal conversion unit interrupt enable, DMA enable, data processing mode configuration (data resolution, data alignment, data sign, data mean and other information), trigger mode and trigger source, etc.
[0106] Channel parameter register: This register group mainly includes the sampling time configuration of each signal channel corresponding to the signal conversion unit.
[0107] Regular group registers: This register group mainly includes regular group conversion length, regular group conversion sequence configuration, regular group data storage (in addition to storing processed data, it will also calculate and verify based on the data), occasional group conversion end flag, regular group data offset configuration, etc.
[0108] Occasional group registers: This register group mainly includes the occasional group conversion length, the occasional group conversion sequence configuration, the occasional group data storage (in addition to storing the processed data, it will also calculate and verify based on the data), the occasional group conversion end flag, the occasional group data offset configuration, etc.
[0109] Data monitoring register: This register group mainly includes high and low threshold registers, etc.
[0110] The embodiment of the present application further provides an electronic device, comprising the ADC control circuit in the above embodiment. The electronic device can achieve the same or at least similar technical effects as any embodiment of the ADC control circuit, which will not be described in detail here.
[0111] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0112] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. An ADC control circuit, characterized in that: include: A signal conversion unit, used for converting an analog signal into a digital signal, wherein the analog signal includes a normal analog signal and an occasional analog signal; A regular group signal channel and an occasional group signal channel, each of which includes a plurality of signal channels, the regular group signal channel is used to receive the normal analog signal, and the occasional group signal channel is used to receive the occasional analog signal; A sequence conversion unit is electrically connected between the signal conversion unit and the regular group signal channel, and is electrically connected between the signal conversion unit and the occasional group signal channel. The sequence conversion unit is used to control the signal conversion unit to terminate the conversion process of the normal analog signal, convert the occasional analog signal, and reconvert the unconverted normal analog signal after the conversion of the occasional analog signal is completed, or the signal conversion unit is also used to control the signal conversion unit to convert the occasional analog signal after all the normal analog signals are converted, when the occasional analog signal is received.
2. The ADC control circuit according to claim 1, characterized in that: Also includes: A mode conversion unit, electrically connected to the sequence conversion unit, the mode conversion unit being used to convert a conversion mode of the analog signal converted by the signal conversion unit; Among them, different conversion modes correspond to different conversion sequences.
3. The ADC control circuit according to claim 2, characterized in that: The switching mode includes an occasional group continuous trigger mode; In the occasional group continuous trigger mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the received occasional group trigger signal, and converts the occasional analog signals of all the signal channels in the received occasional group signal channel.
4. The ADC control circuit according to claim 2, characterized in that: The switching mode includes an occasional group interval trigger mode; In the occasional group interval trigger mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the received occasional group trigger signal, and converts the occasional analog signal of a single signal channel in the received occasional group signal channel.
5. The ADC control circuit according to claim 2, characterized in that: The switching mode also includes an occasional group of continuous cycle modes; In the sporadic group continuous cycle mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the preset sporadic analog signal generation cycle, and converts the sporadic analog signals of all the signal channels in the received sporadic group signal channels.
6. The ADC control circuit according to claim 2, characterized in that: The switching mode also includes an occasional group interval periodic mode; In the occasional group interval period mode, the sequence conversion unit controls the signal conversion unit to terminate the conversion process of the normal analog signal based on the preset occasional analog signal generation period, and converts the occasional analog signal of a single signal channel in the received occasional group signal channel.
7. The ADC control circuit according to claim 2, characterized in that: The conversion mode also includes a conventional group priority mode; In the normal group priority mode, the sequence conversion unit controls the signal conversion unit to convert the sporadic analog signal after all the normal analog signals are converted based on the received sporadic group trigger signal or based on the preset sporadic analog signal generation cycle.
8. The ADC control circuit according to claim 2, characterized in that: The conventional group of signal channels includes a plurality of conventional sub-group signal channels, and each of the conventional sub-group signal channels includes at least one of the signal channels; The conversion mode also includes a conventional subgroup scan mode: In the normal sub-group scanning mode, after the signal conversion unit completes the conversion of the normal analog signal of the normal sub-group signal channel of the current group, it enters an idle state until receiving the normal analog signal of the normal sub-group signal channel of the next group.
9. The ADC control circuit according to claim 2, characterized in that: The sporadic group signal channel includes a plurality of groups of sporadic sub-group signal channels, and each group of the sporadic sub-group signal channels includes at least one of the signal channels; The conversion mode also includes an occasional subgroup scan mode: In the occasional subgroup scanning mode, after the signal conversion unit completes the conversion of the normal analog signal of the occasional subgroup signal channel of the current group, it enters an idle state until receiving the normal analog signal of the occasional subgroup signal channel of the next group.
10. The ADC control circuit according to claim 1, characterized in that: It also includes a synchronous trigger unit; the signal conversion unit includes at least a first subunit and a second subunit; the first subunit and the second subunit are both used to convert the analog signal into the digital signal; the synchronous trigger unit is electrically connected to the first subunit and the second subunit; The synchronous trigger unit is used to control the first subunit and the second subunit to convert the same analog signal simultaneously.