Check code generation method and check code generation device

Abstract

The invention discloses a check code generation method and a check code generation device, and the method comprises the steps: obtaining to-be-processed data, and determining a first effective data length and a second effective data length; determining a first check code length based on the first effective data length and a preset relationship, and determining a second check code length based on the second effective data length and the preset relationship; determining a first position weight according to the arrangement sequence of each data bit of the to-be-processed data along the first direction, and determining a second position weight according to the arrangement sequence of each data bit of the to-be-processed data along the second direction; determining a first check code according to the to-be-processed data, the first effective data length, the first check code length and the first position weight, and determining a second check code according to the to-be-processed data, the second effective data length, the second check code length and the second position weight; and determining a check code according to the first check code and the second check code. According to the method, the check code is generated in an orthogonal coding mode, and the cost of coding the check bit is reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a verification code generation method and a verification code generation device. Background Art

[0002] ECC (Error Correcting Code) is a coding technology used to detect and correct errors in data transmission or storage. Error detection and correction is achieved by adding additional check bits to the original data. These check bits are transmitted or stored together with the original data, and the receiver calculates the check bits to detect whether the data is wrong and correct single-bit errors or multi-bit errors.

[0003] In the related art, Hamming codes, BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon codes) codes are used for encoding. However, this encoding method will cause a large part of the capacity of the storage array to be occupied by weight data, and encoding any bit error will generate a lot of redundant data, resulting in capacity waste and reducing computing efficiency. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present application is to propose a check code generation method, which significantly reduces the cost of encoding check bits by defining two orthogonal directions in a storage array and cross-coding, improves calculation efficiency, and reduces the cost of check code generation.

[0005] The second objective of the present application is to provide a verification code generating device.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application proposes a method for generating a check code, which includes: obtaining data to be processed, and determining a first valid data length of the data to be processed along a first direction and a second valid data length along a second direction, wherein the first direction is perpendicular to the second direction; determining the first check code length of the data to be processed based on the first valid data length and a preset relationship, and determining the second check code length of the data to be processed based on the second valid data length and a preset relationship; determining the first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction, and determining the second position weight corresponding to each data bit of the data to be processed along the second direction according to the arrangement order of each data bit of the data to be processed along the second direction; determining the first check code according to the data to be processed, the first valid data length, the first check code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and determining the second check code according to the data to be processed, the second valid data length, the second check code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction; determining the check code of the data to be processed according to the first check code and the second check code.

[0007] According to the verification code generation method of the embodiment of the present application, firstly, the data to be processed is acquired, and the first valid data length of the data to be processed along the first direction and the second valid data length along the second direction are determined, wherein the first direction is perpendicular to the second direction, the first verification code length of the data to be processed is determined based on the first valid data length and a preset relationship, the second verification code length of the data to be processed is determined based on the second valid data length and a preset relationship, the first position weight corresponding to each data bit of the data to be processed along the first direction is determined according to the arrangement order of each data bit of the data to be processed along the first direction, and the second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction, then, the first verification code is determined according to the data to be processed, the first valid data length, the first verification code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and the second verification code is determined according to the data to be processed, the second valid data length, the second verification code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction, so as to determine the verification code of the data to be processed based on the first verification code and the second verification code. Therefore, the method significantly reduces the cost of coding check bits by defining two orthogonal directions in the storage array and cross-coding, improves calculation efficiency, and reduces the cost of generating check codes.

[0008] In addition, the verification code generation method according to the above embodiment of the present application may also have the following additional technical features:

[0009] According to an embodiment of the present application, the preset relationship is expressed by the following formula:

[0010] 2 m ≥b+m+1

[0011] Among them, m represents the check code length, and b represents the valid data length;

[0012] Determining a first check code length of the data to be processed based on the first valid data length and a preset relationship includes: obtaining a minimum value of the check code length that satisfies the preset relationship based on the first valid data length to obtain the first check code length; determining a second check code length of the data to be processed based on the second valid data length and a preset relationship includes: obtaining a minimum value of the check code length that satisfies the preset relationship based on the second valid data length to obtain the second check code length.

[0013] According to an embodiment of the present application, a first check code is determined according to the data to be processed, the first valid data length, the first check code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, including: obtaining the sum of the first valid data length and the first check code length plus one to obtain a first value; obtaining the sum of the products of the data of each data bit of the data to be processed along the first direction and the corresponding first position weight to obtain a second value corresponding to each data bit of the data to be processed along the first direction; obtaining the sum of the second values ​​of each data bit of the data to be processed along the first direction to obtain a third value; obtaining the remainder between the third value and the first value to obtain a fourth value; performing binary conversion on the fourth value to obtain A first check code; determining a second check code according to the data to be processed, the second valid data length, the second check code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction, including: obtaining the sum of the second valid data length and the second check code length plus one to obtain a fifth value; obtaining the sum of the products of the data of each data bit of the data to be processed along the second direction and the corresponding second position weight to obtain a sixth value corresponding to each data bit of the data to be processed along the second direction; obtaining the sum of the sixth values ​​of each data bit of the data to be processed along the second direction to obtain a seventh value; obtaining the remainder between the seventh value and the fifth value to obtain an eighth value; performing binary conversion on the eighth value to obtain a second check code.

[0014] According to an embodiment of the present application, determining a check code of the data to be processed according to the first check code and the second check code includes: arranging the first check code and the second check code in sequence along a first direction to obtain the check code of the data to be processed.

[0015] According to one embodiment of the present application, the verification code generation method also includes: determining the third position weight corresponding to each data bit in the first verification code based on the arrangement order of each data bit in the first verification code, and determining the fourth position weight corresponding to each data bit in the second verification code based on the arrangement order of each data bit in the second verification code; determining the target weight vector according to the first position weight corresponding to each data bit of the data to be processed along the first direction, the second position weight corresponding to each data bit of the data to be processed along the second direction, the third position weight corresponding to each data bit in the first verification code, and the fourth position weight corresponding to each data bit in the second verification code; performing data verification decoding operations based on the target weight vector.

[0016] According to one embodiment of the present application, a first position weight corresponding to each data bit of the data to be processed along the first direction is determined according to the arrangement order of each data bit of the data to be processed along the first direction, including: using non-integer powers of two in positive integers in ascending order as the first position weight corresponding to each data bit of the data to be processed along the first direction; a third position weight corresponding to each data bit in the first check code is determined based on the arrangement order of each data bit in the first check code, including: using integer powers of two in positive integers in ascending order as the third position weight corresponding to each data bit in the first check code; a second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction, including: using non-integer powers of two in positive integers in ascending order as the second position weight corresponding to each data bit of the data to be processed along the second direction; a fourth position weight corresponding to each data bit in the second check code is determined based on the arrangement order of each data bit in the second check code, including: using integer powers of two in positive integers in ascending order as the fourth position weight corresponding to each data bit in the second check code.

[0017] According to one embodiment of the present application, a data verification decoding operation is performed based on a target weight vector, including: obtaining the data to be verified, and determining a result vector of the data to be verified, wherein the result vector includes valid data and a verification code; decoding and verifying the data to be verified according to the target weight vector and the result vector to determine the data status of the data to be verified.

[0018] According to one embodiment of the present application, the target weight vector includes a first weight vector corresponding to a first direction and a second weight vector corresponding to a second direction, and the result vector includes a first result vector corresponding to the first direction and a second result vector corresponding to the second direction, wherein the data to be verified is decoded and verified according to the target weight vector and the result vector to determine the data state of the data to be verified, including: obtaining the product between the first result vector and the first weight vector, and the remainder between the first numerical value, to obtain the decoding result corresponding to the first direction; obtaining the product between the second result vector and the second weight vector, and the remainder between the fifth numerical value, to obtain the decoding result corresponding to the second direction; when the decoding result corresponding to the first direction and the decoding result corresponding to the second direction are both zero, it is determined that no data error has occurred in the data to be verified; when at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, it is determined that a data error has occurred in the data to be verified.

[0019] According to one embodiment of the present application, when at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, the method also includes: when the decoding result corresponding to the first direction is any first position weight or the decoding result corresponding to the first direction is the difference between the first numerical value and any first position weight, a data error occurs in the data bit corresponding to any first position weight; when the decoding result corresponding to the second direction is any second position weight or the decoding result corresponding to the second direction is the difference between the fifth numerical value and any second position weight, a data error occurs in the data bit corresponding to any second position weight.

[0020] To achieve the above-mentioned purpose, the second aspect of the present application proposes a verification code generating device, which includes: an acquisition module, used to acquire the data to be processed, and determine a first valid data length of the data to be processed along a first direction and a second valid data length along a second direction, wherein the first direction is perpendicular to the second direction; a first determination module, used to determine the first verification code length of the data to be processed based on the first valid data length and a preset relationship, and to determine the second verification code length of the data to be processed based on the second valid data length and the preset relationship; a second determination module, used to determine the length of each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction a first position weight corresponding to a data bit, and a second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction; a third determination module is used to determine the first check code according to the data to be processed, the first valid data length, the first check code length and the first position weight corresponding to each data bit of the data to be processed along the first direction, and determine the second check code according to the data to be processed, the second valid data length, the second check code length and the second position weight corresponding to each data bit of the data to be processed along the second direction; a fourth determination module is used to determine the check code of the data to be processed according to the first check code and the second check code.

[0021] According to the verification code generating device of the embodiment of the present application, the data to be processed is acquired by the acquisition module, and the first valid data length of the data to be processed along the first direction and the second valid data length along the second direction are determined, wherein the first direction is perpendicular to the second direction, the first verification code length of the data to be processed is determined by the first determination module based on the first valid data length and a preset relationship, and the second verification code length of the data to be processed is determined based on the second valid data length and a preset relationship, the first position weight corresponding to each data bit of the data to be processed along the first direction is determined by the second determination module according to the arrangement order of each data bit of the data to be processed along the first direction, and the second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction, the first verification code is determined by the third determination module according to the data to be processed, the first valid data length, the first verification code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and the second verification code is determined according to the data to be processed, the second valid data length, the second verification code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction, and the fourth determination module determines the verification code of the data to be processed according to the first verification code and the second verification code. Therefore, the device significantly reduces the cost of coding check bits by defining two orthogonal directions in the storage array and cross-coding, thereby improving calculation efficiency and reducing the cost of generating check codes.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a flowchart of a verification code generation method according to an embodiment of the present application;

[0024] Figure 2 A schematic diagram of an orthogonal coding space according to a specific embodiment of the present application;

[0025] Figure 3 A schematic diagram of verification code generation according to a specific embodiment of the present application;

[0026] Figure 4 A schematic diagram of storage of a verification code according to a specific embodiment of the present application;

[0027] Figure 5 It is a flowchart of a verification code generation method according to a specific embodiment of the present application;

[0028] Figure 6 is a flowchart of a decoding verification method according to a specific embodiment of the present application;

[0029] Figure 7 A schematic diagram of near-storage computing / storage-computing integration implementation according to a specific embodiment of the present application;

[0030] Figure 8 A schematic diagram of a decoding circuit for orthogonal coding according to a specific embodiment of the present application;

[0031] Fig. 9 A schematic diagram of an adding circuit according to a specific embodiment of the present application;

[0032] Fig.10 FIG. 4 is a connection diagram of a verification code generating device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0034] The verification code generation method and verification code generation device proposed in the embodiments of the present application are described below with reference to the accompanying drawings.

[0035] With the emergence of new-generation information technologies such as artificial intelligence and big models, the amount of data that needs to be processed is growing explosively. In order to break through the limitations of storage walls and power consumption walls, AI (Artificial Intelligence) computing chips have conducted research on new architectures such as near-memory computing / storage-computing integration. Vector-matrix multiplication and addition and matrix-matrix multiplication and addition calculations with vector multiplication and addition as the basic units are gradually developed with storage as the center.

[0036] The ECC memory error correction coding in the related technology is usually for the purpose of storage, and is committed to correcting errors that occur in any bit in the storage array. In the context of AI computing, the use of the ECC encoding method in the related technology will cause two problems: first, the weight scale of the AI ​​algorithm is large, and a large part of the capacity of the storage array will be occupied by weight data. Encoding any bit error will generate a lot of redundant data, resulting in capacity waste; second, the decoding method is usually implemented using XOR gate circuits, which has poor scalability, and the area and power consumption increase significantly with the increase in effective data bits, which seriously deteriorates the energy efficiency of AI computing.

[0037] To solve at least one of the above technical problems, the present application proposes a check code generation method, which significantly reduces the cost of the coding check bit by defining two orthogonal directions in the storage array and cross-coding. The check code generation method of the present application is described in detail below in conjunction with the accompanying drawings.

[0038] Figure 1 Flow chart of a verification code generation method according to an embodiment of the present application.

[0039] like Figure 1 As shown, the verification code generation method of the embodiment of the present application may include:

[0040] S1, obtaining data to be processed, and determining a first valid data length of the data to be processed along a first direction and a second valid data length along a second direction, wherein the first direction is perpendicular to the second direction;

[0041] S2, determining a first check code length of the data to be processed based on the first valid data length and a preset relationship, and determining a second check code length of the data to be processed based on the second valid data length and a preset relationship;

[0042] S3, determining a first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction, and determining a second position weight corresponding to each data bit of the data to be processed along the second direction according to the arrangement order of each data bit of the data to be processed along the second direction;

[0043] S4, determining a first check code according to the data to be processed, the first valid data length, the first check code length, and a first position weight corresponding to each data bit of the data to be processed along the first direction, and determining a second check code according to the data to be processed, the second valid data length, the second check code length, and a second position weight corresponding to each data bit of the data to be processed along the second direction;

[0044] S5, determining a check code for the data to be processed according to the first check code and the second check code.

[0045] Specifically, assuming that the first direction is the x direction and the second direction is the y direction, the first valid data length of the data to be processed along the first direction corresponds to the row data length of the data to be processed, and the second valid data length of the data to be processed along the second direction corresponds to the column data length of the data to be processed. Figure 2 and Figure 3 For example, assuming that the data to be processed is 4×8 data, the first valid data length is 8 bits, and the second valid data length is 4 bits. When the data to be processed is in an orthogonal coding space, the orthogonal coding space contains by=4 banks in total, and the word length of each bank is bx=8 bits.

[0046] The preset relationship is used to characterize the relationship between the effective data length and the corresponding check code length, and can be set according to the actual situation, and can be used in the form of a calculation formula, a relationship table, etc. In the actual application process, the first effective data length obtained is brought into the preset relationship to obtain the first check code length corresponding to the first direction, and the second effective data length obtained is brought into the preset relationship to obtain the second check code length corresponding to the second direction.

[0047] The position weights can be set in sequence according to the order of data bits, or can be set in sequence according to different requirements, so as to be used in subsequent check code calculations. Figure 3 As shown, position weights of non-integer powers of 2 are assigned to valid data bits, then the first position weights corresponding to each data bit along the x-direction are 3, 5, 6, 7, 9, 10, 11, and 12, and the second position weights corresponding to each data bit along the y-direction are 3, 5, 6, and 7, respectively.

[0048] The first check code corresponding to the first direction is calculated according to the data to be processed, the first valid data length, the first check code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction. The second check code is calculated according to the data to be processed, the second valid data length, the second check code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction. For example, the relationship between the data to be processed, the valid data length, the check code length, the position weight and the check code can be preset, and the first check code and the second check code are calculated and obtained during the application process. The check code corresponding to the data to be processed is jointly determined based on the first check code and the second check code. For example, the first check code and the second check code can be arranged in order to generate a check code, or the check code can be generated according to the weight calculation.

[0049] This embodiment significantly reduces the cost of encoding check bits by defining two orthogonal directions in the storage array and performing cross encoding.

[0050] According to an embodiment of the present application, the preset relationship is expressed by the following formula:

[0051] 2 m ≥b+m+1 (1)

[0052] Among them, m represents the check code length, and b represents the valid data length;

[0053] Determining a first check code length of the data to be processed based on the first valid data length and a preset relationship includes: obtaining a minimum value of the check code length that satisfies the preset relationship based on the first valid data length to obtain the first check code length; determining a second check code length of the data to be processed based on the second valid data length and a preset relationship includes: obtaining a minimum value of the check code length that satisfies the preset relationship based on the second valid data length to obtain the second check code length.

[0054] Specifically, this embodiment performs check code encoding based on the Hamming metric principle and the Berlekamp coding method. First, several symbols for orthogonal coding are defined: let the effective data length be b, the check code length be m, the total data length be n=b+m, let β=n+1, then m and β need to satisfy formula 2 m ≥β, thereby determining the preset relationship (1) satisfied by the effective data length and the check code length.

[0055] Continue with Figure 3 For example, assuming that the orthogonal coding space corresponding to the data to be processed contains a total of b y = 4 banks, each bank has a word length of b x = 8 bits. The first valid data length of the data to be processed along the x direction is b x =8, the second valid data along the y direction is by =4. At this time, the length of the first check code in the x direction needs to satisfy the inequality b x =8 is substituted into the calculation to obtain m that satisfies the inequality x The minimum value is 4, so the length of the first check code is m x =4, the total data length in the x direction is n x =12, β in the x direction x =13. Similarly, the length of the second check code in the y direction satisfies the inequality b y =4 is substituted into the calculation to obtain m that satisfies the inequality y The minimum value is 3, so the length of the second check code is m y =3, the total data length in the y direction is n y =7, β in the y direction y =8.

[0056] In one embodiment of the present application, the first check code is determined according to the data to be processed, the first valid data length, the first check code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, including: obtaining the sum of the first valid data length and the first check code length plus one to obtain a first value; obtaining the sum of the product of the data of each data bit of the data to be processed along the first direction and the corresponding first position weight to obtain a second value corresponding to each data bit of the data to be processed along the first direction; obtaining the sum of the second values ​​of each data bit of the data to be processed along the first direction to obtain a third value; obtaining the remainder between the third value and the first value to obtain a fourth value; performing binary conversion on the fourth value to obtain A first check code; determining a second check code according to the data to be processed, the second valid data length, the second check code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction, including: obtaining the sum of the second valid data length and the second check code length plus one to obtain a fifth value; obtaining the sum of the products of the data of each data bit of the data to be processed along the second direction and the corresponding second position weight to obtain a sixth value corresponding to each data bit of the data to be processed along the second direction; obtaining the sum of the sixth values ​​of each data bit of the data to be processed along the second direction to obtain a seventh value; obtaining the remainder between the seventh value and the fifth value to obtain an eighth value; performing binary conversion on the eighth value to obtain a second check code.

[0057] In the cross-coding area, the x direction is assumed to be the bit direction and the y direction is the bank direction. For a data vector, the i-th row and j-th column data are represented as d i,j , the corresponding x-direction encoding bit is expressed as The y-direction check bit is expressed as Satisfies the following formula:

[0058]

[0059] in, Indicates the first check code in decimal format, m x Indicates the first code length, represents the sth data bit in the first check code, represents the position weight of the sth data bit in the first check code, b x Indicates the first valid data length, d i,j represents the data bit in row i and column j, represents the first position weight of the data bit in the i-th row and j-th column, β x =m x +b x +1.

[0060]

[0061] in, Indicates the second check code in decimal format, m y represents the second code length, represents the tth data bit in the second check code, represents the position weight of the tth data bit in the second check code, b y Indicates the second valid data length, d i,j represents the data bit in row i and column j, a yj represents the first position weight of the data bit in the i-th row and j-th column, β y =m y +b y +1.

[0062] Therefore, continue with Figure 3 For example, according to the first valid data length b x = 8 and formula (1) to calculate the first check code length m x is 4, calculate the first value β x is 13, and the first position weights corresponding to each data bit of the data to be processed along the x direction are determined to be 3, 5, 6, 7, 9, 10, 11, and 12 in sequence. Combined with the value of each data bit of the data to be processed, it is substituted into formula (2) to calculate Convert 15 into binary form, and the first check code in the x direction is 1111.

[0063] Similarly, according to the second valid data length b y =4 and formula (1) to calculate the second check code length m y is 3, calculate the fifth value β yis 8, and the second position weights corresponding to each data bit of the to-be-processed data along the y direction are determined to be 3, 5, 6, and 7, respectively. Combined with the value of each data bit of the to-be-processed data, it is substituted into formula (3) to calculate Convert 5 into binary form, and the first check code in the y direction is 101.

[0064] In one embodiment of the present application, determining the check code of the data to be processed according to the first check code and the second check code includes: arranging the first check code and the second check code in sequence along a first direction to obtain the check code of the data to be processed.

[0065] Specifically, taking the first check code in the x-direction as 1111 and the second check code in the y-direction as 101 as an example, the check code of the data to be processed obtained by arranging 1111 and 101 in sequence along the x-axis direction is 1111101. This check code can be stored in a bank separately, such as Figure 5 As shown, the orthogonal code of the data to be processed at this time is 1111101.

[0066] In one embodiment of the present application, the verification code generation method also includes: determining the third position weight corresponding to each data bit in the first verification code based on the arrangement order of each data bit in the first verification code, and determining the fourth position weight corresponding to each data bit in the second verification code based on the arrangement order of each data bit in the second verification code; determining the target weight vector according to the first position weight corresponding to each data bit of the data to be processed along the first direction, the second position weight corresponding to each data bit of the data to be processed along the second direction, the third position weight corresponding to each data bit in the first verification code, and the fourth position weight corresponding to each data bit in the second verification code; performing data verification decoding operations based on the target weight vector.

[0067] Specifically, the position weights of the check codes can be set in sequence according to the arrangement order of the data bits, or can be set in sequence according to different requirements, so as to be used in subsequent check code calculations. Figure 3 As shown, the position weights of integer powers of 2 are assigned to each data bit of the check code in turn, then the third position weights corresponding to each data bit of the first check code in the x direction are 1, 2, 4, and 8 respectively, and the fourth position weights corresponding to each data bit of the second check code in the y direction are 1, 2, and 4 respectively.

[0068] A weight matrix is ​​constructed based on the first position weight corresponding to each data bit of the data to be processed along the first direction, the second position weight corresponding to each data bit of the data to be processed along the second direction, the third position weight corresponding to each data bit in the first check code, and the fourth position weight corresponding to each data bit in the second check code, so as to determine the target weights to be connected for decoding and checking the received data to be checked. It can be understood that the received data to be checked is data for generating a check code based on the above method.

[0069] In one embodiment of the present application, a first position weight corresponding to each data bit of the data to be processed along the first direction is determined according to the arrangement order of each data bit of the data to be processed along the first direction, including: using non-integer powers of two in positive integers in ascending order as the first position weight corresponding to each data bit of the data to be processed along the first direction; a third position weight corresponding to each data bit in the first check code is determined based on the arrangement order of each data bit in the first check code, including: using integer powers of two in positive integers in ascending order as the third position weight corresponding to each data bit in the first check code; a second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction, including: using non-integer powers of two in positive integers in ascending order as the second position weight corresponding to each data bit of the data to be processed along the second direction; a fourth position weight corresponding to each data bit in the second check code is determined based on the arrangement order of each data bit in the second check code, including: using integer powers of two in positive integers in ascending order as the fourth position weight corresponding to each data bit in the second check code.

[0070] Specifically, continue to combine Figure 3 As shown, the position weights of the data to be processed in the orthogonal coding space are 1, 2, 3, 4, ..., wherein the position weights of integer powers of 2 are assigned to the data bits of the check code, and the position weights of integer powers of 2 are assigned to the data bits of the valid data. Therefore, the first position weights corresponding to each data bit of the first valid data in the x direction are 3, 5, 6, 7, 9, 10, 11, 12, respectively, and the third position weights corresponding to each data bit of the first check code are 1, 2, 4, 8, respectively; the second position weights corresponding to each data bit of the second valid data in the y direction are 3, 5, 6, 7, respectively, and the fourth position weights corresponding to each data bit of the second check code are 1, 2, 4, respectively.

[0071] In one embodiment of the present application, a data verification decoding operation is performed based on a target weight vector, including: obtaining the data to be verified, and determining a result vector of the data to be verified, wherein the result vector includes valid data and a verification code; decoding and verifying the data to be verified according to the target weight vector and the result vector to determine the data status of the data to be verified.

[0072] Specifically, the data to be checked is the output data of the check code generated based on the above orthogonal encoding method, and the result vector read out from the data to be checked is in, is the data vector actually read out consisting of valid data, is a check code vector composed of check codes. According to the calculation results of the target weight vector and the result vector, the decoding check of the data to be checked is completed to determine whether the valid data of the data to be checked has errors.

[0073] In one embodiment of the present application, the target weight vector includes a first weight vector corresponding to a first direction and a second weight vector corresponding to a second direction, and the result vector includes a first result vector corresponding to the first direction and a second result vector corresponding to the second direction, wherein the data to be verified is decoded and verified according to the target weight vector and the result vector to determine the data state of the data to be verified, including: obtaining the product between the first result vector and the first weight vector, and the remainder between the first numerical value, to obtain the decoding result corresponding to the first direction; obtaining the product between the second result vector and the second weight vector, and the remainder between the fifth numerical value, to obtain the decoding result corresponding to the second direction; when the decoding result corresponding to the first direction and the decoding result corresponding to the second direction are both zero, it is determined that no data error has occurred in the data to be verified; when at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, it is determined that a data error has occurred in the data to be verified.

[0074] That is, the x direction and y direction are decoded respectively by the following formulas:

[0075]

[0076] in, represents the result vector, represents the target weight vector.

[0077] If the decoding result s=0, no error occurs; if s≠0, it is determined that an error occurs in the data.

[0078] For example, the data to be tested is obtained after orthogonal coding Figure 4 Take data as an example, when decoding the x direction, read the result vector The first weight vector is

[0079] β x =13, substitute into formula (4) to get Therefore, no error occurs; otherwise, the decoding result is not equal to 0, and it is determined that a data error occurs.

[0080] In one embodiment of the present application, when at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, the method also includes: when the decoding result corresponding to the first direction is any first position weight or the decoding result corresponding to the first direction is the difference between the first numerical value and any first position weight, a data error occurs in the data bit corresponding to any first position weight; when the decoding result corresponding to the second direction is any second position weight or the decoding result corresponding to the second direction is the difference between the fifth numerical value and any second position weight, a data error occurs in the data bit corresponding to any second position weight.

[0081] Specifically, continue with Figure 4 For example, assuming d′ 4,2 =1 A single bit error occurs: First decode the x direction, and read the result for each bank. For 4 data banks and 1 check bank, the vector result is Calculated Indicates the x direction The position of is wrong, corresponding to d′ 4,y . Then decode the y direction, and read out the result of each bit. For 4 data banks and 1 verification bank, Calculated Indicates the y direction The position of is wrong, corresponding to d′ 4,2 .

[0083] Thus, the data error in this embodiment is calculated by Decoding yields: If s = 0, no error occurs; if s = α k or s=β-α k ,k∈[0,b), then the data vector An error occurs at the kth bit, if s≠0ands≠α k and s≠β-α k ,k∈[0,b), it is determined that multiple bit errors have occurred.

[0084] As a specific embodiment of the present application, Figure 5 As shown, the verification code generation method may include the following steps:

[0085] S101, obtaining data to be processed, and determining a first valid data length of the data to be processed along a first direction and a second valid data length along a second direction.

[0086] S102: Acquire a minimum value of a check code length that satisfies a preset relationship based on the first valid data length to obtain a first check code length.

[0087] S103, using the non-integer powers of two in the positive integers in ascending order as the first position weight corresponding to each data bit of the data to be processed along the first direction, and using the integer powers of two in the positive integers in ascending order as the third position weight corresponding to each data bit in the first check code.

[0088] S104, obtain the sum of the first valid data length and the first check code length and add one to obtain a first value.

[0089] S105, obtaining the sum of the products of the data of each data bit of the data to be processed along the first direction and the corresponding first position weight, to obtain a second numerical value corresponding to each data bit of the data to be processed along the first direction.

[0090] S106, obtaining the sum of the second values ​​of each data bit of the data to be processed along the first direction to obtain a third value.

[0091] S107, obtaining a remainder between the third value and the first value to obtain a fourth value.

[0092] S108, perform binary conversion on the fourth value to obtain a first check code. Execute step S116.

[0093] S109, acquiring a minimum value of a check code length that satisfies a preset relationship based on the second valid data length to obtain a second check code length.

[0094] S110, the non-integer powers of two in the positive integers are used in ascending order as the second position weight corresponding to each data bit of the data to be processed along the second direction, and the integer powers of two in the positive integers are used in ascending order as the fourth position weight corresponding to each data bit in the second check code.

[0095] S111, obtain the sum of the second valid data length and the second check code length and add one to obtain a fifth value.

[0096] S112, obtaining the sum of the products of the data of each data bit of the data to be processed along the second direction and the corresponding second position weight, to obtain a sixth numerical value corresponding to each data bit of the data to be processed along the second direction.

[0097] S113, obtaining the sum of the sixth values ​​of each data bit of the data to be processed along the second direction to obtain a seventh value.

[0098] S114, obtaining a remainder between the seventh value and the fifth value to obtain an eighth value.

[0099] S115, performing binary conversion on the eighth value to obtain a second check code.

[0100] S116, arranging the first check code and the second check code in sequence along the first direction to obtain the check code of the data to be processed, and storing the check code as output data.

[0101] In addition, in the verification method of the data to be verified based on the above verification code generation verification code, Figure 6 As shown, the following steps may be included:

[0102] S201, determine the target weight vector based on the first position weight corresponding to each data bit of the data to be processed along the first direction, the second position weight corresponding to each data bit of the data to be processed along the second direction, the third position weight corresponding to each data bit in the first check code, and the fourth position weight corresponding to each data bit in the second check code.

[0103] S202, obtaining the data to be verified, and determining a result vector of the data to be verified.

[0104] S203, obtaining a product of the first result vector and the first weight vector, and a remainder thereof with respect to the first value, to obtain a decoding result corresponding to the first direction.

[0105] S204, obtaining a remainder between the product of the second result vector and the second weight vector and the fifth value, to obtain a decoding result corresponding to the second direction.

[0106] S205, determine whether the two decoding results are both zero. If so, execute step S206; if not, execute step S207.

[0107] S206, determining that no data error occurs in the data to be verified.

[0108] S207, determining that a data error occurs in the data to be verified.

[0109] Furthermore, the near-storage computing / storage computing integrated circuit includes a vector multiplication and addition circuit, and the circuit structure is as follows: Figure 7 As shown, during the decoding process The calculation can be realized by multiplexing the multiplication and addition circuit. In addition to the multiplication and addition calculation, an additional modulus circuit needs to be designed. The circuit architecture is as follows Figure 8 In addition, in the near-storage computing / storage-computing integrated circuit, fixed weight data is usually stored in the storage array. Since there is data reuse in neural network calculations, a data stream with fixed weights can be used for calculations. A weight vector taken out will be multiplied and added with multiple groups of data vectors. Therefore, the verification and decoding process only needs to be performed once when the weight vector is taken out, and multiple repeated calculations can be performed after the error is corrected.

[0110] Based on the positional relationship between the computing circuit and the storage array, the computing architecture can be roughly divided into two types: near-memory computing and integrated computing and storage. Figure 7 In the figure, the multiplication and addition circuit shows a typical circuit architecture of near-memory computing. The storage body can be DRAM (Dynamic Random Access Memory), RRAM (Resistive Random Access Memory), SRAM (Static Random Access Memory), etc. The multiplication and addition calculation circuit is very close to the bank, which can increase the bandwidth of data transmission and reduce the power consumption of data transmission. In addition, in the integrated storage and computing circuit architecture, the calculation circuit is built into the bank and is located before the SA (DRAM Sense Amplifier) ​​readout circuit. Multiplication can be achieved by multipliers or accumulation, and addition can be spatial domain addition (such as Fig. 9 As shown in a), it can also be time domain addition (as shown in Fig. 9 In addition, in the multiplication and addition circuit based on the in-situ computing architecture of the new storage, it usually uses basic physical laws, such as Ohm's law and Kirchhoff's current law to realize multiplication and addition. The circuit setting can be made according to the actual situation, and there is no specific limitation.

[0111] The present application provides an orthogonal coding verification method and decoding implementation based on vector multiplication and addition. By defining two orthogonal directions in a storage array and cross-coding them, the cost of the coding check bits is significantly reduced, so that it can be applied to the fault tolerance characteristics of AI algorithms; the AI ​​computing chip based on the near-memory computing / storage-computing integrated architecture contains parallel multiplication-addition circuits near or inside the storage module, which can realize the reuse of computing units. By combining the dot product-based decoding method with the circuit modules in the near-memory computing / storage-computing integrated architecture, the multiplication-addition circuits are reused to reduce the decoding cost; there is data reuse in AI computing, and not every calculation requires ECC (Error Checking and Correcting) verification. The error detection process needs to be combined with the computing data stream. This embodiment provides an orthogonal decoding process embedded in the computing data stream. The encoding method and its corresponding circuit have the advantages of fewer encoding bits and less hardware overhead.

[0112] In summary, according to the verification code generation method of the embodiment of the present application, first, the data to be processed is obtained, and the first valid data length of the data to be processed along the first direction and the second valid data length along the second direction are determined, wherein the first direction is perpendicular to the second direction, the first verification code length of the data to be processed is determined based on the first valid data length and a preset relationship, the second verification code length of the data to be processed is determined based on the second valid data length and a preset relationship, the first position weight corresponding to each data bit of the data to be processed along the first direction is determined according to the arrangement order of each data bit of the data to be processed along the first direction, and the second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction, then, the first verification code is determined according to the data to be processed, the first valid data length, the first verification code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and the second verification code is determined according to the data to be processed, the second valid data length, the second verification code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction, so as to determine the verification code of the data to be processed based on the first verification code and the second verification code. Therefore, the method significantly reduces the cost of encoding check bits and reduces the cost of generating check codes by defining two orthogonal directions in the storage array and performing cross-coding.

[0113] Corresponding to the above embodiment, the present application also proposes a verification code generating device.

[0114] like Fig.10 As shown, the verification code generating device of the embodiment of the present application may include: an acquisition module 10, a first determination module 20, a second determination module 30, a third determination module 40 and a fourth determination module 50.

[0115] Among them, the acquisition module 10 is used to acquire the data to be processed, and determine the first valid data length of the data to be processed along the first direction and the second valid data length along the second direction, wherein the first direction is perpendicular to the second direction. The first determination module 20 is used to determine the first check code length of the data to be processed based on the first valid data length and the preset relationship, and determine the second check code length of the data to be processed based on the second valid data length and the preset relationship. The second determination module 30 is used to determine the first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction, and determine the second position weight corresponding to each data bit of the data to be processed along the second direction according to the arrangement order of each data bit of the data to be processed along the second direction. The third determination module 40 is used to determine the first check code according to the data to be processed, the first valid data length, the first check code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and determine the second check code according to the data to be processed, the second valid data length, the second check code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction. The fourth determination module 50 is used to determine the check code of the data to be processed according to the first check code and the second check code.

[0116] According to an embodiment of the present application, the preset relationship is expressed by the following formula:

[0117] 2 m ≥b+m+1

[0118] Among them, m represents the check code length, and b represents the valid data length;

[0119] The first determination module 20 determines the first check code length of the data to be processed based on the first valid data length and the preset relationship, and is specifically used to: obtain the minimum value of the check code length that satisfies the preset relationship based on the first valid data length to obtain the first check code length; the first determination module 20 determines the second check code length of the data to be processed based on the second valid data length and the preset relationship, and is specifically used to: obtain the minimum value of the check code length that satisfies the preset relationship based on the second valid data length to obtain the second check code length.

[0120] According to one embodiment of the present application, the third determination module 40 determines the first check code according to the data to be processed, the first valid data length, the first check code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and is specifically used to: obtain the sum of the first valid data length and the first check code length plus one to obtain a first value; obtain the sum of the product of the data of each data bit of the data to be processed along the first direction and the corresponding first position weight to obtain a second value corresponding to each data bit of the data to be processed along the first direction; obtain the sum of the second values ​​of each data bit of the data to be processed along the first direction to obtain a third value; obtain the remainder between the third value and the first value to obtain a fourth value; perform binary conversion on the fourth value to obtain The first check code; the third determination module 40 determines the second check code according to the data to be processed, the second valid data length, the second check code length and the second position weight corresponding to each data bit of the data to be processed along the second direction, and is specifically used for: obtaining the sum of the second valid data length and the second check code length plus one to obtain a fifth value; obtaining the sum of the products of the data of each data bit of the data to be processed along the second direction and the corresponding second position weight to obtain a sixth value corresponding to each data bit of the data to be processed along the second direction; obtaining the sum of the sixth values ​​of each data bit of the data to be processed along the second direction to obtain a seventh value; obtaining the remainder between the seventh value and the fifth value to obtain an eighth value; performing binary conversion on the eighth value to obtain the second check code.

[0121] According to an embodiment of the present application, the fourth determination module 50 determines the verification code of the data to be processed according to the first verification code and the second verification code, and is specifically used to: arrange the first verification code and the second verification code in sequence along the first direction to obtain the verification code of the data to be processed.

[0122] According to one embodiment of the present application, the verification code generating device also includes a decoding and verification module, wherein the second determination module 30 is also used to: determine the third position weight corresponding to each data bit in the first verification code based on the arrangement order of each data bit in the first verification code, and determine the fourth position weight corresponding to each data bit in the second verification code based on the arrangement order of each data bit in the second verification code; determine the target weight vector according to the first position weight corresponding to each data bit of the data to be processed along the first direction, the second position weight corresponding to each data bit of the data to be processed along the second direction, the third position weight corresponding to each data bit in the first verification code, and the fourth position weight corresponding to each data bit in the second verification code; the decoding and verification module is used to perform data verification decoding operations based on the target weight vector.

[0123] According to one embodiment of the present application, the second determination module 30 determines the first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction, and is specifically used to: use the non-integer power of two in the positive integers in order from small to large as the first position weight corresponding to each data bit of the data to be processed along the first direction; the second determination module 30 determines the third position weight corresponding to each data bit in the first check code based on the arrangement order of each data bit in the first check code, and is specifically used to: use the integer power of two in the positive integers in order from small to large as the third position weight corresponding to each data bit of the first check code three position weights; the second determination module 30 determines the second position weight corresponding to each data bit of the data to be processed along the second direction according to the arrangement order of each data bit of the data to be processed along the second direction, specifically for: using the non-integer powers of two in the positive integers in ascending order as the second position weight corresponding to each data bit of the data to be processed along the second direction; the second determination module 30 determines the fourth position weight corresponding to each data bit in the second check code based on the arrangement order of each data bit in the second check code, specifically for: using the integer powers of two in the positive integers in ascending order as the fourth position weight corresponding to each data bit in the second check code.

[0124] According to one embodiment of the present application, the decoding and verification module performs a data verification decoding operation based on a target weight vector, and is specifically used to: obtain the data to be verified, and determine a result vector of the data to be verified, wherein the result vector includes valid data and a verification code; and decode and verify the data to be verified according to the target weight vector and the result vector to determine the data status of the data to be verified.

[0125] According to one embodiment of the present application, the target weight vector includes a first weight vector corresponding to a first direction and a second weight vector corresponding to a second direction, and the result vector includes a first result vector corresponding to the first direction and a second result vector corresponding to the second direction, wherein the decoding and verification module decodes and verifies the data to be verified according to the target weight vector and the result vector to determine the data state of the data to be verified, and is specifically used for: obtaining the product between the first result vector and the first weight vector, and the remainder between the first numerical value, to obtain the decoding result corresponding to the first direction; obtaining the product between the second result vector and the second weight vector, and the remainder between the fifth numerical value, to obtain the decoding result corresponding to the second direction; when the decoding result corresponding to the first direction and the decoding result corresponding to the second direction are both zero, it is determined that no data error has occurred in the data to be verified; when at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, it is determined that a data error has occurred in the data to be verified.

[0126] According to one embodiment of the present application, when at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, the decoding verification module is also used for: when the decoding result corresponding to the first direction is any first position weight or the decoding result corresponding to the first direction is the difference between the first numerical value and any first position weight, a data error occurs in the data bit corresponding to any first position weight; when the decoding result corresponding to the second direction is any second position weight or the decoding result corresponding to the second direction is the difference between the fifth numerical value and any second position weight, a data error occurs in the data bit corresponding to any second position weight.

[0127] It should be noted that for details not disclosed in the verification code generation device of the embodiment of the present application, please refer to the details disclosed in the verification code generation method of the above embodiment of the present application, and the details will not be repeated here.

[0128] According to the verification code generating device of the embodiment of the present application, the data to be processed is acquired by the acquisition module, and the first valid data length of the data to be processed along the first direction and the second valid data length along the second direction are determined, wherein the first direction is perpendicular to the second direction, the first verification code length of the data to be processed is determined by the first determination module based on the first valid data length and a preset relationship, and the second verification code length of the data to be processed is determined based on the second valid data length and a preset relationship, the first position weight corresponding to each data bit of the data to be processed along the first direction is determined by the second determination module according to the arrangement order of each data bit of the data to be processed along the first direction, and the second position weight corresponding to each data bit of the data to be processed along the second direction is determined according to the arrangement order of each data bit of the data to be processed along the second direction, the first verification code is determined by the third determination module according to the data to be processed, the first valid data length, the first verification code length, and the first position weight corresponding to each data bit of the data to be processed along the first direction, and the second verification code is determined according to the data to be processed, the second valid data length, the second verification code length, and the second position weight corresponding to each data bit of the data to be processed along the second direction, and the fourth determination module determines the verification code of the data to be processed according to the first verification code and the second verification code. Therefore, the device significantly reduces the cost of encoding check bits and reduces the cost of generating check codes by defining two orthogonal directions in the storage array and performing cross-coding.

[0129] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0130] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0131] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0132] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0133] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0134] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A verification code generation method, characterized in that: The method comprises: Acquire data to be processed, and determine a first valid data length of the data to be processed along a first direction and a second valid data length along a second direction, wherein the first direction is perpendicular to the second direction; Determine a first check code length of the data to be processed based on the first valid data length and a preset relationship, and determine a second check code length of the data to be processed based on the second valid data length and the preset relationship; Determine a first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction, and determine a second position weight corresponding to each data bit of the data to be processed along the second direction according to the arrangement order of each data bit of the data to be processed along the second direction; Determine a first check code according to the data to be processed, the first valid data length, the first check code length, and a first position weight corresponding to each data bit of the data to be processed along a first direction, and determine a second check code according to the data to be processed, the second valid data length, the second check code length, and a second position weight corresponding to each data bit of the data to be processed along a second direction; A check code for the data to be processed is determined according to the first check code and the second check code.

2. The verification code generation method according to claim 1, characterized in that: The preset relationship is expressed by the following formula: 2 m ≥b+m+1 Among them, m represents the check code length, and b represents the valid data length; The determining the first check code length of the data to be processed based on the first valid data length and a preset relationship includes: Acquire a minimum value of a check code length that satisfies the preset relationship based on the first valid data length to obtain the first check code length; The determining the second check code length of the data to be processed based on the second valid data length and the preset relationship includes: A minimum value of a check code length that satisfies the preset relationship is acquired based on the second valid data length to obtain the second check code length.

3. The verification code generation method according to claim 1, characterized in that: The determining the first check code according to the data to be processed, the first valid data length, the first check code length, and a first position weight corresponding to each data bit of the data to be processed along the first direction includes: Obtain a sum of the first valid data length and the first check code length and add one to obtain a first value; Obtaining the sum of the products of the data of each data bit of the data to be processed along the first direction and the corresponding first position weight, to obtain a second numerical value corresponding to each data bit of the data to be processed along the first direction; Obtaining the sum of the second values ​​of each data bit of the to-be-processed data along the first direction to obtain a third value; Obtaining a remainder between the third value and the first value to obtain a fourth value; Performing binary conversion on the fourth value to obtain the first check code; The determining the second check code according to the data to be processed, the second valid data length, the second check code length, and a second position weight corresponding to each data bit of the data to be processed along the second direction includes: Obtain a sum of the second valid data length and the second check code length and add one to obtain a fifth value; Obtaining the sum of the products of the data of each data bit of the data to be processed along the second direction and the corresponding second position weight, to obtain a sixth value corresponding to each data bit of the data to be processed along the second direction; Obtaining the sum of the sixth values ​​of each data bit of the to-be-processed data along the second direction to obtain a seventh value; Obtaining a remainder between the seventh value and the fifth value to obtain an eighth value; The eighth value is converted into binary to obtain the second check code.

4. The verification code generation method according to claim 3, characterized in that: The determining the check code of the to-be-processed data according to the first check code and the second check code comprises: The first check code and the second check code are arranged in sequence along the first direction to obtain the check code of the data to be processed.

5. The verification code generation method according to claim 4, characterized in that: The method further comprises: Determine a third position weight corresponding to each data bit in the first check code based on the arrangement order of each data bit in the first check code, and determine a fourth position weight corresponding to each data bit in the second check code based on the arrangement order of each data bit in the second check code; Determine a target weight vector according to a first position weight corresponding to each data bit of the to-be-processed data along the first direction, a second position weight corresponding to each data bit of the to-be-processed data along the second direction, a third position weight corresponding to each data bit in the first check code, and a fourth position weight corresponding to each data bit in the second check code; A data check decoding operation is performed based on the target weight vector.

6. The verification code generation method according to claim 5, characterized in that: The step of determining a first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction comprises: Sequentially, in ascending order, non-integer powers of two in the positive integers are used as first position weights corresponding to each data bit of the to-be-processed data along the first direction; The determining, based on the arrangement order of each data bit in the first check code, a third position weight corresponding to each data bit in the first check code includes: In order from small to large, the integer powers of two in the positive integers are used as the third position weight corresponding to each data bit in the first check code; The determining, according to the arrangement order of each data bit of the data to be processed along the second direction, the second position weight corresponding to each data bit of the data to be processed along the second direction comprises: Sequentially, in ascending order, non-integer powers of two in the positive integers are used as second position weights corresponding to each data bit of the to-be-processed data along the second direction; The determining, based on the arrangement order of each data bit in the second check code, a fourth position weight corresponding to each data bit in the second check code includes: The integer powers of two in the positive integers are sequentially used in ascending order as the fourth position weight corresponding to each data bit in the second check code.

7. The verification code generation method according to claim 5, characterized in that: The performing a data verification decoding operation based on the target weight vector includes: Acquire the data to be verified, and determine a result vector of the data to be verified, wherein the result vector includes valid data and a verification code; The data to be verified is decoded and verified according to the target weight vector and the result vector to determine the data status of the data to be verified.

8. The verification code generation method according to claim 7, characterized in that: The target weight vector includes a first weight vector corresponding to the first direction and a second weight vector corresponding to the second direction, and the result vector includes a first result vector corresponding to the first direction and a second result vector corresponding to the second direction, wherein decoding and verifying the data to be verified according to the target weight vector and the result vector to determine the data state of the data to be verified includes: Obtain a remainder between the product of the first result vector and the first weight vector and the first value, to obtain a decoding result corresponding to the first direction; Obtain a remainder between the product of the second result vector and the second weight vector and the fifth value to obtain a decoding result corresponding to the second direction; When the decoding result corresponding to the first direction and the decoding result corresponding to the second direction are both zero, determining that no data error occurs in the data to be verified; When at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, it is determined that a data error occurs in the data to be checked.

9. The verification code generation method according to claim 8, characterized in that: When at least one of the decoding result corresponding to the first direction and the decoding result corresponding to the second direction is not zero, the method further includes: When the decoding result corresponding to the first direction is any one of the first position weights or the decoding result corresponding to the first direction is the difference between the first value and any one of the first position weights, a data error occurs in the data bit corresponding to the any one of the first position weights; When the decoding result corresponding to the second direction is any second position weight or the decoding result corresponding to the second direction is the difference between the fifth value and any second position weight, a data error occurs in the data bit corresponding to the any second position weight.

10. A verification code generating device, characterized in that: The device comprises: An acquisition module, used for acquiring data to be processed, and determining a first valid data length of the data to be processed along a first direction and a second valid data length along a second direction, wherein the first direction is perpendicular to the second direction; A first determination module, configured to determine a first check code length of the data to be processed based on the first valid data length and a preset relationship, and to determine a second check code length of the data to be processed based on the second valid data length and the preset relationship; A second determination module is used to determine a first position weight corresponding to each data bit of the data to be processed along the first direction according to the arrangement order of each data bit of the data to be processed along the first direction, and to determine a second position weight corresponding to each data bit of the data to be processed along the second direction according to the arrangement order of each data bit of the data to be processed along the second direction; A third determination module is used to determine a first check code according to the data to be processed, the first valid data length, the first check code length, and a first position weight corresponding to each data bit of the data to be processed along the first direction, and to determine a second check code according to the data to be processed, the second valid data length, the second check code length, and a second position weight corresponding to each data bit of the data to be processed along the second direction; A fourth determination module is used to determine the check code of the data to be processed according to the first check code and the second check code.

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