Expansion method of Ethernet interface

Abstract

The invention discloses an expansion method of an Ethernet interface. The expansion method of the Ethernet interface comprises the steps that an MAC interface of a main processor is connected to an FPGA, a plurality of MAC layers are simulated through the FPGA to form a plurality of simulated MAC interfaces, one MAC interface of the main processor corresponds to the plurality of simulated MAC interfaces, each simulated MAC interface is suitable for being connected with only one physical layer chip, and each physical layer chip is suitable for being connected with one physical layer chip; one physical layer chip only corresponds to one Ethernet interface, so that one MAC interface of the main processor corresponds to a plurality of Ethernet interfaces through a plurality of analog MAC interfaces. Therefore, the expansion method of the Ethernet interface can realize the interface expansion of the Ethernet under the condition that the hardware structure of the processor is not changed, so that the processor with a single MAC interface can be applied to a scene needing two or more than two paths of Ethernet, and the requirement on the MAC interface of the processor is reduced.

Description

Technical Field

[0001] The present application relates to the field of Ethernet, and in particular to a method for extending an Ethernet interface. Background Art

[0002] In the field of industrial control, Ethernet protocol is widely used. There are many chips with hardware support for Ethernet applications. At present, among the mainstream products of many manufacturers, chips that support Ethernet application solutions generally have an Ethernet media access control (MAC) interface. A few chips have two Ethernet MAC interfaces. Chips with two Ethernet MAC interfaces are often more expensive, and chips with more than two Ethernet MAC interfaces are very rare.

[0003] In actual applications, field control networks often use redundant links, which requires the hardware to support two or more Ethernet channels. Ordinary hardware solutions can hardly meet application requirements. Summary of the invention

[0004] One advantage of the present application is that it provides a method for expanding an Ethernet interface, wherein the method for expanding the Ethernet interface can realize Ethernet interface expansion without changing the hardware structure of the processor, so that a processor with only a single MAC interface can be applied to scenarios requiring two or more Ethernet networks, thereby reducing the requirements for the processor's MAC interface, and further reducing the difficulty of hardware selection and hardware costs.

[0005] According to one aspect of the present application, a method for extending an Ethernet interface is provided, comprising the steps of: connecting a MAC interface of a main processor to an FPGA, and simulating multiple MAC layers through the FPGA to form multiple simulated MAC interfaces, wherein one MAC interface of the main processor corresponds to multiple simulated MAC interfaces, and each simulated MAC interface is suitable for being connected to only one physical layer chip, and one physical layer chip corresponds to only one Ethernet interface, so that one MAC interface of the main processor corresponds to multiple Ethernet interfaces through multiple simulated MAC interfaces; and transmitting data between the FPGA and the main processor, wherein, in the process of transmitting data between the FPGA and the main processor, the data transmitted between the FPGA and the main processor is marked, and the simulated MAC interface corresponding to the data transmitted between the FPGA and the main processor is identified by the mark carried by the data transmitted between the FPGA and the main processor.

[0006] In one embodiment of the Ethernet interface expansion method described in the present application, during the process of the main processor transmitting data to the FPGA, the data transmitted by the main processor to the FPGA is distributed and marked to generate at least one portion of distributed data with a mark, wherein the mark in the distributed data with a mark is used to characterize the analog MAC interface corresponding to the distributed data with a mark; the distributed data with a mark is transmitted to the corresponding analog MAC interface; during the process of the FPGA transmitting data to the main processor, the data transmitted by at least one of the analog MAC interfaces of the FPGA to the main processor is marked by a data processing unit of the FPGA to generate at least one portion of marked data; the marked data is sent to the main processor through a data transceiver interface of the FPGA; and the analog MAC interface corresponding to the marked data is determined by the main processor.

[0007] In one embodiment of the Ethernet interface expansion method described in the present application, the data received by the FPGA from the main processor includes verification information. In the process of the main processor transmitting data to the FPGA, after the FPGA receives the data from the main processor, a confirmation signal is sent to the main processor through the FPGA; if the main processor receives the confirmation signal, it is determined that effective transmission is possible between the FPGA and the main processor; when it is determined that effective transmission is possible between the FPGA and the main processor, the FPGA determines whether the data received from the main processor is complete based on the verification information, and if the verification information is correct, it is determined that the data received by the FPGA from the main processor is complete; when it is determined that effective transmission is possible between the FPGA and the main processor and the data received by the FPGA from the main processor is complete, it is determined whether the FPGA correctly transmits the marked allocated data to the corresponding analog MAC interface.

[0008] In one implementation of the Ethernet interface expansion method according to the present application, the Ethernet interface expansion method further includes the step of: configuring and monitoring the FPGA and lower-level chips by the main processor.

[0009] In one implementation of the Ethernet interface expansion method described in the present application, during the process of configuring and monitoring the FPGA and the lower-level chips through the main processor, a control interface of the FPGA is connected to an I / O interface of the main processor; a state control unit of the FPGA is communicatively connected to the control interface and the analog MAC interface; when the state control unit of the FPGA receives a control signal from the main processor, the lower-level chip of the FPGA is configured, and the working status of the lower-level chip of the FPGA and the corresponding analog MAC interface is queried; and the working status of the lower-level chip of the FPGA and the corresponding analog MAC interface is then fed back to the main processor.

[0010] In one embodiment of the Ethernet interface expansion method described in the present application, during the process of configuring and monitoring the FPGA and the lower-level chip by the main processor, when the working status of the lower-level chip of the FPGA and the corresponding working status of the analog MAC interface are both normal, data transmission is performed through the MAC interface of the main processor and the analog MAC interface of the FPGA.

[0011] In one embodiment of the Ethernet interface expansion method described in the present application, during the process of configuring and monitoring the FPGA and the lower-level chips through the main processor, if the communication between the main processor and the FPGA is interrupted or erroneous, the simulated MAC interface is restarted and the lower-level chips of the FPGA are reconfigured.

[0012] Further objectives and advantages of the present application will be fully reflected through understanding of the following description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0014] Figure 1 The figure illustrates a schematic diagram of the architecture block diagram of the FPGA and the main processor in the Ethernet interface expansion method according to an embodiment of the present application.

[0015] Figure 2 A flowchart schematic diagram of a method for extending an Ethernet interface according to an embodiment of the present application is illustrated.

[0016] Figure 3The figure illustrates a flowchart schematic diagram of a step of a method for extending an Ethernet interface according to an embodiment of the present application.

[0017] Figure 4 A flowchart schematic diagram of another step of the method for extending the Ethernet interface according to an embodiment of the present application is illustrated. DETAILED DESCRIPTION

[0018] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0019] It is understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "one" cannot be understood as a limitation on the number. "Multiple" means greater than or equal to two.

[0020] Although ordinals such as "first," "second," and the like will be used to describe various components, those components are not limited herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component without departing from the teachings of the present application. The term "and / or" as used herein includes any and all combinations of one or more associated listed items.

[0021] The terms used herein are only used for the purpose of describing various embodiments and are not intended to be limiting. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates an exception. It will also be understood that the terms "including" and / or "having" when used in this specification specify the presence of the described features, numbers, operations, components, elements, or combinations thereof, without excluding the presence or addition of one or more other features, numbers, operations, components, elements, or combinations thereof.

[0022] In Ethernet applications, a physical layer chip is usually connected to a MAC interface, and one physical layer chip corresponds to one Ethernet interface. This configuration method meets most usage scenarios. In application cases that require multiple Ethernet interfaces, it is generally necessary to select a processor with the same number of MAC interfaces as the number of Ethernet interfaces to improve the processor level. The performance parameters of processors with multiple MAC ports are improved, but the corresponding hardware cost will increase, and it will also bring a series of problems such as complex hardware development.

[0023] Considering that Field Programmable Gate Array (FPGA) has high programmability and parallel processing capabilities, the present application proposes to expand the Ethernet interface by connecting the media access control (MAC) interface of the main processor to the FPGA.

[0024] Specifically, multiple MAC layers are simulated by the FPGA to form multiple simulated MAC interfaces, wherein each simulated MAC interface is suitable for connecting to only one physical layer chip, and one physical layer chip corresponds to only one Ethernet interface, so that one MAC interface of the main processor corresponds to multiple Ethernet interfaces, for example, three Ethernet interfaces, through multiple simulated MAC interfaces. In this way, the present application implements the expansion of the MAC interface through the FPGA, and then realizes the expansion of the Ethernet interface under the hardware parameters of the main processor with the same performance, so that the main processor with a single MAC interface meets the application scenario requiring multiple independent Ethernet interfaces.

[0025] like Figures 1 to 4 As shown, the expansion method of the Ethernet interface according to the embodiment of the present application is explained. Figure 1 and 2 As shown, the Ethernet interface expansion method includes the steps of: S110, connecting the MAC interface of the main processor to the FPGA, and simulating multiple MAC layers through the FPGA to form multiple simulated MAC interfaces, wherein one MAC interface of the main processor corresponds to multiple simulated MAC interfaces, and each simulated MAC interface is suitable for connecting to only one physical layer chip, and one physical layer chip corresponds to only one Ethernet interface, so that one MAC interface of the main processor corresponds to multiple Ethernet interfaces through multiple simulated MAC interfaces.

[0026] In step S110, each physical layer chip corresponds to an independent Ethernet interface. The FPGA configures an independent MAC address for each of the simulated MAC interfaces, and provides an independent MAC address and corresponding control logic for each of the Ethernet interfaces to ensure that each of the simulated MAC interfaces works independently of each other, and each of the Ethernet interfaces works independently of each other.

[0027] In one embodiment of the present application, Figure 1 As shown, one MAC interface 11 of the main processor 10 corresponds to the three simulated MAC interfaces of the FPGA 20, and further corresponds to three Ethernet interfaces; wherein the three simulated MAC interfaces are: a first simulated MAC interface 201, a second simulated MAC interface 202 and a third simulated MAC interface 203.

[0028] It is worth mentioning that, considering that one MAC interface of the main processor corresponds to multiple analog MAC interfaces of the FPGA, problems such as data transmission confusion, loss, and repeated transmission may occur during data transmission between the FPGA and the main processor. The present application proposes a data transmission mechanism: marking the transmission data, identifying the analog MAC interface corresponding to the transmission data by marking, so as to carry out bidirectional data transmission between the FPGA and the main processor in an orderly manner.

[0029] Correspondingly, the expansion method of the Ethernet interface also includes step S120, transmitting data between the FPGA and the main processor, wherein, in the process of transmitting data between the FPGA and the main processor, the data transmitted between the FPGA and the main processor is marked, and the analog MAC interface corresponding to the data transmitted between the FPGA and the main processor is identified by the mark carried by the data transmitted between the FPGA and the main processor.

[0030] Specifically, Figure 1 As shown, the FPGA 20 includes at least one data transceiver interface 21 and a data processing unit 22. The data transceiver interface 21 can be communicatively connected to the MAC interface 11 of the main processor 10; the data processing unit 22 can be communicatively connected to the data transceiver interface 21 and the analog MAC interface.

[0031] In the process of transmitting data from the main processor to the FPGA, the data transmitted from the main processor to the FPGA is distributed by the main processor to generate at least one distributed data, and each distributed data is marked to obtain at least one distributed data with a mark, wherein the mark in the marked distributed data is used to characterize the analog MAC interface corresponding to the marked distributed data; the marked distributed data is received by the data transceiver interface, and the mark in the marked distributed data is judged by the data processing unit, and the marked distributed data is transmitted to the corresponding analog MAC interface based on the judgment result of the mark in the marked distributed data.

[0032] For example, in the process of transmitting data from the main processor to the FPGA, the data transmitted by the main processor to the FPGA is distributed by the main processor to generate three distributed data, and each of the distributed data is marked to obtain three distributed data with marks; the three distributed data with marks are received through the data transceiver interface, wherein the three distributed data with marks are: the first distributed data with marks, the second distributed data with marks and the third distributed data with marks; the mark in the first distributed data with marks indicates that the first distributed data with marks corresponds to the first analog MAC interface. port; the mark in the second portion of the tagged allocated data indicates that the second portion of the tagged allocated data corresponds to the second simulated MAC interface; the mark in the third portion of the tagged allocated data indicates that the third portion of the tagged allocated data corresponds to the third simulated MAC interface; the marks in the three portions of the tagged allocated data are judged by the data processing unit, and based on the judgment result of the marks in the tagged allocated data, the first portion of the tagged allocated data, the second portion of the tagged allocated data and the third portion of the tagged allocated data are transmitted to the first simulated MAC interface, the simulated MAC interface and the third simulated MAC interface respectively.

[0033] During the process of transmitting data from the FPGA to the main processor, the data transmitted from at least one of the analog MAC interfaces of the FPGA to the main processor is marked by the data processing unit of the FPGA to generate at least one piece of marked data; the marked data is sent to the main processor through the data transceiver interface of the FPGA; and the analog MAC interface corresponding to the marked data is determined by the main processor.

[0034] Accordingly, if Figure 3As shown, step S120 includes the steps of: S121, in the process of the main processor transmitting data to the FPGA, allocating and marking the data transmitted by the main processor to the FPGA to generate at least one portion of the allocated data with a mark, wherein the mark in the allocated data with a mark is used to characterize the analog MAC interface corresponding to the allocated data with a mark; transmitting the allocated data with a mark to the corresponding analog MAC interface; and S122, in the process of the FPGA transmitting data to the main processor, marking the data transmitted by at least one of the analog MAC interfaces of the FPGA to the main processor through a data processing unit of the FPGA to generate at least one portion of the marked data; sending the marked data to the main processor through a data transceiver interface of the FPGA; and determining the analog MAC interface corresponding to the marked data through the main processor.

[0035] It is worth mentioning that in the process of marking and forwarding data packets, it is necessary to ensure that the data packets are not tampered with and accurately mark the correct interface information. Any marking error or marking recognition error may cause the data to be sent to the wrong destination or cannot be correctly parsed. Ensure that the data integrity and correctness are maintained during the process of transmitting data between the FPGA and the main processor and marking the data. The present application sets up a judgment mechanism, first, to judge the validity of the transmission between the FPGA and the main processor, then to judge the integrity of the transmitted data, and finally to judge the accuracy of data distribution.

[0036] In the process of judging the validity of the transmission between the FPGA and the main processor, it is mainly judged whether the FPGA and the main processor can communicate normally and transmit data. Specifically, when the FPGA receives the data from the main processor, a confirmation signal is sent to the main processor through the FPGA; if the main processor receives the confirmation signal, it is judged that the data from the main processor has been received by the FPGA, and the FPGA and the main processor can be effectively transmitted; if the main processor does not receive the confirmation signal, it is judged that the data from the main processor has not been received by the FPGA; there is no effective transmission between the FPGA and the main processor; the data is resent to the FPGA through the main processor.

[0037] After determining that the FPGA and the main processor can effectively transmit data, the integrity of the transmitted data is determined. In the process of determining the integrity of the transmitted data, it is mainly determined whether the data transmitted between the FPGA and the main processor is complete and not lost or damaged. Specifically, the data received by the FPGA from the main processor includes verification information, and the FPGA determines whether the data received from the main processor is complete based on the verification information. If the verification information is correct, it is determined that the data received by the FPGA from the main processor is complete, otherwise it is determined that the data received by the FPGA from the main processor is incomplete; the data is resent to the FPGA by the main processor.

[0038] When it is determined that the FPGA and the main processor can be effectively transmitted and the data received by the FPGA from the main processor is complete, the accuracy of data allocation is determined. In the process of determining the accuracy of data allocation, it is mainly determined whether the FPGA correctly transmits the marked allocated data to the corresponding analog MAC interface.

[0039] Accordingly, if Figure 4 As shown, step S121 includes the steps of: S1211, when the FPGA receives the data from the main processor, sending a confirmation signal to the main processor through the FPGA; if the main processor receives the confirmation signal, determining that the FPGA and the main processor can be effectively transmitted; S1212, when it is determined that the FPGA and the main processor can be effectively transmitted, determining whether the data received from the main processor is complete based on the verification information through the FPGA, if the verification information is correct, determining that the data received from the main processor by the FPGA is complete; and, S1213, when it is determined that the FPGA and the main processor can be effectively transmitted and the data received from the main processor by the FPGA is complete, determining whether the FPGA correctly transmits the marked allocated data to the corresponding analog MAC interface.

[0040] It is worth mentioning that in the embodiment of the present application, the main processor configures and controls the status of the lower-level chip through the FPGA to further reduce the resource requirements of the hardware interface of the main processor and reduce hardware costs. At the same time, compared with directly configuring its lower-level chips through the main processor, the main processor configures the lower-level chips through FPGA to reduce hardware startup time, shorten hardware startup configuration time, and reduce the impact of complex timing problems of hardware interfaces.

[0041] Regarding the main processor configuring the lower-level chip through FPGA, it can reduce the hardware startup time. On the one hand, FPGA has a high degree of parallel processing capability and can execute multiple tasks simultaneously internally. This means that the FPGA can initialize and configure multiple lower-level chips (such as Ethernet physical layer chips) concurrently, without having to configure each lower-level chip one by one in sequence like the main processor. On the other hand, since the FPGA can be directly connected to the lower-level chip and implements the necessary control logic inside it, it can immediately respond to the signal from the main processor and start the configuration process without the intervention of the main processor or waiting for bus resources. On the other hand, the FPGA can quickly load the pre-set configuration data into its internal memory after power-on. These data include specific configuration parameters for each lower-level chip. Once the startup signal is received, these configurations can be quickly applied without waiting for a long hardware startup time, reducing the time delay for obtaining configuration information from the main processor.

[0042] Regarding the main processor configuring the lower-level chip through FPGA, it can reduce the impact of complex timing problems of the hardware interface. On the one hand, FPGA allows developers to accurately define and adjust the timing requirements for interaction with external devices. The lower-level chips of different manufacturers may have different timing specifications. Using FPGA, key timing parameters such as clock frequency, data setup time and hold time can be flexibly adjusted according to specific needs to ensure compatibility and stability. If the main processor is directly responsible for the initialization of all peripherals, it is necessary to write complex drivers to manage various timing requirements. This not only increases the workload of software development, but also may lead to performance bottlenecks. Transferring this part of the function to FPGA can enable the main processor to focus on higher-level task processing and improve the efficiency of the overall system. On the other hand, FPGA, as an intermediate layer, can effectively isolate the complex interaction details between the main processor and the lower-level chip. In this way, even if the lower-level chip changes (for example, a different model of physical layer chip is replaced), only the relevant modules inside the FPGA need to be modified, without changing the code on the main processor.

[0043] Correspondingly, the Ethernet interface expansion method further includes step S130, configuring and monitoring the FPGA and lower-level chips by the main processor.

[0044] Specifically, in the embodiment of the present application, the main processor includes an input / output (I / O) interface. Figure 1As shown, the FPGA 20 further includes a control interface 23 and a state control unit 24. The control interface 23 is communicably connected to the I / O interface 12 of the main processor 10. The state control unit 24 is communicably connected to the control interface 23 and the analog MAC interface.

[0045] In an embodiment of the present application, in the process of configuring and monitoring the FPGA and the lower-level chips by the main processor, the main processor configures and monitors the status of the FPAG; the FPAG configures and monitors its lower-level chips; the main processor configures and monitors the lower-level chips of the FPGA; and the FPGA provides information feedback to the main processor.

[0046] In an embodiment of the present application, the configuration and status of the physical layer chip of the Ethernet are monitored by the state control unit. The FPGA is formed with multiple management serial interface buses (Management Data Input / Output Interface, MDIO). Each of the analog MAC interfaces corresponds to one MDIO. The MDIO is arranged between the analog MAC interface and the physical layer chip, so that the state control unit can configure the lower-level chip of the FPGA.

[0047] Specifically, when the FPGA is powered on, the state control unit waits for the signal of the control interface, and after receiving the control signal from the main processor, configures the lower-level chip of the FPGA through MDIO. After the configuration of the lower-level chip of the FPGA is completed, the state of the lower-level chip of the FPGA and the corresponding working state of the analog MAC interface are queried through the state control unit to obtain the working state of the lower-level chip of the FPGA and the corresponding working state of the analog MAC interface, and the working state of the lower-level chip of the FPGA and the corresponding working state of the analog MAC interface are fed back to the main processor. When the main processor receives the working state of the lower-level chip of the FPGA and the corresponding working state of the analog MAC interface, and the working state of the lower-level chip of the FPGA and the corresponding working state of the analog MAC interface are both normal, data transmission is performed through the MAC interface of the main processor and the analog MAC interface of the FPGA.

[0048] If the communication between the main processor and the FPGA is interrupted or erroneous, the simulated MAC interface may be restarted. Specifically, a control signal is sent to the FPGA through the I / O interface of the main processing chip; when the control interface of the FPGA receives the control signal from the main processor, the corresponding simulated MAC interface is controlled to restart through the state control unit, and the lower-level chip of the FPGA is reconfigured.

[0049] It is worth mentioning that in the embodiment of the present application, the configuration of the lower-level chip of the FPGA is completed by the state control unit of the FPGA, which can reduce the configuration process of the main processor. Usually, the configuration of the lower-level chip of the FPGA and the corresponding analog MAC interface are fixed commands, and the main processor only needs to restart and configure the lower-level chip of the FPGA and the corresponding analog MAC interface through the I / O interface.

[0050] In summary, the Ethernet interface expansion method is explained. The Ethernet interface expansion method connects the MAC interface of the main processor to the FPGA, and simulates multiple MAC layers through the FPGA to form multiple simulated MAC interfaces, so that a processor with only a single MAC interface can be applied to scenarios requiring two or more Ethernets, thereby reducing the requirements for the MAC interface of the processor, thereby reducing the difficulty of hardware selection and hardware costs.

[0051] The present application and its implementation methods are described above, and such description is not restrictive. The drawings show only one implementation method of the present application, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design structural methods and embodiments similar to the technical solution without creative design without departing from the inventive purpose of the present application, they should all fall within the protection scope of the present application.

Claims

1. A method for extending an Ethernet interface, characterized in that: The method comprises the following steps: connecting the MAC interface of the main processor to an FPGA, and simulating multiple MAC layers through the FPGA to form multiple simulated MAC interfaces, wherein one MAC interface of the main processor corresponds to multiple simulated MAC interfaces, and each simulated MAC interface is suitable for being connected to only one physical layer chip, and one physical layer chip corresponds to only one Ethernet interface, so that one MAC interface of the main processor corresponds to multiple Ethernet interfaces through multiple simulated MAC interfaces; and transmitting data between the FPGA and the main processor, wherein in the process of transmitting data between the FPGA and the main processor, marking the data transmitted between the FPGA and the main processor, and identifying the simulated MAC interface corresponding to the data transmitted between the FPGA and the main processor through the mark carried by the data transmitted between the FPGA and the main processor.

2. The method for extending the Ethernet interface according to claim 1, characterized in that: During the process of data transmission from the main processor to the FPGA, the data transmitted from the main processor to the FPGA is distributed and marked to generate at least one portion of distributed data with a mark, wherein the mark in the distributed data with a mark is used to characterize the analog MAC interface corresponding to the distributed data with a mark; the distributed data with a mark is transmitted to the corresponding analog MAC interface; during the process of data transmission from the FPGA to the main processor, the data transmitted from at least one of the analog MAC interfaces of the FPGA to the main processor is marked by a data processing unit of the FPGA to generate at least one portion of marked data; the marked data is sent to the main processor through a data transceiver interface of the FPGA; and the analog MAC interface corresponding to the marked data is determined by the main processor.

3. The method for extending the Ethernet interface according to claim 2, characterized in that: The data received by the FPGA from the main processor includes verification information. In the process of the main processor transmitting data to the FPGA, after the FPGA receives the data from the main processor, a confirmation signal is sent to the main processor through the FPGA; if the main processor receives the confirmation signal, it is determined that the FPGA and the main processor can be effectively transmitted; after it is determined that the FPGA and the main processor can be effectively transmitted, the FPGA determines whether the data received from the main processor is complete based on the verification information, and if the verification information is correct, it is determined that the data received by the FPGA from the main processor is complete; When it is determined that the FPGA and the main processor can transmit effectively and the data received by the FPGA from the main processor is complete, it is determined whether the FPGA correctly transmits the marked allocated data to the corresponding analog MAC interface.

4. The method for extending the Ethernet interface according to claim 3, characterized in that: The Ethernet interface expansion method also includes the steps of: configuring and monitoring the FPGA and lower-level chips through the main processor.

5. The method for extending the Ethernet interface according to claim 4, characterized in that: In the process of configuring and monitoring the FPGA and lower-level chips through the main processor, a control interface of the FPGA is connected to an I / O interface of the main processor; a state control unit of the FPGA is communicatively connected to the control interface and the analog MAC interface; when the state control unit of the FPGA receives a control signal from the main processor, the lower-level chip of the FPGA is configured, and the working status of the lower-level chip of the FPGA and the corresponding analog MAC interface is queried; and the working status of the lower-level chip of the FPGA and the corresponding analog MAC interface is then fed back to the main processor.

6. The method for extending the Ethernet interface according to claim 5, characterized in that: During the process of configuring and monitoring the FPGA and the lower-level chip through the main processor, when the working status of the lower-level chip of the FPGA and the corresponding working status of the analog MAC interface are both normal, data transmission is performed through the MAC interface of the main processor and the analog MAC interface of the FPGA.

7. The method for extending the Ethernet interface according to claim 6, characterized in that: During the process of configuring and monitoring the FPGA and the lower-level chips by the main processor, if the communication between the main processor and the FPGA is interrupted or erroneous, the simulated MAC interface is restarted and the lower-level chips of the FPGA are reconfigured.

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