Digital gain control method and system for power grid dual-mode communication

Abstract

The invention discloses a digital gain control method and system for power grid dual-mode communication, and belongs to the technical field of communication. The system comprises an analog front-end module, a digital system module and a synchronous system module; the analog front-end module comprises a programmable gain amplifier and a digital-to-analog converter; the digital system module comprises a digital filtering module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module and a processor; after a received signal is processed by the analog front-end module, a quantized digital signal obtained after processing is transmitted to the digital system module, and finally data processed by the digital system module is output to the synchronous system module, so that digital gain control of communication is completed. The technical problems of poor signal data consistency and poor stability in a digital gain control process in the prior art are solved.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to a digital gain control method and system for power grid dual-mode communication. Background Art

[0002] With the rapid development of smart grids, high-speed power line carrier communication (HPLC) and high-reliability radio frequency communication (HRF) as two main communication methods play an important role in the fields of power grid automation, power consumption information collection, and distributed energy access. However, the power line channel environment is complex, with problems such as large noise interference and severe attenuation; wireless communication is easily affected by environmental factors, with problems such as signal fading and multipath effects. These factors will lead to a decrease in the quality of communication signals, affecting the reliability and stability of communication.

[0003] To overcome the above problems, Orthogonal Frequency Division Multiplexing (OFDM) technology has been introduced into the field of power grid communications. OFDM is a multi-carrier transmission scheme that can effectively combat specific frequency attenuation and narrowband interference. It divides the entire communication frequency band into multiple mutually orthogonal and overlapping sub-bands, significantly improving the spectrum utilization efficiency and having strong anti-interference capabilities. In a dual-mode communication system based on OFDM technology, wired and wireless have similar physical frame structures, including preamble, frame control, and frame payload. At the receiving end, the signal processing process usually includes the following steps: 1. Automatic Gain Control (AGC): Utilizes the time-domain repetition characteristics of the preamble sequence to adjust the amplitude of the received signal so that its energy remains moderate and stable.

[0004] 2. Frame synchronization: Determine the starting position of valid data through delayed correlation or local cross-correlation calculation.

[0005] 3. Channel estimation and frequency offset estimation: Channel and frequency offset estimation is performed based on the leading data.

[0006] 4. Demodulation and decoding: Demodulate, deinterleave and decode the frame payload to ultimately recover the user data.

[0007] In the above process, AGC, as a key module of the receiver, directly affects the accuracy of signal synchronization, channel estimation and frequency offset estimation, and thus determines the overall performance of the receiver. If the AGC is not adjusted properly, it may cause signal distortion, synchronization failure or channel estimation error, seriously affecting the communication quality.

[0008] At present, a two-stage cascade AGC structure is generally used in receivers to optimize the dynamic range and stabilize the processing of received signals. This structure includes an analog gain control stage and a digital gain control stage. Through the coordinated work of the two-stage gain control, it ensures that the received signal can obtain accurate gain adjustment in both the analog domain and the digital domain, thereby improving the dynamic range and signal processing performance of the system.

[0009] However, traditional digital AGC still has the following problems in practical applications: 1. Long window time: Traditional methods usually require a longer signal window to cover signal characteristics, which increases the time pressure of synchronization.

[0010] 2. Data consistency destruction: Before the AGC is stable, the signal data is affected by the gain change, which may cause data consistency destruction, especially when the lead time is short or the synchronization lock delay is large, and the data may even be unavailable. Summary of the invention

[0011] In view of the problems of long window time and data consistency destruction in the prior art, the present invention proposes a digital gain control method and system for power grid dual-mode communication, aiming to improve the accuracy and stability of digital gain control.

[0012] To achieve the above object, the present invention provides a digital gain control method for power grid dual-mode communication.

[0013] Preferably, the received signal is quantized to obtain a quantized digital signal, and then the quantized digital signal is subjected to gain control calculation, and finally the calculated gain control data is output to the synchronization module to complete the digital gain control of the communication.

[0014] Preferably, the gain control calculation includes the following steps: configuration startup, inputting quantized data and reading cached data, calculating gain, amplifying quantized data and updating cached data, updating cached data and reading cached data, cached data gain compensation, clearing cached data and switching data paths.

[0015] Preferably, the configuration startup step includes: the processor configures the parameters of the digital automatic gain control module, and after the configuration is completed, the digital automatic gain control calculation process begins; the parameters include the total number of data points, the number of input data points, the number of stored data points, the amplitude interval data point filtering threshold and the number of amplification retention shift bits.

[0016] Preferably, the steps of inputting quantized data and reading cached data include: a digital filter transmits the quantized data to a control core according to the number of input data points and a data stack transmits the quantized data to a control core according to the number of stored data points.

[0017] Preferably, the step of calculating the gain includes: the control core filters the threshold and the number of amplified and retained shift bits according to the number of amplitude interval data points, and calculates the number of left-shifted amplified bits based on input quantization and cached data.

[0018] Preferably, the quantized data amplification and cache data update steps include: the left shift amplifier receives the left shift amplification bit number of the control core and amplifies the input data, and transmits the output data to the data stack, and the data stack updates the data.

[0019] Preferably, the step of updating and reading the cached data includes: after the data stack receives the synchronous locking signal, the data stack updates the data and reads the data in the stack to the bidirectional shift amplifier.

[0020] Preferably, the cache data gain compensation step includes: after the bidirectional shift amplifier receives the synchronization lock signal, the bidirectional shift amplifier receives the left shift amplification bit output by the control core and performs shift amplification bit compensation on the data from the data stack.

[0021] Preferably, the steps of clearing the cached data and switching the data path include: after the data stack receives the synchronization lock signal, determining whether the data in the data stack is empty; if it is empty, selecting the first data path from the left shift amplifier; if it is not empty, selecting the second data path from the bidirectional shift amplifier and performing channel estimation and frequency deviation calculation.

[0022] To achieve the above object, the present invention also provides a digital gain control system for power grid dual-mode communication, including an analog front-end module, a digital system module, and a synchronous system module.

[0023] Preferably, after the received signal is processed by the analog front-end module, the quantized digital signal obtained after the processing is transmitted to the digital system module, and finally the data processed by the digital system is output to the synchronization system module to complete the digital gain control of the communication.

[0024] Preferably, the analog front end includes a programmable gain amplifier and a digital-to-analog converter; Preferably, the digital system includes a digital filter module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor.

[0025] Preferably, the programmable gain amplifier adopts a two-stage cascade structure, and its gain configuration is derived from a digital system.

[0026] Preferably, the programmable gain amplifier transmits the signal to the digital-to-analog converter, and the digital-to-analog converter processes the signal to obtain a quantized digital signal.

[0027] Preferably, the configuration parameters of the core control module are sourced from the processor, and the configuration parameters include: the total number of calculated data points N, the number of input data points N1, the number of stored data points N2, and the filtering threshold for the number of data points in the amplitude range , the amplification retention shift number R; the configuration parameters satisfy: N = N1 + N2, 1 < < N / (W - 1), 1 < R < W, where W is the digital quantization data bit width; the digital filter module and the data stack pass the data to the core control module, and the left shift amplifier receives the amplification factor output by the core control module and performs an arithmetic left shift operation on the data passed in by the digital filter module.

[0028] Preferably, the left shift amplifier passes the data to the data stack and caches the data after the left shift operation and the number of bits of the left shift operation; Preferably, the data stack adopts a ping-pong storage structure and stores the data output by the left shift amplifier in real time before the synchronization module issues a synchronization signal, and provides backtracking data to the core control module for digital gain calculation in each digital gain control cycle; the storage and read data addresses of the data stack adopt a unidirectional increasing and loop-back manner; after the synchronization module releases the synchronization signal and before its own read-empty signal is valid, the data stack stores the data output by the left shift amplifier in real time and outputs the backtracking data to the bidirectional shift amplifier; the backtracking data includes left-shifted amplified data and the number of left-shifted amplification bits.

[0029] Preferably, the input data of the bidirectional shift amplifier comes from the data stack, including: left-shifted amplified data and the corresponding amplification shift number; the bidirectional shift amplifier receives the amplification shift number locked by the core control module; when the data path of the bidirectional shift amplifier is gated, the calculation of the effective amplification shift number is performed: the effective amplification shift number is equal to the difference between the corresponding amplification shift number and the amplification shift number locked by the core control module; when the effective amplification shift number is greater than zero, the bidirectional shift amplifier performs a right shift reduction operation; when the effective amplification shift number is less than zero, the bidirectional shift amplifier performs a left shift amplification operation; when the effective amplification shift number is equal to zero, the data remains unchanged.

[0030] Preferably, the first path data of the first data path selector comes from the left shift amplifier, and the second path data comes from the bidirectional shift amplifier. When the data in the data stack is empty, the first data path selector selects the first path data, otherwise it selects the second path data; the first path data of the second data path selector comes from the first data selector, and the second path data comes from the left shift amplifier. When the lock signal of the synchronization module is high and remains valid, the second data path selector selects the first signal, otherwise it selects the second path signal.

[0031] Preferably, the synchronization module sends a locking signal. After the locking signal is locked, the receiver used in the digital gain control process traces back part of the data before the locking signal is locked from the data stack and performs channel estimation and frequency deviation calculation. This part of the data is consistent with the locking amplification shift number after passing through the bidirectional shift amplifier.

[0032] Compared with the prior art, the technical solution of the present invention has the following advantages / benefits: 1. Through the reverse compensation mechanism of the data stack and the bidirectional shift amplifier, the consistency of signal data is ensured, the amount of available signal data is increased, and the overall performance of the system is improved.

[0033] 2. The signal peak is retrieved through the data retrieval method, which significantly reduces the settling time of the digital gain control process. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 The present invention is a flowchart of a digital gain control method for dual-mode communication in a power grid.

[0036] Figure 2 It is a gain control calculation flow chart used in the present invention.

[0037] Figure 3 It is a schematic diagram of a digital gain control system for dual-mode communication in a power grid according to the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. Therefore, the detailed description of the embodiments of the present invention provided below is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention.

[0039] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and thus, once an item is defined in one drawing, it may not be further defined or explained in the subsequent drawings.

[0040] Embodiment 1: According to the signal-to-noise ratio formula: In the formula is the signal power, is the noise power.

[0041] If the signal is amplified in the digital domain, the signal and noise powers are amplified synchronously, and the SNR remains unchanged.

[0042] For a uniform quantizer, according to the signal-to-noise ratio formula:,, where N in the formula is the number of bits of the quantizer.

[0043] If the signal is attenuated in the digital domain, and a low-bit truncation operation (equivalent to division) is used, it is equivalent to a decrease in the quantization bit number N, which will cause the SNR to decrease.

[0044] After the fixed-point design of the digital receiver, when a large signal is input, there is enough margin in the internal bit width W, and no arithmetic overflow will occur. When a small signal is input, key components such as the synchronization module have a lower limit threshold −Δ for the signal amplitude (or energy). When the signal is below this threshold, it may not be possible to lock the valid signal, resulting in packet loss.

[0045] Combined with the above signal-to-noise ratio calculation formula, in order not to affect the performance of the digital receiver and avoid packet loss under small-signal conditions, an amplification operation should be performed when the input signal is less than the set target amplitude to avoid packet loss, and a holding operation should be performed when the input signal is greater than the set target amplitude to avoid affecting the SNR.

[0046] The digital AGC performs scaling control on the digital-domain signal according to the target amplitude (or energy) set by the system. Assuming the system target amplitude is, the allowable deviation range is Δ, and the effective interval is [−Δ, +Δ]. Usually, the digital receiver can receive normally within this interval. Therefore, the accuracy requirement for the amplification factor (or gain) of the digital AGC can be relaxed, that is, it satisfies, n + <W - 1, where W is the digital quantization data bit width and is the effective bit width of the input data.

[0047] Amplifying data in the digital circuit and satisfying can be simplified to a bit left shift operation in hardware; similarly, attenuating data and satisfying can be simplified to a bit right shift operation in hardware. There is no need for a hardware multiplier or divider, which greatly simplifies the hardware complexity.

[0048] Divide the absolute value range into W - 1 intervals. The k-th interval corresponds to ∣x∣∈[,), where k ∈ {0, 1,..., W - 2}. Count the number of data points scattered in each amplitude interval, find the interval k where = 0 and the amplitude is the smallest, and then the maximum shift amplification factor of the digital AGC can be calculated to ensure data amplification without overflow, and n = W - k - 2 can be obtained.

[0049] When pulse interference exists, the possible influence of the pulse on is filtered out by setting a threshold, and n is calculated based on it.

[0050] like Figure 1 As shown, according to the above principle, the present invention provides a digital gain control method for power grid dual-mode communication, which is applicable to both wired communication and wireless communication.

[0051] The received signal is quantized to obtain a quantized digital signal, and then the quantized digital signal is subjected to gain control calculation, and finally the calculated gain control data is output to the synchronization module to complete the digital gain control of the communication.

[0052] like Figure 2 As shown, the gain control calculation includes the following steps: configuration startup, inputting quantized data and reading cached data, calculating gain, amplifying quantized data and updating cached data, updating cached data and reading cached data, cached data gain compensation, clearing cached data and switching data paths.

[0053] The configuration startup step includes: the processor configures the parameters of the digital automatic gain control module, and after the configuration is completed, the digital automatic gain control calculation process begins; the parameters include the total number of data points, the number of input data points, the number of stored data points, the amplitude interval data point filtering threshold and the number of amplification retention shift bits.

[0054] The steps of inputting quantized data and reading cached data include: a digital filter transmits the quantized data to a control core according to the number of input data points, and a data stack transmits the quantized data to a control core according to the number of stored data points.

[0055] The gain calculation step includes: the control core filters the threshold and amplifies the number of retained shift bits according to the number of amplitude interval data points, and calculates the number of left-shift amplification bits based on input quantization and cache data.

[0056] The steps of quantized data amplification and cache data updating include: the left shift amplifier receives the left shift amplification bit number of the control core and amplifies the input data, and transmits the output data to the data stack, and the data stack updates the data.

[0057] The steps of updating and reading cached data include: after the data stack receives the synchronous locking signal, the data stack updates the data and reads the data in the stack to the bidirectional shift amplifier.

[0058] The cache data gain compensation step includes: after the bidirectional shift amplifier receives the synchronous locking signal, the bidirectional shift amplifier receives the left shift amplification bit output by the control core and performs shift amplification bit compensation on the data from the data stack.

[0059] The steps of clearing the cache data and switching the data path include: after the data stack receives the synchronization lock signal, it determines whether the data in the data stack is empty; if it is empty, it selects the first path of data from the left shift amplifier, and if it is not empty, it selects the second path of data from the bidirectional shift amplifier and performs channel estimation and frequency offset calculation.

[0060] After completing the above steps, the calculation result is output, and the entire gain control process is completed.

[0061] Embodiment 2: As Figure 3 shown, a digital gain control system for dual-mode power grid communication is provided, including an analog front-end module, a digital system module, and a synchronization system module.

[0062] After the received signal is processed by the analog front-end module, the quantized digital signal obtained after processing is transmitted to the digital system module, and finally the data processed by the digital system is output to the synchronization system module to complete the digital gain control of communication.

[0063] The analog front-end includes a programmable gain amplifier and a digital-to-analog converter. The programmable gain amplifier adopts a two-stage cascaded structure, and its gain configuration comes from the digital system. The overall dynamic range is -20dB~67dB, and the gain step is 3dB. The quantization bit width of the digital-to-analog converter is 14bit, and the sampling rate is 25MHz; the programmable gain amplifier transmits the signal to the digital-to-analog converter to obtain a quantized digital signal.

[0064] The digital system includes a digital filter module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module, and a processor.

[0065] The programmable gain amplifier adopts a two-stage cascaded structure, and its gain configuration comes from the digital system.

[0066] The programmable gain amplifier transmits the signal to the digital-to-analog converter, and the quantized digital signal is obtained after being processed by the digital-to-analog converter.

[0067] The configuration parameters of the core control module come from the processor, and the configuration parameters include: the total number of calculated data points N, the number of input data points N1, the number of stored data points N2, the amplitude interval data point filtering threshold, and the amplification retention shift number R; the configuration parameters satisfy: N = N1 + N2, 1 << N / (W - 1), 1 < R < W, where W is the digital quantization data bit width; The digital filter module and the data stack transmit the data to the core control module. The left shift amplifier receives the amplification factor output by the core control module and performs an arithmetic left shift operation on the data transmitted by the digital filter module.

[0068] The left shift amplifier transfers the data to the data stack and caches the data after the left shift operation and the number of bits of the left shift operation; The data stack adopts a ping-pong storage structure, and stores the data output by the left-shift amplifier in real time before the synchronization module sends a synchronization signal, and provides traceback data to the core control module in each digital gain control cycle for digital gain calculation; the storage and reading data addresses of the data stack adopt a unidirectional increasing and looping method; after the synchronization module releases the synchronization signal and before its own read-empty signal is effective, the data stack stores the data output by the left-shift amplifier in real time, and outputs the traceback data to the bidirectional shift amplifier at the same time; the traceback data includes the left-shift amplified data and the number of left-shift amplified bits.

[0069] The input data of the bidirectional shift amplifier comes from the data stack, including: left-shift amplified data and corresponding amplified shift number; the bidirectional shift amplifier receives the amplified shift number locked by the core control module; when the data path of the bidirectional shift amplifier is selected, the effective amplified shift number is calculated: the effective amplified shift number is equal to the difference between the corresponding amplified shift number and the amplified shift number locked by the core control module; when the effective amplified shift number is greater than zero, the bidirectional shift amplifier performs a right shift reduction operation; when the effective amplified shift number is less than zero, the bidirectional shift amplifier performs a left shift amplification operation; when the effective amplified shift number is equal to zero, the data is kept unchanged.

[0070] The first data path selector of the first data path selector is derived from the left shift amplifier, and the second data path is derived from the bidirectional shift amplifier. When the data in the data stack is empty, the first data path selector selects the first data path, otherwise the second data path selector is selected; the first data path selector of the second data path selector is derived from the first data selector, and the second data path is derived from the left shift amplifier. When the synchronization module locking signal is high and continuously valid, the second data selector selects the first signal, otherwise the second signal is selected.

[0071] The synchronization module sends a locking signal. After the locking signal is locked, the receiver used in the digital gain control process traces back part of the data before the locking signal is locked from the data stack and performs channel estimation and frequency deviation calculation. This part of the data is consistent with the locking amplification shift number after passing through the bidirectional shift amplifier.

[0072] The digital system comprises a digital filtering module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module and a processor.

[0073] The above are only preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be regarded as limiting the present invention, and the protection scope of the present invention should be based on the scope defined by the claims. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the spirit and scope of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A digital gain control method for power grid dual-mode communication, characterized in that: The received signal is quantized to obtain a quantized digital signal, and then the quantized digital signal is subjected to gain control calculation, and finally the calculated gain control data is output to the synchronization module to complete the digital gain control of the communication.

2. A digital gain control method for power grid dual-mode communication according to claim 1, characterized in that: The gain control calculation includes the following steps: configuration startup, inputting quantized data and reading cache data, calculating gain, quantized data amplification and cache data update, cache data update and reading cache data, cache data gain compensation, clearing cache data and switching data path.

3. A digital gain control method for power grid dual-mode communication according to claim 2, characterized in that: The configuration startup step refers to the processor configuring the parameters of the digital automatic gain control module, and starting the digital automatic gain control calculation process after the configuration is completed; the parameters include the total number of data points, the number of input data points, the number of stored data points, the amplitude interval data point filtering threshold and the number of amplification retention shift bits; The step of inputting quantized data and reading cached data includes: the digital filter transmits the quantized data to the control core according to the number of input data points and the data stack transmits the quantized data to the control core according to the number of stored data points; The step of calculating the gain includes: controlling the core to filter the threshold and the number of amplified and retained shift bits according to the number of amplitude interval data points, and calculating the number of left-shifted amplified bits based on input quantization and cached data; The quantized data amplification and cache data updating steps include: the left shift amplifier receives the left shift amplification bit of the control core and amplifies the input data, and transmits the output data to the data stack, and the data stack updates the data; The cache data updating and reading cache data step comprises: after the data stack receives the synchronization lock signal, the data stack updates the data and reads the data in the stack to the bidirectional shift amplifier; The cache data gain compensation step includes: after the bidirectional shift amplifier receives the synchronization lock signal, the bidirectional shift amplifier receives the left shift amplification bit output by the control core, and performs shift amplification bit compensation on the data from the data stack; The steps of clearing cached data and switching data paths include: after the data stack receives a synchronization lock signal, determining whether the data in the data stack is empty; if it is empty, selecting the first data path from the left shift amplifier; if it is not empty, selecting the second data path from the bidirectional shift amplifier and performing channel estimation and frequency deviation calculation.

4. A digital gain control system for dual-mode communication in a power grid, characterized in that: Including analog front-end module, digital system module, and synchronous system module; After the received signal is processed by the analog front-end module, the quantized digital signal obtained after processing is transmitted to the digital system module, and finally the data processed by the digital system is output to the synchronization system module to complete the digital gain control of the communication.

5. A digital gain control system for power grid dual-mode communication according to claim 4, characterized in that: The analog front end includes a programmable gain amplifier and a digital-to-analog converter; The digital system comprises a digital filtering module, a left shift amplifier, a data stack, a bidirectional shift amplifier, a first data path selector, a second data path selector, a core control module and a processor.

6. A digital gain control system for power grid dual-mode communication according to claim 5, characterized in that: The programmable gain amplifier adopts a two-stage cascade structure, and its gain configuration is derived from a digital system; The programmable gain amplifier transmits the signal to the digital-to-analog converter, and the digital-to-analog converter processes the signal to obtain a quantized digital signal.

7. A digital gain control system for power grid dual-mode communication according to claim 6, characterized in that: The configuration parameters of the core control module are sourced from the processor. The configuration parameters include: the total number of calculated data points N, the number of input data points N1, the number of stored data points N2, the filtering threshold for the number of data points in the amplitude range, and the amplification retention shift number R. The configuration parameters satisfy: N = N1 + N2, 1 < < N / (W - 1), 1 < R < W, where W is the digital quantization data bit width. The digital filter module and the data stack pass data into the core control module. The left shift amplifier receives the amplification factor output by the core control module and performs an arithmetic left shift operation on the data passed in by the digital filter module.

8. A digital gain control system for power grid dual-mode communication according to claim 7, characterized in that: The left shift amplifier transfers the data to the data stack and caches the data after the left shift operation and the number of bits of the left shift operation. The data stack adopts a ping-pong storage structure and stores the data output by the left shift amplifier in real time before the synchronization module issues a synchronization signal. And in each digital gain control cycle, it provides backtracking data to the core control module for digital gain calculation. The storage and read data addresses of the data stack adopt a unidirectional increasing and loop-back method. After the synchronization module releases the synchronization signal and before its own read-empty signal is valid, the data stack stores the data output by the left shift amplifier in real time and outputs the backtracking data to the bidirectional shift amplifier at the same time. The backtracking data includes the left-shifted amplified data and the left-shifted amplification number.

9. A digital gain control system for power grid dual-mode communication according to claim 8, characterized in that: The input data of the bidirectional shift amplifier comes from the data stack, including: the left-shifted amplified data and the corresponding amplification shift number. The bidirectional shift amplifier receives the amplification shift number locked by the core control module. When the data path of the bidirectional shift amplifier is selected, the calculation of the effective amplification shift number is performed: the effective amplification shift number is equal to the difference between the corresponding amplification shift number and the amplification shift number locked by the core control module. When the effective amplification shift number is greater than zero, the bidirectional shift amplifier performs a right shift reduction operation. When the effective amplification shift number is less than zero, the bidirectional shift amplifier performs a left shift amplification operation. When the effective amplification shift number is equal to zero, the data remains unchanged.

10. A digital gain control system for power grid dual-mode communication according to claim 9, characterized in that: The first path data of the first data path selector comes from the left shift amplifier, and the second path data comes from the bidirectional shift amplifier. When the data in the data stack is empty, the first data path selector selects the first path data, otherwise it selects the second path data. The first path data of the second data path selector comes from the first data selector, and the second path data comes from the left shift amplifier. When the lock signal of the synchronization module is high and remains valid, the second data path selector selects the first signal, otherwise it selects the second path signal. The synchronization module issues a lock signal. After the lock signal is locked, the receiver used in the digital gain control process backtracks some data before the lock signal is locked from the data stack and performs channel estimation and frequency offset calculation. And this part of the data is consistent with the locked amplification shift number after passing through the bidirectional shift amplifier.

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