A method for monitoring the processing delay of data packet software, an electronic device, and a storage medium

Abstract

The present invention relates to the technical field of chip design, and particularly to a method for monitoring the software processing delay of data packets, an electronic device, and a storage medium. It obtains a server, a processor, and an expansion card; wherein, the server and the processor are interconnected through a high-speed interface; the expansion card is interconnected with the server through a high-speed interface and is interconnected with the processor through an output interface; the server sends data packets to the processor; when the expansion card detects the data packets sent by the server, it sends a control signal to the processor; when the processor receives the control signal, it records the time t1 when the control signal is received; when the processor receives the data packets, it records the time t2 when the data packets are received; the software processing delay of the data packets is obtained according to t1 and t2. Both t1 and t2 are the timestamps of the processor itself, which solves the problem of the asynchronous time of the server sending data packets and the processor receiving data packets.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a method for monitoring the software processing delay of data packets, an electronic device, and a storage medium. Background Art

[0002] During the data transmission process, when the server sends a data packet to the processor, the data packet needs to go through multiple processing stages before it can be finally obtained by the processor. First, the data packet needs to be transmitted through the physical connection between the server and the processor, and this process will generate a certain time delay. Secondly, after the data packet arrives at the processor, it also needs to go through software processing inside the processor, and this step will also introduce additional time delay. Therefore, the time when the processor actually obtains the data packet includes the time delay of the physical connection and the time delay of the software processing inside the processor, resulting in a relatively long overall time delay.

[0003] In addition, the data packet usually carries a sent timestamp when it is sent to record the sending time of the data packet. However, due to the existence of the above time delay, there is a significant difference between this timestamp and the time when the processor actually obtains the data packet. This time difference may make it difficult for the system to perform effective synchronization processing, thereby affecting the synchronization accuracy. Especially in application scenarios with strict requirements for time accuracy, this time delay and the decrease in synchronization accuracy may have an adverse impact. Summary of the Invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a method for monitoring the software processing delay of data packets, the method comprising:

[0005] S100, obtaining a server, a processor, and an expansion card; wherein, the server and the processor are interconnected through a high-speed interface; the expansion card is interconnected with the server through a high-speed interface and is interconnected with the processor through an output interface.

[0006] S200, the server sends a data packet to the processor.

[0007] S300, when the expansion card monitors that the server sends the data packet, it sends a control signal to the processor.

[0008] S400, when the processor receives the control signal, the processor records the current timestamp t1 internally.

[0009] S500, when the processor receives the data packet, the processor records the timestamp t2 when it receives the data packet; and obtains the software processing delay of the data packet according to t1 and t2.

[0010] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program segment is stored, and the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above method.

[0011] In addition, the present invention also provides an electronic device, including a processor and the above non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects:

[0013] A method for monitoring the software processing delay of data packets, an electronic device and a storage medium provided by the present invention, when an expansion card monitors that a server sends a data packet, it sends a control signal to the processor, so that the processor records the time t1 when it receives the control signal; the processor records the time t2 when it receives the data packet; the software processing delay of the data packet is obtained according to t1 and t2, where both t1 and t2 are timestamps of the processor itself, which solves the problem of asynchronous time between the server sending the data packet and the processor receiving the data packet. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 It is a flowchart of a method for monitoring the software processing delay of data packets provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0017] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meaning as commonly understood by those of ordinary skill in the art.

[0018] Please refer to Figure 1 , which shows a flowchart of a method for monitoring the software processing delay of data packets. The method includes:

[0019] S100, obtain a server, a processor, and an expansion card; wherein, the server and the processor are interconnected through a high-speed interface; the expansion card is interconnected with the server through a high-speed interface and interconnected with the processor through an output interface.

[0020] In one implementation, the processor is a Graphics Processing Unit (GPU), a Tensor Processing Unit (TPU), or a Neural Processing Unit (NPU). Other types of processors also fall within the protection scope of the present invention.

[0021] In one implementation, the expansion card is a General Purpose Input / Output (GPIO). Other expansion cards that can be used to monitor data packets sent by a microcontroller and send level signals to the processor also fall within the protection scope of the present invention.

[0022] In one implementation, the high-speed interface is a Peripheral Component Interconnect Express (PCIE) interface, a CXL interface (Compute Express Link), or an NVLink interface. Other high-speed interfaces used for interconnection also fall within the protection scope of the present invention.

[0023] In one implementation, the high-speed interface between the server and the processor and the high-speed interface between the expansion card and the server can be of the same type or different types. When the two are of the same type of high-speed interface, the monitoring delay is more accurate than when they are of different types of high-speed interfaces.

[0024] S200, the server sends a data packet to the processor.

[0025] S300, when the expansion card monitors that the server sends the data packet, send a control signal to the processor.

[0026] Wherein, the control signal is a level signal. In one implementation, the valid edge of the level signal is a rising edge or a falling edge. Other types of valid edges also fall within the protection scope of the present invention.

[0027] S400, when the processor receives the control signal, the processor internally records the current timestamp t1.

[0028] Among them, the processor receives a control signal, and t1 is the time when the control signal triggers the processor to record according to the processor's own time reference. After the server sends out the data packet, it is directly captured by the hardware expansion card and a control signal is sent to the processor. The whole process is completed by the hardware, and the hardware delay is very small compared with the software delay and is within an acceptable range. Among them, the software delay refers to the additional time delay introduced by software-level factors such as the processing of the operating system and network protocol stack, the preparation and scheduling of application programs, the interaction with the database, and security processing before the processor receives the data packet. This software delay is relatively large compared with the hardware delay. For example, the hardware delay may be at the nanosecond level, while the software delay may be at the millisecond or microsecond level.

[0029] In one embodiment, S400 further includes that when the processor receives the control signal, preprocessing operations for receiving the data packet are performed inside the processor. In one embodiment, the preprocessing operations include one or more of the following operations: performing time synchronization through t1 to ensure that the communication between the processor and the server is consistent in time; preallocating necessary resources, such as buffers and processing units, etc., so as to improve the processing efficiency; dynamically adjusting the resource allocation to achieve better load balancing; preconfiguring the data path for parallel processing so that the data packet can be processed immediately after arrival, reducing the waiting time. Other types of preprocessing operations performed after t1 and before receiving the data packet all fall within the protection scope of the present invention.

[0030] S500, when the processor receives the data packet, the processor records the timestamp t2 when it receives the data packet; obtains the software processing delay of the data packet according to t1 and t2.

[0031] In one embodiment, the software processing delay △t of the data packet satisfies: △t = t2 - t1. In another embodiment, △t can also satisfy: △t = t2 - (t1 + tt1), where tt1 is a preset hardware delay. Other schemes for obtaining the software processing delay of the data packet according to t1 and t2 all fall within the protection scope of the present invention.

[0032] In one embodiment, the way for the processor to record the timestamp internally is to use one or more hardware counters to track time; when the processor receives the control signal, immediately read the value of the counter and store it in a register or a memory location. Other types of ways to record the timestamp also fall within the protection scope of the present invention.

[0033] Among them, the software processing delay is calculated through t1 instead of based on the timestamp carried in the data packet because the timestamp carried in the data packet is the time point when the server sends the data packet and is based on the internal time of the server. It is impossible to achieve very precise time synchronization between the server and the processor. Once there is a time difference between the two, it will lead to inaccurate calculation of the software delay. The hardware delay of t1 is very short. If the hardware delay is ignored, it can be approximately considered that t1 is the time point when the server sends the data packet, and this timestamp t1 is recorded according to the time reference of the processor itself. t2 is also recorded according to the time reference of the processor itself. The two have the same reference, solving the problem of asynchronous time between the server sending the data packet and the processor receiving the data packet.

[0034] In one embodiment, S100 further includes a network analyzer, which is connected between the server and the processor and is used to obtain the data packets transmitted between the server and the processor.

[0035] Among them, the network analyzer is also called a protocol analyzer or a packet capture device and is used to capture and analyze network data packets.

[0036] In one embodiment, the network analyzer is interconnected with the server through a high-speed interface. Among them, the definition of the high-speed interface between the network analyzer and the server is the same as that of the high-speed interface between the server and the processor, and will not be elaborated here.

[0037] In one embodiment, the network analyzer is interconnected with the processor through a high-speed interface. Among them, the definition of the high-speed interface between the network analyzer and the processor is the same as that of the high-speed interface between the server and the processor, and will not be elaborated here.

[0038] It should be noted that the high-speed interfaces used to connect different components can be of the same type or different types, and can be adjusted according to specific application scenarios.

[0039] In one embodiment, S100 further includes: the network analyzer is interconnected with the expansion card through a high-speed interface. S300 further includes: when the expansion card monitors the data packet sent by the server, it also sends the control signal to the network analyzer at the same time. That is, the expansion card sends control signals to the processor and the network analyzer at the same time, triggering the processor and the network analyzer to record the corresponding timestamps and perform preprocessing operations for receiving data packets simultaneously.

[0040] In one embodiment, the network analyzer is further configured to: obtain the timestamp t3 of the data packet, trace the target control signal that triggers the network analyzer to obtain the data packet through the t3, obtain the data packet sent by the server within the error range through the target control signal, and the target function called before the server sends the data packet, so as to obtain the alignment information among the target control signal, t3, the data packet, and the target function. That is, through this method, it is possible to clearly know the data packet currently received by the processor and the target function that generates the data packet, and obtain the mapping relationship between the data packet and the target function, which is convenient for subsequent analysis.

[0041] In summary, the present invention provides a method for monitoring the software processing delay of data packets. When the expansion card monitors that the server sends a data packet, it sends a control signal to the processor, causing the processor to record the time t1 when it receives the control signal; the processor records the time t2 when it receives the data packet; and the software processing delay of the data packet is obtained according to t1 and t2, where both t1 and t2 are the timestamps of the processor itself, thereby solving the problem of asynchronous time between the server sending the data packet and the processor receiving the data packet.

[0042] An embodiment of the present invention further provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one segment of a program related to implementing a method in the method embodiment. The at least one instruction or the at least one segment of the program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0043] An embodiment of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0044] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps in the methods according to various exemplary embodiments of the present invention described above in this specification.

[0045] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0046] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention disclosed is defined by the appended claims.

Claims

1. A method for monitoring data packet software processing delay, characterized in that: The method comprises: S100, obtaining a server, a processor and an expansion card; wherein the server and the processor are interconnected via a high-speed interface; the expansion card is interconnected with the server via the high-speed interface and is interconnected with the processor via an output interface; S200, the server sends a data packet to the processor; S300, when the expansion card detects that the server sends the data packet, the expansion card sends a control signal to the processor; S400, when the processor receives the control signal, the processor records the current timestamp t1 internally; S500, when the processor receives the data packet, the processor records the timestamp t2 of receiving the data packet; obtains the software processing delay of the data packet according to t1 and t2; wherein the software processing delay △t of the data packet satisfies: △t=t2-t1; or, △t=t2-(t1+tt1), wherein tt1 is a preset hardware delay.

2. The method according to claim 1, characterized in that S100 also includes a network analyzer, which is connected between the server and the processor and is used to obtain data packets transmitted between the server and the processor.

3. The method according to claim 2, characterized in that The S100 also includes: The network analyzer is interconnected with the expansion card via a high-speed interface; S300 also includes: when the expansion card detects the data packet sent by the server, the expansion card also sends the control signal to the network analyzer at the same time.

4. The method according to claim 3, characterized in that The network analyzer is also used to: obtain the timestamp t3 of the data packet, track and trigger the network analyzer to obtain the target control signal of the data packet through the t3, obtain the data packet sent by the server within the error range through the target control signal, and the target function called before the server sends the data packet, and obtain the alignment information among the target control signal, t3, the data packet and the target function.

5. The method according to claim 1, characterized in that S400 also includes: when the processor receives the control signal, the processor performs a pre-processing operation for receiving the data packet.

6. The method according to claim 5, characterized in that The preprocessing operation includes one or more of the following operations: Time synchronization is performed through t1; Pre-allocate buffers and processing units; Dynamically adjust resource allocation; Preconfigure the data path for parallel processing.

7. The method according to claim 1, characterized in that The processor records timestamps internally by using one or more hardware counters to track time; when the processor receives a control signal, it immediately reads the value of the counter and stores it in a register or memory location.

8. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 8.

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