Method, apparatus, and article of manufacture for addressing device coupled to network bus

Abstract

The invention relates to a method, an apparatus, and an article of manufacture for addressing a device coupled to a network bus. An example apparatus (104) includes a configurable counter (204), an analog-to-digital converter (206), communication circuitry (208), and control circuitry (202). The example analog-to-digital converter (206) may be configured to sample a first voltage at a first node (222) on a bus (106). The example communication circuitry (208) may be configured to set a second node (224) on the bus (106) to a second voltage. In addition, the example control circuitry (202) may be configured to incrementally increase the counter (204) when the first voltage does not meet a threshold, and assign an address for a device based on a value of the counter (204) when the first voltage meets the threshold.

Description

Technical Field

[0001] The present specification relates generally to networking and, more particularly, to methods, apparatus, and articles of manufacture for addressing devices coupled to a network bus. Background Art

[0002] Vehicles (e.g., motor vehicles, manufacturing vehicles, etc.) typically include electronic devices to assist in the operation of corresponding components of the vehicle. For example, a vehicle may include an engine control unit (ECU) to assist in the operation of an engine, a transmission control unit (TCU) to assist in the operation of a transmission, an anti-lock braking system (ABS) to assist in the operation of brakes, and / or a body control module (BCM) to assist in the operation of components in the vehicle body (e.g., power windows, power mirrors, air conditioning, anti-theft systems, central locking systems, etc.). The electronic devices in the vehicle communicate via a dedicated internal communication network (e.g., a vehicle network), which interconnects the electronic devices of the vehicle via a vehicle bus. The vehicle bus may be implemented according to various communication protocols, such as a controller area network (CAN) protocol or a local interconnect network (LIN) protocol. Summary of the invention

[0003] For methods, apparatus, and articles of manufacture for addressing a device coupled to a network bus, an example apparatus includes a configurable counter, an analog / digital converter, communication circuitry, and control circuitry. The example analog / digital converter may be configured to sample a first voltage at a first node on the bus. The example communication circuitry may be configured to set a second node on the bus to a second voltage. Additionally, the example control circuitry may be configured to increment the counter when the first voltage does not meet a threshold, and to assign an address to the device based on a value of the counter when the first voltage meets the threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example environment in which an example commander device communicates with an example responder device via an example bus.

[0005] Figure 2 yes Figure 1 A block diagram of an example implementation of one or more of the responder devices.

[0006] Figure 3 Yes means you can use Figure 2 The present invention provides a flowchart of example machine-readable instructions and / or example operations to execute, instantiate and / or perform example programmable circuitry implementations of one or more of the responder devices of the present invention.

[0007] Figure 4is a block diagram of an example processing platform including a processor configured to execute, instantiate and / or perform example machine-readable instructions and / or perform Figure 3 Example operations to implement Figure 2 Programmable circuitry of one or more of the responder devices.

[0008] Figure 5 yes Figure 4 A block diagram of an example implementation of a programmable circuit system.

[0009] Figure 6 yes Figure 4 A block diagram of another example implementation of a programmable circuit system.

[0010] Figure 7 is used to transfer software, instructions and / or firmware (e.g., corresponding to Figure 3 Block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) for distributing example machine-readable instructions of the present invention to client devices associated with end users and / or consumers (e.g., for licensing, sale and / or use), retailers (e.g., for sale, resale, licensing and / or sublicensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to other end users such as retailers and / or direct purchasing customers).

[0011] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0012] The drawings are not necessarily drawn to scale. In general, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show areas with clean lines and borders, some or all of these lines and / or borders may be idealized. In reality, borders and / or lines may be unobservable, blended, and / or irregular.

[0013] Example vehicle buses are implemented according to communication protocols. Example communication protocols include CAN protocols and LIN protocols. A communication network implemented according to a specific communication protocol can be referred to by a communication protocol. Similarly, a bus implemented according to a specific communication protocol can be referred to by a communication protocol. For example, a communication network and a bus implemented according to a LIN protocol can be referred to as a LIN network and a LIN bus.

[0014] The LIN protocol is a serial network protocol. An example LIN bus can be implemented as a single conductor that supports communications up to 19.2 kilobits per second (Kbits / s) over a bus length of up to 40 meters. In some instances, a LIN network is a broadcast serial network that includes up to 16 devices. For example, a LIN network includes one commander device and up to 15 responder devices.

[0015] In an example operation of a LIN network, a message is initiated by a commander device, wherein a responder device replies to a given message identifier or responder device address. The commander device may also act as a responder device by replying to its own message. Because communication is initiated by a commander device, some LIN networks do not implement a message conflict detection mechanism. The example commander device and / or the example responder device may be implemented as a microcontroller, an application specific integrated circuit (ASIC), and / or other circuit systems.

[0016] As described above, a commander device of a LIN network can communicate with a responder device of a LIN network via a message addressed to the responder device address. In some LIN networks, the responder device uses hardware and / or software to deploy different addresses to the responder device. For example, the responder device uses hardware and / or software unique to the manufacturer, developer and / or seller of the responder device to deploy the address to the responder device. Thus, when multiple responder devices are used in a LIN network, multiple different hardware and / or software implementations can be used to provide addresses to the responder devices.

[0017] Thus, maintenance of a LIN network may include maintenance of various hardware and / or software implementations for providing addresses to responder devices. Thus, maintaining a LIN network using various responder devices may be difficult and / or expensive, at least due to the various hardware and / or software implementations for providing addresses to responder devices. Examples described herein include automated techniques for assigning addresses to responder devices. The disclosed methods, apparatus, and articles described herein assign addresses to responder devices based on time and / or location with respect to a commander device. For example, the responder devices use the same hardware and / or software implementation, and when the responder devices are enabled (e.g., turned on), the responder devices enter a configuration mode of operation, wherein each responder device identifies a distance between the responder device and the commander device (e.g., the distance may be determined as a function of time), and then assigns addresses to the responder devices based on the distance (and / or time).

[0018] Figure 1 1 is a block diagram of an example environment 100 in which an example commander device 102 communicates with an example responder device 104 via an example bus 106. For example, the environment 100 includes an example first responder device 104. A, Example Second Responder Device 104 B , Example third responder device 104 C and the example fourth responder device 104 D .exist Figure 1 In the example of FIG. 1 , the bus 106 is implemented according to the LIN protocol. Therefore, the bus 106 can be referred to as a LIN bus.

[0019] exist Figure 1 In the example of FIG. 1 , bus 106 includes a first responder device 104 A The corresponding example first resistor 108 A (For example, R1 A ) and the second responder device 104 B The corresponding example first resistor 108 B (For example, R1 B In addition, the bus 106 includes a third responder device 104 C The corresponding example first resistor 108 C (For example, R1 C ) and the fourth responder device 104 D The corresponding example first resistor 108 D (For example, R1 D ).exist Figure 1 In the example of , the respective responder device 104 is coupled to the example second resistor 110 , the example third resistor 112 , and the example ground terminal 114 .

[0020] exist Figure 1 In the example shown, the commander device 102 includes input and / or output (I / O) terminals. Example I / O terminals of the commander device 102 are connected to the first resistor 108. A (For example, R1 A ) is coupled to the bus 106 at a first terminal. In addition, an example I / O terminal of the commander device 102 is coupled to the first responder device 104 A The corresponding example second resistor 110 A The first terminal of Figure 1 In the example of , the commander device 102 includes example communication circuitry and example controller circuitry. In example operation, the commander device 102 sets (eg, maintains) the bus 106 to a first voltage (eg, a high voltage such as 12 volts (V)).

[0021] exist Figure 1 In the example shown, the first responder device 104 A It includes a first terminal, a second terminal, a third terminal and a fourth terminal. Figure 1 In the example ofA The first terminal of the first resistor 108 A (For example, R1 A ) and the first resistor 108 B (For example, R1 B ) is coupled to the bus 106 at a first terminal. In addition, the first responder device 104 A The first terminal is coupled to the second responder device 104 B The corresponding example second resistor 110 B (For example, R2 B ) first terminal. Figure 1 In the example of A The second terminal of the second resistor 110 is coupled to A (For example, R2 A ) and the first responder device 104 A The corresponding example third resistor 112 A (For example, R3 A ) first terminal.

[0022] exist Figure 1 In the example shown, the first responder device 104 A The third terminal is coupled to the third resistor 112 A (For example, R3 A ) second terminal. Figure 1 In the example of A The fourth terminal is coupled to the example first ground terminal 114 A Example First Responder Device 104 A The first responder device 104 includes example communication circuitry, example controller circuitry, example sampling circuitry, example counter circuitry, and example oscillator circuitry. When enabled (eg, turned on), the first responder device 104 A Enters the configuration mode of operation described further in this document.

[0023] exist Figure 1 In the example shown, the second responder device 104 B It includes a first terminal, a second terminal, a third terminal and a fourth terminal. Figure 1 In the example of B The first terminal of the first resistor 108 B (For example, R1 B ) and the second terminal of the first resistor 108 C (For example, R1 C ) is coupled to the bus 106 at a first terminal. In addition, the second responder device 104 BThe first terminal is coupled to the third responder device 104 C The corresponding example second resistor 110 C (For example, R2 C ) first terminal. Figure 1 In the example of B The second terminal of the second resistor 110 is coupled to B (For example, R2 B ) and the second responder device 104 B The corresponding example third resistor 112 B (For example, R3 B ) first terminal.

[0024] exist Figure 1 In the example shown, the second responder device 104 B The third terminal is coupled to the third resistor 112 B (For example, R3 B ) second terminal. Figure 1 In the example of B The fourth terminal is coupled to the example second ground terminal 114 B Example Second Responder Device 104 B The second responder device 104 includes an example communication circuit system, an example controller circuit system, an example sampling circuit system, an example counter circuit system, and an example oscillator circuit system. When enabled (eg, turned on), the second responder device 104 B Enters the configuration mode of operation described further in this document.

[0025] exist Figure 1 In the example shown, the third responder device 104 C It includes a first terminal, a second terminal, a third terminal and a fourth terminal. Figure 1 In the example of C The first terminal of the first resistor 108 C (For example, R1 C ) and the second terminal of the first resistor 108 D (For example, R1 D ) is coupled to the bus 106 at a first terminal. In addition, the third responder device 104 C The first terminal is coupled to the fourth responder device 104 D The corresponding example second resistor 110 D (For example, R2 D ) first terminal. Figure 1 In the example of C The second terminal of the second resistor 110 is coupled toC (For example, R2 C ) and the third responder device 104 C The corresponding example third resistor 112 C (For example, R3 C ) first terminal.

[0026] exist Figure 1 In the example shown, the third responder device 104 C The third terminal is coupled to the third resistor 112 C (For example, R3 C ) second terminal. Figure 1 In the example of C The fourth terminal is coupled to the example third ground terminal 114 C Example Third Responder Device 104 C The third responder device 104 includes an example communication circuit system, an example controller circuit system, an example sampling circuit system, an example counter circuit system, and an example oscillator circuit system. When enabled (eg, turned on), the third responder device 104 C Enters the configuration mode of operation described further in this document.

[0027] exist Figure 1 In the example shown, the fourth responder device 104 D It includes a first terminal, a second terminal, a third terminal and a fourth terminal. Figure 1 In the example of D The first terminal of the first resistor 108 D (For example, R1 D ) is coupled to bus 106 at a second terminal. Figure 1 In the example, the fourth responder device 104 D The second terminal of the second resistor 110 is coupled to D (For example, R2 D ) and the fourth responder device 104 D The corresponding example third resistor 112 D (For example, R3 D ) first terminal.

[0028] exist Figure 1 In the example shown, the fourth responder device 104 D The third terminal is coupled to the third resistor 112 D (For example, R3 D ) second terminal. Figure 1 In the example, the fourth responder device 104 D The fourth terminal of the example is coupled to the fourth ground terminal 114D Example Fourth Responder Device 104 D The fourth responder device 104 includes an example communication circuit system, an example controller circuit system, an example sampling circuit system, an example counter circuit system, and an example oscillator circuit system. When enabled (eg, turned on), the fourth responder device 104 D Enters the configuration mode of operation described further in this document.

[0029] As described above, some of the responder devices 104 may be physically closer to the commander device 102 than other responder devices 104. Figure 1 In the example of A The second responder device 104 B , the third responder device 104 C and the fourth responder device 104 D is physically closer to the commander device 102. Figure 1 In the example of B The third responder device 104 C and the fourth responder device 104 D is physically closer to the commander device 102. Figure 1 In the example of C The fourth responder device 104 D Physically closer to commander device 102 .

[0030] In an example configuration mode of operation (sometimes referred to as configuration mode), each of the responder devices 104 assigns itself an address based on the respective distance of the responder device 104 relative to the commander device 102 along the bus 106. For example, during a first iteration of configuration mode, the first responder device 104 A By including the second resistor 110 A and the third resistor 112 A The voltage divider samples the voltage to monitor the first resistor 108 A (For example, R1 A During the first iteration of the configuration mode, the first responder device 104 A The first resistor 108 A The voltage at the second terminal of is set to a second voltage (eg, a low voltage such as 0V). Additionally, during the first iteration of the configuration mode, the second responder device 104 B By including the second resistor 110 B and the third resistor 112 BThe voltage divider samples the voltage to monitor the first resistor 108 B (For example, R1 B During the first iteration of the configuration mode, the second responder device 104 B The first resistor 108 B The voltage at the second terminal of is set to a second voltage (eg, a low voltage such as 0 V).

[0031] Therefore, during the first iteration of the configuration mode, the first responder device 104 A By including the second resistor 110 A and the third resistor 112 A The voltage divider for the first resistor 108 A (For example, R1 A ) is sampled at a first voltage (e.g., 12V) at a first terminal of the second responder device 104. B By including the second resistor 110 B and the third resistor 112 B The voltage divider for the first resistor 108 B (For example, R1 B ) is sampled. Each of the responder devices 104 compares the sampled voltage with a preset threshold. B The voltage at the first terminal of is the second voltage (eg, 0V), so the second responder device 104 B The sampled voltage (eg, 0 V) ​​does not meet a preset threshold.

[0032] On the contrary, since the first resistor 108 A The voltage at the first terminal of is set to a first voltage (eg, 12 V), so the first responder device 104 A The sampled voltage is non-zero and may meet a preset threshold. A If the sampled voltage meets (eg, exceeds) a preset threshold, the first responder device 104 A Based on the first responder device 104 A Maintaining a counter and / or timer to the first responder device 104 A Assigning Addresses. In the examples described herein, each of the responder devices 104 increments a counter and / or timer in each iteration of the configuration mode.

[0033] During the second iteration of the configuration mode, the first responder device 104 A The first resistor 108A The voltage at the second terminal of is set to a first voltage (eg, a high voltage such as 12V). Additionally, during a second iteration of the configuration mode, the second responder device 104 B By including the second resistor 110 B and the third resistor 112 B The voltage divider samples the voltage to monitor the first resistor 108 B (For example, R1 B During the second iteration of the configuration mode, the second responder device 104 B The first resistor 108 B The voltage at the second terminal of is set to a second voltage (eg, a low voltage such as 0 V).

[0034] Therefore, during the second iteration of the configuration mode, the second responder device 104 B By including the second resistor 110 B and the third resistor 112 B The voltage divider for the first resistor 108 B (For example, R1 B ) is sampled by sampling a first voltage (eg, 12V) at a first terminal of the second responder device 104. B The sampled voltage is compared with a preset threshold. B The voltage at the first terminal of is the first voltage (eg, 12V), so the second responder device 104 B The sampled voltage is non-zero and may satisfy a preset threshold. B If the sampled voltage meets (eg, exceeds) a preset threshold, the second responder device 104 B Based on the second responder device 104 B The counter and / or timer is maintained to send a signal to the second responder device 104 B Assigning addresses. As described above, responder devices that are physically closer to the commander device 102 on the bus 106 assign corresponding addresses to themselves before devices that are physically farther away from the commander device 102. Therefore, the responder devices 104 assign corresponding addresses to themselves in a cascade order based on the distance (e.g., position) of the responder devices 104 relative to the commander device 102 on the bus 106.

[0035] According to the techniques of the present disclosure, when commander device 102 sets the voltage on bus 106, first responder device 104 A The first responder device 104 then assigns an address value to itself. A For the next responder device (eg, the second responder device 104B ) sets the voltage on bus 106. In a cascaded manner, each of the responder devices 104 assigns an address value to itself after the previous responder device or commander device 102 sets the voltage on bus 106. The described techniques may be easier to implement than other solutions, allowing responder devices manufactured by different manufacturers to operate autonomously using only the voltage on bus 106 as input. The described techniques may be implemented in hardware, software, and / or firmware. In addition, the described techniques may be pre-programmed or pre-built on each of the responder devices 104, and / or programmed into the responder devices after manufacture and assembly.

[0036] Figure 2 yes Figure 1 A block diagram of an example implementation of one or more of the responder devices 104 of FIG. Figure 2 In the example of , an example implementation of one or more of the responder devices 104 includes an example control circuit system 202, an example counter circuit system 204, an example analog-to-digital converter (ADC) 206, an example communication circuit system 208, an example oscillator circuit system 210, and an example data storage area 212. Figure 2 In the example of , an example implementation of one or more of the responder devices 104 also includes an example voltage source 216 (e.g., V SUPPLY ), an example diode 218, and an example fourth resistor 220 (e.g., R4). In the examples described herein, the commander device 102 includes similar circuitry (an example voltage source, an example diode, and an example pull-up resistor) to establish a voltage (e.g., 12V) on the bus 106.

[0037] exist Figure 2 In the example shown, control circuitry 202, counter circuitry 204, ADC 206, communication circuitry 208, oscillator circuitry 210, and data storage area 212 are coupled via an example internal bus 214. For example, internal bus 214 can be implemented using any suitable wired and / or wireless communications. In additional or alternative examples, internal bus 214 includes software, machine-readable instructions, and / or a communication protocol by which information is transferred between control circuitry 202, counter circuitry 204, ADC 206, communication circuitry 208, oscillator circuitry 210, and data storage area 212.

[0038] exist Figure 2 In the example shown, the bus 106 includes an example first node 222 at a first terminal of the first resistor 108 (eg, R1) and an example second node 224 at a second terminal of the first resistor 108 (eg, R1). Figure 2In the example of , the resistance of the first resistor 108 (eg, R1) is one thousand ohms (KΩ). Figure 2 In the example of , a first terminal of the control circuit system 202 is coupled to the internal bus 214. In addition, a first terminal of the counter circuit system 204 is coupled to the internal bus 214. Figure 2 In the example of , a first terminal of ADC 206 is coupled to internal bus 214. In addition, a second terminal of ADC 206 is coupled to a second terminal of second resistor 110 (eg, R2) and a first terminal of third resistor 112 (eg, R3). Figure 2 In the example of , a first terminal of the second resistor 110 (eg, R2) is coupled to the bus 106 at a first node 222. Figure 2 In the example of , the resistance of the second resistor 110 (eg, R2) is 10KΩ. In addition, the third terminal of the ADC 206 is coupled to the second terminal of the third resistor 112 (eg, R3). Figure 2 In the example of , the resistance of the third resistor 112 (eg, R1) is 2KΩ. Figure 2 In the example of , the fourth terminal of ADC 206 is coupled to the ground terminal 114 .

[0039] exist Figure 2 In the example shown, a first terminal of the communication circuit system 208 is coupled to the bus 106 and a second terminal of a fourth resistor 220 (eg, R4) at a second node 224. Additionally, a second terminal of the communication circuit system 208 is coupled to the internal bus 214. Figure 2 In the example of , a first terminal of the oscillator circuit system 210 is coupled to the internal bus 214. In addition, a first terminal of the data storage area 212 is coupled to the internal bus 214. Figure 2 In the example of FIG. 1 , the first terminal of the diode 218 is coupled to the voltage source 216 (eg, V SUPPLY ). In addition, a second terminal of the diode 218 is coupled to a first terminal of a fourth resistor 220 (eg, R4).

[0040] exist Figure 2 In the example shown, one or more of the example control circuit system 202, the example counter circuit system 204, the example ADC 206, the example communication circuit system 208, the example oscillator circuit system 210, or the example data storage area 212 can be instantiated (e.g., create an instance, generate for any length of time, materialize, implement, etc.) by programmable circuitry such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, in Figure 2In the example of, the example control circuit system 202, the example counter circuit system 204, the example ADC 206, the example communication circuit system 208, the example oscillator circuit system 210, or the example data storage area 212 can be instantiated (e.g., create an instance, generate, materialize, implement, etc. for any length of time) by (i) an application specific integrated circuit system (ASIC) and / or (ii) a field programmable gate array (FPGA) structured and / or configured to perform operations corresponding to the first instruction in response to executing the second instruction. It should be understood that Figure 2 Some or all of the circuitry may thus be instantiated at the same or different times. Figure 2 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute simultaneously on hardware and / or execute serially on hardware. Furthermore, in some instances, Figure 2 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry operating to implement one or more virtual machines and / or containers.

[0041] exist Figure 2 In the example shown, the control circuit system 202 is composed of, for example Figure 5 In addition or alternatively, the control circuit system 202 is implemented by an ASIC and / or a microcontroller such as a microprocessor 500. Figure 6 In some examples, the control circuit system 202 is implemented by executing control instructions and / or is configured to perform, for example, Figure 3 The operations represented by the flowcharts are instantiated by programmable circuitry. Figure 2 In the example of Figure 2 For example, the control circuit system 202 controls an example implementation of one or more of the responder devices 104 during a configuration operating mode and / or one or more post-configuration operating modes.

[0042] In some examples, an exemplary implementation of one or more of responder devices 104 includes means for controlling. For example, means for controlling can be implemented by control circuitry 202. In some examples, control circuitry 202 can be implemented by, for example, Figure 4 For example, the control circuit system 202 may be implemented by executing machine executable instructions (e.g., by Figure 3 at least those instructions implemented by blocks 302, 310, 312, 314, 316, 318, 322, and 324) Figure 5In some examples, the control circuit system 202 may be instantiated by a hardware logic circuit system, which may be an ASIC, an XPU, or a processor configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 6 The control circuit system 202 may be implemented by the FPGA circuit system 600 of the embodiment of the present invention. Additionally or alternatively, the control circuit system 202 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the control circuit system 202 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) without executing software or firmware, and the hardware circuit system is configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions, but other structures are equally suitable.

[0043] exist Figure 2 In the example shown, counter circuit system 204 is implemented by two or more flip-flops coupled in cascade. For example, counter circuit system 204 can be implemented as an asynchronous counter (e.g., a ripple counter) or a synchronous counter (e.g., a decade counter, a ring counter, a Johnson counter, etc.). In some examples, counter circuit system 204 is implemented by a timer or timer circuit system. In such examples, control circuit system 202 can be configured to assign addresses based on time values ​​stored in the timer circuit system. In some examples, counter circuit system 204 is implemented by executing counter instructions and / or timer instructions and / or is configured to perform, for example Figure 3 The operations represented by the flowcharts are instantiated by programmable circuitry. Figure 2 In an example of , counter circuitry 204 maintains a count to track the number of iterations of the configuration operating mode. For example, as described below, the count indicates the number of iterations of the configuration operating mode that occurred before control circuitry 202 assigned an address to an implementation of one or more of responder devices 104 (e.g., communication circuitry 208).

[0044] In some examples, an exemplary implementation of one or more of the responder devices 104 includes means for counting and / or for timing. For example, the means for counting and / or for timing may be implemented by the counter circuit system 204. In some examples, the counter circuit system 204 may be implemented by, for example, Figure 4 For example, the counter circuit system 204 may be implemented by a programmable circuit system such as the example programmable circuit system 412 of ... Figure 5In some examples, the counter circuit system 204 can be instantiated by hardware logic circuit system, which can be implemented by an ASIC, an XPU, or a processor configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 6 FPGA circuit system 600. Additionally or alternatively, counter circuit system 204 may be instantiated by any other combination of hardware, software, and / or firmware. For example, counter circuit system 204 may be implemented by at least one or more hardware circuits (e.g., processor circuit system, discrete and / or integrated analog and / or digital circuit system, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) without executing software or firmware, and the hardware circuit system is configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions, but other structures are equally suitable.

[0045] exist Figure 2 In the example shown, ADC 206 is comprised of, for example, Figure 5 In addition or alternatively, ADC 206 may be implemented by an ASIC and / or a microcontroller such as a microprocessor 500. Figure 6 In some examples, ADC 206 is implemented by executing sampling instructions and / or is configured to perform, for example, Figure 3 The operations represented by the flowcharts are instantiated by programmable circuitry. Figure 2 In the example of , ADC 206 includes a transistor. Figure 2 In the example of , the ADC 206 samples the voltage at the first node 222 on the bus 106 during the sampling period via a voltage divider including the second resistor 110 and the third resistor 112. For example, to sample the voltage at the first node 222, the ADC 206 couples the third resistor 112 (e.g., R3) to the ground terminal 114, thereby creating a voltage divider. Figure 2 In the example of , the transistor of ADC 206 is implemented by a metal oxide semiconductor field effect transistor (MOSFET). Thus, when sampling the voltage at the first node 222, ADC 206 connects the drain of the MOSFET to the third resistor 112 (eg, R3) and connects the source of the MOSFET to the ground terminal 114.

[0046] In some examples, an exemplary implementation of one or more of responder devices 104 includes means for sampling. For example, the means for sampling can be implemented by ADC circuitry, such as ADC 206. In some examples, ADC 206 can be implemented by, for example, Figure 4 4. For example, ADC 206 may be implemented by executing machine executable instructions (e.g., at least Figure 3 Those machine executable instructions implemented by blocks 304 and 308 of Figure 5 In some examples, ADC 206 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or a processor configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 6 206 may be implemented by an FPGA circuit system 600. Additionally or alternatively, ADC 206 may be instantiated by any other combination of hardware, software, and / or firmware. For example, ADC 206 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) without executing software or firmware, and the hardware circuit systems are configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions, but other structures are equally suitable.

[0047] exist Figure 2 In the example shown, the communication circuit system 208 is implemented by a transmitter, a receiver, and / or a transceiver. In some examples, the communication circuit system 208 is implemented by, for example, Figure 5 In addition or alternatively, the communication circuit system 208 is implemented by an ASIC and / or a microcontroller such as a microprocessor 500. Figure 6 In some examples, the communication circuit system 208 is implemented by executing communication instructions and / or being configured to perform, for example, Figure 3 The operations represented by the flowcharts are instantiated by programmable circuitry. Figure 2 In an example of , communication circuitry 208 controls the voltage at second node 224. For example, before control circuitry 202 assigns an address to an example implementation of one or more of responder devices 104, communication circuitry 208 sets second node 224 to a second voltage (e.g., a low voltage such as 0V). Additionally, after control circuitry 202 assigns an address to an example implementation of one or more of responder devices 104, communication circuitry 208 controls the voltage at second node 224 via voltage source 216 (e.g., V SUPPLY ), the diode 218 and the fourth resistor 220 (eg, R4) set the second node 224 to a first voltage (eg, a high voltage such as 12V).

[0048] In some examples, an example implementation of one or more of responder devices 104 includes means for communicating. For example, means for communicating may be implemented by communication circuitry 208. In some examples, communication circuitry 208 may be implemented by, for example, Figure 4 For example, communication circuit system 208 may be implemented by executing machine-executable instructions (e.g., by Figure 3 at least those instructions implemented by blocks 306 and 320) Figure 5 In some examples, the communication circuit system 208 may be instantiated by a hardware logic circuit system, which may be an ASIC, an XPU, or a processor configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 6 The communication circuit system 208 may be implemented by the FPGA circuit system 600 of the embodiment of the present invention. Additionally or alternatively, the communication circuit system 208 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the communication circuit system 208 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) without executing software or firmware, and the hardware circuit systems are configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions, but other structures are equally suitable.

[0049] exist Figure 2 In the example shown, oscillator circuit system 210 is implemented as a resistor-capacitor (RC) oscillator. For example, oscillator circuit system 210 can be implemented by a phase-shift oscillator, a twin-T oscillator, a quadrature oscillator, and / or a Wienbridge oscillator, etc. In additional or alternative examples, oscillator circuit system 210 can be implemented by a crystal oscillator. In some examples, oscillator circuit system 210 is implemented by executing clock instructions and / or is configured to perform, for example Figure 3 The operations represented by the flowcharts are instantiated by programmable circuitry. Figure 2 In an example of , oscillator circuitry 210 maintains a clock for an example implementation of one or more of responder devices 104 .

[0050] In some examples, an exemplary implementation of one or more of the responder devices 104 includes means for timing. For example, the means for timing can be implemented by the oscillator circuit system 210. In some examples, the oscillator circuit system 210 can be implemented by, for example, Figure 44. For example, oscillator circuit system 210 may be implemented by executing machine executable instructions. Figure 5 In some examples, the oscillator circuit system 210 can be instantiated by hardware logic circuit system, which can be implemented by an ASIC, an XPU, or a processor configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 6 The oscillator circuit system 210 may be implemented by the FPGA circuit system 600 of the embodiment of the present invention. Additionally or alternatively, the oscillator circuit system 210 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the oscillator circuit system 210 may be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) without executing software or firmware, and the hardware circuit systems are configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions, but other structures are equally suitable.

[0051] exist Figure 2 In the example shown, data storage area 212 includes data associated with configuring the operating mode. For example, data storage area 212 includes data indicating a threshold value to be used to determine whether to assign an address to an example embodiment of one or more of responder devices 104, indicating Figure 1 The example data storage area 212 also includes data indicating the length of a sampling period of the ADC 206 and / or data indicating the length of time to be used in determining the remaining amount of an addressing period of a configuration operating mode.

[0052] exist Figure 2In the example shown, the data storage area 212 can be implemented by volatile memory (e.g., synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), etc.) and / or non-volatile memory (e.g., flash memory). The data storage area 212 can also or alternatively be implemented by one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, DDR5, mobile DDR (mDDR), DDR SDRAM, etc. The data storage area 212 can also or alternatively be implemented by one or more mass storage devices, such as hard disk drives (HDDs), compact disk (CD) drives, digital versatile disk (DVD) drives, solid state disks (SSD) drives, secure digital (SD) cards, compact flash (CF) cards, etc. Although the data storage area 212 is shown as a single data storage area in the example shown, the data storage area 212 can be implemented by any number and / or type of data storage areas. Furthermore, the data stored in the data storage area 212 may be in any data format, such as binary data, comma-delimited data, tab-delimited data, structured query language (SQL) structures, and the like.

[0053] In an example operation, during the configuration mode of operation, the control circuitry 202 initializes the counter circuitry 204. For example, the control circuitry 202 initializes the counter circuitry 204 to a value of one. As described above, in some instances, the counter circuitry 204 may be implemented by a timer (e.g., timer circuitry). During the configuration mode of operation, the ADC 206 waits for the first node 222 on the bus 106 to stabilize at a first voltage (e.g., 12V). For example, the ADC 206 waits for 50 milliseconds (ms) for the first node 222 to stabilize at the first voltage. Additionally, during the configuration mode of operation, the communication circuitry 208 sets the second node 224 on the bus 106 to a second voltage (e.g., 0V).

[0054] In an example operation, during the configuration mode of operation, after the ADC 206 has waited for the first node 222 to stabilize at the first voltage, the ADC 206 samples the first voltage at the first node 222 on the bus 106 during a sampling period. Figure 2 In the example of , the sampling period used by ADC 206 is set to a value that allows the sampled voltage to stabilize. For example, ADC 206 samples the first voltage at first node 222 within a sampling period of 100 ms. During the configuration operation mode, control circuit system 202 calculates an average value of the first voltage sampled from first node 222 and determines whether the average value of the voltage meets (e.g., is greater than or equal to) a threshold value.

[0055] As described above, each of the commander device 102 and the responder device 104 includes a voltage source, a diode, and a pull-up resistor (e.g., R4). Therefore, when the communication circuit system 208 sets the second node 224 to a second voltage (e.g., 0V) during the sampling period, the pull-up resistor (e.g., R4) of the previous device in the LIN network and the first resistor 108 (e.g., R1) of the responder device that determines the threshold value form a voltage divider. Thus, the threshold value is determined based on the voltage divider, which includes the pull-up resistor (e.g., R4) of the previous device in the LIN network and the first resistor 108 (e.g., R1) of the responder device that determines the threshold value. For example, the threshold value is calculated according to the following equation 1.

[0056]

[0057] In the example of Equation 1, V 阈值 represents a threshold voltage value. For example, to determine whether a responder device is eligible to be assigned an address, the control circuit system 202 determines whether the voltage at the first node 222 meets (e.g., is greater than or equal to) the bus voltage (e.g., 12V). Thus, when the voltage at the first node 222 is set to the bus voltage (by the commander device 102 or another responder device), the voltage sampled by the ADC 206 will meet (e.g., be equal to or exceed) the threshold voltage value.

[0058] In the example of Equation 1, R1 indicates the resistance of the first resistor 108 (eg, R1) of the previous device in the LIN network, and R4 indicates the resistance of the fourth resistor 220 (eg, R4) of the previous device in the LIN network. SUPPLY Indicates the voltage source 216 (eg, V SUPPLLY ) voltage, and V D Indicates the voltage drop across diode 218 of the previous device in the LIN network. Figure 2 In the example of 阈值 ) is equal to 1.027V (for example, ).

[0059] exist Figure 2 In the example shown, during the configuration mode of operation, if the control circuit system 202 determines that the average value of the first voltage at the first node 222 satisfies (eg, is greater than or equal to) a threshold value (eg, V 阈值 )(For example, the average value is V O), control circuitry 202 assigns an address to an implementation of one or more of responder devices 104 (e.g., communication circuitry 208) based on the value of the counter maintained by counter circuitry 204. For example, the value of the counter may be mapped to an address for an implementation of one or more of responder devices 104 via a LUT. Thus, control circuitry 202 may determine the address to assign to an implementation of one or more of responder devices 104 by looking up the address in the LUT based on the value of the counter maintained by counter circuitry 204.

[0060] exist Figure 2 In the example shown, during the configuration mode of operation, if the control circuit system 202 determines that the average value of the first voltage at the first node 222 satisfies (eg, is greater than or equal to) a threshold value (eg, V 阈值 ), the control circuit system 202 increments the counter maintained by the counter circuit system 204. Therefore, the control circuit system 202 increments the counter circuit system 204 to track the iteration of the configuration operation mode. As described above, responder devices on the bus 106 that are physically closer to the commander device 102 assign corresponding addresses to themselves before devices that are physically farther away from the commander device 102. Thus, the value of the counter maintained by the counter circuit system 204 indicates the distance of the responder device from the commander device 102. Therefore, the control circuit system 202 assigns addresses to example embodiments of one or more of the responder devices 104 based on the distance of the example embodiments of the one or more of the responder devices 104 from the commander device 102.

[0061] exist Figure 2 In the example shown, during the configuration mode of operation, after control circuitry 202 assigns an address to an example implementation of one or more of responder devices 104, communication circuitry 208 supplies power to the device via voltage source 216 (e.g., V SUPPLY ), diode 218 and fourth resistor 220 (e.g., R4) set second node 224 to a first voltage (e.g., a high voltage, such as 12V). Thus, communication circuit system 208 allows subsequent responder devices in the LIN network to assign addresses to themselves. For example, Table 1 shows multiple iterations of configuring the operating mode.

[0062] Table 1

[0063]

[0064] In the example of Table 1, reference Figure 1, during the first iteration of the configuration mode, the commander device 102 sets the voltage at the I / O terminal of the commander device 102 to a high voltage (e.g., 12V). Additionally, during the first iteration of the configuration mode shown in Table 1, each of the responder devices 104 sets the voltage at the corresponding first terminal of the responder device 104 to a low voltage (e.g., 0V). Thus, only the first resistor 108 A The voltage sampled at the first terminal of meets the threshold voltage value (for example, V O ), and in the first resistor 108 B , first resistor 108 C and the first resistor 108 D The voltage sampled at the first terminal of is zero volts. Thus, during the first iteration of the configuration mode, only the first responder device 104 A Assigns an address to itself.

[0065] In the example of Table 1, reference Figure 1 During the second iteration of the configuration mode, the commander device 102 sets the voltage at the I / O terminal of the commander device 102 to a high voltage (e.g., 12V). Similarly, during the second iteration of the configuration mode shown in Table 1, the first responder device 104 A The first responder device 104 A The voltage at the first terminal of is set to a high voltage (eg, 12V). In addition, during the second iteration of the configuration mode shown in Table 1, the second responder device 104 B , the third responder device 104 C and the fourth responder device 104 D Each of the second responder devices 104 B , the third responder device 104 C and the fourth responder device 104 D The voltage at the corresponding first terminal of the resistor 108 is set to a low voltage (eg, 0V). A The first terminal is at a power supply voltage (e.g., V SUPPLY ). Therefore, only the first resistor 108 B The voltage sampled at the first terminal of meets the threshold voltage value (for example, V O ), and in the first resistor 108 C and the first resistor 108 D The voltage sampled at the first terminal of is zero volts. Thus, during the second iteration of the configuration mode, only the second responder device 104 B Assigns an address to itself.

[0066] In the example of Table 1, reference Figure 1During the third iteration of the configuration mode, the commander device 102 sets the voltage at the I / O terminal of the commander device 102 to a high voltage (e.g., 12V). Similarly, during the third iteration of the configuration mode shown in Table 1, the first responder device 104 A and the second responder device 104 B Each of the first responder devices 104 A and the second responder device 104 B The voltage at the corresponding first terminal of is set to a high voltage (eg, 12V). In addition, during the third iteration of the configuration mode shown in Table 1, the third responder device 104 C and the fourth responder device 104 D Each of the third responder devices 104 C and the fourth responder device 104 D The voltage at the corresponding first terminal of the resistor 108 is set to a low voltage (eg, 0V). A and the first resistor 108 B The first terminal is at a power supply voltage (e.g., V SUPPLY ). Therefore, only the first resistor 108 C The voltage sampled at the first terminal of meets the threshold voltage value (for example, V O ), and in the first resistor 108 D The voltage sampled at the first terminal of is zero volts. Thus, during the third iteration of the configuration mode, only the third responder device 104 C Assigns an address to itself.

[0067] In the example of Table 1, reference Figure 1 During the fourth iteration of the configuration mode, the commander device 102 sets the voltage at the I / O terminal of the commander device 102 to a high voltage (e.g., 12V). Similarly, during the fourth iteration of the configuration mode shown in Table 1, the first responder device 104 A , second responder device 104 B and the third responder device 104 C Each of the first responder devices 104 A , second responder device 104 B and the third responder device 104 C The voltage at the corresponding first terminal of is set to a high voltage (eg, 12V). In addition, during the fourth iteration of the configuration mode shown in Table 1, the fourth responder device 104 D The fourth responder device 104 D The voltage at the first terminal of is set to a low voltage (eg, 0V). Therefore, the first resistor 108 A, first resistor 108 B and the first resistor 108 C The first terminal is at a power supply voltage (e.g., V SUPPLY ). Therefore, only the first resistor 108 D The voltage sampled at the first terminal of meets the threshold voltage value (for example, V O ). Thus, during the fourth iteration of the configuration mode, only the fourth responder device 104 D Assigns an address to itself.

[0068] Despite Figure 2 The implementation is shown in Figure 1 An example embodiment of one or more of the responder devices 104, but Figure 2 One or more of the elements, processes, and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. In addition, the example control circuit system 202, the example counter circuit system 204, the example ADC 206, the example communication circuit system 208, the example oscillator circuit system 210, the example data storage area 212, and / or more generally Figure 2 One or more of the example responder devices 104 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the example control circuitry 202, the example counter circuitry 204, the example ADC 206, the example communication circuitry 208, the example oscillator circuitry 210, the example data storage area 212, and / or more generally the example responder devices 104 may be implemented by programmable circuitry with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), and / or a field programmable logic device (FPLD) such as an FPGA. Further, Figure 2 One or more of the example responder devices 104 may include Figure 2 The present invention may include one or more elements, processes and / or devices in addition to and / or in place of the elements, processes and / or devices shown in the present invention, and / or may include more than one of any or all of the elements, processes and devices shown.

[0069] Figure 3 A flowchart is shown in FIG. 1, which indicates that a programmable circuit system may execute to implement and / or instantiate Figure 2 Example machine-readable instructions of one or more of the responder devices 104 of the present invention and / or instructions executable by the programmable circuitry (eg, instructions that cause the programmable circuitry) to implement and / or instantiate Figure 2The machine-readable instructions may be instructions that are executed by a programmable circuit system (e.g., as described below in conjunction with Figure 4 The programmable circuit system 412 shown in the example programmable circuit system platform 400 described herein may be executed by one or more executable programs or one or more executable programs or portions thereof, and / or may be described below in conjunction with Figure 5 In some examples, the machine-readable instructions cause operations, tasks, etc. to be performed and / or carried out in an automated manner in the real world. As used herein, "automatic" means without human intervention.

[0070] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROMs, solid-state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memory, etc.), volatile memories (e.g., any type of random access memory (RAM), etc.), and / or any other storage devices or storage disks. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuit systems located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than programmable circuit systems. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Furthermore, although reference is made to Figure 3The flowchart shown in describes an example procedure, but many other methods of implementing one or more of the example responder devices 104 may be used instead. For example, the execution order of the blocks of the flowchart may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuit, etc.) without executing software or firmware, and the hardware circuitry is configured to perform the corresponding operations. The programmable circuitry may be distributed at different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit system (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0071] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.), or a data structure (e.g., instructions, portions of code, representations of code, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations of a network or collection of networks (e.g., in the cloud, an edge device, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, etc., so that they can be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions that are separately compressed, encrypted, and / or stored on separate computing devices, wherein the portions, when decrypted, decompressed, and / or combined, form a computer-executable and / or machine-executable instruction set that implements one or more functions and / or operations that may together form, for example, the procedures described herein.

[0072] In another example, the machine-readable instructions may be stored in a state in which they can be read by the programmable circuit system, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., may need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable and / or machine-readable media may contain instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or programs.

[0073] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0074] As mentioned above, Figure 3The example operations of can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagation signals and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks, wherein information is stored for any duration (e.g., for an extended period of time, permanently, for a short instance, for a temporary buffer, and / or for cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware that retains information for a period of time, but excludes propagating signals and excludes transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuit system, that may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0075] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any kind of claim statement, it is understood that additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or statement. As used herein, the phrase "at least" when used as a transitional term, such as in a claim preamble, is open-ended, in the same way that the terms "comprising" and "including" are open-ended.

[0076] As used herein, singular references (e.g., "a", "an", "first", "second", etc.) do not exclude the plural. As used herein, the term "a" or "an" object refers to one or more of said objects. The terms "a" (or "an"), "one or more" and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different instances or claims, these features may be combined, and inclusion in different instances or claims does not mean that a combination of features is not feasible and / or disadvantageous.

[0077] Figure 3 Yes means you can use Figure 2 A flowchart of example machine readable instructions and / or example operations 300 to be executed, instantiated, and / or performed by an example programmable circuitry implementation of one or more of the responder devices 104 of the present invention. Figure 3 The example machine readable instructions and / or example operations 300 of the embodiment begin at block 302, where the control circuitry 202 initializes a counter maintained by the counter circuitry 204. For example, the control circuitry 202 initializes the counter to a value of zero or one. The control circuitry 202 may be configured to initialize the counter circuitry 204 at startup (e.g., in response to the responder device 104 being powered on). For example, the control circuitry 202 may initialize the counter circuitry 204 in response to receiving power at a power supply node (e.g., a VDD rail).

[0078] exist Figure 3 In the example shown, at block 304, ADC 206 waits for a first node on the bus to stabilize at a first voltage. For example, ADC 206 waits for a first node 222 on bus 106 to stabilize at a high value (e.g., 12V). For another example, ADC 206 waits for 100 ms for a first node 222 on bus 106 to stabilize at a high value (e.g., 12V). At block 306, communication circuit system 208 sets a second node on the bus to a second voltage (e.g., the machine-readable instructions and / or operations 300 cause the communication circuit system to set a second node on the bus to a second voltage). For example, communication circuit system 208 sets a second node 224 on bus 106 to a low value (e.g., 0V). At block 308, ADC 206 samples a first voltage at a first node on the bus. For example, ADC 206 samples a first voltage at a first node 222 on bus 106.

[0079] exist Figure 3In the example shown, at block 310, the control circuit system 202 determines whether the sampling period has ended (e.g., expired). For example, the sampling period is 100 ms. Based on (e.g., in response to) the control circuit system 202 determining that the sampling period has not ended (block 310: No), the machine-readable instructions and / or operations 300 return to block 308. Based on (e.g., in response to) the control circuit system 202 determining that the sampling period has ended (block 310: Yes), the machine-readable instructions and / or operations 300 proceed to block 312.

[0080] exist Figure 3 In the example shown, at block 312, the control circuit system 202 calculates an average value of the first voltage at the first node over the sampling period. At block 314, the control circuit system 202 determines whether the average value of the first voltage at the first node satisfies a threshold value. Based on (e.g., in response to) the control circuit system 202 determining that the average value of the first voltage at the first node does not satisfy the threshold value (block 314: No), the machine-readable instructions and / or operations 300 proceed to block 316. At block 316, the control circuit system 202 increments a counter maintained by the counter circuit system 204. Based on (e.g., in response to) the control circuit system 202 determining that the average value of the first voltage at the first node does satisfy the threshold value (block 314: Yes), the machine-readable instructions and / or operations 300 proceed to block 318.

[0081] exist Figure 3 In the example shown, at block 318, control circuitry 202 assigns addresses to communication circuitry of one or more of responder devices 104 based on the value of the counter. For example, control circuitry 202 assigns addresses to communication circuitry 208 based on Table 2 below, which may be implemented as a LUT.

[0082] Table 2

[0083] Counter value address 1 0x51 2 0x52 3 0x53 4 0x54

[0084] exist Figure 3In the example shown, at block 320, the communication circuit system 208 sets the second node to a first voltage. For example, the communication circuit system 208 sets the voltage at the second node 224 to a high value (e.g., 12V). At block 322, the control circuit system 202 determines whether the addressing cycle has ended. In the example described herein, at block 322, the remaining period of the addressing cycle at each of the responder devices 104 is different based on the number of responder devices remaining to be addressed. For example, the remaining period of the addressing cycle is based on the value of the counter maintained by the counter circuit system and the number of responder devices in the LIN network. For example, if there are four responder devices in the LIN network, and at block 322, the counter value is two (which has been initialized to one), the control circuit system 202 determines that two responder devices in the LIN network have self-assigned addresses, and two responder devices in the LIN network have not self-assigned addresses. Thus, the remaining period of the addressing cycle can be calculated based on the number of responder devices that have not self-assigned addresses and the delay of each iteration of the configuration operation mode. For example, the delay for each iteration of the configuration operation mode is 200ms.

[0085] exist Figure 3 In the example shown, based on (e.g., in response to) the control circuitry 202 determining that the addressing period has not ended (block 322: No), the machine-readable instructions and / or operations 300 return to block 320. Based on (e.g., in response to) the control circuitry 202 determining that the addressing period has ended (block 322: Yes), the machine-readable instructions and / or operations 300 proceed to block 324. At block 324, the control circuitry 202 operates in the post-configuration operating mode.

[0086] Figure 4 is a block diagram of an example programmable circuit system platform 400 that is configured to execute and / or instantiate Figure 3 Example machine readable instructions and / or example operations to implement Figure 2 The programmable circuit system platform 400 may be, for example, a microcontroller, a semiconductor device, an integrated circuit (IC), a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, an iPad, etc.). TM tablet computer (e.g., a tablet computer, a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, headphones (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0087] The programmable circuit system platform 400 of the illustrated example includes a programmable circuit system 412. The programmable circuit system 412 of the illustrated example is hardware. For example, the programmable circuit system 412 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired series or manufacturer. The programmable circuit system 412 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 412 implements the example control circuit system 202, the example counter circuit system 204, the example ADC 206, the example communication circuit system 208, and the example oscillator circuit system 210.

[0088] The programmable circuit system 412 of the illustrated example includes a local memory 413 (e.g., cache, registers, etc.). The programmable circuit system 412 of the illustrated example communicates with a main memory 414, 416 via a bus 418, wherein the main memory includes a volatile memory 414 and a non-volatile memory 416. The volatile memory 414 may be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 416 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 414, 416 of the illustrated example is controlled by a memory controller 417. In some examples, the memory controller 417 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer to manage the flow of data to and from the main memories 414, 416.

[0089] The programmable circuit system platform 400 of the illustrated example also includes an interface circuit system 420. The interface circuit system 420 can be implemented by hardware that complies with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0090] In the example shown, one or more input devices 422 are connected to the interface circuitry 420. The input devices 422 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 412. The input devices 422 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isochronous device, and / or a voice recognition system.

[0091] One or more output devices 424 are also connected to the interface circuit system 420 of the illustrated example. The output device 424 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit system 420 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit system such as a GPU.

[0092] The interface circuitry 420 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any type of computing device) via the network 426. Communications may occur via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0093] The programmable circuit system platform 400 of the illustrated example also includes one or more mass storage disks or devices 428 for storing firmware, software, and / or data. In this example, the one or more mass storage disks or devices 428 implement the example data storage area 212. Examples of such mass storage disks or devices 428 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0094] Can be Figure 3 The machine-readable instructions 432 implemented by the machine-readable instructions may be stored in the mass storage device 428, in the volatile memory 414, in the non-volatile storage 416, and / or on at least one non-transitory computer-readable storage medium such as a CD or DVD that may be removable.

[0095] Figure 5 yes Figure 4 412. In this example, Figure 4 The programmable circuit system 412 is implemented by the microprocessor 500. For example, the microprocessor 500 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 500 executes Figure 3 Some or all of the machine-readable instructions of the flowchart to effectively Figure 2 The circuit system is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such instances, Figure 2The circuit system is instantiated by the hardware circuits of the microprocessor 500 in combination with machine-readable instructions. For example, the microprocessor 500 may be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although it may include any number of example cores 502 (e.g., 1 core), the microprocessor 500 of this example is a multi-core semiconductor device including N cores. The cores 502 of the microprocessor 500 may operate independently or may cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 502, or may be executed by multiple of the cores 502 at the same or different times. In some instances, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more cores 502. The software program may correspond to a program executed by Figure 3 A flowchart may represent a portion or all of machine-readable instructions and / or operations.

[0096] The core 502 can communicate via a first example bus 504. In some instances, the first bus 504 can be implemented by a communication bus to enable communications associated with one or more cores 502. For example, the first bus 504 can be implemented by at least one of an inter-integrated circuit system (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 504 can be implemented by any other type of computing or electrical bus. The core 502 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit system 506. The core 502 can output data, instructions, and / or signals to one or more external devices via the interface circuit system 506. Although the cores 502 of this example include example local memory 520 (e.g., a level 1 (L1) cache that can be divided into a L1 data cache and an L1 instruction cache), the microprocessor 500 also includes example shared memory 510 that can be shared by the cores (e.g., a level 2 (L2) cache) for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from the shared memory 510. The local memory 520 and shared memory 510 of each of the cores 502 can be a plurality of levels of cache memory and main memory (e.g., Figure 4 Cache memory is part of a hierarchy of storage devices (main memory 414, 416). Generally, memory at higher levels in the hierarchy exhibits less access time and has less storage capacity than memory at lower levels. Changes in corresponding levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0097] Each core 502 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit system. Each core 502 includes a control unit circuit system 514, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 516, a plurality of registers 518, a local memory 520, and a second example bus 522. Other structures may exist. For example, each core 502 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating point unit (FPU) circuit system, etc. The control unit circuit system 514 includes a semiconductor-based circuit configured to control (e.g., coordinate) data movement within the corresponding core 502. The AL circuit system 516 includes a semiconductor-based circuit configured to perform one or more mathematical and / or logical operations on data within the corresponding core 502. The AL circuit system 516 of some instances performs integer-based operations. In other instances, the AL circuit system 516 also performs floating-point operations. In still other examples, AL circuitry 516 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 516 may be referred to as an arithmetic logic unit (ALU).

[0098] Registers 518 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more operations performed by the AL circuit system 516 of the corresponding core 502. For example, registers 518 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 518 may be as follows: Figure 5 The registers 518 are shown arranged in a bank. Alternatively, the registers 518 may be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 502 to reduce access time. The second bus 522 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0099] Each core 502 and / or more generally the microprocessor 500 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stops (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuitry. The microprocessor 500 is a semiconductor device that is fabricated to include many interconnected transistors to implement the structures described above in one or more integrated circuit systems (ICs) contained in one or more packages.

[0100] The microprocessor 500 may include and / or collaborate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, the accelerator is implemented by a logic circuitry to perform certain tasks faster and / or more efficiently than can be performed by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be on board the microprocessor 500, in the same chip package as the microprocessor 500, and / or in one or more packages separate from the microprocessor 500.

[0101] Figure 6 yes Figure 4 6 is a block diagram of another example embodiment of programmable circuit system 412. In this example, programmable circuit system 412 is implemented by FPGA circuit system 600. For example, FPGA circuit system 600 can be implemented by an FPGA. FPGA circuit system 600 can be used, for example, to perform operations that might otherwise be performed by executing corresponding machine-readable instructions. Figure 5 However, once configured, FPGA circuitry 600 instantiates operations and / or functions corresponding to machine-readable instructions in hardware, and thus can typically perform the operations / functions more quickly than if the operations / functions could be performed by a general-purpose microprocessor executing corresponding software.

[0102] More specifically, Figure 5 The microprocessor 500 (which can be programmed to execute Figure 3 Compared to a general purpose device in which some or all of the machine-readable instructions are represented by a flowchart, but whose interconnections and logic circuitry are fixed once manufactured, Figure 6 The FPGA circuit system 600 of the example includes a circuit that can be configured, structured, programmed and / or interconnected in different ways after manufacturing to instantiate, for example, Figure 3 FPGA circuit system 600 may be thought of as an array of logic gates, interconnects, and switches. The switches may be programmed to change the way the logic gates are interconnected via the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit system 600 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by the input circuit system. These operations may correspond to the operations performed by the FPGA circuit system. Figure 3 Thus, FPGA circuit system 600 can be configured and / or constructed to effectively instantiate the same as Figure 3, as a dedicated logic circuit, performs the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Thus, the FPGA circuit system 600 can perform operations / functions corresponding to those software instructions faster than a general-purpose microprocessor can perform. Figure 3 Some or all of the machine-readable instructions correspond to operations / functions.

[0103] exist Figure 6 In an example, the FPGA circuit system 600 is configured and / or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, a binary file can be compiled and / or generated based on instructions using a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in an HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Figure 6 The FPGA circuit system 600 can access and / or load the binary file so that Figure 6 The FPGA circuit system 600 is configured and / or constructed to perform one or more operations / functions. For example, the FPGA circuit system 600 may be ... Figure 6 The FPGA circuit system 600 can access the machine-readable instruction implementation binary file to enable the Figure 6 Configuration and / or construction of FPGA circuit system 600 or a portion thereof.

[0104] In some instances, the binary file is compiled, generated, converted, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform may translate a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in an HDL. In some such instances, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instruction. In some instances, Figure 6 The FPGA circuit system 600 can access and / or load the binary file so that Figure 6The FPGA circuit system 600 is configured and / or constructed to perform one or more operations / functions. For example, the FPGA circuit system 600 may be ... Figure 6 The FPGA circuit system 600 can access the machine-readable instruction implementation binary file to enable the Figure 6 Configuration and / or construction of FPGA circuit system 600 or a portion thereof.

[0105] Figure 6 The FPGA circuit system 600 includes an example input / output (I / O) circuit system 602 to obtain data from and / or output data to an example configuration circuit system 604 and / or external hardware 606. For example, the configuration circuit system 604 can be implemented by an interface circuit system, which can obtain a binary file that can be implemented by a bitstream, data, and / or machine-readable instructions to configure the FPGA circuit system 600 or a portion thereof. In some such instances, the configuration circuit system 604 can obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any combination thereof. In some instances, the external hardware 606 can be implemented by an external hardware circuit system. For example, the external hardware 606 can be implemented by Figure 5 The microprocessor 500 is implemented.

[0106] FPGA circuitry 600 also includes an array of example logic gate circuitry 608, a plurality of example configurable interconnects 610, and example storage circuitry 612. Logic gate circuitry 608 and configurable interconnects 610 may be configured to instantiate Figure 3 One or more operations / functions corresponding to at least some of the machine-readable instructions and / or other desired operations. Figure 6 The logic gate circuit system 608 shown in is manufactured in the form of blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. An electrically controlled switch (e.g., a transistor) is present in each of the logic gate circuit system 608 to enable the electrical structure and / or the logic gate to be configured to form a circuit system that performs the desired operation / function. The logic gate circuit system 608 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0107] The configurable interconnect 610 of the illustrated example is a conductive path, trace, via, etc. that may include electrically controlled switches (e.g., transistors), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit systems 608 to program the desired logic circuit.

[0108] The storage circuit system 612 of the illustrated example is configured to store the results of one or more operations performed by corresponding logic gates. The storage circuit system 612 may be implemented by registers, etc. In the illustrated example, the storage circuit system 612 is distributed among the logic gate circuit system 608 to facilitate access and increase execution speed.

[0109] Figure 6 The example FPGA circuit system 600 also includes an example special operation circuit system 614. In this example, the special operation circuit system 614 includes a special circuit system 616, which can be called to implement commonly used functions, thereby avoiding the need to program those functions on site. Examples of such special circuit systems 616 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. There may be other types of special circuit systems. In some examples, the FPGA circuit system 600 may also include an example general programmable circuit system 618, such as an example CPU 620 and / or an example DSP 622. There may be other general programmable circuit systems 618 that can be programmed to perform other operations, such as GPUs, XPUs, etc., in addition or alternatively.

[0110] although Figure 5 and 6 Show Figure 4 These are two example implementations of programmable circuitry 412, but many other approaches are contemplated. For example, the FPGA circuitry may include an onboard CPU, such as Figure 5 One or more of the example CPUs 620. Thus, Figure 4 The programmable circuit system 412 may additionally be configured by combining at least Figure 5 An example microprocessor 500 and Figure 6 In some such hybrid examples, Figure 5 One or more cores 502 may execute Figure 3 The flowchart represents a first portion of machine-readable instructions to perform a first operation / function, Figure 6 The FPGA circuit system 600 may be configured and / or constructed to perform the same Figure 3The second operation / function corresponding to the second portion of the machine-readable instructions represented by the flowchart, and / or the ASIC may be configured and / or constructed to perform the same as that represented by Figure 3 The flowchart represents a third portion of the machine-readable instructions corresponding to a third operation / function.

[0111] It should be understood that Figure 2 Some or all of the circuitry of may thus be instantiated at the same or different times. Figure 5 The same and / or different portions of the microprocessor 500 may be programmed to execute portions of the machine-readable instructions at the same and / or different times. In some examples, Figure 6 The same and / or different portions of FPGA circuitry 600 may be configured and / or constructed to perform operations / functions corresponding to portions of the machine-readable instructions at the same and / or different times.

[0112] In some instances, Figure 2 Some or all of the circuitry of may be instantiated, for example, in one or more threads that execute in parallel and / or serially. Figure 5 The microprocessor 500 can execute machine-readable instructions in one or more threads of execution in parallel and / or serially. In some examples, Figure 6 The FPGA circuit system 600 can be configured and / or constructed to perform operations / functions in parallel and / or serially. In addition, in some examples, Figure 2 Some or all of the circuitry in the Figure 5 The system is implemented in one or more virtual machines and / or containers executed on the microprocessor 500.

[0113] In some instances, Figure 4 The programmable circuit system 412 may be in one or more packages. For example, Figure 5 The microprocessor 500 and / or Figure 6 The FPGA circuit system 600 can be in one or more packages. In some examples, the XPU can be composed of Figure 4 The XPU may be implemented in a programmable circuit system 412, which may be in one or more packages. For example, the XPU may be included in a CPU (e.g., Figure 5 Microprocessor 500, Figure 6 CPU 620, etc.), a DSP in another package (e.g., Figure 6 DSP622 of ), a GPU in yet another package, and an FPGA in yet another package (e.g., Figure 6 FPGA circuit system 600).

[0114] Figure 7The block diagram shown shows an example software distribution platform 705, which will be, for example Figure 4 The example software distribution platform 705 may be implemented by any computer server, data facility, cloud service, etc. that is capable of storing and transferring software to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform 705. For example, the entity that owns and / or operates the software distribution platform 705 may be, for example, Figure 4 The third party may be a consumer, user, retailer, OEM, etc., who purchases and / or licenses the software for use and / or resale and / or sublicensing. In the illustrated example, the software distribution platform 705 includes one or more servers and one or more storage devices. The storage device stores the machine readable instructions 432, which may correspond to the above-described Figure 3 The example software distribution platform 705 includes one or more servers that communicate with an example network 710, which may correspond to the Internet and / or any one or more of the above-described example networks. In some instances, as part of a commercial transaction, one or more servers respond to a request to transfer software to a requesting party. Payment for the delivery, sale, and / or license of the software may be processed by one or more servers of the software distribution platform and / or by a third-party payment entity. The server enables a purchaser and / or licensor to download machine-readable instructions 432 from the software distribution platform 705. For example, the example network 710 may correspond to Figure 3 The software of the example machine readable instructions of can be downloaded to the example programmable circuit system platform 400, which will execute the machine readable instructions 432 to implement one or more of the responder devices 104. In some examples, one or more servers of the software distribution platform 705 periodically distribute the software (e.g., Figure 4 Example machine readable instructions 432 of the present invention provide, transmit and / or force updates to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end-user device. Although referred to as software above, the distributed "software" may also be firmware.

[0115] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0116] In this specification, the term "coupled" may encompass connections, communications, or signal paths that support a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0117] Numerical identifiers, such as "first", "second", and "third", etc., are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers used in the detailed description are not necessarily consistent with the identifiers used in the claims.

[0118] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by the manufacturer to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through construction and / or arrangement of hardware components and interconnection of the device, or through a combination of these operations.

[0119] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0120] A circuit or device described herein as including specific components may actually be adapted to be coupled to these components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0121] The circuit described herein can be reconfigured to include replaced components to provide functions that are at least partially similar to the functions available before the component replacement. Unless otherwise specified, the components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, the resistor or capacitor shown and described as a single component herein can actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, the resistor or capacitor shown and described as a single component herein can actually be a plurality of resistors or capacitors coupled in series between the two nodes identical to a single resistor or capacitor, respectively. Although some elements of the described examples are included in the integrated circuit, and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features can be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit can be included in the integrated circuit, and / or some features shown as being inside the integrated circuit can be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are: (i) integrated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0122] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise specified, "approximately", "substantially" or "substantially" preceding a value means + / -10% of the value, or, if the value is zero, means a reasonable range of values ​​around zero.

[0123] Modifications may be made in the described embodiments, and other embodiments are possible within the scope of the claims.

[0124] As can be appreciated from the foregoing, example systems, devices, articles, and methods have been described that reduce the difficulty of maintaining a LIN network via automated techniques for assigning addresses to responder devices. The described systems, devices, articles, and methods improve the efficiency of using computing devices by increasing the amount of time a LIN network can operate without human intervention. For example, according to the examples described herein, when a responder device is added to a LIN network, addresses can be assigned to the LIN network without human intervention. The described systems, devices, articles, and methods are accordingly directed to one or more improvements in the operation of a machine such as a computer or other electronic and / or mechanical device.

[0125] The attached claims are incorporated into this detailed description by reference. Although certain example systems, devices, articles, and methods have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device comprising: counter; an analog-to-digital converter configurable to sample a first voltage at a first node on the bus; communications circuitry configurable to set a second node on the bus to a second voltage; as well as A control circuit system that can be configured to: When the first voltage does not meet a threshold, incrementing the counter; as well as When the first voltage satisfies the threshold, an address is assigned to the device based on the value of the counter.

2. The apparatus of claim 1, wherein the bus is a local interconnect network bus.

3. The device according to claim 1, wherein: The analog / digital converter can be configured to sample the first voltage within a sampling period; and The control circuitry can be configured to calculate an average value of the first voltage over the sampling period. 4 . The apparatus of claim 3 , wherein to increment the counter, the control circuitry is configurable to increment the counter when the average value of the first voltage does not satisfy the threshold value.

5. The device of claim 1 , wherein the device is a first responder device, and the control circuit system is configurable to operate in a post-configuration mode of operation after an addressing cycle has ended for the first responder device and at least a second responder device, at least the second responder device communicating with a commander device via the bus.

6. The device according to claim 1, wherein: After assigning the address to the device, the communication circuitry can be configured to set the second node to the first voltage.

7. The device according to claim 6, wherein: The communication circuitry can be configured to set the second node to the first voltage for a duration of an addressing period; and The addressing cycle is based on the value of the counter and the number of responder devices communicating with a commander device over the bus.

8. The apparatus of claim 1, wherein the control circuit system is configurable to: determining that the first voltage does not satisfy the threshold; incrementing the counter in response to determining that the first voltage does not satisfy the threshold; After incrementing the counter, determining that the first voltage satisfies the threshold; and In response to determining that the first voltage satisfies the threshold, the device is assigned the address based on the value of the counter.

9. The apparatus of claim 1, wherein the control circuit system is configurable to: In response to determining that the value of the counter is a first value, assigning a first address to the device; and In response to determining that the value of the counter is a second value, the device is assigned a second address, the second address being different from the first address.

10. A non-transitory machine-readable storage medium comprising programmable circuitry that causes a device to perform at least the following operations: causing an analog-to-digital converter to sample a first voltage at a first node on the bus; causing the communication circuitry to set a second node on the bus to a second voltage; When the first voltage does not meet the threshold, incrementing the counter; as well as When the first voltage satisfies the threshold, an address is assigned to the device based on the value of the counter.

11. The non-transitory machine-readable storage medium of claim 10, wherein the instructions cause the programmable circuit system to: determining that the first voltage does not satisfy the threshold; incrementing the counter in response to determining that the first voltage does not satisfy the threshold; After incrementing the counter, determining that the first voltage satisfies the threshold; and In response to determining that the first voltage satisfies the threshold, the device is assigned the address based on the value of the counter.

12. A system comprising: a bus comprising a resistor coupled in series with the bus, the resistor comprising a first terminal and a second terminal; a first responder device comprising a first terminal coupled to the first terminal of the resistor and a second terminal coupled to the second terminal of the resistor, wherein the first responder device is configurable to: sampling a first voltage at the first terminal of the resistor; setting the second terminal of the resistor to a second voltage; as well as assigning an address to the first responder device based on a value of a first counter when the first voltage satisfies a threshold; as well as a second responder device comprising a first terminal coupled to the second terminal of the resistor, wherein the second responder device is configurable to: sampling the second voltage at the second terminal of the resistor; as well as When the second voltage does not satisfy the threshold, a second counter is incremented.

13. The system of claim 12, wherein the bus is a local interconnect network bus.

14. The system of claim 12, wherein the first responder device is configured to: sampling the first voltage within a sampling period; and An average value of the first voltage within the sampling period is calculated.

15. The system of claim 14, wherein to increment the first counter, the first responder device is configured to increment the first counter when the average value of the first voltage does not satisfy the threshold value.

16. The system of claim 12, wherein the first responder device is to operate in a post-configuration mode of operation after an addressing period has ended for the first responder device and the second responder device.

17. The system of claim 12, wherein: After assigning the address to the first responder device, the first responder device sets the second terminal to the first voltage.

18. The system of claim 17, further comprising a commander device, wherein: The first responder device is used to set the second terminal to the first voltage for a continuous addressing period; and The addressing cycle is based on the value of the first counter and a number of responder devices communicating with the commander device over the bus.

19. The system of claim 12, wherein the first responder device is configured to: determining that the first voltage does not satisfy the threshold; incrementing the first counter in response to determining that the first voltage does not satisfy the threshold; After incrementing the first counter, determining that the first voltage satisfies the threshold; and In response to determining that the first voltage satisfies the threshold, the first responder device is assigned the address based on the value of the first counter.

20. The system of claim 12, wherein the first responder device is configured to: In response to determining that the value of the first counter is a first value, assigning a first address to the first responder device; and In response to determining that the value of the first counter is a second value, the first responder device is assigned a second address, the second address being different from the first address.

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