Semiconductor device and manufacturing method thereof
By designing a structure with a cap layer part located in the first recess in the semiconductor device, the problem of depressed defects on the surface of the insulating structure is solved, the insulation performance and manufacturing environment are improved, and the reliability and performance of the device are improved.
Patent Information
- Application Number
- CN202510185365.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2025-05-16
AI Technical Summary
The existing dynamic random access memory has surface depression defects in the insulation structure, resulting in reduced insulation performance and increased manufacturing difficulty.
A semiconductor device is designed, including a substrate having a first region and a second region, a first insulating structure, a plurality of word line structures, and a cap layer. The cover layer part is located in the first recess, and an insulating structure is formed by a chemical mechanical grinding process to improve insulation performance and reduce manufacturing difficulty.
It effectively improves the insulation performance of the first insulating structure, provides a good process environment, reduces the manufacturing difficulty and cost of semiconductor devices, and improves the reliability and performance of the devices.
Smart Images
Figure CN120018495A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array area consisting of multiple memory cells and a peripheral area consisting of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor, and the transistor controls the storage or release of the charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to the limitations of process technology, the existing dynamic random access memory still has many defects, and further improvements are needed to effectively enhance the performance and reliability of related memory components. Summary of the invention
[0003] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the reliability and performance of the semiconductor device.
[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a semiconductor device, comprising:
[0005] a substrate, comprising a first region and a second region;
[0006] a first insulating structure located within the substrate in the first region;
[0007] A plurality of word line structures are disposed in the first insulating structure in a manner separated from each other;
[0008] a capping layer, located above the word line structure;
[0009] a plurality of first recesses, located in the first insulating structure between adjacent word line structures;
[0010] Wherein, the cover layer is partially located in the first recess.
[0011] Optionally, the semiconductor device may further include:
[0012] A conductive plug is located between adjacent first recesses and is electrically connected to the word line structure.
[0013] Optionally, the semiconductor device may further include:
[0014] a plurality of second insulating structures located within the substrate in the second region;
[0015] a plurality of second recesses, located in the second insulating structure;
[0016] Wherein, the cover layer is partially located in the second recess.
[0017] Optionally, the first insulating structure may include a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence from bottom to top, and the second insulating structure includes at least the first insulating layer.
[0018] Optionally, a portion of the capping layer located on the word line structure and a portion of the capping layer located in the first recess may be isolated from each other.
[0019] Optionally, the bottom of the first recess may be lower than the bottom of the second recess.
[0020] Optionally, the cover layer may include a first sublayer and a second sublayer, and the first sublayer and the second sublayer are both partially located in the first recess.
[0021] Optionally, the conductive plug may pass through the first sub-layer and the second sub-layer to be electrically connected to the word line structure.
[0022] Optionally, the cover layers located in a plurality of the first recesses may be interconnected.
[0023] Optionally, a portion of the capping layer located on the word line structure may be higher than a portion of the capping layer located in the first recess in a vertical direction.
[0024] In a second aspect, in order to solve the above technical problems, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising:
[0025] providing a substrate including a first region and a second region;
[0026] forming a first insulating structure located within the substrate in the first region;
[0027] forming a plurality of word line structures and a plurality of first recesses, wherein the plurality of word line structures are disposed in the first insulating structure in a spaced manner from one another, and the plurality of first recesses are located in the first insulating structure between adjacent word line structures;
[0028] A capping layer is formed above the word line structure, wherein a portion of the capping layer is located in the first recess.
[0029] Optionally, the method for manufacturing the semiconductor device may further include:
[0030] A conductive plug is formed, which is located between adjacent first recesses and is electrically connected to the word line structure.
[0031] Optionally, the method for manufacturing the semiconductor device may further include:
[0032] forming a plurality of second insulating structures located within the substrate in the second region;
[0033] forming a plurality of second recesses located in the second insulating structure;
[0034] Wherein, the cover layer is partially located in the second recess.
[0035] Optionally, the step of forming the first insulating structure and the second insulating structure may include:
[0036] forming a trench in the substrate of the first region;
[0037] forming an insulating material layer located in the trench;
[0038] Chemical mechanical polishing is performed on the insulating material layer.
[0039] Optionally, the cover layer may include a first sublayer and a second sublayer, and the first sublayer and the second sublayer are both partially located in the first recess.
[0040] Optionally, a portion of the capping layer located on the word line structure and a portion of the capping layer located in the first recess may be isolated from each other.
[0041] Optionally, the first sub-layer and the second sub-layer located in the plurality of first recesses may be connected.
[0042] Optionally, the conductive plug may pass through the first sub-layer and the second sub-layer to be electrically connected to the word line structure.
[0043] In the present invention, the semiconductor device comprises a substrate having a first region and a second region, a first insulating structure located in the substrate in the first region, a plurality of word line structures arranged in the first insulating structure in a spaced relationship from each other, a cap layer located above the word line structure, and a plurality of first recesses located in the first insulating structure between adjacent word line structures. Since the cap layer is partially located in the first recess, when the first insulating structure is formed by a chemical mechanical polishing process, the surface recesses (such as the first recesses) of the first insulating structure caused by the process defects of the chemical mechanical polishing process can be well improved, thereby improving the insulating performance of the first insulating structure, providing an excellent process environment for subsequent processes, reducing the manufacturing difficulty and cost of the semiconductor device, and improving the reliability and performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:
[0045] Figures 1 to 13 It is a schematic diagram of the structure of the semiconductor device provided in an embodiment of the present invention during the preparation process.
[0046] Wherein, the accompanying drawings are marked as follows:
[0047] 100-substrate, 101-first region, 102-second region, AR-active region, 110-insulating structure, 110a-first insulating structure, 110b-second insulating structure, 111-first insulating layer, 112-second insulating layer, 113-third insulating layer, 113.1-arc-shaped upper surface of the insulating material layer forming the first insulating structure after CMP, 111.1-groove of the insulating material layer forming the second insulating structure after CMP, 120-word line structure, 121-gate dielectric layer, 122-conductive layer, 140-capping layer, 141-first sublayer, 142-second sublayer, 143-third sublayer, 130-first recess, 111.2-second recess, 150-dielectric layer, 160-conductive plug.
[0048] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION
[0049] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.
[0050] It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understandable that the meanings of "on...", "above..." and "above..." in the present invention should be interpreted in the broadest way, so that "on..." not only means that it is "on" something without intervening features or layers (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers. In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present invention can be arbitrarily combined without conflict.
[0051] Please refer to Figure 8 , which is a partial cross-sectional view of a semiconductor device according to the first embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM), and the present invention can also be applied to other types of memory without departing from the spirit of the present invention.
[0052] like Figure 8 As shown, the semiconductor device includes a substrate 100, a first insulating structure 110a, a plurality of word line structures 120, a cap layer 140, and a plurality of first recesses (such as Figure 5 The substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, but is not limited thereto. Figure 1 or Figure 4 , the substrate 100 may include a first region 101 and a second region 102. In one embodiment, the second region 102 is, for example, a storage region (cell region) of a semiconductor device, the first region 101 is, for example, an isolation region between a storage region and a peripheral region (periphery region) of a semiconductor device, and the first region 101 is, for example, surrounding the outside of the second region 102, but not limited thereto. Since the main inventive point of the semiconductor device and the manufacturing method thereof provided in the embodiment of the present invention is on the first region 101 of the substrate 100, it can be understood by a person skilled in the art of the present invention that most of the drawings provided in the embodiment of the present invention only reflect the preparation process of the corresponding semiconductor structure and the manufacturing method thereof on the first region 101, while the preparation process of the corresponding semiconductor structure and the manufacturing method thereof on the second region 102 is reflected in other small parts of the drawings.
[0053] Continue to refer to Figure 8 , a first insulating structure 110a having a large depth-width ratio is formed in the substrate 100 of the first region 101 along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). Specifically, the first insulating structure 110a may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113 stacked in sequence from bottom to top, the first insulating layer 111 covers the inner surface of the corresponding trench used to construct the first insulating structure 110a, the second insulating layer 111 conformally covers the surface of the first insulating layer 111, and the third insulating layer 113 fills the remaining space of the corresponding trench used to construct the first insulating structure 110a, but is not limited thereto. In one embodiment, the materials of the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113 may be the same or different insulating materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low dielectric constant (low-k) dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on silicon glass (spin-on glass), porous low-k dielectric material (porous low-k dielectric material), organic polymer dielectric material, or a combination of the above materials, but not limited thereto. Show Example The material of the first insulating layer 111 is silicon oxide, the material of the second insulating layer 112 is silicon nitride, and the material of the third insulating layer 113 is silicon oxide, but not limited thereto.
[0054] Further, combined with Figure 4 As shown, the plurality of word line structures 120 may span the second region 102 and a portion of the first region 101 in a horizontal direction and be arranged at intervals from each other. Figure 8, the parts of the multiple word line structures 120 located in the first insulating structure 110a are spaced from each other; the word line structure 120 may include a gate dielectric layer 121 and a conductive layer 122. Specifically, the gate dielectric layer 121 is located on the inner surface of the word line groove, and the conductive layer 122 covers the gate dielectric layer 121 and only fills the lower part of the word line groove, so as to expose the upper part of the word line groove whose sidewall is covered with the gate dielectric layer 121. The cap layer 140 fills the exposed upper part of the word line groove and extends to fill the multiple first recesses in the surface layer of the first insulating structure 110a between the adjacent word line structures 120, and in the horizontal direction, the closer the bottom surface of the cap layer 140 in the first recess is to the center line of the first insulating structure 110a, the closer it is to the bottom surface of the substrate 100, which can also be understood as the closer the first recess is to the center line of the first insulating structure 110a, the deeper it is recessed into the bottom surface of the substrate 100. In one embodiment, the material of the gate dielectric layer 121 may be silicon oxide, the material of the conductive layer 122 may be metal tungsten, and the material of the cap layer 140 may be oxide or nitride, but is not limited thereto; under this setting, the cap layer 140 of insulating material fills the multiple first recesses on the surface of the first insulating structure 110a, which can avoid the problem of surface recess defects of the first insulating structure 110a caused by the chemical mechanical polishing process and the resulting reduction in the insulation performance of the first insulating structure 110a during the formation of the first insulating structure 110a.
[0055] Furthermore, the semiconductor device in the first embodiment of the present invention further includes a dielectric layer 150, and the dielectric layer 150 may specifically cover the plurality of word line structures 120, the first insulating structure 110a, and the surface of the substrate 100. The conductive plug 160 passes through the dielectric layer 150 and the cap layer 140 in the word line structure 120, and is electrically connected to the word line structure 120 located between adjacent first recesses. In one embodiment, the dielectric layer 150 may be a single layer of dielectric material, such as a silicon oxide layer or a silicon nitride layer, or may include multiple layers of dielectric material (such as Figure 8 The conductive plug 160 may be made of metal, such as metal tungsten or metal aluminum, but is not limited thereto.
[0056] It should be understood that Fig. 9 As shown, combined with Figure 8 and Figure 4The conductive plug 160 is electrically connected to some of the word line structures 120, and the cap layer 140 and the dielectric layer 150 above some of the word line structures 120 are not provided with the conductive plug 160. Therefore, the cap layer 140 and the dielectric layer 150 on the multiple word line structures 120 without the conductive plug 160 are respectively connected (connected into one piece).
[0057] In addition, combined Figures 1 to 7 In the first embodiment of the present invention, a plurality of second insulating structures 110b are arranged in the substrate 100 of the second zone 102, and together with the first insulating structure 110a in the substrate 100 of the first zone 101, they form an insulating structure 110. The shapes of the plurality of second insulating structures 110b in the second zone 102 can be long strips extending in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction), and some of the second insulating structures 110b are single-layer insulating material layers, that is, some of the second insulating structures 110b are composed of only the first insulating layer 111, and the remaining second insulating structures 110b are multiple insulating material layers, for example, composed of the first insulating layer 111 and the second insulating layer 112, but not limited thereto. Since the second zone 102 is the storage area of the semiconductor device, the substrate 100 of the second zone 102 can be divided into a plurality of active areas AR by the plurality of second insulating structures 110b, such as Figure 1 or Figure 2 shown.
[0058] Furthermore, since the first insulating structure 110a and the second insulating structure 110b in the first embodiment of the present invention are formed simultaneously, the surface layers of the plurality of second insulating structures 110b in the substrate 100 in the second region 102 also have a surface depression defect after the chemical mechanical polishing process, that is, the top surface layer of the second insulating structure 110b has a second depression, for example Figure 3 111.1 shown, and no matter whether the second insulating structure 110b is a single-layer insulating material layer or a multi-layer insulating material layer, the second recess is only located in the first insulating layer 111 of the second insulating structure 110b; specifically, when the second insulating structure 110b only includes the first insulating layer 111, its top surface layer has a second recess that is recessed toward the bottom of the substrate 100 as a whole, and when the second insulating structure 110b includes the first insulating layer 111 and the second insulating layer 112, the two ends of its top surface layer respectively have a second recess, but not limited thereto. In addition, the cover layer 140 will further partially fill the second recess, such as Figure 7 shown.
[0059] It should be understood that the “common shape” in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and associations between two or more shapes.
[0060] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present invention may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present invention will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.
[0061] Please refer to Fig.10 , which is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention. Fig.10 As shown, the structure of the semiconductor device of this embodiment is substantially the same as the structure of the semiconductor device in the aforementioned first embodiment, such as the semiconductor device also includes a substrate 100, the substrate 100 also includes a first region 101 and a second region 102, a first insulating structure 110a, a plurality of word line structures 120, a cap layer 140, a plurality of first recesses filled with the cap layer 140, a dielectric layer 150 and a conductive plug 160, the cap layer 140 is further filled into a word line groove for constructing the word line structure 120, etc., and the same parts are not repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment is that the top surface of the capping layer 140 filled in some of the word line grooves in the second embodiment of the present invention is higher in the vertical direction than the top surface of the capping layer 140 located in the first recesses on both sides of the word line structure 120, that is, the top surface of the capping layer 140 on the conductive layer 122 located in some of the word line structures 120 is not flush with the top surface filled in the first recess (located at different horizontal heights), for example, the top surface of the capping layer 140 on the conductive layer 122 located in some of the word line structures 120 may be higher in the vertical direction than the top surface filled in the first recess and have a height difference H, where H>0. Under this setting, the dielectric layer 150 in the second embodiment of the present invention will be uneven in the horizontal direction, that is, it will be protruding on the cover layer 140 located on the part of the word line structure 120; in one embodiment, the dielectric layer 150 is a multi-layer dielectric material, and only at least one layer of dielectric material that is directly in contact with and / or adjacent to the cover layer 140 is protruding on the part located on the part of the word line structure 120, but it is not limited to this.
[0062] Please refer to Fig.13 , which is a partial cross-sectional view of a semiconductor device according to a third embodiment of the present invention. Fig.13As shown, the structure of the semiconductor device of this embodiment is substantially the same as that of the semiconductor device in the first or second embodiment described above, such as the semiconductor device also includes a substrate 100, the substrate 100 also includes a first region 101 and a second region 102, a first insulating structure 110a, a plurality of word line structures 120, a cap layer 140, a plurality of first recesses filled with the cap layer 140, a dielectric layer 150 and a conductive plug 160, the cap layer 140 is further filled into the word line groove for constructing the word line structure 120, etc., and the same parts are not repeated here. The main difference between the semiconductor device of this embodiment and the first or second embodiment described above is that the cap layer 140 in the third embodiment of the present invention can be a composite structure, for example, it can include a first sub-layer 141, a second sub-layer 142, and a third sub-layer 143. The third sublayer 143 is located in the word line groove for constructing the word line structure 120; the first sublayer 141 and the second sublayer 142 are partially located in the first depression at the same time, and extend to cover the third sublayer 143 and the remaining surface exposed by the substrate 100 and the first insulating structure 110a of the first region 101, and the first sublayer 141 and the second sublayer 142 located in multiple first depressions are respectively connected, so that the first sublayer 141 and the second sublayer 142 located in the two first depressions on both sides of a word line structure 120 are in the shape of a "concave" as a whole, but not limited to this. Under this setting, the conductive plug 160 in the third embodiment of the present invention is electrically connected to the corresponding word line structure 120 after passing through the first sublayer 141, the second sublayer 142, and the third sublayer 143. In one embodiment, the materials of the first sub-layer 141, the second sub-layer 142 and the third sub-layer 143 may be different. For example, the material of the first sub-layer 141 may be oxide (e.g., silicon dioxide), the material of the second sub-layer 142 may be nitride (e.g., silicon nitride), and the material of the third sub-layer 143 may be nitride (e.g., silicon nitride), but is not limited to this.
[0063] In order to enable a general technician in the technical field to which the present invention belongs to easily understand the semiconductor devices in the first to second embodiments of the present invention, the present invention also provides a method for preparing the semiconductor device. The following will further illustrate the method for preparing the semiconductor device proposed in the present invention in combination with various structural schematic diagrams of the method for preparing the semiconductor device during the preparation process.
[0064] in, Figures 1 to 10 It is a structural schematic diagram of the semiconductor device manufacturing method provided in the first to second embodiments of the present invention during the manufacturing process.
[0065] Please refer to Figure 1 and Figure 2 , Figure 1The diagram is a partial top view of the semiconductor device after the trench is filled with insulating material according to the first and second embodiments of the present invention. Figure 2 for Figure 1 The semiconductor structure shown is a local cross-sectional view corresponding to the AA cut line and the BB cut line. Figure 1 and Figure 2 As shown, a substrate 100 (material such as a silicon substrate) may be provided first, and the substrate 100 may be divided into a first area 101 and a second area 102, wherein the first area 101 is an isolation area, and the second area 102 is a storage area; then, an etching method may be used to form a trench (not shown) in the substrate 100 of the first area 101, and a plurality of trenches (not shown) may be formed in the substrate 100 of the second area 102, and then insulating materials (materials such as silicon oxide or silicon oxynitride, etc.) may be filled into the plurality of trenches. In one embodiment, the trenches in the substrate 100 located in the first area 101 may be filled with three layers of insulating materials, for example, including a first insulating layer 111 (for example, silicon oxide), a second insulating layer 112 (for example, silicon nitride) and a third insulating layer 113 (for example, silicon oxide) stacked in sequence, and some of the trenches located in the second area 102 are filled with a single layer of insulating material, for example, only the first insulating layer 111, and the remaining trenches are filled with multiple layers of insulating materials, for example, including a first insulating layer 111 and a second insulating layer 112, but not limited to this.
[0066] Please refer to Figure 3 and Figure 4 , Figure 3 The illustrated diagram is a partial cross-sectional view of the semiconductor device after the insulating structure is formed in the first and second embodiments of the present invention. Figure 4 for Figure 3 The semiconductor structure shown is a local top view corresponding to the AA cut line and the BB cut line. Figure 3 and Figure 4 As shown, the insulating material filled in the trench of the first region 101 can be further polished by a chemical mechanical polishing process to remove a portion of the insulating material at a height. Similarly, the insulating material filled in the trench of the second region 102 can also be polished to remove a portion of the insulating material at a height, so as to form a first insulating structure 110a in the substrate 100 of the first region 101, and to form a plurality of second insulating structures 110b and a plurality of active regions AR defined by the plurality of second insulating structures 110b in the substrate 100 of the second region 102. However, due to the process defects of the chemical mechanical polishing process, the top surface layers of the first insulating structure 110a and the second insulating structure 110b formed will inevitably have concave defects, such as Figure 3The top surface of the first insulating structure 110a shown has an arc-shaped depression 113.1 (which can also be understood as the arc-shaped upper surface of the insulating material of the first insulating structure 110a after CMP), and a groove 111.1 exists on part of the top surface of the second insulating structure 110b. In one embodiment, the first insulating structure 110a includes three layers of insulating material, for example, a first insulating layer 111 (for example, silicon oxide), a second insulating layer 112 (for example, silicon nitride) and a third insulating layer 113 (for example, silicon oxide) stacked in sequence, but not limited thereto. The arc-shaped depression 113.1 is located on the surface of the third insulating layer 113 of the first insulating structure 110a, and the groove 111.1 is located on the surface of the first insulating layer 111 of the second insulating structure 110b.
[0067] Please refer to Figure 5 , Figure 5 The illustrated diagrams are partial cross-sectional views of the semiconductor devices according to the first and second embodiments of the present invention after the word line structures are formed along the AA and BB cut lines. Figure 5As shown, an etching process can be further used to form a plurality of word line grooves (not shown), a plurality of first recesses 130 and a plurality of second recesses 111.2 in the insulating structure 110 (including the first insulating structure 110a and the second insulating structure 110b) of the first region 101 and the second region 102. The plurality of word line grooves and the plurality of first recesses 130 are located in the first insulating structure 110a of the first region 101, and the plurality of word line grooves and the plurality of first recesses 130 are adjacent and spaced apart, while the second recesses 111.2 are all located in the second insulating structure 110b of the second region 102, and the plurality of second recesses 111.2 may have different recess shapes, but are not limited thereto. Then, a deposition process is used to sequentially form a gate dielectric layer 121 and a conductive layer 122 (such as metal tungsten) in the plurality of word line grooves to form a word line structure 120. It should be understood that since the surfaces of the first insulating structure 110a and the second insulating structure 110b already have surface depressions before the word line groove, the first depression and the second depression are formed, the depth of the arc-shaped depression 113.1 on the surface of the third insulating layer 113 in the first insulating structure 110a and the depression depth of the depression 111.1 on the surface of the first insulating layer 111 in the second insulating structure 110b will be further deepened during the etching process of forming the word line groove in this step, that is, the arc-shaped depression 113.1 with a deeper depth constitutes the first depression 130, and the depression 111.1 with a deeper depth constitutes the second depression 111.2, and in the horizontal direction, the closer the bottom surface of the first depression 130 is to the center line of the first insulating structure 110a, the closer it is to the bottom surface of the substrate 100. It can also be understood that the closer the first depression 130 is to the center line of the first insulating structure 110a, the deeper it is depressed toward the bottom surface of the substrate 100, but this is not limited to this.
[0068] Please refer to Figure 6 and Figure 7 , Figure 6 The illustrated diagrams are partial cross-sectional views along the AA and BB cut lines respectively after the cap layer is formed in the semiconductor device of the first and second embodiments of the present invention. Figure 7 The illustrated diagrams are partial cross-sectional views of the semiconductor device according to the first and second embodiments of the present invention after the cap layer is etched back along the AA cut line and the BB cut line. Figure 6As shown, a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, may be further used to fill the remaining space of the word line groove, the first recess 130, and the second recess 111.2 with a capping layer 140 (such as silicon dioxide or silicon nitride). It should be understood that in the second embodiment of the present invention, the top of the capping layer 140 formed in this step in some word line grooves may be higher than the top of the first recess, and the thickness of the capping layer 140 in the first recess 130 closer to the center line of the first insulating structure 110a along the horizontal direction (such as Figure 6 The thickness of the cover layer 140 closer to the two end edges of the first insulating structure 110a along the horizontal direction (eg Figure 6 The reference numeral H2 in the figure indicates the position). Figure 7 As shown, an etching process, such as a dry etching process, may be used to etch a portion of the capping layer 140 downward in a vertical direction.
[0069] Please refer to Figures 8 to 10 , Figure 8 The figure is a partial cross-sectional view of a semiconductor device according to the first embodiment of the present invention. Fig. 9 The illustrated part is a cross-sectional view of a semiconductor device without a conductive plug after the conductive plug is formed in the first or second embodiment of the present invention. Fig.10 The illustrated diagram is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention; Figures 8 to 10 As shown, the dielectric layer 150 can be further formed by a deposition process such as a chemical vapor deposition process, and then an etching process such as a dry etching process is used to form a through hole (not shown) penetrating the dielectric layer 150 and the cap layer 140, and a conductive plug 160 (such as metal copper) located in the through hole, and the cap layer 140 and the dielectric layer 150 on the multiple word line structures 120 without the conductive plug 160 are respectively connected (connected into one piece).
[0070] In order to enable a general technician in the technical field to which the present invention belongs to easily understand the semiconductor device in the third embodiment of the present invention, the present invention also provides a method for preparing the semiconductor device. The following will further illustrate the method for preparing the semiconductor device proposed in the present invention in combination with various structural schematic diagrams of the method for preparing the semiconductor device during the preparation process.
[0071] in, Figure 1 to Figure 7 as well as Figure 11 to Figure 13 FIG. 1 is a schematic diagram of the structure of the semiconductor device manufacturing method provided in the third embodiment of the present invention during the manufacturing process. Since the semiconductor device of the third embodiment of the present invention is substantially the same as the first to second embodiments described above, Figure 1 to Figure 7The corresponding steps, and therefore the preparation methods of the corresponding components and / or devices, are also the same. The following will not repeat the same parts of the preparation methods of the third embodiment of the present invention as those of the first to third embodiments, and only the different preparation processes between the two will be explained.
[0072] Specifically, if Fig.11 As shown, after forming the capping layer 140 in the word line groove and the first recess 130 by a deposition process, the manufacturing process of the semiconductor device corresponding to the third embodiment of the present invention further needs to use an etching process, such as a dry etching process, to remove the capping layer 140 previously deposited in the first recess 130, and retain the capping layer 140 filled in the word line groove to expose the first recess 130 again; for easy distinction, the third embodiment of the present invention marks the capping layer retained in the word line groove with a covering mark 143 and names it as the third sub-layer. Fig.11 As shown, a deposition process such as a chemical vapor deposition process is then further used to sequentially form a first sublayer 141 and a second sublayer 142 on the re-exposed first recess 130 and the film layers on both sides thereof, that is, to form a capping layer consisting of the first sublayer 141, the second sublayer 142 and the third sublayer. Fig.12 As shown, a dielectric layer 150 and a conductive plug 160 are then formed in sequence by deposition and etching processes.
[0073] In summary, in the present invention, the semiconductor device includes a substrate having a first region and a second region, a first insulating structure located in the substrate in the first region, a plurality of word line structures arranged in the first insulating structure in a spaced relationship from each other, a cap layer located above the word line structure, and a plurality of first recesses located in the first insulating structure between adjacent word line structures. Since the cap layer is partially located in the first recess, when the first insulating structure is formed by a chemical mechanical polishing process, the surface recesses (such as the first recesses) of the first insulating structure caused by the process defects of the chemical mechanical polishing process can be well improved, thereby improving the insulation performance of the first insulating structure, providing an excellent process environment for subsequent processes, reducing the manufacturing difficulty and cost of the semiconductor device, and improving the reliability and performance of the semiconductor device.
[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A semiconductor device, characterized in that: include: a substrate, comprising a first region and a second region; a first insulating structure located within the substrate in the first region; A plurality of word line structures are disposed in the first insulating structure in a manner separated from each other; a capping layer, located above the word line structure; a plurality of first recesses, located in the first insulating structure between adjacent word line structures; Wherein, the cover layer is partially located in the first recess.
2. The semiconductor device according to claim 1, wherein Also includes: A conductive plug is located between adjacent first recesses and is electrically connected to the word line structure.
3. The semiconductor device according to claim 1, wherein Also includes: a plurality of second insulating structures located within the substrate in the second region; a plurality of second recesses, located in the second insulating structure; Wherein, the cover layer is partially located in the second recess.
4. The semiconductor device according to claim 3, characterized in that The first insulating structure includes a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence from bottom to top, and the second insulating structure includes at least the first insulating layer.
5. The semiconductor device according to claim 1, wherein: A portion of the capping layer located on the word line structure and a portion of the capping layer located in the first recess are isolated from each other.
6. The semiconductor device according to claim 3, wherein: The bottom of the first recess is lower than the bottom of the second recess.
7. The semiconductor device according to claim 1, wherein: The cover layer includes a first sublayer and a second sublayer, and the first sublayer and the second sublayer are both partially located in the first recess.
8. The semiconductor device according to claim 7, wherein: The conductive plug passes through the first sub-layer and the second sub-layer and is electrically connected to the word line structure.
9. The semiconductor device according to claim 7, wherein: The cover layers located in the plurality of the first recesses are connected.
10. The semiconductor device according to claim 1, wherein A portion of the capping layer located on the word line structure is higher in a vertical direction than a portion of the capping layer located in the first recess.
11. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate including a first region and a second region; forming a first insulating structure located within the substrate in the first region; forming a plurality of word line structures and a plurality of first recesses, wherein the plurality of word line structures are disposed in the first insulating structure in a spaced manner from one another, and the plurality of first recesses are located in the first insulating structure between adjacent word line structures; A capping layer is formed above the word line structure, wherein a portion of the capping layer is located in the first recess.
12. The method for manufacturing a semiconductor device according to claim 11, wherein: Also includes: A conductive plug is formed between adjacent first recesses and electrically connected to the word line structure.
13. The method for manufacturing a semiconductor device according to claim 11, wherein: Also includes: forming a plurality of second insulating structures located within the substrate in the second region; forming a plurality of second recesses located in the second insulating structure; Wherein, the cover layer is partially located in the second recess.
14. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of forming the first insulating structure and the second insulating structure includes: forming a trench in the substrate of the first region; forming an insulating material layer located in the trench; Chemical mechanical polishing is performed on the insulating material layer.
15. The method for manufacturing a semiconductor device according to claim 12, wherein: The cover layer includes a first sublayer and a second sublayer, and the first sublayer and the second sublayer are both partially located in the first recess.
16. The method for manufacturing a semiconductor device according to claim 11, wherein: A portion of the capping layer located on the word line structure and a portion of the capping layer located in the first recess are isolated from each other.
17. The method for manufacturing a semiconductor device according to claim 15, wherein: The first sub-layer and the second sub-layer located in the plurality of the first recesses are connected.
18. The method for manufacturing a semiconductor device according to claim 15, wherein: The conductive plug passes through the first sub-layer and the second sub-layer and is electrically connected to the word line structure.