Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The suspension gate layer is located on the top of the substrate; the cap layer is located at the top of the suspended gate layer; the gate insulating layer is located at the top of the cap layer, and the dielectric constant of the cap layer is larger than that of the gate insulating layer; the control gate layer is located on the substrate and covers the top and the side wall of the suspension gate layer, and the control gate layer further covers the gate insulating layer. The cap layer is formed on the top of the suspension gate layer, and the dielectric constant of the cap layer is larger than that of the gate insulating layer, so that compared with the scheme that the gate insulating layer is formed on the top of the suspension gate layer, the dielectric constant of the cap layer is larger than that of the gate insulating layer; the cap layer enables the charges at the corners of the suspended gate layer to be redistributed through the electrostatic induction effect, enables a part of the charges at the corners to be separated, reduces the probability of charge aggregation at the top corners of the suspended gate layer, enables the reliability of the semiconductor structure to be improved, and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Flash memory is a non-volatile memory (NVM). The main feature of flash memory is that it can retain stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasure and rewrite, etc. Therefore, it has been widely used in many fields such as microcomputers and automation control.

[0003] According to different structures, flash memory can be divided into two types: NOR Flash and NAND Flash. Among them, NOR Flash, also known as coded flash memory, has become the mainstream non-volatile memory in flash memory technology because of its features such as direct code execution, high reliability and fast reading speed.

[0004] However, the performance of existing or non-flash memory devices still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor device.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a suspended gate layer, located on the top of the substrate; a cap layer, located on the top of the suspended gate layer; a gate insulating layer, located on the top of the cap layer, the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer; a control gate layer, located on the substrate and covering the top and side walls of the suspended gate layer, the control gate layer also covering the gate insulating layer.

[0007] Optionally, the material of the capping layer includes titanium nitride.

[0008] Optionally, along the normal direction of the substrate surface, the thickness of the capping layer ranges from 5 nanometers to 30 nanometers.

[0009] Optionally, the semiconductor structure further includes: a sidewall layer located on the sidewall of the floating gate layer; and a control gate layer covering the sidewall and top of the sidewall layer.

[0010] Optionally, the semiconductor structure further includes: a gate oxide layer located on the top of the substrate; the floating gate layer located on the top of the gate oxide layer; and the control gate layer covering the gate oxide layer exposed by the floating gate layer.

[0011] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, a floating gate layer being formed on the top of the substrate; forming a cap layer on the top of the floating gate layer and a gate insulation layer covering the top of the cap layer, the dielectric constant of the cap layer being greater than the dielectric constant of the gate insulation layer; forming a control gate layer on the substrate covering the top and sides of the floating gate layer, the control gate layer covering the gate insulation layer.

[0012] Optionally, in the step of providing a substrate, a dielectric layer is formed on the substrate where the floating gate layer is exposed, and the dielectric layer covers the side walls of the floating gate layer; the step of forming the cap layer and the gate insulating layer includes: forming a cap material layer on top of the floating gate layer and the dielectric layer; forming a gate insulating material layer on top of the cap material layer; forming a mask layer covering the gate insulating material layer above the floating gate layer; using the mask layer as a mask, patterning the gate insulating material layer and the cap material layer to form a cap layer on top of the floating gate layer and a gate insulating layer covering the cap layer; and removing the mask layer.

[0013] Optionally, the step of forming the cap layer and the gate insulating layer further includes: removing the dielectric layer to expose the sidewall of the floating gate layer.

[0014] Optionally, the process of forming the cap material layer includes an atomic layer deposition process.

[0015] Optionally, the process of patterning the gate insulating material layer and the capping material layer includes a dry etching process.

[0016] Optionally, the material of the capping layer includes titanium nitride.

[0017] Optionally, along the normal direction of the substrate surface, the thickness of the capping layer ranges from 5 nanometers to 30 nanometers.

[0018] Optionally, in the step of providing a substrate, a gate oxide layer is also formed on the top of the substrate, and the floating gate layer is formed on the top of the gate oxide layer; in the step of forming the control gate layer, the control gate layer covers the gate oxide layer exposed by the floating gate layer.

[0019] Optionally, after forming the cap layer and the gate insulation layer and before forming the control gate layer, it also includes: forming a sidewall layer covering the sidewall of the floating gate layer on the substrate; in the step of forming the control gate layer, the control gate layer covers the sidewall and top of the sidewall layer.

[0020] Optionally, the step of forming the sidewall layer includes: forming a sidewall material layer on the top of the substrate exposed by the floating gate layer, the sidewall of the floating gate layer, the sidewall of the cap layer, and the sidewall and top of the gate insulation layer; removing the sidewall material layer on the top of the substrate exposed by the floating gate layer and the sidewall material layer on the top of the gate insulation layer, and using the remaining sidewall material layer located on the sidewall of the floating gate layer as the sidewall layer.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0022] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a cap layer and a gate insulating layer covering the top of the cap layer are formed on the top of the floating gate layer, and a control gate layer covering the top and side of the floating gate layer is formed on the substrate, and the control gate layer covers the gate insulating layer. By forming the cap layer on the top of the floating gate layer, the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer. Compared with the scheme of forming the gate insulating layer on the top of the existing floating gate layer, in this embodiment, since the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer, the cap layer can redistribute the charges at the corners of the floating gate layer through the electrostatic induction effect, so that a part of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corners of the floating gate layer, thereby improving the reliability of the semiconductor structure, and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a corresponding structural schematic diagram of a semiconductor structure;

[0024] Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0025] Figures 3 to 8 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0026] At present, the performance of semiconductor structures still needs to be improved. The reasons why the performance of semiconductor structures needs to be improved are analyzed in combination with a schematic diagram of a semiconductor structure.

[0027] Figure 1 It is a corresponding structural schematic diagram of a semiconductor structure.

[0028] The semiconductor structure includes: a substrate 10; a gate oxide layer 12, located on the top of the substrate 10 and covering the gate oxide layer 12; a suspended gate layer 14, protruding from the top of the gate oxide layer 12; a gate insulating layer 16, located on the top and sidewalls of the suspended gate layer 14; and a control gate layer 14, located on the substrate 10 where the suspended gate layer 14 is exposed, and covering the suspended gate layer 14 and the gate insulating layer 16.

[0029] Research has found that as the process size of the semiconductor structure becomes smaller and smaller, the gate insulation layer 16 is located between the control gate layer 14 and the floating gate layer 14, and the curvature of the corner of the floating gate layer 14 becomes smaller and smaller, which means that the corner of the floating gate layer 14 becomes sharper and sharper. When the semiconductor structure is in a working state, the charge at the corner of the floating gate layer 14 becomes denser and denser. Under the action of the electric field, the charge will gather at the corner, making it easy for voltage to gather at the corner of the floating gate layer 14, so that leakage current will appear in the semiconductor structure, and the performance of the semiconductor structure is affected.

[0030] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a suspended gate layer, located on the top of the substrate; a cap layer, located on the top of the suspended gate layer; a gate insulating layer, located on the top of the cap layer, the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer; a control gate layer, located on the substrate and covering the top and side walls of the suspended gate layer, the control gate layer also covering the gate insulating layer and the sidewall layer.

[0031] The semiconductor structure provided by the embodiment of the present invention comprises a cap layer and a gate insulating layer covering the top of the cap layer, and a control gate layer covering the top and side of the floating gate layer is formed on a substrate, and the control gate layer covers the gate insulating layer. The cap layer is formed on the top of the floating gate layer, and the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer. Compared with the scheme of forming the gate insulating layer on the top of the existing floating gate layer, in this embodiment, since the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer, the cap layer can redistribute the charges at the corners of the floating gate layer through the electrostatic induction effect, so that a part of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corners of the floating gate layer, thereby improving the reliability of the semiconductor structure, and further improving the performance of the semiconductor structure.

[0032] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figure 2 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0034] The semiconductor structure includes: a substrate 200; a suspended gate layer 204, located on the top of the substrate 200; a cap layer 216, located on the top of the suspended gate layer 204; a gate insulating layer 215, located on the top of the cap layer 216, the dielectric constant of the cap layer 216 is greater than the dielectric constant of the gate insulating layer 215; a control gate layer 230, located on the substrate 200 and covering the top and side walls of the suspended gate layer 204, the control gate layer 230 also covering the gate insulating layer 215.

[0035] It should be noted that a cap layer 216 and a gate insulating layer 215 covering the top of the cap layer 216 are arranged on the top of the floating gate layer 204, and a control gate layer 230 covering the top and side of the floating gate layer 204 is formed on the substrate 200, and the control gate layer 230 covers the gate insulating layer 215. By setting the cap layer 216 on the top of the floating gate layer 204, compared with the existing solution of setting the gate insulating layer 215 on the top of the floating gate layer 204, in this embodiment, since the dielectric constant of the cap layer 216 is greater than the dielectric constant of the gate insulating layer 215, the cap layer 216 can redistribute the charges at the corners of the floating gate layer 204 through the electrostatic induction effect, so that a part of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corners of the floating gate layer 204, thereby improving the reliability of the semiconductor structure, and further improving the performance of the semiconductor structure.

[0036] The substrate 200 provides a process platform for setting up a non-volatile memory.

[0037] As an example, the non-volatile memory is a NOR Flash device.

[0038] In this embodiment, the substrate 200 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0039] The floating gate layer 204 is used to store electrons during the operation of the NOR flash memory device, so that the NOR flash memory device can perform the function of data storage.

[0040] In this embodiment, the material of the floating gate layer 204 is polysilicon.

[0041] As an example, the semiconductor structure further includes: a gate oxide layer 202 located on the top of the substrate 200 , and a floating gate layer 204 located on the top of the gate oxide layer 202 .

[0042] Specifically, the gate oxide layer 202 is a tunnel oxide layer (Tunnel Oxide) of the NOR flash memory, which is used as an isolation insulating layer between the suspended gate layer 204 and the substrate 200, so that when the flash memory is working, the tunneling effect is used to allow electrons to enter the suspended gate layer 204 through the gate oxide layer 202. Moreover, during the data storage process, the electrons stored in the suspended gate layer 204 are prevented from entering the silicon substrate, thereby reducing the loss of electrons. That is, the gate oxide layer 202 is suitable for preventing the data stored in the suspended gate layer 204 from being lost.

[0043] As an example, the material of the gate oxide layer 202 is silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

[0044] It should be noted that the thickness of the gate oxide layer 202 should not be too large or too small. If the thickness of the gate oxide layer 202 is too large, after the control gate layer 230 is subsequently formed, it is easy to cause the overall height of the NOR flash memory to be too high, which is not conducive to further shrinking the semiconductor structure; if the thickness of the gate oxide layer 202 is too small, during the data storage process, the probability of the electrons stored in the floating gate layer 204 entering the substrate 200 is increased, thereby increasing the probability of electron loss, and further affecting the storage performance of the NOR flash memory. For this reason, in this embodiment, the thickness of the gate oxide layer 202 is 5 nanometers to 30 nanometers.

[0045] As an example, the semiconductor structure further includes: an isolation structure 201 located in the substrate 200 on both sides of the floating gate layer 204 .

[0046] Specifically, the isolation structure 201 is used to electrically isolate adjacent floating gate layers 204 , thereby reducing the risk of electrical leakage from adjacent floating gate layers 204 through the substrate 200 .

[0047] The material of the isolation structure 201 is a dielectric material. In this embodiment, the material of the isolation structure 201 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the isolation structure 201 is silicon oxide.

[0048] Specifically, by setting a cap layer 216 on the top of the floating gate layer 204, compared with the existing solution of setting a gate insulating layer 215 on the top of the floating gate layer 204, in this embodiment, since the dielectric constant of the cap layer 216 is greater than the dielectric constant of the gate insulating layer 215, the cap layer 216 can redistribute the charges at the corners of the floating gate layer 204 through the electrostatic induction effect, so that a part of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corner of the floating gate layer 204, thereby improving the reliability of the semiconductor structure, and further improving the performance of the semiconductor structure.

[0049] It should be noted that, by disposing the cap layer 216 on the top of the floating gate layer 204 , the cap layer 216 has an insulating effect, which can further reduce the risk of leakage between the floating gate layer 204 and the control gate layer 230 formed subsequently.

[0050] It should be noted that the thickness range of the cap layer 216 along the normal direction of the surface of the substrate 200 should not be too large or too small. If the thickness of the cap layer 216 is too large, after the control gate layer 230 is set, it is easy to cause the overall height of the NOR flash memory to be too high, which is not conducive to further shrinking the semiconductor structure; if the thickness of the cap layer 216 is too small, the function of the cap layer 216 to redistribute the charge at the corner of the floating gate layer 204 through the electrostatic induction effect will be affected, increasing the probability of charge accumulation at the top corner of the floating gate layer 204, thereby affecting the reliability of the semiconductor structure, and further affecting the performance of the semiconductor structure. For this reason, in this embodiment, along the normal direction of the surface of the substrate 200, the thickness range of the cap layer 216 is 5 nanometers to 30 nanometers.

[0051] In this embodiment, the material of the cap layer 216 includes titanium nitride.

[0052] Specifically, the dielectric constant of titanium nitride is relatively large and is greater than the dielectric constant of the gate insulating layer 215. Under the electrostatic induction effect, titanium nitride can redistribute the charges at the corners of the floating gate layer 204, so that a portion of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corner of the floating gate layer 204, thereby improving the reliability of the semiconductor structure.

[0053] The gate insulating layer 215 serves to electrically isolate the floating gate layer 204 and the control gate layer 230 .

[0054] In this embodiment, the gate insulating layer 215 is an Oxide-Nitride-Oxide (ONO) structure.

[0055] As an example, the semiconductor structure further includes: a spacer layer 226 located on the sidewall of the floating gate layer 204 .

[0056] The spacer layer 226 is used to electrically isolate the floating gate layer 204 from the control gate layer 230 .

[0057] As an example, the spacer layer 226 is a stacked structure, and the spacer layer 226 is a silicon oxide layer-silicon nitride layer-silicon oxide layer (Oxide-Nitride-Oxide, ONO) structure.

[0058] In other embodiments, the material of the spacer layer may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, or silicon nitride oxide.

[0059] The control gate layer 230 is used to implement logic control operations of the NOR flash memory device, such as write control, read control, etc.

[0060] In this embodiment, the material of the control gate layer 230 is the same as that of the floating gate layer 204 , that is, the material of the control gate layer 230 is polysilicon.

[0061] In this embodiment, the control gate layer 230 covers the gate oxide layer 202 exposed by the floating gate layer 204 .

[0062] Specifically, the control gate layer 230 covers the gate oxide layer 202 exposed by the floating gate layer 204 , thereby reducing the risk of leakage between the control gate layer 230 and the floating gate layer 204 through the substrate 200 .

[0063] In this embodiment, the sidewall layer 226 covers the sidewalls of the floating gate layer 204. Accordingly, in the process of setting the control gate layer 230, the control gate layer 230 covers the sidewalls and the top of the sidewall layer 226, which means that the sidewall layer 226 can electrically isolate the control gate layer 230 from the floating gate layer 204.

[0064] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure.

[0065] refer to Figures 3 to 8 , showing a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0066] refer to Figure 3 , providing a substrate 100 , a floating gate layer 104 is formed on the top of the substrate 100 .

[0067] The substrate 100 provides a process platform for subsequently forming a non-volatile memory.

[0068] As an example, the non-volatile memory is a NOR Flash device.

[0069] In this embodiment, the substrate 100 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0070] The floating gate layer 104 is used to store electrons during the operation of the NOR flash memory device, so that the NOR flash memory device can perform the function of data storage.

[0071] In this embodiment, the material of the floating gate layer 104 is polysilicon.

[0072] In this embodiment, the steps of forming the floating gate layer 104 include: forming a first gate film (not shown) on the substrate 100; forming a patterned photoresist layer (not shown) on the first gate film; using the patterned photoresist layer as a mask, patterning the first gate film, and using the remaining first gate film as the floating gate layer 104.

[0073] As an example, the process of patterning the first gate film includes a dry etching process.

[0074] Specifically, the first gate film is patterned by using a dry etching process, which is beneficial to improving the morphology quality of the sidewall of the floating gate layer 104 .

[0075] It should be noted that after forming the floating gate layer 104 , the patterned photoresist layer is removed.

[0076] Continue to refer Figure 3 In this embodiment, a gate oxide layer 102 is formed on the top of the substrate 100 , and the floating gate layer 104 forms the top of the gate oxide layer 102 .

[0077] Specifically, the gate oxide layer 102 is a tunnel oxide layer (Tunnel Oxide) of the NOR flash memory, which is used as an isolation insulating layer between the floating gate layer 104 and the substrate 100, so that when the flash memory is working, the tunneling effect is used to allow electrons to enter the floating gate layer 104 through the gate oxide layer 102. Moreover, during the data storage process, the electrons stored in the floating gate layer 104 are prevented from entering the silicon substrate, thereby reducing the loss of electrons. That is, the gate oxide layer 102 is suitable for preventing the data stored in the floating gate layer 104 from being lost.

[0078] As an example, the material of the gate oxide layer 102 is silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

[0079] It should be noted that the thickness of the gate oxide layer 102 should not be too large or too small. If the thickness of the gate oxide layer 102 is too large, after the control gate layer is subsequently formed, it is easy to cause the overall height of the NOR flash memory to be too high, which is not conducive to further shrinking the semiconductor structure; if the thickness of the gate oxide layer 102 is too small, during the data storage process, the probability of the electrons stored in the floating gate layer 104 entering the substrate 100 is increased, thereby increasing the probability of electron loss, and further affecting the storage performance of the NOR flash memory. For this reason, in this embodiment, the thickness of the gate oxide layer 102 is 5 nanometers to 30 nanometers.

[0080] like Figure 3 As shown, in this embodiment, isolation structures 101 are formed in the substrate 100 on both sides of the floating gate layer 104 .

[0081] Specifically, the isolation structure 101 is used to electrically isolate adjacent floating gate layers 104 , thereby reducing the risk of electrical leakage from adjacent floating gate layers 104 through the substrate 100 .

[0082] The material of the isolation structure 101 is a dielectric material. In this embodiment, the material of the isolation structure 101 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the isolation structure 101 is silicon oxide.

[0083] In this embodiment, in the step of providing the substrate 100 , a dielectric layer 103 is formed on the substrate 100 where the floating gate layer 104 is exposed, and the dielectric layer 103 covers the sidewalls of the floating gate layer 104 .

[0084] Specifically, the dielectric layer 103 protects the side walls of the suspended gate layer 104. In the subsequent process of forming the cap layer and the gate insulating layer, the probability of the process of forming the cap layer and the gate insulating layer causing damage to the side walls of the suspended gate layer 104 is reduced. At the same time, the dielectric layer 103 covers the side walls of the suspended gate layer 104, so that the top surface of the dielectric layer 103 is flush with the top surface of the suspended gate layer 104, which can make the top surfaces of the suspended gate layer 104 and the dielectric layer 103 have higher flatness. In the subsequent process of forming the cap layer and the gate insulating layer, it is necessary to first deposit the cap material layer and the gate insulating material layer, and then perform patterning on the cap material layer and the gate insulating material layer. Since the top surfaces of the suspended gate layer 104 and the dielectric layer 103 have higher flatness, the process difficulty of depositing the cap material layer and the gate insulating material layer is reduced. At the same time, the process difficulty of patterning the cap material layer and the gate insulating material layer is also reduced.

[0085] As an example, the material of the dielectric layer 103 includes silicon oxide.

[0086] In other embodiments, the material of the dielectric layer may also be silicon oxynitride.

[0087] refer to Figures 4 to 6 A capping layer 116 and a gate insulating layer 115 covering the top of the capping layer 116 are formed on the top of the floating gate layer 104 .

[0088] Specifically, by setting a cap layer 116 on the top of the floating gate layer 104, compared with the solution of setting a gate insulating layer 115 on the top of the floating gate layer 104, in this embodiment, since the dielectric constant of the cap layer 116 is greater than the dielectric constant of the gate insulating layer 115, the cap layer 116 can redistribute the charges at the corners of the floating gate layer 104 through the electrostatic induction effect, so that a part of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corner of the floating gate layer 104, thereby improving the reliability of the semiconductor structure, and further improving the performance of the semiconductor structure.

[0089] It should be noted that, by providing the cap layer 116 on the top of the floating gate layer 104 , the cap layer 116 has an insulating effect, which can further reduce the risk of leakage between the floating gate layer 104 and the control gate layer formed subsequently.

[0090] Combined with reference Figures 4 to 6 , the steps of forming the cap layer 116 and the gate insulating layer 115 are described in detail.

[0091] refer to Figure 4 , a cap material layer 106 is formed on top of the floating gate layer 104 and the dielectric layer 103 .

[0092] Specifically, the capping material layer 106 provides material for forming the capping layer 116 .

[0093] In this embodiment, the process of forming the cap material layer 106 includes an atomic layer deposition process.

[0094] The atomic layer deposition process has the characteristics of good film filling performance, etc., which can make the subsequently formed cap layer 116 fit tightly with the suspended gate layer 104. The cap layer 116 can redistribute the charges at the corners of the suspended gate layer 104 through the electrostatic induction effect, so that part of the charges at the corners are taken away, reducing the probability of charge accumulation at the top corner of the suspended gate layer 104.

[0095] Continue to refer Figure 4 , a gate insulating material layer 105 is formed on the top of the cap material layer 106 .

[0096] Specifically, the gate insulating material layer 105 provides material for forming a gate insulating layer 115 , and the gate insulating layer 115 serves to electrically isolate the floating gate layer 104 and a control gate layer formed subsequently.

[0097] In this embodiment, the process of forming the gate insulating material layer 105 includes an atomic layer deposition process.

[0098] The atomic layer deposition process has the characteristic of uniform film deposition thickness. By forming the gate insulating material layer 105 using the atomic layer deposition process, the thickness of the subsequently formed gate insulating layer 115 can be made uniform, so that the gate insulating layer 115 can electrically isolate the floating gate layer 104 and the subsequently formed control gate layer.

[0099] In this embodiment, the gate insulating material layer 105 is a silicon oxide layer-silicon nitride layer-silicon oxide layer (Oxide-Nitride-Oxide, ONO) structure.

[0100] In other embodiments, the gate insulating material layer may also be only one or two of a silicon oxide layer and a silicon nitride layer.

[0101] refer to Figure 5 , a mask layer 110 covering the gate insulating material layer 105 is formed above the floating gate layer 104 .

[0102] Specifically, the mask layer 110 is used as an etching mask for forming the gate insulating layer 115 and the capping layer 116 in a subsequent patterning process.

[0103] As an example, the material of the mask layer 110 is photoresist. In other embodiments, the material of the mask layer may also be one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0104] refer to Figure 6 , using the mask layer 110 as a mask, the gate insulating material layer 105 and the capping material layer 106 are patterned to form a capping layer 116 on top of the floating gate layer 104 and a gate insulating layer 115 covering the capping layer 116 .

[0105] Specifically, patterning the gate insulating material layer 105 and the capping material layer 106 refers to removing the gate insulating material layer 105 and the capping material layer 106 above the dielectric layer 103 .

[0106] In this embodiment, the process of patterning the gate insulating material layer 105 and the capping material layer 106 includes a dry etching process.

[0107] Specifically, the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is greater than the lateral etching rate, and the process controllability is high. In the process of removing the gate insulating material layer 105 and the cap material layer 106 above the dielectric layer 103, the morphology quality of the side wall of the floating gate layer 104 can be ensured, and the probability of the side wall of the floating gate layer 104 being damaged can be reduced. At the same time, by selecting the dry etching process to perform patterning on the gate insulating material layer 105 and the cap material layer 106, the side wall of the cap layer 116 can be flush with the side wall of the floating gate layer 104, reducing the probability of charge accumulation at the top corner of the floating gate layer 104, thereby improving the reliability of the semiconductor structure, and further improving the performance of the semiconductor structure.

[0108] As an example, the gate insulating layer 115 and the capping layer 116 are formed in the same step, which can reduce the process steps and lower the process cost.

[0109] In other embodiments, the gate insulating layer and the capping layer may also be formed separately in different steps.

[0110] It should be noted that the thickness range of the cap layer 116 along the normal direction of the surface of the substrate 100 should not be too large or too small. If the thickness of the cap layer 116 is too large, after the control gate layer is subsequently formed, it is easy to cause the overall height of the NOR flash memory to be too high, which is not conducive to further shrinking the semiconductor structure; if the thickness of the cap layer 116 is too small, the function of the cap layer 116 to redistribute the charge at the corner of the floating gate layer 104 through the electrostatic induction effect will be affected, increasing the probability of charge accumulation at the top corner of the floating gate layer 104, thereby affecting the reliability of the semiconductor structure, and further affecting the performance of the semiconductor structure. For this reason, in this embodiment, along the normal direction of the surface of the substrate 100, the thickness range of the cap layer 116 is 5 nanometers to 30 nanometers.

[0111] In this embodiment, the material of the cap layer 116 includes titanium nitride.

[0112] Specifically, the dielectric constant of titanium nitride is relatively large and greater than the dielectric constant of the gate insulating layer 115. Under the electrostatic induction effect, titanium nitride can redistribute the charges at the corners of the floating gate layer 104, so that a part of the charges at the corners are taken away, thereby reducing the probability of charge accumulation at the top corner of the floating gate layer 104, thereby improving the reliability of the semiconductor structure.

[0113] Continue to refer Figure 6 In the step of forming the cap layer 116 and the gate insulating layer 115 , the step further includes: removing the dielectric layer 103 to expose the side wall of the floating gate layer 104 .

[0114] Specifically, the dielectric layer 103 is removed to provide a space for the subsequent formation of a spacer layer and a control gate layer covering the floating gate layer 104 .

[0115] In this embodiment, the process of removing the dielectric layer 103 includes a dry etching process.

[0116] As an example, removing the dielectric layer 103 during the process of patterning the gate insulating material layer 105 and the capping material layer 106 can reduce process steps and lower process costs.

[0117] In other embodiments, the dielectric layer may be removed by other etching processes after the gate insulation layer and the capping layer are formed.

[0118] It should be noted that, after forming the cap layer 116 and the gate insulation layer 115 , the method for forming the semiconductor structure further includes: removing the mask layer 110 .

[0119] Removing the mask layer 110 can expose the top surface of the gate insulating layer 115 , thereby providing a process basis for the subsequent formation of a spacer layer and a control gate layer.

[0120] In this embodiment, the process of removing the mask layer 110 includes an ashing process.

[0121] refer to Figure 7 After forming the cap layer 116 and the gate insulating layer 115 and before subsequently forming the control gate layer, the method further includes: forming a sidewall layer 126 on the substrate 100 to cover the sidewall of the floating gate layer 104 .

[0122] The spacer layer 126 is used to electrically isolate the floating gate layer 104 from a control gate layer to be formed subsequently.

[0123] In this embodiment, the step of forming the sidewall layer 126 includes: forming a sidewall material layer (not shown) on the top of the substrate 100 exposed by the floating gate layer 104, the sidewall of the floating gate layer 104, the sidewall of the cap layer 116, and the sidewall and top of the gate insulation layer 115; removing the sidewall material layer on the top of the substrate 100 exposed by the floating gate layer 104 and the sidewall material layer on the top of the gate insulation layer 115, and using the remaining sidewall material layer located on the sidewall of the floating gate layer 104 as the sidewall layer 126.

[0124] Specifically, the process of removing the spacer material layer on the top of the substrate 100 exposed by the floating gate layer 104 and the spacer material layer on the top of the gate insulating layer 115 includes a dry etching process.

[0125] As an example, the spacer layer 126 is a stacked structure, and the spacer layer 126 is a silicon oxide layer-silicon nitride layer-silicon oxide layer (Oxide-Nitride-Oxide, ONO) structure.

[0126] In other embodiments, the material of the spacer layer may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, or silicon nitride oxide.

[0127] refer to Figure 8 A control gate layer 130 is formed on the substrate 100 to cover the top and side of the floating gate layer 104 , and the control gate layer 130 covers the gate insulating layer 115 .

[0128] The control gate layer 130 is used to implement logic control operations of the NOR flash memory device, such as write control, read control, etc.

[0129] In this embodiment, the material of the control gate layer 130 is the same as that of the floating gate layer 104 , that is, the material of the control gate layer 130 is polysilicon.

[0130] In this embodiment, the process of forming the control gate layer 130 includes an atomic layer deposition process or a chemical vapor deposition process.

[0131] In this embodiment, in the step of forming the control gate layer 130 , the control gate layer 130 covers the gate oxide layer 102 exposed by the floating gate layer 104 .

[0132] Specifically, the control gate layer 130 covers the gate oxide layer 102 exposed by the floating gate layer 104 , thereby reducing the risk of leakage between the control gate layer 130 and the floating gate layer 104 through the substrate 100 .

[0133] As described above, the spacer layer 126 covers the sidewalls of the floating gate layer 104 . Accordingly, in the process of forming the control gate layer 130 , the control gate layer 130 covers the sidewalls and the top of the spacer layer 126 , which means that the spacer layer 126 can electrically isolate the control gate layer 130 from the floating gate layer 104 .

[0134] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A suspended gate layer, located on top of the substrate; A capping layer, located on the top of the suspended grid layer; A gate insulating layer, located on top of the capping layer, wherein the dielectric constant of the capping layer is greater than the dielectric constant of the gate insulating layer; The control gate layer is located on the substrate and covers the top and sidewalls of the floating gate layer. The control gate layer also covers the gate insulating layer.

2. The semiconductor structure according to claim 1, wherein: The material of the capping layer includes titanium nitride.

3. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the thickness of the capping layer ranges from 5 nanometers to 30 nanometers.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a spacer layer located on a sidewall of the floating gate layer; The control gate layer covers the sidewall and top of the spacer layer.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a gate oxide layer located on top of the substrate; The suspended gate layer is located on top of the gate oxide layer; The control gate layer covers the gate oxide layer exposed by the floating gate layer.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, with a suspended gate layer formed on the top of the substrate; forming a cap layer and a gate insulating layer covering the top of the cap layer on the top of the floating gate layer, wherein the dielectric constant of the cap layer is greater than the dielectric constant of the gate insulating layer; A control gate layer covering the top and side of the floating gate layer is formed on the substrate, and the control gate layer covers the gate insulating layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: In the step of providing a substrate, a dielectric layer is formed on the substrate where the floating gate layer is exposed, and the dielectric layer covers the sidewalls of the floating gate layer; The steps of forming the capping layer and the gate insulating layer include: forming a capping material layer on top of the suspended gate layer and the dielectric layer; forming a gate insulating material layer on top of the capping material layer; forming a mask layer covering the gate insulating material layer above the suspended gate layer; using the mask layer as a mask, patterning the gate insulating material layer and the capping material layer to form a capping layer on top of the suspended gate layer and a gate insulating layer covering the capping layer; and removing the mask layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the cap layer and the gate insulating layer also includes: removing the dielectric layer to expose the side wall of the floating gate layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the cap material layer includes an atomic layer deposition process.

10. The method for forming a semiconductor structure according to claim 7, wherein: The process of patterning the gate insulating material layer and the capping material layer includes a dry etching process.

11. The method for forming a semiconductor structure according to claim 6, wherein: The material of the capping layer includes titanium nitride.

12. The method for forming a semiconductor structure according to claim 6, wherein: Along the normal direction of the substrate surface, the thickness of the capping layer ranges from 5 nanometers to 30 nanometers.

13. The method for forming a semiconductor structure according to claim 6, wherein: In the step of providing a substrate, a gate oxide layer is also formed on the top of the substrate, and the suspended gate layer is formed on the top of the gate oxide layer; In the step of forming the control gate layer, the control gate layer covers the gate oxide layer exposed by the floating gate layer.

14. The method for forming a semiconductor structure according to claim 6, wherein: After forming the cap layer and the gate insulating layer and before forming the control gate layer, the method further comprises: forming a sidewall layer covering the sidewall of the floating gate layer on the substrate; In the step of forming the control gate layer, the control gate layer covers the sidewall and the top of the spacer layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming the sidewall layer includes: forming a sidewall material layer on the top of the substrate exposed by the floating gate layer, the sidewall of the floating gate layer, the sidewall of the cap layer, and the sidewall and top of the gate insulation layer; removing the sidewall material layer on the top of the substrate exposed by the floating gate layer and the sidewall material layer on the top of the gate insulation layer, and using the remaining sidewall material layer located on the sidewall of the floating gate layer as the sidewall layer.

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