Preparation method of flash memory device

Abstract

The invention provides a preparation method of a flash memory device, which comprises the following steps of: after a polycrystalline silicon material layer for filling a groove and covering a hard mask layer is formed, removing a part of thickness of the polycrystalline silicon material layer by adopting a dry etching process to obtain word line polycrystalline silicon; then removing the hard mask layer with partial thickness and the first silicon oxide layer and the second silicon oxide layer with partial height by adopting a wet etching process; and then removing the silicon nitride layer exceeding the partial height of the upper surface of the word line polycrystalline silicon. The polycrystalline silicon material layer with a certain thickness, the hard mask layer with a certain thickness, the first silicon oxide layer with a certain height, the second silicon oxide layer with a certain height and the silicon nitride layer with a certain height are removed through step-by-step etching, so that the upper surface of the hard mask layer with the residual thickness and the top end of the side wall structure are flush with the upper surface of the word line polycrystalline silicon; the problems of large thickness fluctuation of a hard mask layer and large height fluctuation of a flash memory unit caused by instability of multiple layers of films due to one-step grinding in a traditional CMP process are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a flash memory device. Background Art

[0002] NORD FLASH is a non-volatile memory. The height adjustment of several flash memory cells in NORD FLASH is achieved through a chemical mechanical polishing (CMP) process. Specifically, the height adjustment of the flash memory cells here refers to the thickness adjustment / thinning of the polysilicon material forming the word line, which is currently usually achieved by removing excess polysilicon material and hard mask layer through a chemical mechanical polishing process.

[0003] Due to the complex film structure of flash memory devices, one-step grinding through the CMP process will result in poor stability of the multi-layer film, causing large fluctuations in the thickness of the hard mask layer of the flash memory device and the height of the flash memory unit, thereby affecting the yield of the device.

[0004] At present, the hard mask layer used as a barrier layer in the multi-step etching process of flash memory devices and its own removal have high requirements for thickness stability. At the same time, the high requirements of the continuous iteration of the flash memory device preparation process also require a more stable process. Summary of the invention

[0005] The present application provides a method for preparing a flash memory device, which can solve the problem that the traditional height adjustment process of the flash memory unit in the flash memory device leads to poor stability of the device's multi-layer film, thereby causing large fluctuations in the thickness of the multi-layer film of the flash memory device and large fluctuations in the height of the flash memory unit, affecting the device yield.

[0006] The present invention provides a method for preparing a flash memory device, comprising: A semiconductor structure is provided, the semiconductor structure at least comprising: a plurality of flash memory cells, wherein each of the flash memory cells comprises: a substrate, a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a hard mask layer, a trench is formed in the hard mask layer, the control gate layer, the ONO film layer and the floating gate layer, a sidewall structure is formed on the sidewall of the trench, wherein the sidewall structure comprises a first silicon oxide layer covering the sidewall of the trench, a silicon nitride layer covering the first silicon oxide layer and a second silicon oxide layer covering the silicon nitride layer; forming a polysilicon material layer, wherein the polysilicon material layer fills the trench and covers the hard mask layer; Removing the polysilicon material layer on the top of the hard mask layer and a portion of the polysilicon material layer in the trench to obtain word line polysilicon; Removing a portion of the thickness of the hard mask layer and a portion of the height of the first silicon oxide layer and the second silicon oxide layer in the sidewall structure, so that the upper surface of the remaining thickness of the hard mask layer is flush with the upper surface of the word line polysilicon in the trench; removing a portion of the silicon nitride layer in the spacer structure that exceeds the upper surface of the word line polysilicon; and A word line protection layer is formed, where the word line protection layer covers the remaining thickness of the hard mask layer and the word line polysilicon.

[0007] Optionally, in the method for preparing the flash memory device, a dry etching process is used to remove the polysilicon material layer on the top of the hard mask layer and a partial thickness of the polysilicon material layer in the groove to obtain word line polysilicon.

[0008] Optionally, in the method for preparing the flash memory device, a wet etching process is used to remove a portion of the thickness of the hard mask layer and a portion of the height of the first silicon oxide layer and the second silicon oxide layer in the sidewall structure, so that the upper surface of the remaining thickness of the hard mask layer is flush with the upper surface of the word line polysilicon in the groove.

[0009] Optionally, in the method for preparing the flash memory device, a wet etching process is used to remove a portion of the silicon nitride layer in the sidewall structure that exceeds the upper surface of the word line polysilicon.

[0010] Optionally, in the method for preparing the flash memory device, the word line protection layer is a TEOS film layer.

[0011] Optionally, in the method for preparing the flash memory device, the word line protection layer is formed by adopting a CVD process in a gas environment containing at least TEOS gas and O3.

[0012] Optionally, in the method for preparing the flash memory device, after removing a portion of the height of the silicon nitride layer in the sidewall structure that exceeds the upper surface of the word line polysilicon, the remaining heights of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer are the same in height, and the upper surfaces of the remaining heights of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer are flush with the upper surface of the word line polysilicon.

[0013] Optionally, in the method for preparing the flash memory device, the material of the hard mask layer is silicon dioxide.

[0014] The technical solution of this application has at least the following advantages: After forming a polysilicon material layer filling the groove and covering the hard mask layer, the present application first uses a dry etching process to remove a portion of the polysilicon material layer to obtain word line polysilicon; then uses a wet etching process to remove a portion of the hard mask layer and a portion of the first silicon oxide layer and the second silicon oxide layer; then removes a portion of the silicon nitride layer that exceeds the upper surface of the word line polysilicon. The present application uses step-by-step etching to remove a polysilicon material layer of a certain thickness, a hard mask layer of a certain thickness, and a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer of a certain height, respectively, so that the upper surface of the remaining thickness of the hard mask layer and the top of the sidewall structure are flush with the upper surface of the word line polysilicon, solving the problem of large fluctuations in the thickness of the hard mask layer and large fluctuations in the height of the flash memory unit caused by the instability of the multi-layer thin film caused by one-step grinding in the traditional CMP process, while further reducing the size of the flash memory device, the yield of the flash memory device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention; Figure 2-Figure 7 is a schematic diagram of a semiconductor structure in each process step of preparing a flash memory device according to an embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 20-gate oxide layer, 30-floating gate layer, 40-ONO film layer, 50-control gate layer, 60-hard mask layer, 61-trench, 70-sidewall structure, 71-first silicon oxide layer, 72-silicon nitride layer, 73-second silicon oxide layer, 80-polysilicon material layer, 81-word line polysilicon, 90-word line protection layer. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] The present application provides a method for preparing a flash memory device, referring to Figure 1 , Figure 1 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention, wherein the method for preparing a flash memory device comprises: First, perform step S1: refer to Figure 2 , Figure 2 1 is a schematic diagram of a semiconductor structure with a sidewall structure formed in an embodiment of the present application, and a semiconductor structure is provided, wherein the semiconductor structure at least includes: a plurality of flash memory units, wherein each of the flash memory units includes: a substrate 10, a gate oxide layer 20, a floating gate layer 30, an ONO film layer 40, a control gate layer 50 and a hard mask layer 60, a groove 61 is formed in the hard mask layer 60, the control gate layer 50, the ONO film layer 40 and the floating gate layer 30, and a sidewall structure 70 is formed on the sidewall of the groove 61, wherein the sidewall structure 70 includes a first silicon oxide layer 71 covering the sidewall of the groove 61, a silicon nitride layer 72 covering the first silicon oxide layer 71 and a second silicon oxide layer 73 covering the silicon nitride layer 72.

[0022] In this embodiment, the material of the hard mask layer 60 is silicon dioxide.

[0023] Then, execute step S2: refer to Figure 3 , Figure 3 Schematic diagram of the semiconductor structure after a polysilicon material layer is formed according to an embodiment of the present application, wherein a polysilicon material layer 80 is formed, and the polysilicon material layer 80 fills the trench 61 and covers the hard mask layer 60 .

[0024] Next, execute step S3: refer to Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after removing a portion of the thickness of the polysilicon material layer to obtain the word line polysilicon in an embodiment of the present application, wherein the polysilicon material layer 80 on the top of the hard mask layer 60 and a portion of the thickness of the polysilicon material layer 80 in the groove 61 are removed to obtain the word line polysilicon 81.

[0025] Preferably, a dry etching process is used to remove the polysilicon material layer 80 on the top of the hard mask layer 60 and a portion of the polysilicon material layer 80 in the trench 61 to obtain the word line polysilicon 81 .

[0026] The flash memory device provided in the embodiment of the present application is a flash memory device that shares word lines.

[0027] It is worth noting that in the process of etching and removing the polysilicon material layer 80 on the top of the hard mask layer 60, the present application will inevitably etch part of the hard mask layer 60, but the speed of etching the polysilicon material layer 80 is much greater than the speed of etching the hard mask layer 60, that is, the present application uses a high selectivity to etch the polysilicon material layer 80 to reduce the height of the word line polysilicon, and during the etching process, by capturing the hard mask layer 60 signal, the hard mask layer 60 is avoided as much as possible, and the height of the polysilicon material layer 80 is flexibly controlled and adjusted.

[0028] Further, step S4 is performed: refer to Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after removing a portion of the thickness of the hard mask layer and a portion of the height of the first silicon oxide layer and the second silicon oxide layer in the sidewall structure according to an embodiment of the present application, wherein a portion of the thickness of the hard mask layer 60 and a portion of the height of the first silicon oxide layer 71 and the second silicon oxide layer 73 in the sidewall structure 70 are removed so that the upper surface of the remaining thickness of the hard mask layer 60 is flush with the upper surface of the word line polysilicon 81 in the trench 61.

[0029] Preferably, a wet etching process is used to remove a portion of the thickness of the hard mask layer 60 and a portion of the height of the first silicon oxide layer 71 and the second silicon oxide layer 73 in the sidewall structure 70, so that the upper surface of the remaining thickness of the hard mask layer 60 is flush with the upper surface of the word line polysilicon 81 in the groove 61, wherein the wet etching solution can be an acidic solution.

[0030] The present application can stably control and flexibly adjust the height of the hard mask layer 60 by controlling the amount of the acidic solution. The silicon nitride layer 72 on the side of the hard mask layer 60 can effectively inhibit wet etching removal, thereby avoiding the side effects of isotropic etching in step S4.

[0031] Next, execute step S5: refer to Figure 6 , Figure 6 It is a schematic diagram of the semiconductor structure after the silicon nitride layer of a portion of the height of the sidewall structure exceeding the upper surface of the word line polysilicon is removed according to an embodiment of the present application, and the silicon nitride layer 72 of a portion of the height of the sidewall structure 70 exceeding the upper surface of the word line polysilicon 81 is removed.

[0032] Preferably, a wet etching process is used to remove a portion of the silicon nitride layer 72 in the sidewall structure 70 that exceeds the upper surface of the word line polysilicon 81 , wherein the wet etching solution may be hot phosphoric acid.

[0033] It is worth noting that after removing the silicon nitride layer 72 to a certain height exceeding the upper surface of the word line polysilicon 81, the remaining heights of the first silicon oxide layer 71, the silicon nitride layer 72 and the second silicon oxide layer 73 are the same, and the upper surfaces of the remaining heights of the first silicon oxide layer 71, the silicon nitride layer 72 and the second silicon oxide layer 73 are flush with the upper surface of the word line polysilicon 81.

[0034] Finally, execute step S6: reference Figure 7 , Figure 7 It is a schematic diagram of the semiconductor structure after forming a word line protection layer according to an embodiment of the present application, wherein a word line protection layer 90 is formed, and the word line protection layer 90 covers the remaining thickness of the hard mask layer 60, the word line polysilicon 81 and the remaining height of the sidewall structure 70.

[0035] Preferably, the word line protection layer 90 is a TEOS film layer.

[0036] In this embodiment, the word line protection layer 90 is formed by a CVD process in a high pressure environment containing at least TEOS gas and O3 gas at 30 Torr to 50 Torr, wherein the flow rate of TEOS gas is 0.15 g / min to 1.35 g / min; the flow rate of O3 gas is 5000 sccm to 10000 sccm.

[0037] The embodiment of the present application uses O3 to prepare the word line protection layer 90 (TEOS film layer), which can make the TEOS film layer have a certain fluidity and filling ability so that the top of the device is more flat.

[0038] In the present application, a polysilicon material layer of a certain thickness, a hard mask layer of a certain thickness, and a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer of a certain height are removed respectively by step-by-step etching, so that the upper surface of the remaining thickness of the hard mask layer and the top of the sidewall structure are flush with the upper surface of the word line polysilicon, thereby solving the problem of large fluctuations in the thickness of the hard mask layer and large fluctuations in the height of the flash memory unit caused by the instability of the multi-layer thin film caused by one-step grinding in the traditional CMP process, and further reducing the size of the flash memory device while improving the yield of the flash memory device.

[0039] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a flash memory device, characterized in that: include: A semiconductor structure is provided, the semiconductor structure at least comprising: a plurality of flash memory cells, wherein each of the flash memory cells comprises: a substrate, a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a hard mask layer, a trench is formed in the hard mask layer, the control gate layer, the ONO film layer and the floating gate layer, a sidewall structure is formed on the sidewall of the trench, wherein the sidewall structure comprises a first silicon oxide layer covering the sidewall of the trench, a silicon nitride layer covering the first silicon oxide layer and a second silicon oxide layer covering the silicon nitride layer; forming a polysilicon material layer, wherein the polysilicon material layer fills the trench and covers the hard mask layer; Removing the polysilicon material layer on the top of the hard mask layer and a portion of the polysilicon material layer in the trench to obtain word line polysilicon; Removing a portion of the thickness of the hard mask layer and a portion of the height of the first silicon oxide layer and the second silicon oxide layer in the sidewall structure, so that the upper surface of the remaining thickness of the hard mask layer is flush with the upper surface of the word line polysilicon in the trench; removing a portion of the silicon nitride layer in the spacer structure that exceeds the upper surface of the word line polysilicon; and A word line protection layer is formed, where the word line protection layer covers the remaining thickness of the hard mask layer and the word line polysilicon.

2. The method for preparing a flash memory device according to claim 1, wherein: The polysilicon material layer on the top of the hard mask layer and a part of the thickness of the polysilicon material layer in the trench are removed by dry etching process to obtain word line polysilicon.

3. The method for preparing a flash memory device according to claim 1, wherein: A wet etching process is used to remove a portion of the thickness of the hard mask layer and a portion of the height of the first silicon oxide layer and the second silicon oxide layer in the sidewall structure, so that the upper surface of the remaining thickness of the hard mask layer is flush with the upper surface of the word line polysilicon in the trench.

4. The method for preparing a flash memory device according to claim 1, wherein: A wet etching process is used to remove a portion of the silicon nitride layer in the sidewall structure that exceeds the upper surface of the word line polysilicon.

5. The method for preparing a flash memory device according to claim 1, wherein: The word line protection layer is a TEOS film layer.

6. The method for preparing a flash memory device according to claim 5, characterized in that: The word line protection layer is formed by using a CVD process in a gas environment containing at least TEOS gas and O3.

7. The method for preparing a flash memory device according to claim 1, characterized in that: After removing a portion of the height of the silicon nitride layer in the sidewall structure that exceeds the upper surface of the word line polysilicon, the remaining heights of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer are the same in height, and the upper surfaces of the remaining heights of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer are flush with the upper surface of the word line polysilicon.

8. The method for preparing a flash memory device according to claim 1, wherein: The material of the hard mask layer is silicon dioxide.

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