Three-dimensional memory device and manufacturing method thereof

Abstract

Embodiments of three-dimensional (3D) memory devices and methods of fabricating the same are disclosed. A disclosed semiconductor device may include: a stacked structure including alternating conductive layers and dielectric layers; and a gate line structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory fingers. The gate line structure may include gate line slot structure segments aligned along the first lateral direction; and at least one first dummy contact structure located between adjacent gate line slot structure segments in the first lateral direction.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device, and a manufacturing method for forming a three-dimensional (3D) memory device. Background Art

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can address density limitations in planar memory cells.

[0003] With the advancement of semiconductor technology, 3D memory devices, such as 3D NAND memory devices, continue to scale more film layers to improve the area utilization of the chip. In some existing 3D NAND memory devices, as the number of film layers increases and the structure of the film layers becomes more complex, the silicon substrate used as a carrier of the film layer may not support the wafer deformation caused by the film stress, which may eventually cause the wafer to be curved. In addition, as the number of oxide / nitride (ON) layers increases, the etching depth of the gate line slit (GLS) increases accordingly, resulting in changes in the critical dimension of the GLS, thereby increasing the risk of structural instability due to stress and other factors. This unstable structure may cause storage finger bending / collapse, wafer bow effect, and affect subsequent 3D memory device manufacturing processes, such as increasing the overlap error in the lithography alignment process. Summary of the invention

[0004] Embodiments of three-dimensional (3D) memory devices and methods of making the same are disclosed herein.

[0005] One aspect of the present disclosure provides a semiconductor device, comprising: a stacked structure including alternating conductive layers and dielectric layers; and a gate line structure extending vertically through the stacked structure and laterally along a first lateral direction to divide the stacked structure into storage fingers, the gate line structure comprising: gate line gap structure segments aligned along the first lateral direction; and at least one first dummy contact structure located between adjacent gate line gap structure segments in the first lateral direction.

[0006] In some embodiments, the at least one first dummy contact structure is located in an array region or a step region.

[0007] In some embodiments, there are a plurality of first dummy contact structures located between two adjacent gate line gap structure segments along the first lateral direction.

[0008] In some embodiments, the semiconductor device further includes: a second dummy contact structure in the step region; wherein a first distance between adjacent first dummy contact structures is smaller than a second distance between adjacent second dummy contact structures.

[0009] In some embodiments, each of the first dummy contact structure and the second dummy contact structure includes a via structure, which is insulated from the conductive layer of the stacked structure by a spacer layer; and the thickness of the spacer layer of the first dummy contact structure is substantially equal to the thickness of the spacer layer of the second dummy contact structure.

[0010] In some embodiments, the semiconductor device further includes: a gate line contact structure extending vertically in the step region.

[0011] In some embodiments, the semiconductor device also includes: each gate line gap structure segment includes a wall structure, which extends laterally in the first lateral direction and is insulated from the conductive layer of the stacked structure; and each gate line contact structure includes a conductive via and is electrically connected to the corresponding conductive layer of the stacked structure.

[0012] In some embodiments, the semiconductor device further includes: the conductive via is in contact with a landing conductive layer on the corresponding conductive layer and is insulated from other conductive layers below the corresponding conductive layer.

[0013] In some embodiments, a width of the gate line gap structure segment in a second lateral direction orthogonal to the first lateral direction is substantially equal to a width of the first dummy contact structure in the second lateral direction.

[0014] In some embodiments, the semiconductor device further includes: channel structures, each of which extends vertically in the array region of the stacked structure.

[0015] Another aspect of the present disclosure provides a method for forming a semiconductor device, the method comprising: forming a dielectric stack comprising alternating sacrificial layers and dielectric layers; forming a first through hole, the first through hole being laterally aligned along a first lateral direction and each extending vertically through the dielectric stack; forming a sacrificial filling structure in the first through hole; removing the sacrificial filling structure from a first subset of the first through holes; forming a first dummy contact structure in the first subset of the first through holes; removing the sacrificial filling structure from a second subset of the first through holes to form a gate line gap, wherein the first dummy contact structure is located between the gate line gaps, the first dummy contact structure and the gate line gap are laterally aligned in the first lateral direction; and forming a gate line gap structure segment in the gate line gap.

[0016] In some embodiments, the method also includes: forming a stepped structure on one side of the dielectric stack; forming a second through hole located in the stepped structure; forming a sacrificial filling structure in the second through hole; removing the sacrificial filling structure from the second through hole; and forming a second dummy contact structure in the second through hole.

[0017] In some embodiments, the method also includes: the first through hole and the second through hole are formed simultaneously; the sacrificial filling structure is formed in the first through hole and the second through hole simultaneously; the sacrificial filling structure is removed from the first subset of the first through hole and the second through hole simultaneously; and the first dummy contact structure and the second dummy contact structure are formed in the first subset of the first through hole and the second through hole simultaneously.

[0018] In some embodiments, forming the first dummy contact structure and the second dummy contact structure includes: removing portions of the sacrificial layer exposed by the first subset of the first through holes and the second through holes to form lateral recesses between the dielectric layers, so that adjacent first through holes in each first subset are interconnected with each other through the lateral recesses; forming a first insulating layer in the lateral recesses and side walls of the first subset of the first through holes and the second through holes; and forming a via structure on the first insulating layer to fill the first subset of the first through holes and the second through holes.

[0019] In some embodiments, the method further includes: removing the sacrificial layer through the gate line gaps to form a lateral opening between the dielectric layers; and forming a conductive layer in the lateral opening.

[0020] In some embodiments, forming the gate line gap structure segment includes: removing a portion of the dielectric layer exposed by the gate line gap; forming a second insulating layer on the sidewalls and bottom of the gate line gap; and forming a wall structure on the second insulating layer to fill the gate line gap.

[0021] In some embodiments, the method further includes: removing a portion of the second dummy contact structure to form a third through hole; and forming a gate line contact structure in the third through hole.

[0022] In some embodiments, forming the stepped structure includes forming a landing conductive layer on each step of the stepped structure; forming the third through hole includes exposing the landing conductive layer; and forming the gate line contact structure includes forming a conductive via in the third through hole to contact the landing conductive layer.

[0023] In some embodiments, the method further includes forming channel structures each extending vertically in the array region of the dielectric stack.

[0024] Another aspect of the present disclosure provides a memory device, the memory device comprising: a stacked structure comprising alternating conductive layers and dielectric layers; channel structures, each extending vertically in an array region of the stacked structure; a gate line structure extending vertically through the stacked structure and extending laterally along a first lateral direction to divide the stacked structure into storage fingers, the gate line structure comprising: gate line gap structure segments aligned along the first lateral direction; and first dummy contact structures aligned closely to each other along the first lateral direction and located between the gate line gap structure segments in the first lateral direction; second dummy contact structures, separately aligned to each other and located in a step region of the stacked structure; and a gate line contact structure extending vertically in the step region of the stacked structure.

[0025] Those skilled in the art can understand other aspects of the present disclosure based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, also serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0027] Figure 1 A block diagram of a system having a memory device according to some aspects of the present disclosure is shown.

[0028] Figure 2A A diagram showing a memory card having a storage device according to some embodiments.

[0029] Figure 2B A diagram of a solid-state drive (SSD) having memory according to some embodiments is shown.

[0030] Figure 3 A top view of a 3D memory device according to some embodiments of the present disclosure is shown.

[0031] Figure 4 A perspective view of a portion of a 3D memory array structure according to some embodiments of the present disclosure is shown.

[0032] Figure 5 A top perspective view of a portion of a 3D memory array structure according to some embodiments of the present disclosure is shown.

[0033] Figure 6 A flow chart of a method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0034] Figure 7 In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0035] Fig. 8A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0036] Figure 8B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0037] Figure 8C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0038] Fig.9A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0039] Fig. 9B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0040] Fig. 9C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0041] Fig. 10A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0042] Fig. 10B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0043] Fig. 10C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0044] Fig.11A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0045] Fig. 11B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0046] Fig. 11C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0047] Fig. 12A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0048] Fig. 12B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0049] Fig. 12CIn another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0050] Fig.13A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0051] Fig. 13B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0052] Fig. 13C In another cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0053] Fig.14A In a top perspective view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0054] Fig. 14B In a cross-sectional side view, some embodiments of the present disclosure are shown. Figure 6 Schematic diagram of a portion of a 3D memory device at a certain manufacturing stage of the method shown in FIG.

[0055] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0056] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0057] It should be noted that references in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiments may include certain features, structures, or characteristics, but each embodiment may not necessarily include certain features, structures, or characteristics. In addition, these phrases do not necessarily refer to the same embodiment. In addition, when a certain feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant field to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0058] In general, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, and characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can still be understood to express singular usage or to express plural usage, depending, at least in part, on the context.

[0059] It should be easily understood that the meaning of “on,” “over,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” and “over” not only mean the meaning of “above something” and “on something,” but also include the meaning of “over something” and “on something” with no intervening features or layers therebetween (i.e., directly on something).

[0060] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element (single or multiple) or feature (single or multiple) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0061] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0062] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of lateral planes between the top surface and the bottom surface of a continuous structure. A layer may extend laterally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein contact portions, interconnects and / or vias are formed) and one or more dielectric layers.

[0063] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" may refer to a value of a given quantity that varies within a range of, for example, 10-30% (e.g., ±10%, ±20%, or ±30% of the value).

[0064] As used herein, the term "3D memory device" refers to a semiconductor device having a vertically oriented memory cell transistor string (i.e., a region referred to herein as a "memory string" (e.g., a NAND string)) on a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" refers to a semiconductor device that is nominally orthogonal to a lateral surface of the substrate.

[0065] As described above, 3D NAND memory devices keep scaling more film layers to improve the area utilization of the wafer. In some existing 3D NAND memory devices, as the number of film layers increases and the structure of the film layers becomes more complex, the silicon substrate used as a carrier of the film layers may not support the wafer deformation caused by the film stress, which may eventually cause the wafer to be curved. In addition, as the number of oxide / nitride (ON) layers increases, the etching depth of the gate line gap (GLS) increases accordingly, resulting in changes in the critical dimension of the GLS, thereby increasing the risk of structural instability due to stress and other factors. This unstable structure may cause storage finger bending / collapse, wafer bow effect, and affect subsequent 3D memory device manufacturing processes, such as increasing the overlay error in the lithography alignment process.

[0066] Therefore, according to various embodiments of the present disclosure, a 3D memory device and a manufacturing method for forming the 3D memory device are provided, which has a novel design of a gate line gap (GLS) structure for a memory array (also referred to herein as an "array device"). Based on the GLS extension process, the patterning processes of the channel holes, GLS openings, and through holes can be merged into a single mask. By eliminating the traditional long GLS isolation structure, a storage finger support portion can be designed between the GLS structure segments. The dummy contact structure can be used as a storage finger support portion and can be formed in the same process as the contact structure. And the isolation function can be achieved by a silicon nitride recess process and an oxide deposition process, and is achieved together with the short GLS structure segment.

[0067] Since there is no long GLS running through the entire plane, the risk of structural instability due to stress can be suppressed by using short GLS structural segments and storage finger support portions. The filling oxide and polysilicon materials in the short GLS structural segments and storage finger support portions can significantly reduce device defects, including storage finger bending / collapse and / or wafer bow effect. In addition, by merging the contact formation process and the GLS structure formation process, the application of the photolithography process can be reduced, thereby reducing the process difficulty and production cost. In summary, the present disclosure can solve the manufacturing problems caused by structural stress, thereby breaking through the technical bottleneck in the research and development of higher-level 3D memory devices.

[0068] Figure 1 1 shows a block diagram of a system 100 having a storage device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, the system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more storage devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to the storage device 104 or receive data from the storage device 104.

[0069] The memory device 104 may be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of the present disclosure, the memory controller 106 may control the multi-pass programming on the memory device 104 so that in a non-final programming pass of the multi-pass programming, NGS operations are enabled on all memory cells, even those that have passed corresponding verification operations. A peripheral circuit, such as a word line driver, may apply a low voltage, such as a ground (GND) voltage, to the DSG of each memory string coupled to a selected word line, and may apply a low voltage or a negative voltage to the selected word line to enable NGS operations on all memory cells coupled to the selected word line during a non-final programming pass.

[0070] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multi-media card (embedded multi-media-card, eMMC), which is used as a data storage and enterprise storage array for mobile devices (such as smart phones, tablets, laptops, etc.). The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) regarding data read from or written to the memory device 104. Any other suitable functions may also be performed by the memory controller 106, such as programming the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0071] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2A In one example shown, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The host computer 108 in the embodiment of the present invention is coupled to the memory card connector 208. Figure 2B In another example shown, the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 210. The SSD 210 may also include a processor that connects the SSD 210 to a host (eg, Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 210 is greater than the storage capacity or operating speed of the memory card 202.

[0072] Figure 3 A top view of a 3D memory device 300 according to some embodiments of the present disclosure is shown. The 3D memory device 300 may be a memory chip (package), a memory chip, or any portion of a memory chip, and may include one or more memory planes 301, each of which may include multiple memory blocks 303. The same and concurrent operations may occur at each memory plane 301. The size of the memory block 303 may be megabytes (MB), which may be the minimum size for performing erase operations. Figure 3 As shown, the 3D memory device 300 includes four memory planes 301, and each memory plane 301 includes six memory blocks 303. Each memory block 303 may include a plurality of memory cells, wherein each memory cell may be addressed by interconnections such as bit lines and word lines. The bit lines and word lines may be arranged orthogonally (e.g., in rows and columns, respectively) to form a metal line array. Figure 3In the embodiment of the present invention, the direction of the word line is referred to as the first lateral direction and is marked as the X direction, and the direction of the bit line is referred to as the second lateral direction and is marked as the Y direction. In the present disclosure, the memory block 303 is also referred to as a "memory array" or "array". The memory array is the core area in the memory device that performs the storage function.

[0073] 3D memory device 300 may include a peripheral region 305, an area surrounding storage plane 301. Peripheral region 305 may contain many digital, analog and / or mixed signal circuits to support the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. Peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those of ordinary skill in the art. Note that Figure 3 The arrangement of the memory planes 301 in the 3D memory device 300 and the arrangement of the memory blocks 303 in each memory plane 301 shown in FIG. 3 are provided only as examples, which do not limit the scope of the present disclosure.

[0074] Figure 4 A perspective view of a portion of a 3D memory array structure 400 according to some embodiments of the present disclosure is shown. The memory array structure 400 includes a substrate 430, an insulating film 431 on the substrate 430, one or more levels of bottom select gates (BSG) 432 on the insulating film 431, and multiple levels of control gates 433 stacked on top of the BSG 432 to form a stack structure 435 of alternating conductive layers and dielectric layers, also referred to as "word lines (WL)". For clarity, Figure 4 Not shown are dielectric layers adjacent to the level of the control gate.

[0075] The control gate 433 of each level is separated by the gap structure 416-1 and 416-2 passing through the stack structure 435. The memory array structure 400 may include one or more levels of top select gates (TSG) 434 above the stack of control gates 433. The stack of TSG 434, control gate 433 and BSG 432 is also referred to as a "gate structure". The memory array structure 400 also includes memory strings 412 in the array region 411 and doped source line regions 444 in the portion of the substrate 430 between adjacent BSG 432. Each memory string 412 includes a channel hole 436 extending through the insulating film 431 and the stack structure 435 of alternating conductive layers and dielectric layers. The memory string 412 may also include a memory film 437 (also referred to as a "functional layer") on the sidewalls of the channel hole 436, a channel layer 438 on the memory film 437, and a core filling film 439 surrounded by the channel layer 438. The memory cell 440 may be formed at the intersection of the control gate 433 and the memory string 412. The memory array structure 400 also includes a plurality of bit lines (BL) 441 connected to the memory string 412 over the TSG 434. The memory array structure 400 may include a plurality of metal interconnect lines 443 connected to the gate structure through a plurality of contact structures 414. The edge of the stack structure 435 is configured as a step structure 410 to allow electrical connection to each level of the gate structure.

[0076] exist Figure 4 , for illustrative purposes, three levels of control gates 433-1, 433-2, and 433-3 are shown together with one level of TSG 434 and one level of BSG 432. In this example, each memory string 412 may include three memory cells 440-1, 440-2, and 440-3 corresponding to the control gates 433-1, 433-2, and 433-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 400 may also include other structures, such as TSG cuts, common source contacts, and dummy channel structures. For simplicity, in Figure 4 These structures are not shown.

[0077] refer to Figure 5 , showing in an enlarged top view a portion 500 of a 3D memory device according to some embodiments of the present disclosure (e.g. Figure 3308). As shown, a portion 500 of a 3D memory device may include an array region 510 and a step region 520, the array region 510 including a plurality of channel structures 550, and the step region 520 including a plurality of steps 524. A plurality of slits may extend laterally in parallel along a word line direction (i.e., an X direction) and vertically through the stacked structure. A gate line slit (GLS) structure 530 may be formed in each slit to divide the memory array into a plurality of memory fingers 540. Each memory finger 540 may include a plurality of rows (e.g., nine rows) of channel structures 550 arranged between two adjacent GLS structures 530 in a staggered manner.

[0078] As described above, as the number of film layers increases and the structure of the film layers becomes more complex, the silicon substrate used as a carrier of the film layers may not support the wafer deformation caused by the film stress, which may eventually cause the wafer to be curved. In addition, as the 3D memory device keeps scaling a larger number of ON layers to improve the area utilization of the wafer, the etching depth of the GLS increases accordingly, resulting in the risk of collapse of the storage fingers 540 between adjacent GLS structures 530 due to stress and other factors in subsequent processes. The collapse of the storage fingers 540 can affect the subsequent 3D memory device manufacturing process, such as increasing the overlay error in the photolithography alignment process.

[0079] The present disclosure provides various segmented GLS structural designs as technical solutions to avoid the above problems. Figure 5 In some embodiments shown, each GLS structure 530 may include two or more gate line gap (GLS) structure segments 531 aligned along the word line direction (X direction), and at least one first dummy contact structure 535 located between adjacent GLS structure segments 531 in the word line direction. In some embodiments, there may be one or more first dummy contact structures 535 located in the array region 510, and / or there may be one or more first dummy contact structures 535 located in the step region 520. In some embodiments, there are multiple first dummy contact structures 535 located between two adjacent GLS structure segments 531 along the word line direction. It should be noted that Figure 5 The ones shown in include Figure 5 The illustrated example of three first dummy contact structures 535 located between two adjacent GLS structure segments 531 does not limit the disclosed subject matter.The number of consecutive first dummy contact structures 535 located between two adjacent GLS structure segments 531 may be any suitable number.

[0080] like Figure 5As shown, a plurality of second dummy contact structures 565 may be located in the step region 520. In some embodiments, a first distance between adjacent first dummy contact structures 535 may be less than a second distance between adjacent second dummy contact structures 565. In some embodiments, each of the first dummy contact structure 535 and the second dummy contact structure 565 includes a via structure insulated from a conductive layer of the stacked structure by a spacer layer. In some embodiments, a thickness of the spacer layer of the first dummy contact structure 535 is substantially equal to a thickness of the spacer layer of the second dummy contact structure 565. Figure 5 In some embodiments not shown in FIG. 5 , a plurality of dummy channel structures may be located in the stepped region 520 to replace the second dummy contact structure 565. The second dummy contact structure 565 or the dummy channel structure may provide a support function for the stepped region 520 of the 3D memory device.

[0081] like Figure 5 As shown, a plurality of gate line contact structures 575 may extend vertically in the step region 520. In some embodiments, each GLS structure segment 531 includes a wall structure extending laterally in the word line direction (X direction) and insulated from the conductive layer of the stacked structure. In some embodiments, each gate line contact structure 575 includes a conductive via that is electrically connected to the corresponding conductive layer of the stacked structure. In some embodiments, the conductive via contacts the landing conductive layer 528 on the corresponding conductive layer and is insulated from other conductive layers below the corresponding conductive layer by the spacer layer. In some embodiments, the thickness of the spacer layer of the first dummy contact structure 535 is substantially equal to the thickness of the spacer layer of the gate line contact structure 575. In some embodiments, the width of the GLS structure segment 531 in the bit line direction (Y direction) may be substantially equal to the width of the first dummy contact structure 535 in the bit line direction.

[0082] refer to Figure 6 , a flow chart of a method 600 for forming a 3D memory device according to some embodiments of the present disclosure is shown. Figure 7 , Figures 8A-8C , Figures 9A-9C , Figures 10A-10C , Figures 11A-11C , Figures 12A-12C , Figures 13A-13C and Figures 14A-14B In various views, various embodiments of the present disclosure are shown. Figure 6 6 is a schematic diagram of a portion of a 3D memory device at certain stages of manufacturing of method 600 shown in FIG. 6. It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 6 The different orders are shown.

[0083] like Figure 6 As shown, the method may begin at operation 610 , in which a dielectric stack structure may be formed on a substrate, and a portion of the dielectric stack structure in a step region may be removed to form a step structure. Figure 7 A cross-sectional view of the 3D structure after operation 610 is shown, in accordance with some embodiments of the present disclosure.

[0084] In some embodiments, substrate 710 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polycrystalline silicon (poly-Si) single layer substrate, a poly-Si and metal multi-layer substrate, and the like.

[0085] A dielectric stack structure 720 including a plurality of dielectric layer pairs may be formed on a substrate 710. For example, the dielectric stack structure 720 may include an alternating stack of a first dielectric layer 722 (e.g., silicon oxide) and a second dielectric layer 724 (e.g., silicon nitride) different from the first dielectric layer 722. The plurality of first dielectric layers 722 and second dielectric layers 724 extend in a lateral direction parallel to a surface of the substrate 710. In some embodiments, there are more layers in the dielectric stack structure 720 than dielectric layer pairs made of different materials and having different thicknesses. The dielectric stack structure 720 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0086] In some embodiments, the dielectric stack structure 720 may include a plurality of silicon oxide / nitride layer pairs. Each dielectric layer pair includes a silicon oxide layer 722 and a silicon nitride layer 724. The plurality of oxide / nitride layer pairs are also referred to herein as "alternating oxide / nitride stacks". That is, in the dielectric stack structure 720, a plurality of oxide layers 722 (shown in the solid gray area) and a plurality of nitride layers 724 (shown in the grid area) alternate in the vertical direction. In other words, except for the top and bottom layers of a given alternating oxide / nitride stack, each of the other oxide layers 722 may be sandwiched by two adjacent nitride layers 724, and each of the nitride layers 724 may be sandwiched by two adjacent oxide layers 723.

[0087] The oxide layers may each have the same thickness or have different thicknesses. For example, the thickness of each oxide layer may be in the range of from 10 nm to 100 nm, preferably about 25 nm. Similarly, the nitride layers may each have the same thickness or have different thicknesses. For example, the thickness of each nitride layer may be in the range of from 10 nm to 100 nm, preferably about 35 nm.

[0088] It should be noted that in the present disclosure, the oxide layer 722 and / or the nitride layer 724 may include any suitable oxide material and / or nitride material. For example, the oxide material may include silicide, and the elements of the nitride material may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. In some embodiments, the oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer.

[0089] The dielectric stack structure 720 may include any suitable number of layers of oxide layers 722 and nitride layers 724. In some embodiments, the total number of oxide layers 722 and nitride layers 724 in the dielectric stack structure 720 is equal to or greater than 64. That is, the number of oxide / nitride layer pairs may be equal to or greater than 32. In some embodiments, the alternating oxide / nitride stack 200 includes more oxide layers or more nitride layers having different materials and / or thicknesses than oxide / nitride layer pairs.

[0090] like Figure 7 As shown, a portion of the dielectric stack structure 720 may be removed to form a stepped structure 760 in the stepped region 740. Multiple etching trimming processes may be repeatedly performed to form a set of steps. In some embodiments, each step may include one or more dielectric layer pairs. The insulating structure 750 may be formed to cover a set of steps of the stepped structure 760 and the remaining portion of the dielectric stack structure 720. In some embodiments, the etching trimming process may include a set of repeated etching trimming processes to form the stepped structure 760, and the stepped structure 760 includes a set of steps at the edge of the dielectric stack structure 720.

[0091] Specifically, to form each step, a photoresist layer (not shown) may be used as a mask to expose a portion of the top surface of the dielectric stack structure 720. To form the first step, the width of the exposed top surface of the dielectric stack structure 720 may be the step width. In some embodiments, an anisotropic etching process, such as a reactive ion etching (RIE) process or other suitable dry / wet etching process, may be performed to remove the exposed layer (e.g., the second dielectric layer 724) exposed through the mask (i.e., the photoresist layer). The etching process may stop on the next lower layer (e.g., the first dielectric layer 722). The pattern in the mask (i.e., the photoresist layer) is then transferred to the etched layer (e.g., the second dielectric layer 724). The exposed next lower layer (e.g., the first dielectric layer 722) may then be removed by another etching process that stops on the next lower layer (e.g., the second dielectric layer 724). In this way, a first step may be generated on the first two top layers of the dielectric stack structure 720.

[0092] Next, the size of the mask can be reduced by removing a portion of the mask (i.e., the photoresist layer) above the dielectric stack structure 720 (also referred to as "trimming") (e.g., by an isotropic etching process) to expose another step width of the dielectric stack structure 720. The method can be performed by subjecting the structure to two anisotropic etching processes, the two anisotropic etching processes including removing exposed portions of two exposed layers (e.g., two second dielectric layers 724), and subsequently removing exposed portions of two exposed next lower layers (e.g., first dielectric layer 722). In this way, the first step can be lowered to the third and fourth top layers of the dielectric stack structure 720, and a second step can be generated on the first two top layers of the dielectric stack structure 720.

[0093] In some embodiments, the continuous reduction of the size of the mask (ie, the photoresist layer) and the two-step etching process (also referred to as an etching trimming process) may be repeated so that a stepped structure 760 including a set of steps may be formed in the stepped region 740, such as Figure 7 As shown. The photoresist layer can then be removed. In some embodiments, the removal process can include any suitable etching process and cleaning process. In some embodiments, a sacrificial landing pad 765 can be formed on the exposed top surface of the second dielectric layer 724 of each step. The sacrificial landing pad 765 can be used to form a conductive landing pad in a subsequent process. In some embodiments, the sacrificial landing pad 765 can include any suitable sacrificial material, such as polysilicon, and can be formed by any suitable thin film deposition process.

[0094] like Figure 7As shown, the insulating structure 750 may be formed to cover the step structure 760. In some embodiments, a deposition process may be performed to form the insulating structure 750 to cover the dielectric stack structure 720 including the step structure 760. A chemical mechanical planarization (CMP) process may be performed to planarize the top surface of the insulating structure 750.

[0095] Return to reference Figure 6 , the method 600 may proceed to operation 620 , where a plurality of channel structures may be formed in an array region of the dielectric stack structure. Fig. 8A A schematic diagram of a 3D structure after operation 620 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Figure 8B According to some embodiments of the present disclosure, Fig. 8A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Figure 8C According to some embodiments of the present disclosure, Fig. 8A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0096] like Fig. 8A and 8C As shown, in some embodiments, in operation 620, a plurality of channel structures 850 may be formed in the dielectric stack structure 720. Each channel structure 850 may extend vertically through the dielectric stack structure 720 into the substrate 710. In some embodiments, a plurality of channel structures 850 may be formed in an array form. In some embodiments, the array 850 of channel structures may include multiple rows of channel structures 850. Each row of channel structures 850 may be aligned along the word line direction (X direction). The channel structures 850 of adjacent rows may be misaligned. In some embodiments, the array of channel structures 850 may include multiple columns of channel structures 850. The channel structures 850 of each column may be aligned along the bit line direction (Y direction). The channel structures 850 of adjacent columns may be misaligned.

[0097] In some embodiments, the manufacturing process for forming the plurality of channel structures 850 may include forming a plurality of channel holes (not shown) that penetrate the dielectric stack structure 720. The process for forming the plurality of channel holes may include forming a hard mask layer (not shown) on the dielectric stack structure 720, and coating a photoresist layer (not shown) on the hard mask. A patterning process may be performed to pattern the hard mask layer. Using the hard mask layer as a mask, an etching process may be subsequently performed to etch the dielectric stack structure 720 to form a plurality of channel holes. Each channel hole may completely penetrate the dielectric stack structure 720 and extend into the substrate 710. The etching process for forming the plurality of channel holes may be dry etching, wet etching, or a combination thereof. After the etching process, the photoresist layer and the hard mask layer may be removed.

[0098] A channel structure 850 may be formed in each channel hole in a subsequent process. A plurality of channel structures 850 may be arranged in a staggered array. In some embodiments, each channel structure 850 may include an optional high-k dielectric layer (not shown), a functional layer 810 on the sidewall of the channel hole or covering the high-k dielectric layer, a channel layer 820 covering the functional layer 810, and a filling structure 828 surrounded by the channel layer 820. In some embodiments, the functional layer 810 may include a barrier layer 812, a storage layer 814, and a tunneling layer 816.

[0099] In some embodiments, the manufacturing process for forming the channel structure 850 may include forming an epitaxial layer (not shown) at the bottom of each channel hole. In some embodiments, the epitaxial layer may be a polycrystalline silicon (polysilicon) layer formed by using a selective epitaxial growth (SEG) process. For example, a SEG pre-cleaning process may be performed to clean the plurality of channel holes. A subsequent deposition process may be performed to form a polysilicon layer at the bottom of each channel hole. In some embodiments, any suitable doping process, such as an ion metal plasma (IMP) process, may be performed on the polysilicon layer to form the epitaxial layer. In some embodiments, the epitaxial layer may not be formed directly on the surface of the substrate 710. One or more layers may be formed between the epitaxial layer and the substrate 710. That is, the epitaxial layer overlaps the substrate 710.

[0100] In some embodiments, the manufacturing process of forming the channel structure 850 may include forming a high-k dielectric layer (not shown) on the sidewalls of each channel hole, and forming a functional layer 810 covering the high-k dielectric layer. The functional layer 810 may be a composite dielectric layer, such as a combination of a barrier layer 812, a storage layer 814, and a tunneling layer 816. The high-k dielectric layer, the functional layer 810 including the barrier layer 812, the storage layer 814, and the tunneling layer 816 may be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0101] In some embodiments, a barrier layer 812 and / or a high-k dielectric layer may be formed between the storage layer 814 and the sidewalls of the channel hole. The barrier layer 812 and / or the high-k dielectric layer may be used to block the outflow of electronic charge. In some embodiments, the barrier layer 812 may be a combination of a silicon oxide layer or a silicon oxide / silicon nitride / silicon oxide (silicon oxide / silicon nitride / silicon oxide, ONO) layer. In some embodiments, the high-k dielectric layer includes any suitable high dielectric constant (high-k value) dielectric (e.g., aluminum oxide). In some embodiments, the thickness of the barrier layer 812 and / or the high-k dielectric layer may be in the range of from about 3 nm to about 20 nm.

[0102] The storage layer 814 can be formed between the tunneling layer 816 and the barrier layer 812. Electrons or holes from the channel layer can tunnel to the storage layer 814 through the tunneling layer 816. The storage layer 814 can be used to store electronic charges (electrons or holes) for storage operations. The storage or removal of charge in the storage layer 814 can affect the on / off state and / or conductivity of the semiconductor channel. The storage layer 814 may include one or more material films, including but not limited to silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride or any combination thereof. In some embodiments, the storage layer 814 may include a nitride layer formed by using one or more deposition processes. In some embodiments, the thickness of the storage layer 814 may be in the range of from about 3nm to about 20nm.

[0103] The tunneling layer 816 may be formed on the sidewalls of the storage layer 814. The tunneling layer may be used to tunnel electronic charges (electrons or holes). The tunneling layer 816 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer 816 may be an oxide layer formed using a deposition process. In some embodiments, the thickness of the tunneling layer 816 may be in a range from about 3 nm to about 20 nm.

[0104] In some embodiments, the manufacturing process of forming the channel structure 850 further includes forming a channel layer 820 covering the sidewalls of the functional layer 810. In some embodiments, the channel layer 820 may be an amorphous silicon layer or a polycrystalline silicon layer formed by using a thin film deposition process, such as ALD, CVD, PVD, or any other suitable process. In some embodiments, the thickness of the channel layer 820 may be in a range from about 5 nm to 20 nm.

[0105] In some embodiments, the manufacturing process of forming the channel structure 850 further includes forming a filling structure 828 to cover the channel layer 820 and fill the channel hole. In some embodiments, the filling structure 828 can be an oxide layer formed by using any suitable deposition process, such as ALD, CVD, PVD, etc. In some embodiments, the filling structure 828 can include one or more air gaps (not shown).

[0106] Return to reference Figure 6 , the method 600 may then proceed to operation 630 , in which a plurality of vias may be formed in the array region and the step region of the dielectric stack structure, and a plurality of sacrificial filling structures may be formed in the plurality of vias. Fig. 8A A schematic diagram of a 3D structure after forming a plurality of vias at operation 630 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Figure 8B According to some embodiments of the present disclosure, Fig. 8A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Figure 8C According to some embodiments of the present disclosure, Fig. 8A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig.9A A schematic diagram of a 3D structure after forming a plurality of sacrificial fill structures at operation 630 is shown in a top down perspective view, in accordance with some embodiments of the present disclosure. Fig. 9B According to some embodiments of the present disclosure, Fig.9A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 9C According to some embodiments of the present disclosure, Fig.9A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0107] like Figures 8A-8CAs shown, in operation 630, a plurality of through holes 830 may be formed in the array region 730 and the step region 740 of the dielectric stack structure 720. In some embodiments, the plurality of through holes 830 may include first through holes 834 that are laterally aligned along the word line direction (X direction), and each through hole extends vertically through the dielectric stack structure 720. In some embodiments, the first through hole 834 may be located in the array region 730 and the step region 740. In some embodiments, the plurality of through holes 830 may also include a second through hole 836 located in the step structure. In some embodiments, the second through hole 836 may penetrate the corresponding sacrificial landing pad 765. In some embodiments, the first through hole 834 and the second through hole 836 may be formed simultaneously. In some embodiments, the first distance between adjacent first through holes 834 may be less than the second distance between adjacent second through holes 836.

[0108] The process of forming multiple through holes 830 may include forming a hard mask layer (not shown) on the dielectric stack structure 720, and coating a photoresist layer (not shown) on the hard mask. A patterning process may be performed to pattern the hard mask layer. Using the hard mask layer as a mask, an etching process may be subsequently performed to etch the dielectric stack structure 720 to form multiple through holes 830. Each of the multiple through holes 830 may completely penetrate the dielectric stack structure 720 and extend into the substrate 710. The etching process for forming multiple through holes 830 may be dry etching, wet etching, or a combination thereof. After the etching process, the photoresist layer and the hard mask layer may be removed. In some embodiments, the multiple through holes 830 and the channel holes formed in operation 610 may be formed in the same patterning process by using a single mask.

[0109] like Figures 9A-9C As shown, a plurality of sacrificial filling structures 930 can be formed in the through-hole 830. In some embodiments, a deposition process can be performed to fill the through-hole 830, including the first through-hole 834 and the second through-hole 836, with any suitable sacrificial material (e.g., a carbon-based material) to form the sacrificial filling structure 930. It should be noted that the sacrificial material of the sacrificial filling structure 930 can have a sufficiently high etching selectivity relative to the material of the first dielectric layer 722 and the second dielectric layer 724, so that a subsequent etching process of the sacrificial filling structure 930 can have minimal impact on the first dielectric layer 722 and the second dielectric layer 724.

[0110] Return to reference Figure 6 The method proceeds to operation 640 where the sacrificial fill structure may be removed from the first subset of vias and a plurality of dummy contact structures may be formed in the first subset of vias. Fig. 10AA schematic diagram of the 3D structure after removal of the sacrificial fill structure at operation 640 is shown in a top down perspective view, in accordance with some embodiments of the present disclosure. Fig. 10B According to some embodiments of the present disclosure, Fig. 10A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 10C According to some embodiments of the present disclosure, Fig. 10A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig.11A A schematic diagram of a 3D structure after forming a dummy contact structure at operation 640 is shown in a top-down perspective view, according to some embodiments of the present disclosure. Fig. 11B According to some embodiments of the present disclosure, Fig.11A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 11C According to some embodiments of the present disclosure, Fig.11A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0111] like Figures 10A-10C As shown, the sacrificial filling structure 930 can be removed from the first subset of the first through holes 1034 and the second through hole 836. The sacrificial filling structure 930 in the first subset of the first through holes 1034 and the second through hole 836 can be removed by using any suitable etching process, such as an isotropic dry etching or a wet etching process. The etching process can have a sufficiently high etching selectivity to the sacrificial material of the sacrificial filling structure 930 relative to the material of the first dielectric layer 722 and the second dielectric layer 724, so that the etching process can have minimal impact on the first dielectric layer 722 and the second dielectric layer 724. In this way, the first subset of the first through holes 1034 and the second through hole 836 can be re-formed.

[0112] like Fig. 10B and 10C As shown, a subsequent recess etching process may then be performed to remove portions of the second dielectric layer 724 exposed by the sidewalls of the second vias 836 and the first subset of the first vias 1034. It should be noted that since the first distance between adjacent first vias 1034 is relatively small, the second dielectric layer 724 between the re-formed first subset of the first vias 1034 may be completely removed to form a plurality of transverse trenches 1045 that interconnect the first subset of the first vias 1034, as shown in FIG. Fig. 10BIt should also be noted that since the second distance between adjacent second through holes 836 is relatively large, the second dielectric layer 724 between the re-formed second through holes 1034 can be partially removed to form a plurality of lateral recesses 1055. Fig. 10C As shown, adjacent second through holes 1034 are not interconnected with each other.

[0113] like Figures 11A-11C As shown, a plurality of dummy contact structures 1130 may be formed in the first subset of the first through-holes 1034 and the second through-holes 836. In some embodiments, the plurality of dummy contact structures 1130 may include a plurality of first dummy contact structures 1134 formed in the first subset of the first through-holes 1034, and a plurality of second dummy contact structures 1136 formed in the second through-holes 836. In some embodiments, the first dummy contact structures 1134 and the second dummy contact structures 1136 are simultaneously formed in the first subset of the first through-holes 1034 and the second through-holes 836. In some embodiments, forming the plurality of dummy contact structures 1130 (including the first dummy contact structures 1134 and the second dummy contact structures 1136) may include forming a first insulating layer 1137 in the lateral trenches 1045 and the lateral recesses 1055 and on the sidewalls of the first subset of the first through-holes 1034 and the second through-holes 836. In some embodiments, the first insulating layer 1137 may include any suitable dielectric material (e.g., an oxide material) and may be formed by any suitable thin film deposition process. In some embodiments, forming the plurality of dummy contact structures 1130 may further include forming a via structure 1133 on the first insulating layer 1137 to fill the first subset of the first through holes 1034 and the second through holes 836. In some embodiments, the via structure 1133 may include any suitable filling material (e.g., polysilicon) and may be formed by any suitable thin film deposition process.

[0114] It should be noted that in some embodiments not shown in the figures, a plurality of dummy channel structures may be located in the step region 740 to replace the second dummy contact structure 1136. In such embodiments, the dummy channel structure may be formed simultaneously with the formation of the channel structure 850. The second dummy contact structure 1136 or the dummy channel structure may provide a support function for the step region 740 of the formed 3D structure.

[0115] Return to reference Figure 6 , the method proceeds to operation 650, in which the sacrificial fill structure can be removed from the second subset of vias, a plurality of gate line slits (GLS) can be formed in the dielectric stack structure, and the second dielectric layer in the dielectric stack structure can be removed. Fig. 12AA schematic diagram of a 3D structure after operation 650 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 12B According to some embodiments of the present disclosure, Fig. 12A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 12C According to some embodiments of the present disclosure, Fig. 12A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0116] like Fig. 12A and 12B As shown, the sacrificial filling structures 930 in the remaining first through holes 834 except the first subset of the first through holes 1034 and the portion of the dielectric stack structure 720 adjacent to the sacrificial filling structures 930 may be removed to form a plurality of gate line slits (GLS) 1230. Each of the plurality of GLSs 1230 may extend vertically through the dielectric stack structure 720 into the substrate 710. In some embodiments, the first dummy contact structure 1134 is located between the GLSs 1230, and the first dummy contact structure 1134 and the GLSs 1230 are laterally aligned in a straight line along the word line direction (X direction).

[0117] In some embodiments, a plurality of GLS 1230 may be formed by forming a mask layer (not shown) over the dielectric stack structure 720 and patterning the mask using, for example, photolithography to form openings corresponding to the remaining sacrificial fill structures 930 in the remaining first through holes 834. A suitable etching process, such as dry etching and / or wet etching, may be performed to remove the remaining sacrificial fill structures 930 and portions of the dielectric stack structure 720 exposed by the openings until the plurality of GLS 1230 exposes the substrate 710, as shown. Fig. 12B As shown. The mask layer can be removed after forming multiple GLS1230. In some embodiments, a doped region (not shown) can be formed at the bottom of each GLS1230 in the substrate 710 by using any suitable doping process, such as ion implantation and / or thermal diffusion of GLS1230. The dopant in the doped region can be any suitable N+ or P+ ion. After forming a conductive wall in GLS1230 in a subsequent process, the lower end of each conductive wall can contact the corresponding doped region.

[0118] In some embodiments, the second dielectric layer 724 (eg, silicon nitride) and the sacrificial landing pad 765 of the dielectric stack structure 720 may be removed via the GLS 1230. Fig. 12CIn some embodiments shown, after forming a plurality of GLS 1230, the second dielectric layer 724 in the dielectric stack structure 720 can be removed through the GLS 1230 to form a plurality of transverse grooves 1224. The plurality of transverse grooves 1224 can extend in a lateral direction and can be used as spaces for conductive layers to be formed in subsequent processes. In some embodiments, the sacrificial landing pad 765 on each step of the step structure 760 can also be removed to form a landing area opening 1265.

[0119] The second dielectric layer 724 and the sacrificial landing pad 765 in the dielectric stack structure 720 are both used as sacrificial layers and are removed using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process can have a sufficiently high etching selectivity to the material of the second dielectric layer 724 and / or the sacrificial landing pad 765 relative to the material of the first dielectric layer 722, so that the etching process can have minimal impact on the first dielectric layer 722. The isotropic dry etching and / or wet etching and subsequent cleaning process can remove the second dielectric layer 724 and the sacrificial landing pad 765 in various directions to expose the top and bottom surfaces of each first dielectric layer 722. In this way, a plurality of lateral grooves 1224 can be formed between the first dielectric layers 722, and landing area openings 1265 can be formed on the steps of the stepped structure.

[0120] Return to reference Figure 6 , the method proceeds to operation 660, in which a plurality of conductive layers may be formed in the lateral trench, a plurality of landing conductive layers may be formed in the landing area opening, and a plurality of gate line gap structure segments may be formed in the gate line gap (GLS). Fig.13A A schematic diagram of a 3D structure after operation 660 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 13B According to some embodiments of the present disclosure, Fig.13A Schematic diagram of a portion of the 3D structure in a cross-sectional side view along line AA' shown in FIG. Fig. 13C According to some embodiments of the present disclosure, Fig.13A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0121] like Fig.13A and 13CAs shown, a plurality of conductive layers 1324 may be formed in the lateral trenches 1224, and a plurality of landing conductive layers 1365 may be formed in the landing area openings 1265. In this way, the dielectric stack structure 720 may be converted into a memory stack structure 1320 including a plurality of conductive / dielectric layer pairs. In some embodiments, a gate replacement process (also referred to as a "word line replacement" process) may be performed to replace the second dielectric layer 724 (e.g., silicon nitride) of the dielectric stack structure 720 with the conductive layer 1324. In some embodiments, the plurality of conductive layers 1324 may be used as word lines (i.e., gate electrodes) in a 3D memory device.

[0122] In some embodiments, each conductive layer 1324 may be coated with one or more insulating layers (not shown) that serve as a gate dielectric layer for insulating the corresponding word line (i.e., gate electrode). In some embodiments, one or more insulating layers (not shown) may be formed in each of the plurality of lateral grooves 1224 to cover the exposed surface of the lateral grooves 1224 with one or more suitable insulating materials. For example, one or more suitable deposition processes, such as CVD, PVD, and / or ALD, may be used to deposit one or more insulating materials into the lateral grooves 1224. In some embodiments, recess etching and / or CMP processes may be used to remove excess insulating materials (single or multiple). The one or more insulating materials may include any suitable material (e.g., a high-k dielectric) that provides an electrical insulation function. For example, the one or more insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium nitride, etc., and / or any suitable combination thereof. In some embodiments, the plurality of insulating layers may have different insulating materials.

[0123] Conductive layer 1324 can be formed in each lateral groove 1224 between one or more insulating layers. Conductive layer 1324 can be formed by filling lateral groove 1224 with a suitable gate electrode metal material. Conductive layer 1324 can provide a base material for a subsequently formed word line (i.e., a gate electrode). The gate electrode metal material may include any suitable conductive material for forming a word line (i.e., a gate electrode), such as tungsten, aluminum, copper, cobalt, or any combination thereof. A suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD, can be used to deposit the gate electrode material into the lateral groove. In some embodiments, conductive layer 1324 may include tungsten formed by CVD. In this way, dielectric stack structure 720 is converted into a stack structure 1320 including alternating conductive / dielectric layers.

[0124] The landing conductive layer 1365 can be formed on the top exposed surface of the conductive layer 1324 on the corresponding step of the step structure. In some embodiments, the landing conductive layer 1365 can be used to increase the contact area of ​​the word line contact formed in a subsequent process. In some embodiments, the landing conductive layer 1365 may include any suitable conductive material for forming a word line (i.e., a gate electrode), such as tungsten, aluminum, copper, cobalt, or any combination thereof. The gate electrode material can be deposited into the lateral groove using a suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD. In some embodiments, the conductive layer 1324 may include tungsten formed by CVD.

[0125] like Figures 13A-13B , a plurality of GLS structure segments 1370 may be formed in the GLS 1230. In some embodiments, the manufacturing process for forming the GLS structure segments 1370 may include forming a second insulating layer 1373 on the sidewalls of the plurality of GLSs 1230. The second insulating layer 1373 is also referred to as a gate line spacer (GLSP) layer and may be used to provide electrical insulation between the plurality of conductive layers 1324 and a conductive wall formed in a subsequent process.

[0126] In some embodiments, the manufacturing process for forming the second insulating layer 1373 may include a word line gate recess process. After forming the plurality of conductive layers 1324, portions of the plurality of conductive layers 1324 (word lines) exposed by the GLS 1230 may be removed by a recess etching process. In some embodiments, in order to ensure insulation between the plurality of conductive layers 1324 (word lines), a recess etching process, such as a wet etching process, may be performed to remove portions of the plurality of conductive layers 1324 exposed by the GLS 1230. In doing so, a recess may be formed in each lateral trench adjacent to the GLS 1230.

[0127] In some embodiments, the second insulating layer 1373 may have a laminated structure (not shown) including two or more spacer sublayers formed by using any suitable deposition process (e.g., atomic layer deposition (ALD) process). For example, the second insulating layer 1373 may include a first spacer sublayer (not shown) covering the sidewalls of GLS1230 and the exposed surfaces of the multiple gate structures. The first spacer sublayer may include a low-temperature oxide material, such as silicon oxide, which is configured to prevent the multiple conductive layers 1324 from being oxidized in subsequent processes. The second insulating layer 1373 may also include a second spacer sublayer (not shown) to cover the first spacer sublayer. The second spacer sublayer may include a high-k value material, such as silicon nitride. This laminated structure can effectively increase the equivalent oxide thickness (EOT) of the second insulating layer 1373, thereby improving the isolation performance of the second insulating layer 1373.

[0128] In some embodiments, the manufacturing process for forming the GLS structure segment 1370 may include forming a conductive wall 1375 in each GLS 1230. The conductive wall 1375 may contact a doped region (not shown) in the substrate 710 and serve as an array common source (ACS) for multiple NAND strings. In some embodiments, the conductive wall 1375 may be formed by depositing a conductive material, such as polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof. The conductive material may be deposited into the multiple GLS 1230 using a suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD. A subsequent CMP process may be performed to planarize the top surface of the formed 3D structure.

[0129] Return to reference Figure 6 The method proceeds to operation 670, where the plurality of second dummy contacts in the step region may be removed to form a plurality of third through holes, and a plurality of contact structures may be formed in the plurality of third through holes. Fig.13A A schematic diagram of the 3D structure after removing the second dummy contact at operation 670 is shown in a top perspective view according to some embodiments of the present disclosure.

[0130] Fig. 13C According to some embodiments of the present disclosure, Fig.13A Schematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG. Fig.14A A schematic diagram of a 3D structure after operation 670 is shown in a top-down perspective view, in accordance with some embodiments of the present disclosure. Fig. 14B According to some embodiments of the present disclosure, Fig.14ASchematic diagram of a portion of the 3D structure in a cross-sectional side view of line BB' shown in FIG.

[0131] like Fig.13A and 13C As shown, in some embodiments, forming the contact structure may include removing the plurality of second dummy contacts 1136 in the step region 740 to form a plurality of third through holes 1333. For example, one or more suitable etching processes, such as dry etching and / or wet etching, may be performed to remove a subset of the second dummy contacts 1136 to form a plurality of third through holes 1333. In some embodiments, the plurality of third through holes 1333 may extend and penetrate the storage stack structure 1320. A mask layer (not shown) may be used to control the shape of the third through holes 1333 during the etching process. Fig. 13C In some embodiments shown, the landing conductive layer 1365 can be exposed through the third via hole 1333 without removing the first insulating layer 1137 during the etching process. The mask layer can be removed after the third via hole 1333 is formed.

[0132] like Fig.14A As shown, a plurality of contact structures 1433 may be formed in the plurality of third through holes 1333. Fig. 14B As shown, the contact structure 1433 may include a conductive via that is in direct contact with the corresponding landing conductive layer 1365 and is isolated from the other conductive layers 1324 of the storage stack structure 1320 by the first insulating layer 1137. The contact structure 1433 can be used as a word line contact. The contact structure 1433 can be formed by filling the third through hole 1333 with any suitable conductive material, and the conductive material is, for example, tungsten, aluminum, copper, cobalt, or any combination thereof. A suitable deposition method, such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD, can be used to deposit the conductive material into the third through hole 1333. In some embodiments, the contact structure 1433 may include tungsten formed by CVD.

[0133] Therefore, a 3D memory device and a manufacturing method are provided. Based on the GLS extension process, the patterning process of the channel hole, the GLS opening and the through hole can be merged into a single mask. By eliminating the traditional long GLS isolation structure, a storage finger support portion can be designed between the GLS structure segments. The dummy contact structure can be used as a storage finger support portion and can be formed in the same process as the contact structure. And the isolation function can be achieved by the silicon nitride recess process and the oxide deposition process, and is realized together with the short GLS structure segment.

[0134] Since there is no long GLS passing through the entire plane, the risk of structural instability due to stress can be suppressed by using short GLS structural segments and storage finger support portions. The filling oxide and polysilicon materials in the short GLS structural segments and storage finger support portions can significantly reduce device defects, including storage finger bending / collapse and / or wafer bow effect. In addition, by merging the contact formation process and the GLS structure formation process, the application of the photolithography process can be reduced, thereby reducing the process difficulty and production cost. In summary, the present disclosure can solve the manufacturing problems caused by structural stress, thereby breaking through the technical bottleneck in the research and development of higher-level 3D memory devices.

[0135] The foregoing description of the specific embodiments will fully reveal the general nature of the present disclosure, so that others can easily modify and / or adapt to various applications of such specific embodiments without departing from the overall concept of the present disclosure and without excessive experimentation by applying knowledge within the technical scope of the art. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation, so that the terms or wording of this specification will be interpreted by those skilled in the art based on teaching and guidance.

[0136] The embodiments of the present disclosure have been described above by means of functional building blocks that illustrate the embodiments of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined here. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0137] The Summary and Abstract sections may set forth one or more but not all embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0138] The breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A stacked structure comprising alternating conductive and dielectric layers; as well as a gate line structure extending vertically through the stack structure and extending laterally along a first lateral direction to divide the stack structure into storage fingers, the gate line structure comprising: The gate line gap structure segments are aligned along the first transverse direction; as well as At least one first dummy contact structure is located between adjacent gate line gap structure segments in the first lateral direction.

2. The semiconductor device according to claim 1, wherein: The at least one first dummy contact structure is located in the array region or the step region.

3. The semiconductor device according to claim 2, wherein: There are a plurality of first dummy contact structures located between two adjacent gate line gap structure segments along the first lateral direction.

4. The semiconductor device according to claim 3, further comprising: a second dummy contact structure in the step region; Wherein, a first distance between adjacent first dummy contact structures is smaller than a second distance between adjacent second dummy contact structures.

5. The semiconductor device according to claim 4, wherein: Each of the first dummy contact structure and the second dummy contact structure comprises a via structure, the via structure being insulated from the conductive layer of the stacked structure by a spacer layer; and A thickness of the spacer layer of the first dummy contact structure is substantially equal to a thickness of the spacer layer of the second dummy contact structure.

6. The semiconductor device according to claim 4, further comprising: The gate line contact structure vertically extends in the step region.

7. The semiconductor device according to claim 6, wherein: Each gate line gap structure segment comprises a wall structure extending laterally in the first lateral direction and insulated from the conductive layer of the stacked structure; and Each gate line contact structure includes a conductive via and is electrically connected to a corresponding conductive layer of the stacked structure.

8. The semiconductor device according to claim 7, wherein: The conductive via contacts a landing conductive layer on the corresponding conductive layer and is insulated from other conductive layers below the corresponding conductive layer.

9. The semiconductor device according to claim 1, wherein: A width of the gate line gap structure segment in a second lateral direction orthogonal to the first lateral direction is substantially equal to a width of the first dummy contact structure in the second lateral direction.

10. The semiconductor device according to claim 6, further comprising: The channel structures all extend vertically in the array region of the stacked structure.

11. A method for forming a semiconductor device, comprising: forming a dielectric stack comprising alternating sacrificial layers and dielectric layers; forming first through holes that are laterally aligned along a first lateral direction and each extend vertically through the dielectric stack; forming a sacrificial filling structure in the first through hole; removing the sacrificial fill structure from a first subset of the first through holes; forming a first dummy contact structure in the first subset of the first through holes; removing the sacrificial fill structure from a second subset of the first through holes to form gate line gaps, wherein the first dummy contact structure is located between the gate line gaps, and the first dummy contact structure and the gate line gaps are laterally aligned in the first lateral direction; as well as A gate line gap structure segment is formed in the gate line gap.

12. The method according to claim 11, further comprising: forming a stepped structure on one side of the dielectric stack; forming a second through hole in the stepped structure; forming a sacrificial filling structure in the second through hole; removing the sacrificial fill structure from the second through hole; and A second dummy contact structure is formed in the second through hole.

13. The method according to claim 12, wherein: The first through hole and the second through hole are formed simultaneously; The sacrificial filling structure is formed in both the first through hole and the second through hole; removing the sacrificial fill structure from the first subset of the first vias and the second vias simultaneously; and The first dummy contact structure and the second dummy contact structure are simultaneously formed in the first subset of the first through-holes and the second through-holes.

14. The method according to claim 12, wherein: Forming the first dummy contact structure and the second dummy contact structure includes: removing portions of the sacrificial layer exposed by the first subset of the first through-holes and the second through-holes to form lateral recesses between the dielectric layers, such that adjacent first through-holes in each first subset are interconnected with each other through the lateral recesses; forming a first insulating layer in the lateral recess and sidewalls of the first subset of the first vias and the second vias; and A via structure is formed on the first insulating layer to fill the first subset of the first through holes and the second through hole.

15. The method according to claim 14, further comprising: removing the sacrificial layer through the gate line gaps to form lateral openings between the dielectric layers; as well as A conductive layer is formed in the lateral opening.

16. The method according to claim 15, wherein: Forming the gate line gap structure segment includes: removing a portion of the dielectric layer exposed by the gate line gap; forming a second insulating layer on the sidewalls and bottom of the gate line gap; and A wall structure is formed on the second insulating layer to fill the gate line gap.

17. The method according to claim 16, further comprising: removing a portion of the second dummy contact structure to form a third through hole; as well as A gate line contact structure is formed in the third through hole.

18. The method of claim 17, wherein: Forming the stepped structure includes forming a landing conductive layer on each step of the stepped structure; Forming the third through hole includes exposing the landing conductive layer; and Forming the gate line contact structure includes forming a conductive via in the third through hole to contact the landing conductive layer.

19. The method according to claim 11, further comprising: Channel structures are formed that each extend vertically in an array region of the dielectric stack.

20. A storage device comprising: A stacked structure comprising alternating conductive and dielectric layers; The channel structures all extend vertically in the array region of the stacked structure; a gate line structure extending vertically through the stack structure and extending laterally along a first lateral direction to divide the stack structure into storage fingers, the gate line structure comprising: Gate line gap structure segments are aligned along the first lateral direction; and first dummy contact structures, aligned closely to each other along the first lateral direction and located between the gate line gap structure segments in the first lateral direction; second dummy contact structures that are discretely aligned with each other and located in a step region of the stacked structure; and A gate line contact structure extends vertically in the step region of the stacked structure.

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