Semiconductor device and preparation method thereof
By first forming Floating Gate (FG) in the flash chip manufacturing process, then forming Control Gate (CG), and dielectric layer deposition is performed after the CG is finally formed, the complex formation sequence of CG and FG in the existing process is solved, the process is simplified and production efficiency is improved.
Patent Information
- Application Number
- CN202311526335.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-15
- Publication Date
- 2025-05-16
AI Technical Summary
In the existing flash chip manufacturing processes, the molding sequence of Control Gate (CG) and Floating Gate (FG) is complex, resulting in cumbersome processes and low production efficiency.
Floating Gate (FG) is formed on the substrate, then Control Gate (CG) is formed, and a dielectric layer is deposited after the final formation of CG to protect the GATE sidewalls, simplifying the manufacturing process.
By changing the forming order of CG and FG, the manufacturing process is simplified and the production efficiency is improved. The size of the inter-hole distance of the FG can be controlled by yellow light, and the thickness and size are better controlled.
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Figure CN120018510A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for preparing the same. Background Art
[0002] Flash memory chips, such as NOR Flash (also known as NOR flash memory) chips, are the media for storing final data. NOR Flash is actually an EEPOM (power-erasable programmable ROM). The most basic component unit is called a cell, and a cell is an electronic component similar to a MOSFET (metal-oxide semiconductor field-effect transistor). The main parts are the Control Gate (CG for short) and the Floating Gate (FG for short). The function of CG is to charge and discharge FG by applying different voltages to change the bits stored in the cell. FG is an oxide layer that is insulated from the surroundings. Electrons can be stored in FG for a long time without being easily leaked. This is also the reason why NOR Flash chips store non-volatile data.
[0003] In the related art, CG and FG are usually formed by first forming CG through an etching process, then forming a dielectric protection layer on the side wall of CG and defining an FG mask, and then forming FG, and finally forming a dielectric layer to protect the GATE side wall. It is necessary to deposit the side wall dielectric protection layer twice, and the process is relatively complicated. Summary of the invention
[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for preparing the same. In the method, FG is first formed on a substrate and then CG is formed. Compared with the existing technology, the forming order of CG and FG is changed. A dielectric layer can be deposited after the CG is finally formed to protect the GATE side wall, thereby simplifying the manufacturing process and improving production efficiency.
[0005] In order to achieve the above-mentioned object, the present disclosure provides a first aspect of a method for preparing a semiconductor device, comprising:
[0006] A channel oxide layer, a FG polysilicon layer, an ONO dielectric layer, a CG polysilicon layer, an oxide layer and a silicon nitride layer are sequentially formed on the substrate;
[0007] Using a first mask, sequentially etching the silicon nitride layer, the oxide layer, the CG polysilicon layer, the ONO dielectric layer and the FG polysilicon layer to form FG;
[0008] The first mask is removed, and the silicon nitride layer, the oxide layer, the CG polysilicon layer and the ONO dielectric layer are sequentially etched using the second mask to form a CG.
[0009] Optionally, the gap of the CG is larger than the gap of the FG.
[0010] Optionally, the method further comprises:
[0011] A sidewall layer is formed on the sidewalls of the CG and the FG.
[0012] Optionally, the sidewall layer is formed by a layer-by-layer deposition process or a chemical vapor deposition process.
[0013] Optionally, the sidewall layer is an oxide layer-nitride layer structure.
[0014] Optionally, the step of sequentially etching the silicon nitride layer, the oxide layer, the CG polysilicon layer, the ONO dielectric layer and the FG polysilicon layer using a first mask to form the FG layer comprises:
[0015] forming a mask layer on the silicon nitride layer;
[0016] Coating a first photoresist on the mask layer and patterning the first photoresist;
[0017] The first mask is formed on the mask layer by patterning the first photoresist.
[0018] Optionally, the method further comprises:
[0019] forming an anti-reflection layer on the mask layer;
[0020] coating the first photoresist on the anti-reflection layer;
[0021] The first photoresist is patterned using yellow light.
[0022] Optionally, the anti-reflection layer includes a first anti-reflection layer and a second anti-reflection layer.
[0023] Optionally, removing the first mask and sequentially etching the silicon nitride layer, the oxide layer, the CG polysilicon layer and the ONO dielectric layer using a second mask to form a CG comprises:
[0024] Covering the gap between the silicon nitride layer and the FG with a third anti-reflection layer, and coating the first anti-reflection layer with a second photoresist;
[0025] The second photoresist is patterned, and the patterned second photoresist forms a second mask.
[0026] According to a second aspect of the present disclosure, there is further provided a semiconductor device, which is manufactured by using the method for manufacturing a semiconductor device as described in any one of the first aspects of the present disclosure.
[0027] Through the above technical solution, that is, the method for preparing the semiconductor device disclosed in the present invention, a channel oxide layer, a FG polysilicon layer, an ONO dielectric layer, a CG polysilicon layer, an oxide layer and a silicon nitride layer are first formed on a substrate, and then the silicon nitride layer, the oxide layer, the CG polysilicon layer, the ONO dielectric layer and the FG polysilicon layer are sequentially etched using a first mask to form an FG, and then the silicon nitride layer, the oxide layer, the CG polysilicon layer and the ONO dielectric layer are sequentially etched using a second mask to form a CG. Through the above method, that is, FG is first formed on a substrate and then CG is formed. Compared with the current technology, the forming order of CG and FG is changed, and the dielectric layer can be deposited after the CG is finally formed to protect the GATE sidewall, simplifying the manufacturing process and improving production efficiency.
[0028] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0030] Figures 1 to 6 It is a schematic cross-sectional structure diagram of the manufacturing process of the storage cell areas CG and FG of a semiconductor device in the related art.
[0031] Figure 7 is a flow chart of a method for preparing a semiconductor device provided by an exemplary embodiment of the present disclosure.
[0032] Figures 8 to 12 It is a schematic cross-sectional structure diagram of the manufacturing process of the memory cell regions CG and FG of the semiconductor device provided in some embodiments of the present disclosure.
[0033] Description of Reference Numerals
[0034] 10-substrate; 11-channel oxide layer; 12-FG polysilicon layer; 13-ONO dielectric layer; 14-CG polysilicon layer; 15-oxide layer; 16-silicon nitride layer; 21-mask layer; 22-first anti-reflection layer; 23-second anti-reflection layer; 231-third anti-reflection layer; 24-first photoresist; 241-second photoresist; 30-sidewall layer; 30a-first sidewall layer; 30b-second sidewall layer; 31-nitride layer; 32-oxide layer. DETAILED DESCRIPTION
[0035] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0036] In the present disclosure, unless otherwise stated, directional words such as "inside" and "outside" refer to the inside and outside of the outline of a component or structure itself. "First" and "second" are used to distinguish one element from another and do not have order or importance. In addition, in the description with reference to the drawings, the same mark in different drawings represents the same element.
[0037] Figures 1 to 6 The cross-sectional structure schematic diagram of the manufacturing process of the storage unit areas CG and FG of the semiconductor device in the related art is shown. The semiconductor device may be a NOR Flash (also known as a NOR type flash memory) chip.
[0038] Among them, Figure 1 As shown, a channel oxide layer 11, a FG polysilicon layer 12, an ONO dielectric layer 13, a CG polysilicon layer 14, an oxide layer 15 and a silicon nitride layer 16 are sequentially formed on a substrate 10, and then a mask layer 21 (including an APF layer, a DARC+OX layer and a BARC layer) is coated on the silicon nitride layer 16, and a first photoresist 24 is coated on the mask layer 21, and then the first photoresist 24 is patterned, and the mask layer 21, the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 are sequentially etched with the patterned first photoresist 24 to form a CG.
[0039] Next, if Figure 2 As shown, a first sidewall layer 30 a is formed on both sides of each CG. The first sidewall layer 30 a may be an oxide layer-nitride layer (ON) structure, that is, an oxide layer 32 and a nitride layer 31 .
[0040] like Figure 3 As shown, a first photoresist 24 is coated on the sidewall layer between CG and CG to expose the first sidewall layer 30a outside the CG, and the first sidewall layer 30a outside the CG is etched to form Figure 4 The structure shown.
[0041] like Figure 5 As shown, the FG polysilicon layer 12 is etched using the first sidewall layer 30a and CG as masks to form FG.
[0042] As shown in FIG6 , a second sidewall layer 30 b is formed on the sidewalls of CG and FG to protect the sidewall of Gate.
[0043] From the above, it can be seen that the entire process is LELEE, which requires the formation of two sidewall layers, and the CD thickness of FG is difficult to control.
[0044] Based on this, Figure 7 As shown, an embodiment of the present disclosure provides a method for preparing a semiconductor device, the method comprising steps S110 to S130:
[0045] In step S110 , a channel oxide layer 11 , a FG polysilicon layer 12 , an ONO dielectric layer 13 , a CG polysilicon layer 14 , an oxide layer 15 and a silicon nitride layer 16 are sequentially formed on the substrate 10 .
[0046] In step S120, the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14, the ONO dielectric layer 13 and the FG polysilicon layer 12 are sequentially etched using a first mask to form FG.
[0047] In step S130, the first mask is removed, and the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 are sequentially etched using the second mask to form a CG.
[0048] Through the above technical solution, i.e., the method for preparing the semiconductor device disclosed in the present invention, a channel oxide layer 11, a FG polysilicon layer 12, an ONO dielectric layer 13, a CG polysilicon layer 14, an oxide layer 15 and a silicon nitride layer 16 are first formed on a substrate 10, and then the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14, the ONO dielectric layer 13 and the FG polysilicon layer 12 are sequentially etched using a first mask to form FG, and then the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 are sequentially etched using a second mask to form CG. Through the above method, i.e., FG is first formed on the substrate 10 and then CG is formed. Compared with the current technology, the forming order of CG and FG is changed, and the dielectric layer can be deposited after the CG is finally formed to protect the GATE sidewall, simplifying the manufacturing process and improving production efficiency.
[0049] It should be noted that step S110 is a prior art and can be constructed using a process known in the relevant art, which will not be described in detail here.
[0050] In some other embodiments, the gap L1 of CG is larger than the gap L2 of FG. The gap L1 between two adjacent CGs is larger than the gap L2 between two adjacent FGs, that is, the width of CG in the Y direction is smaller than the width of FG in the Y direction, which can increase the electric field between FG and EG, speed up the charge transfer, and thus improve the erasing efficiency of FG.
[0051] In yet another embodiment, the method further comprises:
[0052] A sidewall layer 30 is formed on the sidewalls of CG and FG.
[0053] The step of forming the sidewall layer 30 on the sidewalls of CG and FG is performed after forming CG, and is used to protect the sidewalls of CG and FG, and at the same time, to isolate FG and EG.
[0054] In this embodiment, the sidewall layer 30 is formed after forming CG and FG, and then EG is formed between the two sidewall layers 30. Compared with the process of forming the sidewall layer 30 twice in the related art, the process steps are reduced and the manufacturing efficiency is improved.
[0055] The sidewall layer 30 may be formed by any suitable process. In some embodiments, the sidewall layer 30 may be formed by a layer-by-layer deposition process or a chemical vapor deposition process.
[0056] It is understood that the sidewall layer 30 may be in any suitable structural form, for example, the sidewall layer 30 is an oxide layer-nitride layer (ON) structure, that is, the sidewall layer 30 may be a nitride layer 31 attached to the CG and FG and an oxide layer 32 located outside the nitride layer 31. Of course, the sidewall layer 30 may also be an oxide layer 32 structure.
[0057] In another embodiment, the step of sequentially etching the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14, the ONO dielectric layer 13 and the FG polysilicon layer 12 using a first mask to form the FG includes:
[0058] A mask layer 21 is formed on the silicon nitride layer 16 .
[0059] A first photoresist 24 is coated on the mask layer 21 , and the first photoresist 24 is patterned.
[0060] A first mask is formed on the mask layer 21 by patterning the first photoresist 24 .
[0061] Among them, APF2000A can be coated on the silicon nitride layer 16 to form a mask layer 21. APF2000A is a hard mask with excellent material and can be used to transfer patterns. It is an organic layer rich in carbon and has a hard material. It has a high selectivity for the underlying silicon nitride layer 16 (SiN film). Among them, 2000A represents the thickness of APF.
[0062] It should be noted that the first photoresist 24 can be PR1000A and patterned using yellow light, where 1000A represents the thickness of PR. In some embodiments, the patterned photoresist and the APF2000A mask layer 21 can form a first mask together, and the underlying silicon nitride layer 16, oxide layer 15, CG polysilicon layer 14, ONO dielectric layer 13 and FG polysilicon layer 12 are sequentially etched with the first mask to form FG.
[0063] In order to absorb the lithography reflected light and further improve the lithography efficiency, in some embodiments, the method further includes:
[0064] An anti-reflection layer is formed on the mask layer 21 .
[0065] A first photoresist 24 is coated on the anti-reflection layer.
[0066] The first photoresist 24 is patterned using yellow light.
[0067] It should be noted that the anti-reflection layer includes a first anti-reflection layer 22 and a second anti-reflection layer 23 .
[0068] The step of forming an anti-reflection layer on the mask layer 21 includes: forming a first anti-reflection layer 22 on the mask layer 21, and forming a second anti-reflection layer 23 on the first anti-reflection layer 22. The first anti-reflection layer 22 is a DARC (Developable Bottom Anti-Reflection Coating), and the second anti-reflection layer 23 is a BARC (Bottom Anti-Reflection Coating).
[0069] In addition, the first anti-reflection layer 22 can be DARC250+OX50, where 250 represents the thickness of DARC and 50 represents the thickness of OX. OX50 is a cover layer used to cover the APF layer so that the yellow light can be REWORKed, that is, when the photolithography CD does not meet the specifications, the photoresist can be removed by using the yellow light REWORK. The second anti-reflection layer 23 is BARC 500A.
[0070] In some other embodiments, Fig.10 and Fig.11 As shown, in the step of forming the CG, the first mask is removed, and the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 are sequentially etched using the second mask. The step of forming the CG includes:
[0071] The gap between the silicon nitride layer 16 and the FG is covered with a third anti-reflection layer 231 , and a second photoresist 241 is coated on the first anti-reflection layer 22 .
[0072] The second photoresist 241 is patterned, and the patterned second photoresist 241 forms a second mask.
[0073] The gap between the silicon nitride layer 16 and the FG, as well as the edge position of the FG are covered with a third anti-reflection layer 231, and a second photoresist 241 is coated on the third anti-reflection layer 231. The second photoresist 241 is patterned to form a second mask, and the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 between the two FGs are etched with the second mask to form a CG.
[0074] It should be noted that the exposure width between two FGs in the patterned second photoresist 241 is greater than the spacing between two FGs in the patterned first photoresist 24, and the distance between two FGs etched using the first mask is smaller than the spacing between two CGs etched using the second mask, thereby making the gap between CGs larger than the gap between FGs in the Y direction.
[0075] like Figures 8 to 12 A schematic cross-sectional structure diagram of the manufacturing process of the memory cell regions CG and FG of the semiconductor device disclosed in the present invention is shown.
[0076] like Figure 8 As shown, a channel oxide layer 11, a FG polysilicon layer 12, an ONO dielectric layer 13, a CG polysilicon layer 14, an oxide layer 15 and a silicon nitride layer 16 are sequentially formed on a substrate 10, and then a mask layer 21 (including an APF layer, a DARC+OX layer and a BARC layer) is coated on the silicon nitride layer 16.
[0077] like Fig. 9 As shown, a first photoresist 24 is coated on the mask layer 21, and then the first photoresist 24 is patterned. The mask layer 21, the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14, the ONO dielectric layer 13 and the FG polysilicon layer 12 are sequentially etched with the patterned first photoresist 24 to form FG, and the first photoresist 24 and the mask layer 21 (including the APF layer, the DARC+OX layer and the BARC layer) are removed to expose the silicon nitride layer 16.
[0078] like Fig.10 As shown, the gap between the silicon nitride layer 16 and the FG, as well as the edge position of the FG are covered with the third anti-reflection layer 231, and a second photoresist 241 is coated on the third anti-reflection layer 231. The second mask is formed by patterning the second photoresist 241.
[0079] like Fig.11 As shown, the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 between the two FGs are etched with a second mask to form a CG.
[0080] like Fig.12 As shown, a sidewall layer 30 is formed on the sidewalls of CG and FG.
[0081] Compared with the prior art, the method for preparing a semiconductor device in the embodiment of the present disclosure reverses the preparation order of CG and FG, so that the sidewall dielectric layer can be deposited together, simplifying the process; in addition, the CD (hole-to-hole distance) size of FG can be controlled by yellow light, and the thickness size can be better controlled.
[0082] An embodiment of the present disclosure further provides a semiconductor device, which is manufactured using the above-mentioned method for manufacturing a semiconductor device.
[0083] The semiconductor device and its preparation method disclosed in the present invention first form a channel oxide layer 11, a FG polysilicon layer 12, an ONO dielectric layer 13, a CG polysilicon layer 14, an oxide layer 15 and a silicon nitride layer 16 on a substrate 10, then use a first mask to sequentially etch the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14, the ONO dielectric layer 13 and the FG polysilicon layer 12 to form FG, and then use a second mask to sequentially etch the silicon nitride layer 16, the oxide layer 15, the CG polysilicon layer 14 and the ONO dielectric layer 13 to form CG. Through the above method, that is, first forming FG on the substrate 10 and then forming CG, compared with the current technology, the forming order of CG and FG is changed, and the dielectric layer can be deposited after the CG is finally formed to protect the GATE side wall, simplifying the manufacturing process and improving production efficiency. In addition, the CD (hole-to-hole distance) size of FG can be controlled by yellow light, and the thickness size is better controlled.
[0084] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0085] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0086] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: A channel oxide layer, a FG polysilicon layer, an ONO dielectric layer, a CG polysilicon layer, an oxide layer and a silicon nitride layer are sequentially formed on the substrate; Using a first mask, sequentially etching the silicon nitride layer, the oxide layer, the CG polysilicon layer, the ONO dielectric layer and the FG polysilicon layer to form FG; The first mask is removed, and the silicon nitride layer, the oxide layer, the CG polysilicon layer and the ONO dielectric layer are sequentially etched using the second mask to form a CG.
2. The method for preparing a semiconductor device according to claim 1, wherein: The gap of the CG is larger than the gap of the FG.
3. The method for preparing a semiconductor device according to claim 1 or 2, characterized in that: The method further comprises: A sidewall layer is formed on the sidewalls of the CG and the FG.
4. The method for preparing a semiconductor device according to claim 3, characterized in that: The sidewall layer is formed by a layer-by-layer deposition process or a chemical vapor deposition process.
5. The method for preparing a semiconductor device according to claim 3, characterized in that: The sidewall layer is an oxide layer-nitride layer structure.
6. The method for preparing a semiconductor device according to claim 1, wherein: The method of sequentially etching the silicon nitride layer, the oxide layer, the CG polysilicon layer, the ONO dielectric layer and the FG polysilicon layer using the first mask to form the FG layer comprises: forming a mask layer on the silicon nitride layer; Coating a first photoresist on the mask layer and patterning the first photoresist; The first mask is formed on the mask layer by patterning the first photoresist.
7. The method for preparing a semiconductor device according to claim 6, characterized in that: The method further comprises: forming an anti-reflection layer on the mask layer; coating the first photoresist on the anti-reflection layer; The first photoresist is patterned using yellow light.
8. The method for preparing a semiconductor device according to claim 7, characterized in that: The anti-reflection layer includes a first anti-reflection layer and a second anti-reflection layer.
9. The method for preparing a semiconductor device according to claim 1, wherein: The first mask is removed, and the silicon nitride layer, the oxide layer, the CG polysilicon layer and the ONO dielectric layer are sequentially etched using the second mask to form a CG, including: Covering the gap between the silicon nitride layer and the FG with a third anti-reflection layer, and coating the first anti-reflection layer with a second photoresist; The second photoresist is patterned, and the patterned second photoresist forms a second mask.
10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.