Power device with high voltage change rate controllability and preparation method

Abstract

The invention discloses a power device with high voltage change rate controllability and a preparation method, and relates to the technical field of semiconductor devices.The power device comprises a substrate of a first conduction type and a plurality of groove type cells which are arranged in an active area of the substrate and distributed side by side; any groove type cell comprises an active grid unit, a first auxiliary grid unit group, a second auxiliary grid unit group, a first false grid unit group and a second false grid unit group; the active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, and each of the first false gate unit group and the second false gate unit group at least comprises a false gate unit; the dummy gate unit comprises a dummy gate groove, a second conductive type floating region is arranged below the dummy gate groove, and the second conductive type floating region is at least in contact with the groove bottom of the dummy gate groove. According to the power device, the grid resistor Rg has better control capability on the collector-emitter voltage change rate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a power device with high controllability of voltage change rate and a preparation method thereof. Background Art

[0002] In the early stage of IGBT conduction, the P+ collector will inject a large number of holes into the N-sub region, and the holes will gather on the lower side of the active gate. When the IGBT is turned on, the holes gathered near the active gate will generate displacement current, thereby causing oscillation of the gate voltage, which can easily cause overshoot and excessive collector-emitter voltage change rate (dv / dt) in the turn-on stage.

[0003] In high-frequency operation, in order to reduce losses and heat generation, the gate resistance (Rg) of the IGBT is often designed to be very low, which makes the gate control ability weakened due to the accumulation of holes under the gate caused by too fast a turn-on speed, and the EMI caused by excessive dv / dt more and more serious. Especially when the IGBT is applied to the motor, since the inverter is connected to the motor through a cable, (partial) voltage reflection will be generated at the motor end. The specific reason is that the impedance of the motor and the cable is often mismatched. This will cause the voltage reflected from the motor side to the inverter side to be reflected to the motor side again. The two voltages are superimposed, causing greater voltage stress on the motor side. Therefore, manufacturers usually recommend that the dv / dt on the inverter side of a 400V motor should not exceed 5kV / μs in the worst case.

[0004] When applying IGBT, the only adjustable value is Rg, and it is often necessary to reduce the maximum collector-emitter voltage change rate (dv / dtmax) of the IGBT by increasing Rg. However, increasing Rg will increase the turn-on loss Eon of the IGBT, and the IGBT will heat up severely, exceeding the maximum limit junction temperature. In other words, controlling dv / dtmax through Rg will cause Eon and dv / dtmax to change in opposite directions. When applied to motors, existing IGBTs are often unable to be used because dv / dtmax and junction temperature cannot meet the requirements at the same time. In summary, the key is how to better control dv / dtmax through Rg so that the IGBT has both lower Eon and smaller dv / dtmax. Summary of the invention

[0005] In view of the above problems and technical requirements, the inventors have proposed a power device with high controllability of voltage change rate and a preparation method. The technical solution of the present invention is as follows:

[0006] A power device with high controllability of voltage change rate comprises a substrate with a first conductivity type and an active region prepared in the central region of the substrate, wherein a plurality of trench cells distributed in parallel are arranged in the active region, wherein:

[0007] For any trench type cell, it includes an active gate unit, a first auxiliary gate unit group, a second auxiliary gate unit group, a first dummy gate unit group and a second dummy gate unit group;

[0008] The active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, the first dummy gate unit group is located on a side of the first auxiliary gate unit group away from the active gate unit, and the second dummy gate unit group is located on a side of the second auxiliary gate unit group away from the active gate unit;

[0009] The first auxiliary gate unit group and the second auxiliary gate unit group each include at least one auxiliary gate unit, and the first dummy gate unit group and the second dummy gate unit group each include at least one dummy gate unit;

[0010] The auxiliary gate unit is electrically connected to a first electrode metal for forming a first electrode above the substrate, and the dummy gate unit and the active gate unit are both electrically connected to a second electrode metal for forming a second electrode above the substrate;

[0011] The dummy gate unit comprises a dummy gate trench, a second conductive type floating region is arranged below the dummy gate trench, and the second conductive type floating region at least contacts with the bottom of the dummy gate trench.

[0012] A further technical solution is that the active gate unit comprises an active gate trench, an active gate oxide layer and an active gate polysilicon, the active gate polysilicon is filled in the active gate trench and insulated and isolated from the inner wall of the active gate trench by the active gate oxide layer, and the active gate polysilicon is in ohmic contact with the second electrode metal;

[0013] The auxiliary gate unit comprises an auxiliary gate trench, an auxiliary gate oxide layer and auxiliary gate polysilicon, wherein the auxiliary gate polysilicon is filled in the auxiliary gate trench and insulated and isolated from the inner wall of the auxiliary gate trench by the auxiliary gate oxide layer, and the auxiliary gate polysilicon is in ohmic contact with the first electrode metal;

[0014] The dummy gate unit further includes a dummy gate oxide layer and dummy gate polysilicon. The dummy gate polysilicon is filled in the dummy gate trench and insulated and isolated from the inner wall of the dummy gate trench by the dummy gate oxide layer. The dummy gate polysilicon is in ohmic contact with the second electrode metal.

[0015] A further technical solution is that the depth of the dummy gate trench is greater than the depth of the active gate trench, and the depth of the active gate trench is greater than the depth of the auxiliary gate trench.

[0016] A further technical solution is that the number of auxiliary gate units in the first auxiliary gate unit group and the second auxiliary gate unit group is the same or different;

[0017] When the first auxiliary gate unit group includes more than one auxiliary gate unit, the auxiliary gate units in the first auxiliary gate unit group are arranged in sequence along the direction from the active gate unit to the first auxiliary gate unit group;

[0018] When the second auxiliary gate unit group includes more than one auxiliary gate unit, the auxiliary gate units in the second auxiliary gate unit group are arranged in sequence along a direction from the active gate unit to the second auxiliary gate unit group.

[0019] A further technical solution is that the second conductive type floating region covers the bottom of the dummy gate trench and extends toward the outer side wall of the dummy gate trench.

[0020] A further technical solution is that it also includes a second conductive type base region that traverses the active region, and the depths of the active gate trench, the auxiliary gate trench and the dummy gate trench are all greater than the junction depth of the second conductive type base region.

[0021] A further technical solution is that a first conductive type source region and a second conductive type source region are arranged in a second conductive type base region between an active gate trench and an adjacent auxiliary gate trench;

[0022] The first conductive type source region contacts the sidewall of the active gate trench and the corresponding sidewall of the auxiliary gate trench, and the first conductive type source region also contacts the second conductive type source region, and both the first conductive type source region and the second conductive type source region are in ohmic contact with the first electrode metal.

[0023] A further technical solution is that the trench depths of all auxiliary gate trenches are the same, and the trench depths of all dummy gate trenches are also the same;

[0024] The depth ratio of the dummy gate trench, the active gate trench and the auxiliary gate trench is 1.1:1:0.9.

[0025] A method for preparing a power device with high controllability of voltage change rate, comprising:

[0026] A first conductive type substrate is provided, and a front cell process is performed on the front side of the substrate corresponding to the active area. The front cell process includes preparing a plurality of parallelly distributed trench cells on the front side of the substrate corresponding to the active area, wherein:

[0027] For any trench type cell, it includes an active gate unit, a first auxiliary gate unit group, a second auxiliary gate unit group, a first dummy gate unit group and a second dummy gate unit group;

[0028] The active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, the first dummy gate unit group is located on a side of the first auxiliary gate unit group away from the active gate unit, and the second dummy gate unit group is located on a side of the second auxiliary gate unit group away from the active gate unit;

[0029] The first auxiliary gate unit group and the second auxiliary gate unit group each include at least one auxiliary gate unit, and the first dummy gate unit group and the second dummy gate unit group each include at least one dummy gate unit;

[0030] The auxiliary gate unit is electrically connected to a first electrode metal for forming a first electrode above the substrate, and the dummy gate unit and the active gate unit are both electrically connected to a second electrode metal for forming a second electrode above the substrate;

[0031] The dummy gate unit comprises a dummy gate trench, a second conductive type floating region is arranged below the dummy gate trench, and the second conductive type floating region at least contacts with the bottom of the dummy gate trench.

[0032] A further technical solution is that the active gate unit includes an active gate trench, the auxiliary gate unit includes an auxiliary gate trench, and the active gate trench, the auxiliary gate trench, the dummy gate trench and the second conductive type floating region are prepared, including:

[0033] Etching a prepared active gate trench, a prepared auxiliary gate trench and a prepared dummy gate trench on the front side of the substrate corresponding to the active region, using the bottom of the prepared dummy gate trench as an injection window to inject second conductive type impurities under the prepared dummy gate trench, and annealing to activate the second conductive type impurities and then diffusing the impurities at a high temperature to form a second conductive type floating region;

[0034] Etching the prepared active gate trench, the prepared auxiliary gate trench and the prepared dummy gate trench to obtain the active gate trench, the auxiliary gate trench and the dummy gate trench respectively;

[0035] The width of the prepared active gate trench is smaller than that of the active gate trench, the width of the prepared auxiliary gate trench is smaller than that of the auxiliary gate trench, and the width of the prepared dummy gate trench is smaller than that of the dummy gate trench.

[0036] Among the “first conductivity type” and “second conductivity type”, for N-type power devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power devices, the types referred to by the first conductivity type and the second conductivity type are opposite to those of N-type devices.

[0037] The beneficial technical effects of the present invention are:

[0038] (1) The present invention reduces input capacitance and output capacitance and conduction loss by setting auxiliary gate units and dummy gate units, balances withstand voltage and conduction loss by arranging active gate units, auxiliary gate units and dummy gate units, and especially optimizes the size relationship between Cgc (gate-collector capacitance) and Cge (gate-emitter capacitance), improves the value of Cgc / Cge, and can make the collector-emitter voltage change rate dv / dt change more dramatically with the gate resistance Rg, that is, Rg has better controllability for dv / dtmax. In addition, the relationship curve between dv / dtmax and Eon in the turn-on stage of the IGBT device can be optimized. Compared with the traditional IGBT device, the IGBT device provided by the present invention can have a lower Eon and a smaller dv / dtmax under the same Rg.

[0039] (2) The present invention provides a P-type floating region under the dummy gate groove, and the P-type floating region forms a PN junction with the N-type substrate, which can generate an electric field directed from the P-type floating region to the front direction of the substrate, so that when the IGBT is turned on, it can better attract holes from the emitter to accumulate under the dummy gate groove, reduce the influence of the displacement current on the active gate unit, and avoid the accumulation of holes under the active gate groove to cause current overshoot, large reverse recovery current and large conduction loss. In addition, the holes accumulated under the dummy gate groove can make the IGBT have a lower turn-on speed than the traditional IGBT under the same Rg, that is, it has a smaller dv / dtmax than the traditional IGBT under the same Eon.

[0040] (3) The present invention optimizes the current path of the IGBT by making the groove depth of the dummy gate groove greater than the groove depth of the active gate groove, and making the groove depth of the active gate groove greater than the groove depth of the auxiliary gate groove, so that when the IGBT is turned on, the holes from the emitter are first accumulated under the dummy gate groove. Since the groove depth of the auxiliary gate groove is smaller than that of the dummy gate groove, in the process of the holes under the dummy gate groove moving to the conductive channel formed on both sides of the active gate unit, the holes will be accumulated under the auxiliary gate groove due to the depth difference formed between the auxiliary gate groove and the dummy gate groove, thereby increasing the local hole concentration near the conductive channel, generating an injection enhancement effect, and reducing the on-state voltage drop of the IGBT. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a cross-sectional schematic diagram of an embodiment of a power device with high controllability of voltage change rate provided by the present invention.

[0042] Figure 2-Figure 7 1 is a cross-sectional view of the process steps of an embodiment of a power device with high controllability of voltage change rate provided by the present invention, wherein:

[0043] Figure 2 It is a cross-sectional view of an embodiment of the present invention after preparing the prepared active gate trench, the prepared auxiliary gate trench and the prepared dummy gate trench.

[0044] Figure 3 It is a cross-sectional view of an embodiment of the present invention after the active gate trench, the auxiliary gate trench and the dummy gate trench are prepared.

[0045] Figure 4 It is a cross-sectional view of an embodiment of the present invention in which an N-type source region is prepared.

[0046] Figure 5 It is a cross-sectional view of an embodiment of the present invention after preparing the front metal layer.

[0047] Figure 6 It is a cross-sectional view of an embodiment of the present invention after the back side of the substrate is thinned.

[0048] Figure 7 It is a cross-sectional view of an embodiment of the present invention after the third electrode metal is prepared.

[0049] Figure 8 It is a simulation comparison diagram of the dv / dtmax controllability provided by the present invention.

[0050] Fig. 9 It is a simulation comparison diagram of the relationship curve between dv / dtmax and Eon provided by the present invention.

[0051] Reference numerals:

[0052] 1-substrate, 2-active gate trench, 3-auxiliary gate trench, 4-dummy gate trench, 5-P-type floating region, 6-active gate polysilicon, 7-auxiliary gate polysilicon, 8-dummy gate polysilicon, 9-P-type base region, 10-N-type source region, 11-P-type source region, 12-insulating dielectric layer, 13-first electrode metal, 14-N-type field stop layer, 15-P-type collector region, 21-prepared active gate trench, 31-prepared auxiliary gate trench, 41-prepared dummy gate trench. DETAILED DESCRIPTION

[0053] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0054] The present invention provides a power device with high controllability of voltage change rate. Taking the first conductivity type as N-type as an example, in one embodiment of the present invention, it includes an N-type substrate 1 and an active area prepared in the central area of ​​the substrate 1, wherein a plurality of trench cells distributed in parallel are arranged in the active area, wherein:

[0055] For any trench type cell, it includes an active gate unit, a first auxiliary gate unit group, a second auxiliary gate unit group, a first dummy gate unit group and a second dummy gate unit group;

[0056] The active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, the first dummy gate unit group is located on a side of the first auxiliary gate unit group away from the active gate unit, and the second dummy gate unit group is located on a side of the second auxiliary gate unit group away from the active gate unit;

[0057] The first auxiliary gate unit group and the second auxiliary gate unit group each include at least one auxiliary gate unit, and the first dummy gate unit group and the second dummy gate unit group each include at least one dummy gate unit;

[0058] The auxiliary gate unit is electrically connected to the first electrode metal 13 for forming the first electrode above the substrate 1, and the dummy gate unit and the active gate unit are both electrically connected to the second electrode metal for forming the second electrode above the substrate 1;

[0059] The dummy gate unit includes a dummy gate trench 4 , a P-type floating region 5 is disposed below the dummy gate trench 4 , and the P-type floating region 5 at least contacts the bottom of the dummy gate trench 4 .

[0060] Specifically, for a power device, it generally includes an active area located in the center area of ​​the substrate 1 and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area can be consistent with the prior art. The substrate 1 can be made of existing common materials, such as a silicon substrate, a SiC substrate, etc., to meet application requirements.

[0061] The substrate 1 generally has a front side and a back side corresponding to the front side, and the active gate unit, the first sub-gate unit group, the second sub-gate unit group, the first dummy gate unit group and the second dummy gate unit group are all arranged on the front side of the substrate 1. Generally, for a power device, the front metal layer located on the front side of the substrate 1 includes a first electrode metal 13 for forming a first electrode, and a second electrode metal for forming a second electrode. A third electrode metal for forming a third electrode is also arranged on the back side of the substrate 1. Specifically, according to different settings of the back side structure of the cell, the power device can form a MOSFET type device or an IGBT type device. For a MOSFET type device, the first electrode of the power device is a source, the second electrode is a gate, and the third electrode is a drain; for an IGBT type device, the first electrode of the power device is an emitter, the second electrode is a gate, and the third electrode is a base. In this embodiment, the formation of an IGBT type device is taken as an example for explanation.

[0062] Those skilled in the art will know that the input capacitance and output capacitance of the IGBT device affect the conduction loss of the device. The smaller the input capacitance and output capacitance, the smaller the conduction loss of the device. The input capacitance of the IGBT device is Ciss=Cgc+Cge, and the output capacitance is Coss=Cgc+Cce, where Cgc is the gate-collector capacitance, also known as the Miller capacitance, Cge is the gate-emitter capacitance, and Cce is the collector-emitter capacitance. The auxiliary gate unit in the present invention can reduce the density of the active gate unit in the device, thereby effectively reducing Cgc and Cge, reducing the input capacitance and output capacitance, and reducing the conduction loss. Since the order of magnitude of Cgc is smaller than that of Cge, the value of the reduction of Cge in capacitance value is greater than the value of the reduction of Cgc, therefore, the auxiliary gate unit can also increase Cgc / Cge, so that the voltage change rate dv / dt has higher controllability. For IGBT type devices, the voltage change rate is specifically the collector-emitter voltage change rate dv / dt.

[0063] The high controllability of the voltage change rate means that dv / dt can change dramatically with the gate resistance Rg, thereby increasing the adjustment range when adjusting dv / dtmax through Rg, so as to better control the maximum collector-emitter voltage change rate dv / dtmax through the gate resistance Rg. In addition, the present invention can also optimize the relationship curve between dv / dtmax and conduction loss Eon, so that the IGBT provided by the present invention can have lower Eon and smaller dv / dtmax at the same Rg compared with the traditional IGBT, which can solve the problem of not being able to meet the application parameter requirements when applied to the motor.

[0064] Although the auxiliary gate unit can reduce the conduction loss by reducing the input capacitance and the output capacitance, it will also reduce the withstand voltage of the IGBT. Therefore, the present invention also provides a dummy gate unit to improve the withstand voltage and better balance the withstand voltage and conduction loss. In addition, a P-type floating region 5 is provided below the dummy gate groove 4 in the dummy gate unit, and the P-type floating region 5 is at least in contact with the bottom of the dummy gate groove 4.

[0065] The P-type floating region 5 can form a PN junction with the N-type substrate 1, and can generate an electric field pointing from the P-type floating region 5 to the front direction of the substrate 1, so that when the IGBT is turned on, it can better attract the holes from the emitter to accumulate under the dummy gate groove 4, and suppress the problem of excessive dv / dtmax caused by the accumulation of displacement current under the active gate unit. The thickness of the P-type floating region 5 below the dummy gate groove 4 needs to be set according to actual conditions to meet the hole accumulation effect below the dummy gate groove 4. The holes accumulated under the dummy gate groove can also make the IGBT have a lower turn-on speed than the traditional IGBT under the same Rg, that is, it has a smaller dv / dtmax than the traditional IGBT under the same Eon. Preferably, the P-type floating region 5 covers the bottom of the dummy gate groove 4 and extends to the outer wall of the dummy gate groove 4, forming a Figure 1 At this time, the P-type floating region 5 can also shield the partial coupling between the dummy gate unit and the composite gate unit to reduce Cge, thereby further improving Cgc / Cge.

[0066] Furthermore, the number of auxiliary gate units in the first auxiliary gate unit group and the second auxiliary gate unit group is the same or different;

[0067] When the first auxiliary gate unit group includes more than one auxiliary gate unit, the auxiliary gate units in the first auxiliary gate unit group are arranged in sequence along the direction from the active gate unit to the first auxiliary gate unit group;

[0068] When the second auxiliary gate unit group includes more than one auxiliary gate unit, the auxiliary gate units in the second auxiliary gate unit group are arranged in sequence along a direction from the active gate unit to the second auxiliary gate unit group.

[0069] Preferably, the first sub-gate unit group and the second sub-gate unit group both have a plurality of sub-gate units, and the number of sub-gate units in the first sub-gate unit group and the second sub-gate unit group is the same. Arranging a plurality of sub-gate units in the first sub-gate unit group and the second sub-gate unit group can better reduce the conduction loss. At the same time, when the number of sub-gate units is the same, the arrangement of the sub-gate unit and the dummy gate unit provided by the present invention can reduce Cge as much as possible, thereby improving Cgc / Cge. This is because the dummy gate unit and the adjacent sub-gate unit will couple to increase Cge, that is, the dummy gate unit has a gate potential, the sub-gate unit has an emitter potential, and the coupling capacitance formed by the dummy gate unit and the sub-gate unit with the area between the dummy gate unit and the sub-gate unit as the dielectric layer will increase Cge. If the dummy gate unit is located between two sub-gate units, the dummy gate unit will form a coupling capacitance with the sub-gate units on both sides. In the arrangement provided by the present invention, only one side of the dummy gate unit will form a coupling capacitance with the sub-gate unit, so the arrangement of the sub-gate unit and the dummy gate unit provided by the present invention can reduce Cge as much as possible.

[0070] In one embodiment of the present invention, the first auxiliary gate unit group and the second auxiliary gate unit group each include two auxiliary gate units, the first dummy gate unit group and the second dummy gate unit group each include one dummy gate unit, the auxiliary gate units in the first auxiliary gate unit group and the second auxiliary gate unit group are symmetrically arranged about the active gate unit on both sides of the active gate unit, and the dummy gate units in the first dummy gate unit group and the second dummy gate unit group are also symmetrically arranged about the active gate unit. For ease of description, G represents the active gate unit, E represents the auxiliary gate unit, and D represents the dummy gate unit, such as Figure 1 As shown, in this embodiment, a DEEGEED multi-type gate unit arrangement is formed in a trench cell. Under this arrangement, the IGBT has a good capacitance ratio, that is, a higher Cgc / Cge, which effectively optimizes the relationship curve between dv / dtmax and Eon.

[0071] In order to verify the effect of the multi-type gate unit arrangement provided by the present invention on improving the controllability of dv / dtmax and optimizing the relationship curve between dv / dtmax and Eon, the IGBT structure of the above embodiment and other traditional structures are modeled and simulated for comparison. Figure 8 The figure is a simulation comparison diagram of dv / dtmax controllability, showing the simulation curves of dv / dtmax of the IGBT with Rg changing with the structure of the above embodiment and other five gate unit arrangement structures. The five gate unit arrangement structures compared include a cell structure with three auxiliary gate units on both sides of an active gate unit, a cell structure with three active gate units and three auxiliary gate units, a cell structure with an active gate unit and an auxiliary gate unit, a cell structure with an active gate unit and three auxiliary gate units, and a cell structure with an active gate unit, four auxiliary gate units and a dummy gate unit. Figure 8 It can be seen that the dv / dtmax of the IGBT provided in this embodiment changes more dramatically with Rg and the range of change is wider, that is, the IGBT provided in this embodiment has better dv / dtmax controllability. Fig. 9 The simulation comparison diagram of the relationship curve between dv / dtmax and Eon shows the relationship curve between dv / dtmax and Eon of the IGBT under the above embodiment structure and other five gate unit arrangement structures. Fig. 9 It can be seen that the relationship curve between dv / dtmax and Eon provided in this embodiment is closer to the origin of the coordinate system, and a smaller Eon can be obtained when dv / dtmax is the same within a certain Rg range.

[0072] Further, the active gate unit includes an active gate trench 2, an active gate oxide layer and an active gate polysilicon 6, the active gate polysilicon 6 is filled in the active gate trench 2, and is insulated and isolated from the inner wall of the active gate trench 2 by the active gate oxide layer, and the active gate polysilicon 6 is in ohmic contact with the second electrode metal;

[0073] The auxiliary gate unit includes an auxiliary gate trench 3, an auxiliary gate oxide layer and an auxiliary gate polysilicon 7, wherein the auxiliary gate polysilicon 7 is filled in the auxiliary gate trench 3 and insulated and isolated from the inner wall of the auxiliary gate trench 3 by the auxiliary gate oxide layer, and the auxiliary gate polysilicon 7 is in ohmic contact with the first electrode metal 13;

[0074] The dummy gate unit further includes a dummy gate oxide layer and a dummy gate polysilicon 8. The dummy gate polysilicon 8 is filled in the dummy gate trench 4 and insulated and isolated from the inner wall of the dummy gate trench 4 by the dummy gate oxide layer. The dummy gate polysilicon 8 is in ohmic contact with the second electrode metal.

[0075] Specifically, the active gate trench 2, the auxiliary gate trench 3 and the dummy gate trench 4 all extend vertically from the front side of the substrate 1 to the back side of the substrate 1. The trench depths of all the auxiliary gate trenches 3 are the same, and the trench depths of all the dummy gate trenches 4 are the same. The active gate oxide layer, the auxiliary gate oxide layer and the dummy gate oxide layer are not Figure 1 As shown in FIG. 1 , the active gate oxide layer, the auxiliary gate oxide layer and the dummy gate oxide layer may be made of the same material and may be silicon dioxide. Preferably, the groove angles of the active gate trench 2, the auxiliary gate trench 3 and the dummy gate trench 4 are arc-shaped groove angles to reduce electric field concentration.

[0076] Furthermore, the power device further includes a P-type base region 9 that traverses the active region, the groove depths of the active gate trench 2, the auxiliary gate trench 3, and the dummy gate trench 4 are all greater than the junction depth of the P-type base region 9, and an N-type source region 10 and a P-type source region 11 are arranged in the P-type base region 9 between the active gate trench 2 and the adjacent auxiliary gate trench 3. The N-type source region 10 contacts the sidewall of the active gate trench 2 and the corresponding sidewall of the auxiliary gate trench 3, the N-type source region 10 also contacts the P-type source region 11, and the N-type source region 10 and the P-type source region 11 are both in ohmic contact with the first electrode metal 13.

[0077] Specifically, in the active gate trench 2, the auxiliary gate trench 3 and the dummy gate trench 4, only the N-type source region 10 and the P-type source region 11 are arranged on both sides of the active gate trench 2, that is, when the IGBT is turned on, only the two sides of the active gate trench 2 can form a conductive channel. The specific form of the ohmic contact between the N-type source region 10 and the P-type source region 11 and the first electrode metal 13 can refer to the following description. The doping concentration of the N-type source region 10 is greater than the doping concentration of the N-type substrate, and the doping concentration of the P-type source region 11 is greater than the doping concentration of the P-type base region 9.

[0078] Furthermore, the depth of the dummy gate trench 4 is greater than that of the active gate trench 2, and the depth of the active gate trench 2 is greater than that of the auxiliary gate trench 3, so as to optimize the current path of the IGBT. In this embodiment, the depth ratio of the dummy gate trench 4, the active gate trench 2 and the auxiliary gate trench 3 is 1.1:1:0.9.

[0079] Specifically, since the dummy gate groove 4 has the deepest groove among the active gate groove 2, the auxiliary gate groove 3 and the dummy gate groove 4, and a P-type floating region 5 is also provided below the dummy gate groove 4, when the IGBT is turned on, the holes from the emitter will first accumulate below the dummy gate groove 4, and since the groove depth of the auxiliary gate groove 3 is smaller than that of the dummy gate groove 4, in the process of the holes below the dummy gate groove 4 moving to the conductive channel formed on both sides of the active gate groove 2, the holes will accumulate below the auxiliary gate groove 3 due to the depth difference formed between the auxiliary gate groove 3 and the dummy gate groove 4, thereby increasing the local hole concentration near the conductive channel, generating an injection enhancement effect, and reducing the on-state voltage drop of the IGBT. It should be noted that in the present invention, no carrier storage layer is provided in the N-type substrate 1 to avoid hole accumulation under the active gate unit and to avoid increasing the displacement current.

[0080] For the above-mentioned power device with high controllability of voltage change rate, the present invention provides a method for preparing the power device, the method comprising:

[0081] An N-type substrate 1 is provided, and a front cell process is performed on the front side of the substrate 1 corresponding to the active area. The front cell process includes preparing a plurality of parallelly distributed trench cells on the front side of the substrate 1 corresponding to the active area, wherein:

[0082] For any trench type cell, it includes an active gate unit, a first auxiliary gate unit group, a second auxiliary gate unit group, a first dummy gate unit group and a second dummy gate unit group;

[0083] The active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, the first dummy gate unit group is located on a side of the first auxiliary gate unit group away from the active gate unit, and the second dummy gate unit group is located on a side of the second auxiliary gate unit group away from the active gate unit;

[0084] The first auxiliary gate unit group and the second auxiliary gate unit group each include at least one auxiliary gate unit, and the first dummy gate unit group and the second dummy gate unit group each include at least one dummy gate unit;

[0085] The auxiliary gate unit is electrically connected to a first electrode metal for forming a first electrode above the substrate, and the dummy gate unit and the active gate unit are both electrically connected to a second electrode metal for forming a second electrode above the substrate;

[0086] The dummy gate unit includes a dummy gate trench 4 , a P-type floating region 5 is disposed below the dummy gate trench 4 , and the P-type floating region 5 at least contacts the bottom of the dummy gate trench 4 .

[0087] Generally, a front cell process is first performed on the front side of the substrate 1, and then a back process is performed on the back side of the substrate 1. The front cell process includes preparing an active gate trench 2, a secondary gate trench 3, a dummy gate trench 4, and a P-type floating region 5. Specifically, when preparing the active gate trench 2, the secondary gate trench 3, the dummy gate trench 4, and the P-type floating region 5, the following steps are included:

[0088] A preliminary active gate trench 21, a preliminary auxiliary gate trench 31 and a preliminary dummy gate trench 41 are etched on the front side of the substrate 1 corresponding to the active region, and a P-type impurity is injected into the bottom of the preliminary dummy gate trench 41 using the bottom of the preliminary dummy gate trench 41 as an injection window, and the impurity is diffused at a high temperature after annealing to activate the P-type impurity, so as to form a P-type floating region 5; the width of the preliminary active gate trench 21 is smaller than the width of the active gate trench 2, the width of the preliminary auxiliary gate trench 31 is smaller than the width of the auxiliary gate trench 3, and the width of the preliminary dummy gate trench 41 is smaller than the width of the dummy gate trench 4. The depth of the preliminary active gate trench 21 is the same as the depth of the active gate trench 2, the depth of the preliminary auxiliary gate trench 31 is the same as the depth of the auxiliary gate trench 3, and the depth of the preliminary dummy gate trench 41 is the same as the depth of the dummy gate trench 4.

[0089] Specifically, Figures 2 to 7 The process steps of an embodiment of the above power device manufacturing method are shown below. Figures 2 to 7 The process steps of the power device preparation method in the above embodiment are specifically described as follows: Figure 1 As shown, an N-type silicon wafer is selected as a substrate 1, a first silicon dioxide layer is deposited on the front side of the substrate 1, a photoresist is spin-coated on the first silicon dioxide layer and a first mask is formed by a photolithography process, and an anisotropic etching is performed by a dry etching process using the first mask to prepare a preliminary active gate trench 21; the first mask is removed and a second silicon dioxide layer is deposited, a photoresist is spin-coated on the second silicon dioxide layer and a second mask is formed by a photolithography process, and an anisotropic etching is performed by a dry etching process using the second mask to prepare a preliminary active gate trench 21. Two preliminary auxiliary gate trenches 31 are etched on each side of the active gate trench 21; the second mask is removed and a third silicon dioxide layer is deposited, photoresist is spin-coated on the third silicon dioxide layer and a third mask is formed by a photolithography process, and anisotropic etching is performed by a dry etching process using the third mask to obtain a preliminary dummy gate trench 41 by etching on each side of the preliminary active gate trench 21, and the preliminary auxiliary gate trench 31 on each side of the preliminary active gate trench 21 is located between the preliminary dummy gate trench 41 and the preliminary active gate trench 21 on that side.

[0090] like Figure 3As shown, the bottom of the prepared dummy gate trench 41 is used as an injection window to inject P-type impurities into the bottom of the dummy gate trench 41 and anneal to activate the impurities. After the impurities are activated, the impurities are diffused around at a high temperature of 1200° C. At this time, the P-type impurities form a P-type floating region 5 at the bottom of the prepared dummy gate trench 41 to wrap the bottom of the prepared dummy gate trench 41. Different photomasks are used to perform isotropic etching on the prepared active gate trench 21, the prepared auxiliary gate trench 31 and the prepared dummy gate trench 41, in order to expand the groove width of the prepared active gate trench 21, the prepared auxiliary gate trench 31 and the prepared dummy gate trench 41, and to etch the groove angles of the prepared active gate trench 21, the prepared auxiliary gate trench 31 and the prepared dummy gate trench 41 into smooth groove angles, and at the same time remove the damaged groove inner wall of the prepared dummy gate trench 41 formed by the injection of P-type impurities, and finally obtain the active gate trench 2, the auxiliary gate trench 3 and the dummy gate trench 4. The relationship between the depths and the arrangement of the active gate trench 2 , the auxiliary gate trench 3 and the dummy gate trench 4 are consistent with those of the above embodiment, and reference may be made to the above description.

[0091] like Figure 4 As shown, silicon dioxide is deposited on the inner walls of the active gate trench 2, the auxiliary gate trench 3 and the dummy gate trench 4 to form an active gate oxide layer, an auxiliary gate oxide layer and a dummy gate oxide layer, and after the active gate oxide layer, the auxiliary gate oxide layer and the dummy gate oxide layer are formed, polysilicon is filled into the active gate trench 2, the auxiliary gate trench 3 and the dummy gate trench 4 to form an active gate polysilicon 6, an auxiliary gate polysilicon 7 and a dummy gate polysilicon 8. Thereafter, P-type ions such as B are implanted into the front surface of the substrate 1 corresponding to the active region by ion implantation, and a P-type base region 9 is prepared after high-temperature annealing. N-type doping ions are implanted into the P-type base region 9 between the active gate trench 2 and the adjacent auxiliary gate trench 3, and an N-type source region 10 is prepared after high-temperature annealing.

[0092] like Figure 5 As shown, a silicon dioxide layer 12 with a preset thickness is deposited on the front of the substrate 1, and a contact hole is etched above the N-type source region 10. The contact hole penetrates the insulating dielectric layer 12 and the N-type source region 10. P-type doping ions are injected into the P-type base region 9 below the N-type source region 10 through the contact hole, and high-temperature annealing is performed to form a P-type source region 11 with a higher doping concentration than the P-type base region 9. Metal is deposited on the front of the substrate 1 to form a front metal layer. The metal is simultaneously deposited in the contact hole. The front metal layer is divided into a first electrode metal 13 and a second electrode metal. The first electrode metal 13 is in ohmic contact with the N-type source region 10 and the P-type source region 11 through the metal in the corresponding contact hole. When the contact hole is formed above the N-type source region 10, corresponding contact holes are also formed above the active gate polysilicon 6, the auxiliary gate polysilicon 7, and the dummy gate polysilicon 8 (not shown). Figure 5As shown in the figure), the active gate polysilicon 6 and the dummy gate polysilicon 8 are in ohmic contact with the second electrode metal through the metal in the corresponding contact hole, and the auxiliary gate polysilicon 6 is in ohmic contact with the first electrode metal 13 through the metal in the corresponding contact hole, thereby completing the front cell process.

[0093] A backside process is performed on the backside of the substrate 1, such as Figure 6 and Figure 7 As shown, the substrate 1 is thinned to a preset thickness by a CMP (Chemical-Mechanical Polishing) process on the back side of the substrate 1 to reduce the substrate resistance. Since the power device described in this embodiment is an IGBT device, high-energy H ions and B ions are sequentially implanted on the back side of the substrate, and an N-type field stop layer 14 and a P-type collector region 15 are formed after high-temperature annealing. A metal is deposited on the back side of the substrate 1 to form a third electrode metal, i.e., a collector metal (not shown). Figure 7 As shown in FIG. 1 , the collector metal makes ohmic contact with the P-type collector region 15 to form a collector.

[0094] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0095] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A power device with high controllability of voltage change rate, characterized in that: It includes a substrate with a first conductivity type and an active area prepared in the center area of ​​the substrate, wherein a plurality of trench cells distributed in parallel are arranged in the active area, wherein: For any trench type cell, it includes an active gate unit, a first auxiliary gate unit group, a second auxiliary gate unit group, a first dummy gate unit group and a second dummy gate unit group; The active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, the first dummy gate unit group is located on a side of the first auxiliary gate unit group away from the active gate unit, and the second dummy gate unit group is located on a side of the second auxiliary gate unit group away from the active gate unit; The first auxiliary gate unit group and the second auxiliary gate unit group each include at least one auxiliary gate unit, and the first dummy gate unit group and the second dummy gate unit group each include at least one dummy gate unit; The auxiliary gate unit is electrically connected to a first electrode metal for forming a first electrode above the substrate, and the dummy gate unit and the active gate unit are both electrically connected to a second electrode metal for forming a second electrode above the substrate; The dummy gate unit comprises a dummy gate trench, a second conductive type floating region is arranged below the dummy gate trench, and the second conductive type floating region at least contacts with the bottom of the dummy gate trench.

2. The power device with high controllability of voltage change rate according to claim 1, characterized in that: The active gate unit comprises an active gate trench, an active gate oxide layer and an active gate polysilicon, wherein the active gate polysilicon is filled in the active gate trench and insulated and isolated from the inner wall of the active gate trench by the active gate oxide layer, and the active gate polysilicon is in ohmic contact with the second electrode metal; The auxiliary gate unit comprises an auxiliary gate trench, an auxiliary gate oxide layer and auxiliary gate polysilicon, wherein the auxiliary gate polysilicon is filled in the auxiliary gate trench and insulated and isolated from the inner wall of the auxiliary gate trench by the auxiliary gate oxide layer, and the auxiliary gate polysilicon is in ohmic contact with the first electrode metal; The dummy gate unit further includes a dummy gate oxide layer and dummy gate polysilicon. The dummy gate polysilicon is filled in the dummy gate trench and insulated and isolated from the inner wall of the dummy gate trench by the dummy gate oxide layer. The dummy gate polysilicon is in ohmic contact with the second electrode metal.

3. The power device with high controllability of voltage change rate according to claim 2, characterized in that: The trench depth of the dummy gate trench is greater than the trench depth of the active gate trench, and the trench depth of the active gate trench is greater than the trench depth of the auxiliary gate trench.

4. The power device with high controllability of voltage change rate according to claim 3, characterized in that: The number of auxiliary gate units in the first auxiliary gate unit group and the second auxiliary gate unit group is the same or different; When the first auxiliary gate unit group includes more than one auxiliary gate unit, the auxiliary gate units in the first auxiliary gate unit group are arranged in sequence along the direction from the active gate unit to the first auxiliary gate unit group; When the second auxiliary gate unit group includes more than one auxiliary gate unit, the auxiliary gate units in the second auxiliary gate unit group are arranged in sequence along a direction from the active gate unit to the second auxiliary gate unit group.

5. The power device with high controllability of voltage change rate according to claim 1, characterized in that: The second conductive type floating region covers the bottom of the dummy gate trench and extends toward the outer sidewall of the dummy gate trench.

6. The power device with high controllability of voltage change rate according to claim 2, characterized in that: It also includes a second conductive type base region that traverses the active region, and the depths of the active gate trench, the auxiliary gate trench, and the dummy gate trench are all greater than the junction depth of the second conductive type base region.

7. The power device with high controllability of voltage change rate according to claim 2, characterized in that: A first conductive type source region and a second conductive type source region are arranged in a second conductive type base region between the active gate trench and the adjacent auxiliary gate trench; The first conductive type source region contacts the sidewall of the active gate trench and the corresponding sidewall of the auxiliary gate trench, and the first conductive type source region also contacts the second conductive type source region, and both the first conductive type source region and the second conductive type source region are in ohmic contact with the first electrode metal.

8. The power device with high controllability of voltage change rate according to claim 4, characterized in that: The trench depths of all auxiliary gate trenches are the same, and the trench depths of all dummy gate trenches are also the same; The depth ratio of the dummy gate trench, the active gate trench and the auxiliary gate trench is 1.1:1:0.

9.

9. A method for preparing a power device with high controllability of voltage change rate, characterized in that: Used to prepare the power device according to any one of claims 1 to 8, wherein the method for preparing the power device with high controllability of voltage change rate comprises: A first conductive type substrate is provided, and a front cell process is performed on the front side of the substrate corresponding to the active area. The front cell process includes preparing a plurality of parallelly distributed trench cells on the front side of the substrate corresponding to the active area, wherein: For any trench type cell, it includes an active gate unit, a first auxiliary gate unit group, a second auxiliary gate unit group, a first dummy gate unit group and a second dummy gate unit group; The active gate unit is located between the first auxiliary gate unit group and the second auxiliary gate unit group, the first dummy gate unit group is located on a side of the first auxiliary gate unit group away from the active gate unit, and the second dummy gate unit group is located on a side of the second auxiliary gate unit group away from the active gate unit; The first auxiliary gate unit group and the second auxiliary gate unit group each include at least one auxiliary gate unit, and the first dummy gate unit group and the second dummy gate unit group each include at least one dummy gate unit; The auxiliary gate unit is electrically connected to a first electrode metal for forming a first electrode above the substrate, and the dummy gate unit and the active gate unit are both electrically connected to a second electrode metal for forming a second electrode above the substrate; The dummy gate unit comprises a dummy gate trench, a second conductive type floating region is arranged below the dummy gate trench, and the second conductive type floating region at least contacts with the bottom of the dummy gate trench.

10. The method for preparing a power device with high controllability of voltage change rate according to claim 9, characterized in that: The active gate unit includes an active gate trench, the auxiliary gate unit includes an auxiliary gate trench, and the active gate trench, the auxiliary gate trench, the dummy gate trench and the second conductive type floating region are prepared, including: Etching a prepared active gate trench, a prepared auxiliary gate trench and a prepared dummy gate trench on the front side of the substrate corresponding to the active region, using the bottom of the prepared dummy gate trench as an injection window to inject second conductive type impurities under the prepared dummy gate trench, and annealing to activate the second conductive type impurities and then diffusing the impurities at a high temperature to form a second conductive type floating region; Etching the prepared active gate trench, the prepared auxiliary gate trench and the prepared dummy gate trench to obtain the active gate trench, the auxiliary gate trench and the dummy gate trench respectively; The width of the prepared active gate trench is smaller than that of the active gate trench, the width of the prepared auxiliary gate trench is smaller than that of the auxiliary gate trench, and the width of the prepared dummy gate trench is smaller than that of the dummy gate trench.

Images