Communication structure and manufacturing method thereof, and transistor and manufacturing method thereof

Abstract

The invention provides a communication structure and a manufacturing method thereof, and a transistor and a manufacturing method thereof, and the manufacturing method of the communication structure comprises the steps: forming at least one groove in an epitaxial layer located on the upper surface of a substrate, and enabling the groove to extend into the epitaxial layer from the upper surface of the epitaxial layer; filling a filling material including a dopant in the trench; and diffusing the dopant into the epitaxial layer by adopting a diffusion process so as to form a doped region below the groove, and at least diffusing the doped region to be in contact with the upper surface of the substrate. According to the method, the process steps are simplified, the preparation difficulty is reduced, and the yield of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a connection structure and a manufacturing method thereof, as well as a transistor and a manufacturing method thereof. Background Art

[0002] RF-LDMOS (Radio Frequency-Laterally Diffused Metal Oxide Semiconductor) power transistors are becoming increasingly popular in the field of RF power due to their low cost and high performance.

[0003] like Figure 1 As shown, the RF LDMOS has a lateral channel structure, and the drain region 300, the source region 400, and the gate 500 are all on the surface of the chip. The source region 400 is generally connected to the substrate 100 by a high-doping concentration channel in the body. The method usually adopted to realize the channel is to form a sinking structure 600 by injecting high-concentration p-type doping on the surface of the device and forming a high-concentration substrate at the back by high-temperature push-junction, so as to achieve good interconnection between the surface source terminal electrode and the high-concentration substrate at the back. However, since the thickness of the epitaxial layer 200 required for the high-voltage RF LDMOS is very large, usually greater than 10um, when the sinking structure 600 is prepared by the above method, its diffusion depth must be greater than the thickness of the epitaxial layer, so the diffusion depth is high, the required high-temperature push-junction time is long and the required push-junction temperature is high, resulting in low preparation efficiency; at the same time, due to the long push-junction time and high temperature, the high-concentration substrate 100 diffuses into the low-concentration epitaxial layer 200, reducing the effective epitaxial layer thickness, thereby reducing the device breakdown voltage. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a connection structure and a manufacturing method thereof, as well as a transistor and a manufacturing method thereof, so as to solve the problems existing in the prior art.

[0005] According to a first aspect of the present invention, there is provided a method for manufacturing a connecting structure, comprising: forming at least one groove in an epitaxial layer located on an upper surface of a substrate, the groove extending from the upper surface of the epitaxial layer to the interior thereof; filling the groove with a filling material including a dopant; and using a diffusion process to diffuse the dopant into the epitaxial layer to form a doped region below the groove, wherein the doped region is diffused at least to contact the upper surface of the substrate.

[0006] Preferably, the depth of the trench is set to be greater than three eighths of the thickness of the epitaxial layer and less than five eighths of the thickness of the epitaxial layer.

[0007] Preferably, the doping concentration of the filling material is set to 1e18-1e21 / cm 2 .

[0008] Preferably, the diffusion process is a high temperature push-junction process.

[0009] Preferably, the dopant includes a trivalent element or a pentavalent element.

[0010] Preferably, when the connecting structure is applied to the interconnection between the source and the substrate in a MOS transistor, the upper surface of the trench is connected to the source, the epitaxial layer is set to the first doping type, the substrate is set to the first doping type, and the connecting structure is set to the first doping type.

[0011] Preferably, when the connecting structure is applied to an isolation structure in a device, the connecting structure is set to a first doping type and the epitaxial layer is set to a second doping type, wherein the first doping type is set to one of n-type or P-type and the second doping type is set to the other of n-type or P-type.

[0012] According to a second aspect of the present invention, a method for manufacturing a transistor is provided, comprising: forming a connecting structure according to the above-mentioned method for manufacturing a connecting structure; forming a gate structure on the upper surface of the epitaxial layer; and forming a source region and a drain region of a second doping type in the epitaxial layer; wherein the connecting structure is set to a first doping type, the epitaxial layer is set to the first doping type, the connecting structure is connected to the source region, wherein the first doping type is set to one of n-type or P-type, and the second doping type is set to the other of n-type or P-type.

[0013] Preferably, it also includes: forming a drift region of the second doping type and a body region of the first doping type in the epitaxial layer, wherein the drain region is located in the drift region and the source region is located in the body region; and also forming a body contact region of the first doping type adjacent to the source region in the body region.

[0014] Preferably, the method further comprises forming a first metal silicide on the upper surface of the drain region, and forming a second metal silicide on the upper surfaces of the source region and the connecting structure, so as to achieve connection between the connecting structure and the source region.

[0015] Preferably, a field plate structure is formed on the epitaxial layer, the field plate structure comprises at least one field plate electrode, and the field plate electrode is at least located between the gate structure and the drain region.

[0016] Preferably, when the field plate structure comprises at least two field plate electrodes, the at least two field plate electrodes are arranged at intervals, and projections of two adjacent field plate electrodes in the vertical direction partially overlap.

[0017] Preferably, the method for forming the field plate structure includes: S1: depositing a first dielectric layer on the surface of the substrate and the surface of the gate structure; S2: forming a first metal layer on the first dielectric layer, the first metal layer extending from a portion of the upper surface of the gate structure, through the side surface of the gate structure, to above the epitaxial layer; S3: depositing a second dielectric layer on the surfaces of the first metal layer and the first dielectric layer; S4: forming a second metal layer on the second dielectric layer, the second metal layer extending from a portion of the upper surface of the first metal layer toward the drain region; repeating steps S3 and S4 in sequence to form an nth dielectric layer and an nth metal layer, wherein n is greater than or equal to 2.

[0018] Preferably, it also includes: forming an interlayer dielectric layer covering the epitaxial layer and the gate structure; forming conductive channels that penetrate the interlayer dielectric layer and extend to the first metal silicide, the second metal silicide and the gate structure respectively; forming a metal layer on the conductive channel, and forming a back electrode on the back side of the substrate.

[0019] Preferably, the method for forming the gate structure includes: forming a gate dielectric layer on the substrate, the gate dielectric layer being located on at least a portion of the upper surface of the body region; forming polysilicon on the gate dielectric layer, the polysilicon being of a second doping type and being located above the channel region; and forming metal silicide on the polysilicon.

[0020] According to a third aspect of the present invention, there is provided a connecting structure, comprising: at least one groove extending from the upper surface of an epitaxial layer located on a substrate to the interior of the epitaxial layer; a filling material comprising a dopant filled in the groove, and a doped region extending from the lower surface of the groove at least to the upper surface of the substrate, the doped region being formed by diffusion of the dopant in the filling material.

[0021] Preferably, the depth of the trench is set to be greater than three eighths of the thickness of the epitaxial layer and less than five eighths of the thickness of the epitaxial layer.

[0022] Preferably, the doping concentration of the filling material is set to 1e18-1e21 / cm 2 .

[0023] Preferably, the dopant includes a trivalent element or a pentavalent element.

[0024] Preferably, when the connecting structure is applied to the interconnection between the source and the substrate in a MOS transistor, the upper surface of the trench is connected to the source, the epitaxial layer is set to the first doping type, the substrate is set to the first doping type, and the filling material is set to the first doping type.

[0025] Preferably, when the connecting structure is applied to an isolation structure in a device, the connecting structure is set to a first doping type and the epitaxial layer is set to a second doping type, wherein the first doping type is set to one of n-type or P-type and the second doping type is set to the other of n-type or P-type.

[0026] According to a fourth aspect of the present invention, a transistor is provided, comprising: the above-mentioned connecting structure; a source region and a drain region of a second doping type extending from the upper surface of the epitaxial layer to the interior thereof; a gate structure located on the upper surface of the epitaxial layer and at least above the channel region between the source region and the drain region; and wherein the connecting structure is set to a first doping type, and the epitaxial layer is set to the first doping type, wherein the first doping type is set to one of n-type or P-type, and the second doping type is set to the other of n-type or P-type.

[0027] Preferably, it also includes: a drift region of the second doping type and a body region of the first doping type located in the substrate, wherein the drain region is located in the drift region and the source region is located in the body region; and a body contact region of the first doping type located in the body region and adjacent to the source region.

[0028] Preferably, it also includes a first metal silicide located on the upper surface of the drain region, and a second metal silicide located on the upper surfaces of the source region and the connecting structure, so as to realize the connection between the connecting structure and the source region.

[0029] Preferably, the field plate structure located on the epitaxial layer comprises at least one field plate electrode, and the field plate electrode is located at least between the gate structure and the drain region.

[0030] Preferably, when the field plate structure comprises at least two field plate electrodes, the at least two field plate electrodes are arranged at intervals, and projections of two adjacent field plate electrodes in the vertical direction partially overlap.

[0031] Preferably, the field plate structure includes: a first dielectric layer covering the surface of the substrate and the surface of the gate structure; a first metal layer located on the first dielectric layer, the first metal layer extending from a portion of the upper surface of the gate structure, through the side surface of the gate structure, to above the epitaxial layer; an nth dielectric layer covering the surface of the n-1th metal layer and the n-1th dielectric layer; and an nth metal layer formed on the nth dielectric layer, the nth metal layer extending from a portion of the upper surface of the n-1th metal layer toward the drain region, wherein n is greater than or equal to 2.

[0032] Preferably, it also includes: an interlayer dielectric layer covering the epitaxial layer and the gate structure; a conductive channel penetrating the interlayer dielectric layer and contacting the first metal silicide, the second metal silicide and the gate structure respectively; a metal layer located on the conductive channel, and a back electrode located on the back side of the substrate.

[0033] The transistor provided by the present invention realizes the interconnection between the source and the substrate by setting a trench structure and a doped region located below the trench. Since the depth of the doped region in the present invention is relatively small, the push-in time required for the conventional sinker structure can be greatly reduced, the thermal budget can be reduced, and the diffusion depth of the high-concentration substrate to the low-concentration epitaxial layer can be weakened; on the other hand, the method for forming a transistor provided by the present invention first fills the trench with a filling material containing a dopant, and then uses a diffusion process to diffuse the dopant into the epitaxial layer and contact the substrate. This method simplifies the process steps, reduces the difficulty of preparation, and improves the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0035] Figure 1 A cross-sectional view showing a prior art LDMOS transistor;

[0036] Figure 2 A cross-sectional view showing a communication structure according to an embodiment of the present invention;

[0037] Figure 3 A cross-sectional view showing a transistor according to a first embodiment of the present invention;

[0038] Figure 4 A cross-sectional view showing a transistor according to a second embodiment of the present invention;

[0039] Figure 5 A flow chart showing a method for manufacturing a communication structure according to an embodiment of the present invention;

[0040] Figure 6a-6b Cross-sectional views showing certain stages of a method for manufacturing a communication structure according to an embodiment of the present invention;

[0041] Figure 7 A flow chart showing a method for manufacturing a transistor according to an embodiment of the present invention;

[0042] Figure 8a-8e A cross-sectional view showing some stages of a method for manufacturing a transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0044] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0045] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0046] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0047] The present invention provides a connecting structure, which includes: at least one groove extending from the upper surface of an epitaxial layer located on a substrate to the interior thereof; a filling material including a dopant filled in the groove, and a doped region extending from the lower surface of the groove at least to the upper surface of the substrate, wherein the doped region is formed by diffusion of the dopant in the filling material.

[0048] like Figure 2 , which is a cross-sectional view of a connection structure according to an embodiment of the present invention. The connection structure includes at least one trench 103 extending from the upper surface of the epitaxial layer 102 located on the substrate 101 to the inside of the epitaxial layer, and a filling material including a dopant filled in the trench 103 extending from the lower surface of the trench 103 to at least a doping region 104 on the upper surface of the substrate 101, wherein the doping region 104 is formed by diffusion of the dopant in the filling material. When the filling material and the doping region are of P-type doping type, the dopant may include trivalent elements such as boron, indium, and gallium; when the filling material and the doping region are of N-type doping type, the dopant may include pentavalent elements such as phosphorus and nitrogen.

[0049] In the present embodiment, the depth of the groove 103 is set to be greater than three eighths of the thickness of the epitaxial layer and less than five eighths of the thickness of the epitaxial layer. Preferably, the depth of the groove 103 is set to be half of the thickness of the epitaxial layer 102. The shape of the groove can be set to an equal width structure, or a narrow upper and wide lower structure or other structures. The shape of the groove is not limited here. In the present embodiment, the width of the groove 103 is set to be not less than 0.5um and not more than 2.5um. Preferably, the width of the groove 103 is set to 2um. The number of the grooves is set to 2. In other embodiments, the number of the grooves can be set to the required number according to the device requirements, and is not limited here.

[0050] In addition, the doping concentration of the filling material is set to 1e18~1e21 / cm 2 , that is, the dopant concentration of the doping agent is relatively high, and during the diffusion process, the dopant in the filling material can be better diffused into the epitaxial layer below the trench to form a doped region. In this embodiment, the filling material is preferably set to be a doped polysilicon material. In other embodiments, the filling material can also be other semiconductor materials, such as metal materials.

[0051] It should be noted that when the connecting structure is applied to the interconnection between the source and the substrate in a MOS transistor, the upper surface of the trench is connected to the source, the epitaxial layer is set to the first doping type, the substrate is set to the first doping type, and the filling material is set to the first doping type.

[0052] When the connecting structure is applied to an isolation structure in a device, the connecting structure is set to a first doping type, and the epitaxial layer is set to a second doping type, wherein the first doping type is set to one of n-type or P-type, and the second doping type is set to the other of n-type or P-type, and the connecting structure forms a PN junction isolation with the epitaxial layer to isolate the device structures on both sides of the connecting structure.

[0053] Specifically, the following description will be made by taking the application of the connection structure to the interconnection between the source and the substrate in a MOS transistor as an example.

[0054] like Figure 3, which is a cross-sectional view of a transistor according to a first embodiment of the present invention. The transistor comprises: a substrate 101; an epitaxial layer 102 of a first doping type, located on the upper surface of the substrate 101; a source region 112 and a drain region 110 of a second doping type, extending from the upper surface of the epitaxial layer 102 to the interior thereof, wherein the first doping type is set to one of n-type or P-type, and the second doping type is set to the other of n-type or P-type; a gate structure, located on the upper surface of the epitaxial layer 102, and located above the channel region between the source region 112 and the drain region 110; and a connecting structure, wherein the connecting structure is located on a side of the source region 112 away from the drain region 110, and is connected to the source region 112. The connecting structure includes a trench 103 extending from the upper surface of the epitaxial layer 102 to the inside thereof, a filling material including a dopant filled in the trench 103, and a doped region 104 extending at least from the lower surface of the trench 103 to the upper surface of the substrate 101, wherein the doped region 104 is formed by diffusion of the dopant in the filling material. In this embodiment, the substrate 101 is set to a first doping type.

[0055] Furthermore, the transistor further includes a drift region 108 having a second doping type located in the epitaxial layer, a body region 109 having a first doping type located in the epitaxial layer, and a body contact region 111 located in the body region 109 and adjacent to the source region 112. The drift region 108 and the body region 109 extend from the upper surface of the epitaxial layer to the inside of the epitaxial layer, respectively, and in the lateral direction, the body region 109 extends to below the gate structure. In this embodiment, the body region 109 is adjacent to the drift region 108, and the depth of the body region 109 in the epitaxial layer 102 is greater than the depth of the drift region 108 in the epitaxial layer 102.

[0056] In this embodiment, the gate structure includes a gate dielectric layer 105 and a gate conductor 106 located on the gate dielectric layer 105, and the gate conductor 106 is preferably polysilicon. Further, the polysilicon is set to have a second doping type with a high concentration. The gate structure also includes a third metal silicide 107 located on the gate conductor 106, and the third metal silicide 107 can be set to WSi alloy or NiPtSi alloy or Co2Si alloy or Ti2Si alloy. The transistor also includes a first metal silicide 114 formed on the drain region 110, and a second metal silicide 113 formed on the source region 112, the body contact region 111 and the connecting structure, and the second metal silicide 113 connects the source region 112 and the connecting structure. Among them, the first metal silicide 114 and the second metal silicide 113 are preferably TiSi alloy or NiPtSi alloy or Co2Si alloy or Ti2Si alloy. The gate structure is provided with a doped gate conductor 106 and a third metal silicide 107 to reduce gate resistance and improve the radio frequency performance of the device; the first metal silicide 114 and the second metal silicide 113 are respectively provided to further reduce the contact resistance of the drain region and the source region.

[0057] The transistor also includes an interlayer dielectric layer located on the epitaxial layer and covering the surface of the device, a conductive channel extending through the interlayer dielectric layer to the first metal silicide, the second metal silicide and the third metal silicide, a metal layer located on the conductive channel, and a back electrode located on the back side of the substrate.

[0058] In this embodiment, the gate structure only includes a gate dielectric layer and a gate conductor. In other embodiments, the gate structure may also include a gate field plate dielectric and a gate field plate, wherein the gate field plate dielectric is located on the gate dielectric layer between the gate conductor and the drain region, the gate field plate is formed simultaneously with the gate conductor, and the gate field plate is located on the gate field plate dielectric to further optimize the electric field in the drain region.

[0059] like Figure 4 , which is a cross-sectional view of a transistor according to a second embodiment of the present invention. The difference between the transistor structure of this embodiment and the transistor structure of the first embodiment is that a field plate structure is added, and the other structures are the same and will not be described in detail here.

[0060] In this embodiment, the transistor includes a field plate structure formed on the epitaxial layer, the field plate structure includes at least one field plate electrode, and the field plate electrode is at least located between the gate structure and the drain region. When the field plate structure includes at least two field plate electrodes, the at least two field plate electrodes are arranged at intervals, and the projections of two adjacent field plate electrodes in the vertical direction partially overlap. Specifically, the field plate structure includes: a first dielectric layer 131 covering the surface of the substrate (the upper surface of the gate dielectric layer on the substrate) and the surface of the gate structure; a first metal layer 141 located on the first dielectric layer, the first metal layer 141 extends from a portion of the upper surface of the gate structure, through the side surface of the gate structure, to the top of the epitaxial layer; an nth dielectric layer covering the surface of the n-1 metal layer and the n-1 dielectric layer; and an nth metal layer formed on the nth dielectric layer, the nth metal layer extending from a portion of the upper surface of the n-1 metal layer toward the drain region, wherein n is greater than or equal to 2. In this embodiment, the field plate structure includes a first dielectric layer 131 and a first metal layer 141, a second dielectric layer 132 and a second metal layer 142, and a third dielectric layer 133 and a third metal layer 143, wherein the first metal layer 141, the second metal layer 142 and the third metal layer 143 are field plate electrodes. In the lateral direction, the first metal layer 141, the second metal layer 142 and the third metal layer 143 are arranged in sequence in the direction of the drain region, and in the transistor stacking direction, the projections of the first metal layer 141, the second metal layer 142 and the third metal layer 143 in the vertical direction partially overlap.

[0061] The field plate electrodes (the first metal layer 141 , the second metal layer 142 and the third metal layer 143 ) are connected to a reference ground potential to reduce gate-drain parasitic capacitance.

[0062] The transistor also includes an interlayer dielectric layer 134 located on the epitaxial layer and covering the surface of the device, a conductive channel 170 extending through the interlayer dielectric layer to the first metal silicide and a conductive channel 180 extending to the second metal silicide, metal layers 190 and 191 located on the conductive channels, and a back electrode 160 located on the back side of the substrate.

[0063] Please refer to Figure 5 , which is a flow chart of a method for manufacturing a connecting structure according to an embodiment of the present invention. Figure 5 As shown, the method for manufacturing the communication structure includes steps S11 to S13. Figure 5 The manufacturing method of the interconnecting structure shown can be applied to Figure 1 The connection structure shown in FIG. Figure 6a-6b 2 is a cross-sectional view of various stages of a method for manufacturing a connecting structure according to an embodiment of the present invention.

[0064] Step S11: forming at least one trench in the epitaxial layer on the upper surface of the substrate, wherein the trench extends from the upper surface of the epitaxial layer to the interior thereof. Figure 6a As shown, an epitaxial layer 102 is formed on the upper surface of the substrate 101 by an epitaxial growth process. The substrate and the epitaxial layer may be selected from Si materials. Of course, in other embodiments, the substrate and the epitaxial layer may also be selected from other semiconductor materials, such as SiC, GaN materials, etc. Specifically, the groove is formed by an etching process, and the etching process is preferably a dry etching process. The etching depth of the groove is set to 2 to 10um, and the width of the groove is set to 0.5 to 2um. Preferably, the etching depth of the groove is set to half the thickness of the epitaxial layer. In this embodiment, the number of the grooves is set to 2, and the two grooves are set at intervals. Of course, in other embodiments, the grooves may also be set to 1, 3, etc., and the number of grooves is not limited here.

[0065] Step S12: Filling a filling material including a dopant into the trench 103, wherein the filling material is of the first doping type and the doping concentration of the filling material is set to 1e18 / cm 2 ~1e21 / cm 2 , the higher the doping concentration of the filling material, the better. In this embodiment, the first doping type is P type, and the dopant is preferably boron. Of course, in other embodiments, the dopant may also include other trivalent elements such as indium and gallium. In addition, when the first doping type is N type, the dopant may include pentavalent elements such as phosphorus, nitrogen, and arsenic. The filling material is preferably polysilicon material.

[0066] Step S13: A diffusion process is used to diffuse the dopant into the epitaxial layer 102 to form a doped region 104 below the trench 103, wherein the doped region 104 is diffused at least to contact the upper surface of the substrate 101, as shown in Figure 6b. The diffusion process is a high-temperature push-junction process. It should be noted that in the actual process, the dopant will diffuse not only into the epitaxial layer at the bottom of the trench 103, but also into the epitaxial layer on the side of the trench 103 (not shown in the figure) during the diffusion process into the epitaxial layer 102. Figure 6b The doping region 104 in the figure is only a schematic diagram, and the specific shape of the doping region is determined according to the diffusion conditions of the specific actual process.

[0067] Please refer to Figure 7 , is a flow chart of a method for manufacturing a transistor according to an embodiment of the present invention, the method for manufacturing a transistor includes steps S21 to S27, wherein steps S21 to S22 and Figure 5 The steps S11 to S13 shown are the same and will not be repeated here. Figure 7 The transistor manufacturing method shown can be applied to Figure 2-3 The transistor shown is, but not limited to, this.

[0068] S23: forming a gate structure on the upper surface of the epitaxial layer. Figure 8a As shown, a gate dielectric layer 105 is first formed on the upper surface of the epitaxial layer 102, and then a gate conductor 106 is formed on the gate dielectric layer 105. Further, optionally, a metal silicide 107 is formed on the gate conductor 106. The epitaxial layer 102 is of the first doping type, and the substrate 101 is of the first doping type.

[0069] The gate dielectric layer 105 is configured as an oxide layer prepared by a dry oxygen process, and the gate dielectric layer 105 at least covers the upper surface of the epitaxial layer below the gate conductor 106. In this embodiment, the gate dielectric layer 105 covers the entire upper surface of the epitaxial layer 102. In an optional embodiment, before forming the gate dielectric layer 105, an isolation insulating layer 801 is formed at an edge region of the upper surface of the epitaxial layer 102, the isolation insulating layer 801 is adjacent to the connecting structure, and the isolation insulating layer 801 defines the active region of the transistor. At this time, the gate dielectric layer 105 covers the upper surface of the epitaxial layer 102 exposed by the isolation insulating layer 801.

[0070] Specifically, a conductor layer is deposited on the gate dielectric layer 105, a metal silicide is deposited on the conductor layer, and then the conductor layer and the metal silicide are partially etched to form a gate dielectric layer 105. Figure 8a The gate conductor 106 and the third metal silicide 107 are shown. The gate conductor 106 is preferably a polysilicon material, and further preferably a polysilicon material of a high concentration of the second doping type, so as to reduce the gate resistance and improve the device radio frequency performance. The metal silicide is preferably a WSi alloy.

[0071] S24: forming a drift region of a second doping type and a body region of a first doping type in the epitaxial layer, and forming a source region and a drain region of a second doping type in the body region and the drift region, respectively, wherein the second doping type is opposite to the first doping type.

[0072] like Figure 8bAs shown, specifically, a drift region 108 is formed in the epitaxial layer 102 by ion implantation in a gate self-alignment process, and then a body region 109 is formed in the epitaxial layer 102 by ion implantation in a gate self-alignment process, wherein the body region 109 is adjacent to the connection structure, and the drift region 108 and the body region 109 are respectively located on both sides of the gate, and the body region 109 is laterally extended to the bottom of the gate structure by a high temperature activation push junction process. The formation of the drift region 108 can ensure that the transistor has a high breakdown voltage and meet the application requirements of the transistor. The body region improves the threshold voltage required for the transistor, and at the same time, it limits the electric field between the gate and the drain together with the drift region, thereby controlling the hot carrier effect of the transistor and improving the reliability of the device.

[0073] Finally, by ion implantation, a drain region 110 and a source region 112 are simultaneously formed in the drift region 108 and the body region 109 , respectively. A body contact region 111 adjacent to the source region 112 is formed in the body region 109 .

[0074] S25: Form metal silicide on the drain region 110, the source region 112 and the connecting structure respectively. Specifically, firstly etch the gate dielectric layer covering the drain region 110, the source region 112, the body contact region 111 and the upper surface of the connecting structures 103 and 104 to expose the upper surface of the drain region 110, the source region 112, the body contact region 111 and the connecting structure; then deposit metal on the upper surface of the drain region 110, the source region 112, the body contact region 111 and the connecting structure; and form metal silicide by annealing process. In this embodiment, the metal is Ti metal and the metal silicide is TiSi alloy. Figure 8c As shown, a first metal silicide 114 is formed in contact with the drain region 110, and a second metal silicide 113 is formed in contact with the source region 112, the body contact region 111 and the connecting structure to achieve connection between the source region 112 and the connecting structure.

[0075] S26: forming a field plate structure. Specifically, forming a field plate structure on the epitaxial layer, the field plate structure comprising at least one field plate electrode, the field plate electrode being located at least between the gate structure and the drain region. When the field plate structure comprises at least two field plate electrodes, the at least two field plate electrodes are spaced apart, and projections of two adjacent field plate electrodes in the vertical direction partially overlap.

[0076] like Figure 8dAs shown, the method for forming the field plate structure includes: depositing a first dielectric layer 131 on the surface of the gate dielectric layer (or the surface of the epitaxial layer) and the surface of the gate structure; forming a first metal layer 141 on the first dielectric layer 131, the first metal layer 141 extending from a portion of the upper surface of the gate structure, through the side surface of the gate structure, to the top of the epitaxial layer; depositing a second dielectric layer 132 on the surfaces of the first metal layer 141 and the first dielectric layer 131; forming a second metal layer 142 on the second dielectric layer 132, the second metal layer 142 extending from a portion of the upper surface of the first metal layer 141 toward the drain region; repeating steps S3 and S4 in sequence to form an nth dielectric layer and an nth metal layer, where n is greater than or equal to 2. In this embodiment, n is equal to 3, that is, the field plate electrode includes a first metal layer 141, a second metal layer 142 and a third metal layer 143.

[0077] It should be noted that manufacturing Figure 2 When the transistor is shown, the method for manufacturing the transistor does not include step S26.

[0078] S27: Forming interlayer dielectric layers, conductive channels, interconnecting metals and back electrodes. Figure 8e As shown, an interlayer dielectric layer 134 is deposited to cover Figure 8c or the upper surface of the structure shown in 8d, and then the upper surface of the interlayer dielectric layer is flattened by chemical mechanical polishing technology; then, the interlayer dielectric layer is partially etched to form a conductive via that passes through the interlayer dielectric layer and extends to the first metal silicide and the second metal silicide, and metal is filled in the conductive via to form conductive channels 170 and 180; then, interconnection metals 190 and 191 are formed on the conductive channels. It should be noted that, according to the requirements of the specific transistor, a conductive channel and interconnection metal with a structure of more than or equal to 1 layer can be formed.

[0079] Finally, a passivation layer is formed on the interconnection metal, the substrate 101 is thinned, and a back metal is deposited on the back side of the substrate to form a back electrode 160 .

[0080] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a communication structure, characterized in that: include: forming at least one trench in the epitaxial layer located on the upper surface of the substrate, wherein the trench extends from the upper surface of the epitaxial layer to the interior thereof; Filling a filling material including a dopant into the trench; as well as The dopant is diffused into the epitaxial layer by a diffusion process to form a doped region below the trench. The doped region is diffused at least to contact the upper surface of the substrate.

2. The method according to claim 1, characterized in that The depth of the trench is set to be greater than three eighths of the thickness of the epitaxial layer and less than five eighths of the thickness of the epitaxial layer.

3. The method according to claim 1, characterized in that The doping concentration of the filling material is set to 1e18-1e21 / cm 2 .

4. The method according to claim 1, characterized in that: The diffusion process is a high temperature push-junction process.

5. The method according to claim 1, characterized in that The dopant includes a trivalent element or a pentavalent element.

6. The method according to claim 1, characterized in that When the connecting structure is applied to the interconnection between the source and the substrate in a MOS transistor, the upper surface of the trench is connected to the source, the epitaxial layer is set to the first doping type, the substrate is set to the first doping type, and the connecting structure is set to the first doping type.

7. The method according to claim 1, characterized in that When the connecting structure is applied to an isolation structure in a device, the connecting structure is set to a first doping type and the epitaxial layer is set to a second doping type, wherein the first doping type is set to one of n-type or P-type and the second doping type is set to the other of n-type or P-type.

8. A method for manufacturing a transistor, characterized in that: include: The connecting structure is formed by the method for manufacturing the connecting structure according to any one of claims 1 to 5; forming a gate structure on an upper surface of the epitaxial layer; as well as forming a source region and a drain region of a second doping type in the epitaxial layer; Among them, the connecting structure is set to a first doping type, and the epitaxial layer is set to a first doping type, wherein the first doping type is set to one of n-type and P-type, and the second doping type is set to the other of n-type and P-type.

9. The method according to claim 8, characterized in that Also includes: forming a drift region of a second doping type and a body region of a first doping type in the epitaxial layer, wherein the drain region is located in the drift region and the source region is located in the body region; as well as A body contact region of the first doping type is also formed in the body region adjacent to the source region.

10. The method according to claim 8, characterized in that The method further includes forming a first metal silicide on the upper surface of the drain region, and forming a second metal silicide on the upper surfaces of the source region and the connecting structure to achieve connection between the connecting structure and the source region.

11. The method according to claim 8, characterized in that A field plate structure is formed on the epitaxial layer, wherein the field plate structure includes at least one field plate electrode, and the field plate electrode is at least located between the gate structure and the drain region.

12. The method according to claim 11, characterized in that When the field plate structure includes at least two field plate electrodes, the at least two field plate electrodes are arranged at intervals, and projections of two adjacent field plate electrodes in the vertical direction partially overlap.

13. The method according to claim 12, characterized in that The method of forming the field plate structure includes: S1: depositing a first dielectric layer on the surface of the substrate and the surface of the gate structure; S2: forming a first metal layer on the first dielectric layer, wherein the first metal layer extends from a portion of the upper surface of the gate structure, through the side surface of the gate structure, to above the epitaxial layer; S3: depositing a second dielectric layer on the surface of the first metal layer and the first dielectric layer; S4: forming a second metal layer on the second dielectric layer, wherein the second metal layer extends from a portion of an upper surface of the first metal layer toward the drain region; Steps S3 and S4 are repeated in sequence to form an nth dielectric layer and an nth metal layer, wherein n is greater than or equal to 2.

14. The method according to claim 10, characterized in that Also includes: forming an interlayer dielectric layer covering the epitaxial layer and the gate structure; Forming conductive channels penetrating the interlayer dielectric layer and extending to the first metal silicide, the second metal silicide and the gate structure respectively; forming a metal layer on the conductive path, and A back electrode is formed on the back side of the substrate.

15. A communication structure, characterized in that: include: at least one trench extending from an upper surface of an epitaxial layer on a substrate to an interior of the epitaxial layer; A filling material including a dopant filled in the trench, and A doped region extends from the lower surface of the trench at least to the upper surface of the substrate, and the doped region is formed by diffusion of dopants in the filling material.

16. The communication structure according to claim 15, characterized in that: The depth of the trench is set to be greater than three eighths of the thickness of the epitaxial layer and less than five eighths of the thickness of the epitaxial layer.

17. The communication structure according to claim 15, characterized in that: The doping concentration of the filling material is set to 1e18-1e21 / cm 2 .

18. The communication structure according to claim 1, characterized in that: The dopant includes a trivalent element or a pentavalent element.

19. The communication structure according to claim 15, characterized in that: When the connecting structure is applied to the interconnection between the source and the substrate in a MOS transistor, the upper surface of the trench is connected to the source, the epitaxial layer is set to the first doping type, the substrate is set to the first doping type, and the filling material is set to the first doping type.

20. The communication structure according to claim 15, characterized in that: When the connecting structure is applied to an isolation structure in a device, the connecting structure is set to a first doping type and the epitaxial layer is set to a second doping type, wherein the first doping type is set to one of n-type or P-type and the second doping type is set to the other of n-type or P-type.

21. A transistor, characterized in that: include: The connection structure according to claims 15-18; a source region and a drain region of a second doping type extending from the upper surface of the epitaxial layer to the interior thereof; A gate structure, located on the upper surface of the epitaxial layer and at least above the channel region between the source region and the drain region; as well as Among them, the connecting structure is set to a first doping type, and the epitaxial layer is set to a first doping type, wherein the first doping type is set to one of n-type and P-type, and the second doping type is set to the other of n-type and P-type.

22. The transistor according to claim 21, characterized in that Also includes: a drift region of a second doping type and a body region of a first doping type located in the substrate, wherein the drain region is located in the drift region and the source region is located in the body region; as well as A body contact region of the first doping type is located in the body region and adjacent to the source region.

23. The transistor according to claim 21, characterized in that It also includes a first metal silicide located on the upper surface of the drain region, and a second metal silicide located on the upper surfaces of the source region and the connecting structure, so as to realize the connection between the connecting structure and the source region.

24. The transistor according to claim 21, characterized in that A field plate structure is located on the epitaxial layer, wherein the field plate structure comprises at least one field plate electrode, and the field plate electrode is at least located between the gate structure and the drain region.

25. The transistor according to claim 24, characterized in that When the field plate structure includes at least two field plate electrodes, the at least two field plate electrodes are arranged at intervals, and projections of two adjacent field plate electrodes in the vertical direction partially overlap.

26. The transistor according to claim 25, characterized in that The field plate structure comprises: A first dielectric layer covering the surface of the substrate and the surface of the gate structure; a first metal layer located on the first dielectric layer, the first metal layer extending from a portion of the upper surface of the gate structure, through the side surface of the gate structure, to above the epitaxial layer; an nth dielectric layer covering surfaces of the n-1th metal layer and the n-1th dielectric layer; and An nth metal layer is formed on the nth dielectric layer, and the nth metal layer extends from a portion of the upper surface of the n-1th metal layer toward the drain region, wherein n is greater than or equal to 2.

27. The transistor according to claim 23, characterized in that Also includes: an interlayer dielectric layer covering the epitaxial layer and the gate structure; A conductive channel penetrating the interlayer dielectric layer and contacting the first metal silicide, the second metal silicide and the gate structure respectively; a metal layer located on the conductive path, and A back electrode is located on the back side of the substrate.

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