Novel AlGaN / GaN HEMT epitaxial structure and preparation method thereof

Abstract

The invention discloses a novel AlGaN / GaN HEMT epitaxial structure and a preparation method thereof. The novel AlGaN / GaN HEMT epitaxial structure comprises a substrate layer, and a stress structure debugging layer used for adjusting and balancing stress in an epitaxial layer and preventing stress concentration is arranged above the substrate layer; a defect control layer for controlling and reducing defects in the epitaxial layer and improving the quality of the epitaxial layer is arranged above the stress structure debugging layer; an impurity compensation layer for compensating impurities in the epitaxial layer and improving the electrical performance of the device is arranged above the defect control layer; by introducing structural technologies such as stress debugging, defect control and impurity compensation into an AlGaN / GaN HEMT epitaxial layer, the problems of cracks, current collapse, longitudinal breakdown and the like caused by overlarge stress of a traditional structure are effectively solved, and the performance and the stability of the device are improved. In addition, by optimizing growth conditions, optimization of high electron mobility and low leakage current can be realized, and the performance of the device is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a novel AlGaN / GaN HEMT epitaxial structure and a preparation method thereof. Background Art

[0002] AlGaN / GaN high electron mobility transistors (HEMTs) have become the preferred material for high-frequency and high-power electronic devices due to their excellent electron mobility and breakdown voltage.

[0003] However, in the traditional AlGaN / GaN HEMT epitaxial structure, stress, defects, and impurities may affect the performance and stability of the device. In order to solve these problems, it is necessary to develop a new epitaxial structure to improve the performance and stability of the device.

[0004] Therefore, a novel AlGaN / GaN HEMT epitaxial structure and a preparation method thereof are proposed. Summary of the invention

[0005] The object of the present invention is to provide a novel AlGaN / GaN HEMT epitaxial structure and a preparation method thereof, so as to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions: a novel AlGaN / GaN HEMT epitaxial structure, comprising a substrate layer, a stress structure adjustment layer for adjusting and balancing stress in the epitaxial layer to prevent stress concentration is provided above the substrate layer; A defect control layer is provided above the stress structure adjustment layer for controlling and reducing defects in the epitaxial layer and improving the quality of the epitaxial layer; An impurity compensation layer is provided above the defect control layer for compensating for impurities in the epitaxial layer and improving the electrical performance of the device; A transport layer having high electron mobility and serving as a main transport region for electrons is provided above the impurity compensation layer; A barrier layer for forming a conductive channel of the device and controlling the flow of electrons is provided above the transport layer; A Cap layer is disposed above the barrier layer.

[0007] Preferably: the stress structure adjustment layer includes a first stress adjustment sublayer and a second stress adjustment sublayer; The first stress adjustment sublayer is an AlN single crystal semiconductor multilayer material, and the second stress adjustment sublayer is an AlxGa-xN multilayer structure.

[0008] Preferably, the number of layers of the first stress adjustment sub-layer is 2 to 5, the thickness of a single layer is 20 to 100 nm, and the total thickness is 40 to 500 nm.

[0009] Preferably, the number of layers of the second stress adjustment sub-layer is 2 to 5, the value of x is between 50% and 90%, the thickness of a single layer is 10 to 100 nm, and the total thickness is 20 to 500 nm.

[0010] Preferably: the structure of the defect control layer is an AlxGa1-xN / AlyGa1-yN superlattice structure, wherein x>y, 50%≤x≤100%, 10%≤y<100%, the superlattice range n is 20~150, the thickness of a single period is 10~30nm, and the total thickness of the defect control layer is 200~4500nm.

[0011] Preferably, the impurity compensation layer is a doped GaN layer, the doping source is a C- or Fe-containing compound, and the total thickness is 500-5000 nm.

[0012] Preferably, the total thickness of the transmission layer is 100-1000 nm.

[0013] Preferably, the barrier layer is an AlxGa1-xN layer, and the barrier layer is a single layer or multi-layer structure, wherein the range of x is between 10% and 50%.

[0014] Preferably, the Cap layer is a non-artificially doped GaN layer or a SiN layer or an artificially doped P-type GaN layer.

[0015] A method for preparing a novel AlGaN / GaN HEMT epitaxial structure according to any one of the above items comprises the following steps: S1. Select materials with high thermal conductivity and low thermal expansion coefficient as the substrate layer, and clean and pre-treat them; S2, growing a stress structure adjustment layer on the substrate layer, wherein the growth temperature of the first stress adjustment sub-layer is 600-1200° C., which is a step-wise increase; The growth temperature of the second stress adjustment sublayer is between 800 and 1200°C, and the stress reduction and balance are achieved by adjusting the growth conditions; S3, growing a defect control layer on the stress structure adjustment layer, and controlling and reducing defects by adjusting growth conditions; S4, growing an impurity compensation layer on the defect control layer, and compensating for impurities by adjusting growth conditions; S5. growing a transport layer on the impurity compensation layer at a growth temperature of 1000-1250° C., and achieving high electron mobility by adjusting the growth conditions; S6, growing a barrier layer on the transmission layer to form a conductive channel of the device; S7. Growing a Cap layer on the barrier layer.

[0016] Compared with the prior art, the beneficial effects of the present invention are: by introducing a stress adjustment layer into the AlGaN / GaN HEMT epitaxial layer to optimize stress relaxation, the defect control layer structure blocks dislocation defects from extending upward to the electron conduction layer, reducing the capture of electrons by traps; the above structural technology effectively solves the problems of excessive stress cracks, current collapse, longitudinal breakdown, etc. in the traditional structure, and improves the performance and stability of the device. In addition, by optimizing the growth conditions, the optimization of high electron mobility and low leakage current can be achieved, further improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 is a flow chart of the preparation method of the present invention; Figure 3 A schematic diagram of a second stress adjustment sub-layer of the present invention; Figure 4 is a schematic diagram of a defect control layer of the present invention; Figure 5 is a comparison diagram of edge cracks in Example 1 of the present invention; Figure 6 It is a schematic diagram of epitaxial vertical withstand voltage in Example 1 of the present invention; Figure 7 Schematic diagram for comparing the warping of the epitaxial wafer in Example 2 of the present invention; Figure 8 It is a comparison chart of the epitaxial vertical withstand voltage of Example 1 and Example 2 of the present invention.

[0018] In the figure: 1, substrate layer; 2, stress structure adjustment layer; 21, first stress adjustment sublayer; 22, second stress adjustment sublayer; 3, defect control layer; 4, impurity compensation layer; 5, transmission layer; 6, barrier layer; 7, Cap layer. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0020] See also Figure 1-Figure 8 The present invention provides a technical solution: a novel AlGaN / GaN HEMT epitaxial structure, providing a semiconductor substrate layer 1, the substrate layer 1 can be silicon, sapphire or silicon carbide but not limited to the above, growing an epitaxial layer on the substrate layer 1, wherein the epitaxial functional layer includes the following layers: Stress structure adjustment layer 2: located above the substrate layer 1, it adjusts and balances the stress in the epitaxial layer by adjusting stress relaxation to prevent stress concentration.

[0021] The stress structure adjustment layer 2 includes a first stress adjustment sublayer 21 and a second stress adjustment sublayer 22; the first stress adjustment sublayer 21 is an AlN single crystal semiconductor multilayer material, wherein the multilayer is expressed as n between 2 and 5; the growth temperature is increased from 600 to 1200°C in a stepwise manner, the single layer thickness ranges from 20 to 100 nm, and the total thickness is 40 to 500 nm. The stepwise increase means that each growth layer tends to grow at a constant temperature.

[0022] The second stress adjustment sublayer 22 is an AlxGa1-xN multilayer structure, such as Figure 3 As shown, the multilayer is expressed as n between 2 and 5, x is between 50% and 90%, the growth temperature is between 800 and 1200°C, the multilayer structure is expressed as a decreasing trend of x from bottom to top, the single layer thickness ranges from 10 to 100 nm, and the total thickness ranges from 20 to 500 nm.

[0023] Defect control layer 3: located on the stress structure adjustment layer 2, it forces the longitudinal dislocation to turn through the heterojunction interface, controls and reduces the defects in the epitaxial layer, and improves the quality of the epitaxial layer. The structure of the defect control layer 3 is an AlxGa1-xN / AlyGa1-yN superlattice structure, such as Figure 4 As shown, where x>y, 50%≤x≤100%, 10%≤y<100%, the superlattice range n is 20~150, the single period thickness is 10~30nm, and the total thickness of the defect control layer is in the range of 200~4500nm.

[0024] Impurity compensation layer 4: located on the defect control layer 3, used to compensate for impurities in the epitaxial layer and improve the electrical performance of the device.

[0025] The compensation layer is a doped GaN layer, the doping source contains C or Fe compounds, not limited to C2H4, CP2Fe, and the compensation doping is enhanced along the growth direction gradient, with a total thickness of 500 to 5000nm.

[0026] Transport layer 5: located on the impurity compensation layer 4, as the main electron transport region, with high electron mobility. The growth temperature is in the range of 1000-1250°C, and the thickness is between 100-1000nm.

[0027] Barrier layer 6: located on the transport layer 5, used to form a conductive channel of the device and control the flow of electrons. The barrier layer 6 is an AlxGa1-xN layer, including a single layer or a multilayer structure, where x ranges from 10% to 50%, and the multilayer structure is x decreasing growth.

[0028] A Cap layer 7 is grown on the barrier layer 6 and may be a non-artificially doped GaN layer or SiN layer or an artificially doped P-type GaN layer.

[0029] Embodiment 1:

[0030] The substrate layer 1 is a silicon epitaxial layer grown on the substrate layer 1, wherein the epitaxial functional layer includes the following layers: Stress structure adjustment layer 2: located above the substrate layer 1, it adjusts and balances the stress in the epitaxial layer by adjusting stress relaxation to prevent stress concentration.

[0031] The stress structure adjustment layer 2 includes a first stress adjustment sublayer 21 and a second stress adjustment sublayer 22; the first stress adjustment sublayer 21 is an AlN single crystal semiconductor multilayer material, wherein the multilayer is represented by n being 2; the growth temperature is 600°C, which is a step-by-step increase, the single layer thickness range is 20nm, and the total thickness is 40nm. The step-by-step increase means that each growth layer tends to grow at a constant temperature.

[0032] The second stress adjustment sublayer 22 is an AlxGa1-xN multilayer structure, wherein the multilayer is expressed as n is 2, x is 50%, the growth temperature is 800°C, the multilayer structure is expressed as a decreasing trend of x from bottom to top, the single layer thickness range is 10nm, and the total thickness range is 20nm.

[0033] Defect control layer 3: Located on the stress structure adjustment layer 2, it forces the longitudinal dislocation to turn through the heterojunction interface, controls and reduces the defects in the epitaxial layer, and improves the quality of the epitaxial layer. The structure of defect control layer 3 is AlxGa1-xN / AlyGa1-yN superlattice structure, where x>y, x=90%, y=10%, superlattice range n is 80, single period thickness is 30nm, and the total thickness of the defect control layer is 2400nm.

[0034] Impurity compensation layer 4: located on the defect control layer 3, used to compensate for impurities in the epitaxial layer and improve the electrical performance of the device.

[0035] The compensation layer is a doped GaN layer, the doping source contains C or Fe compounds, not limited to C2H4, CP2Fe, and the compensation doping is enhanced along the growth direction gradient, with a total thickness of 500nm.

[0036] Transport layer 5: located on the impurity compensation layer 4, serving as the main electron transport region, with high electron mobility. The growth temperature is 1000°C and the thickness is 500nm.

[0037] Barrier layer 6: located on the transmission layer 5, used to form a conductive channel of the device and control the flow of electrons. The barrier layer 6 is an AlxGa1-xN layer, including a single layer or a multilayer structure, where x is 25%, and the multilayer structure is x decreasing growth.

[0038] A Cap layer 7 is grown on the barrier layer 6 and is an in-situ grown SiN layer.

[0039] like Figure 5As shown in Figure 1, the thermal expansion coefficient stress of the silicon-based substrate is well controlled, and the edge crack is less than 1 mm. Figure 6 As shown, after the defect control layer and impurity compensation, different points of the same epitaxial film maintain the same high withstand voltage and low leakage characteristics; the vertical withstand voltage VBD>1200V, and the isolation leakage @700v<1E-7A.

[0040] Embodiment 2:

[0041] The substrate layer 1 may be a silicon epitaxial layer grown on the substrate layer 1, wherein the epitaxial functional layer includes the following layers: Stress structure adjustment layer 2: located above the substrate layer 1, it adjusts and balances the stress in the epitaxial layer by adjusting stress relaxation to prevent stress concentration.

[0042] The stress structure adjustment layer 2 includes a first stress adjustment sub-layer 21 and a second stress adjustment sub-layer 22; the first stress adjustment sub-layer 21 is an AlN single crystal semiconductor multilayer material, wherein the multilayer is represented by n being 4; the growth temperature is increased stepwise from 900°C, the single layer thickness is 50nm, and the total thickness is 200nm. The stepwise increase means that each growth layer tends to grow at a constant temperature.

[0043] The second stress adjustment sublayer 22 is an AlxGa1-xN multilayer structure, wherein the multilayer is expressed as n is 4, x is 70%, the growth temperature is 1000°C, the multilayer structure is expressed as a decreasing trend of x from bottom to top, the single layer thickness range is 30nm, and the total thickness range is 120nm.

[0044] Defect control layer 3: Located on the stress structure adjustment layer 2, it forces the longitudinal dislocation to turn through the heterojunction interface, controls and reduces the defects in the epitaxial layer, and improves the quality of the epitaxial layer. The structure of defect control layer 3 is AlxGa1-xN / AlyGa1-yN superlattice structure, where x>y, x=70%, y=30%, superlattice range n is 50, single period thickness is 15nm, and the total thickness of the defect control layer is 750nm.

[0045] Impurity compensation layer 4: located on the defect control layer 3, used to compensate for impurities in the epitaxial layer and improve the electrical performance of the device.

[0046] The compensation layer is a doped GaN layer, the doping source contains C or Fe compounds, not limited to C2H4, CP2Fe, and the compensation doping is enhanced along the growth direction gradient, with a total thickness of 2000nm.

[0047] Transport layer 5: located on the impurity compensation layer 4, serving as the main electron transport region, with high electron mobility. The growth temperature is 1150°C and the thickness is 400nm.

[0048] Barrier layer 6: located on the transmission layer 5, used to form a conductive channel of the device and control the flow of electrons. The barrier layer 6 is an AlxGa1-xN layer, including a single layer or a multilayer structure, where x is 27%, and the multilayer structure is x decreasing growth.

[0049] A Cap layer 7 is grown on the barrier layer 6 and is an in-situ grown SiN layer.

[0050] like Figure 7 As shown, the warpage of the epitaxial wafer is reduced from 30um to a maximum of 10um, which expands the process space for mass production and improves the mass production yield.

[0051] like Figure 8 As shown, the vertical withstand voltage of Application Example 2 meets the 900V requirement when compared with that of Application Example 1. The withstand voltage of Application Example 2 is 10% lower. Application Example 1 is suitable for high voltage and high power (>1000V@30A) applications, such as vehicle-mounted applications, which have relatively high costs and high additional prices. Application Example 2 is suitable for high voltage and low power (>800V@5A) applications, which are more concentrated in consumer electronics, such as fast charging.

[0052] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A novel AlGaN / GaN HEMT epitaxial structure, comprising a substrate layer (1), characterized in that: A stress structure adjustment layer (2) is provided above the substrate layer (1) for adjusting and balancing the stress in the epitaxial layer to prevent stress concentration; A defect control layer (3) is provided above the stress structure adjustment layer (2) for controlling and reducing defects in the epitaxial layer and improving the quality of the epitaxial layer; An impurity compensation layer (4) is provided above the defect control layer (3) for compensating for impurities in the epitaxial layer and improving the electrical performance of the device; A transport layer (5) having a high electron mobility and serving as a main electron transport region is provided above the impurity compensation layer (4); A barrier layer (6) for forming a conductive channel of the device and controlling the flow of electrons is provided above the transport layer (5); A Cap layer (7) is provided above the barrier layer (6).

2. The novel AlGaN / GaN HEMT epitaxial structure according to claim 1, characterized in that: The stress structure adjustment layer (2) comprises a first stress adjustment sub-layer (21) and a second stress adjustment sub-layer (22); The first stress adjustment sub-layer (21) is an AlN single crystal semiconductor multi-layer material, and the second stress adjustment sub-layer (22) is an AlxGa1-xN multi-layer structure.

3. The novel AlGaN / GaN HEMT epitaxial structure according to claim 2, characterized in that: The number of layers of the first stress adjustment sublayer (21) is 2 to 5, the thickness of a single layer is 20 to 100 nm, and the total thickness is 40 to 500 nm.

4. The novel AlGaN / GaN HEMT epitaxial structure according to claim 2, characterized in that: The number of layers of the second stress adjustment sublayer (22) is 2 to 5, the value of x is between 50% and 90%, the thickness of a single layer is 10 to 100 nm, and the total thickness is 20 to 500 nm.

5. The novel AlGaN / GaN HEMT epitaxial structure according to claim 1, characterized in that: The structure of the defect control layer (3) is an AlxGa1-xN / AlyGa1-yN superlattice structure, wherein x>y, 50%≤x≤100%, 10%≤y<100%, the superlattice range n is 20-150, the thickness of a single period is 10-30nm, and the total thickness of the defect control layer (3) is 200-4500nm.

6. The novel AlGaN / GaN HEMT epitaxial structure according to claim 1, characterized in that: The impurity compensation layer (4) is an artificially doped GaN layer, the doping source is a C- or Fe-containing compound, and the total thickness is 500 to 5000 nm.

7. The novel AlGaN / GaN HEMT epitaxial structure according to claim 1, characterized in that: The total thickness of the transmission layer (5) is 100 to 1000 nm.

8. The novel AlGaN / GaN HEMT epitaxial structure according to claim 1, characterized in that: The barrier layer (6) is an AlxGa1-xN layer, and the barrier layer (6) is a single layer or multilayer structure, wherein the range of x is between 10% and 50%.

9. The novel AlGaN / GaN HEMT epitaxial structure according to claim 1, characterized in that: The Cap layer (7) is a non-artificially doped GaN layer or a SiN layer or an artificially doped P-type GaN layer.

10. A method for preparing an epitaxial structure according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1. Select a material with high thermal conductivity and low thermal expansion coefficient as the substrate layer (1), and perform cleaning and pretreatment; S2, growing a stress structure adjustment layer (2) on the substrate layer (1), wherein the growth temperature of the first stress adjustment sublayer (21) is 600-1200° C., which is a step-wise increase; The growth temperature of the second stress adjustment sublayer (22) is between 800°C and 1200°C, and stress reduction and balance are achieved by adjusting the growth conditions; S3, growing a defect control layer (3) on the stress structure adjustment layer (2), and controlling and reducing defects by adjusting growth conditions; S4, growing an impurity compensation layer (4) on the defect control layer (3), and compensating for impurities by adjusting growth conditions; S5, growing a transport layer (5) on the impurity compensation layer (4), with a growth temperature of 1000 to 1250° C., and achieving high electron mobility by adjusting the growth conditions; S6, growing a barrier layer (6) on the transmission layer (5) to form a conductive channel of the device; S7. Growing a Cap layer (7) on the barrier layer (6).

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