Semiconductor device and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises an insulating core, a semiconductor column and a gate structure, the semiconductor column surrounds the insulating core, and the semiconductor column comprises a source region, a channel region and a drain region along a first direction; the first direction is the height direction of the insulating core; the gate structure surrounds the channel region.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of integrated circuits, people began to pursue smaller device size, higher device density and higher performance, which led to the design development of field effect transistors.

[0003] In field effect transistors, vertical transistors are produced in order to reduce the planar size of transistors. However, as the size of transistors continues to shrink, the structure of vertical transistors needs to be further improved to meet design requirements. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: an insulating core, a semiconductor column and a gate structure; the semiconductor column surrounds the insulating core, and the semiconductor column includes a source region, a channel region and a drain region along a first direction; the first direction is a height direction of the insulating core; the gate structure surrounds the channel region.

[0007] In some embodiments, the gate structure includes a gate dielectric layer surrounding the channel region, and a gate layer surrounding the gate dielectric layer; the side of the gate layer away from the gate dielectric layer includes a gate contact layer; the side of the source region and the drain region away from the channel region include a source contact layer and a drain contact layer respectively; the materials of the gate contact layer, the source contact layer and the drain contact layer include metal silicide.

[0008] In some embodiments, a dimension of the insulating core along a second direction is greater than or equal to 10 angstroms, and the second direction is perpendicular to the first direction.

[0009] In some embodiments, a dimension of the channel region along a second direction is less than or equal to 40 angstroms, and the second direction is perpendicular to the first direction.

[0010] In some embodiments, a projection shape of the insulating core on a first plane includes a circle or a polygon, and the first plane is perpendicular to the first direction.

[0011] In a second aspect, an embodiment of the present disclosure also provides a method for preparing a semiconductor device, comprising: providing a base structure; the base structure comprises a substrate and a stacked structure, the stacked structure comprises a first insulating layer, an initial gate layer and a second insulating layer; forming an integrated structure in the stacked structure, the integrated structure comprises an insulating core, a semiconductor column surrounding the insulating core; the semiconductor column comprises a source region, a channel region and a drain region along a first direction; the first direction is a height direction of the insulating core; the initial gate layer surrounds the integrated structure.

[0012] In some embodiments, forming an integrated structure in the stacked structure includes: forming a first through hole penetrating the stacked structure, and forming the integrated structure through the first through hole.

[0013] In some embodiments, before forming the integrated structure, the process further includes: replacing a portion of the initial gate layer with a gate dielectric layer through the first through hole, the gate dielectric layer surrounds the integrated structure, and the remaining initial gate layer surrounds the gate dielectric layer.

[0014] In some embodiments, after forming the gate dielectric layer, it includes: forming an initial semiconductor column through the first through hole, the initial semiconductor column including an initial source region, an initial channel region and an initial drain region along a first direction; forming a second through hole passing through the initial semiconductor column, and forming the insulating core through the second through hole.

[0015] In some embodiments, the method also includes: metallizing the side of the remaining initial gate layer away from the integrated structure to form a gate contact layer; the initial gate layer includes a semiconductor material; metallizing the side of the source region and the drain region away from the channel region to form a source contact layer and a drain contact layer; the materials of the gate contact layer, the source contact layer and the drain contact layer include metal silicide.

[0016] The embodiments of the present disclosure provide a semiconductor device and a method for preparing the same. The semiconductor device includes: an insulating core, a semiconductor column and a gate structure; the semiconductor column surrounds the insulating core, and the semiconductor column includes a source region, a channel region and a drain region along a first direction; the first direction is the height direction of the insulating core; the gate structure surrounds the channel region. The semiconductor device provided by the embodiments of the present disclosure can effectively control the thickness of the channel (reduce the size of the channel) by arranging an insulating core in the semiconductor column, thereby enhancing the control ability of the gate over the channel, and then can achieve full control of the device through a lower gate voltage, thereby reducing the power consumption of the device. At the same time, due to the presence of the insulating core, the semiconductor device can achieve full depletion, that is, the charge in the semiconductor device is completely depleted, and faster switching speeds and smaller leakage currents can be achieved, thereby improving device performance and further reducing power consumption. In addition, due to the presence of the insulating core, interference between devices can be weakened, so that it has a higher ability to resist radio frequency interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure is shown in FIG. Figure 1B for Figure 1A A schematic top view of the semiconductor device shown;

[0018] Figure 2 A schematic diagram of the steps of a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0019] FIG. 3A to FIG. 3I A schematic diagram of the structure of a semiconductor device at various stages in a method for preparing a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0021] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0022] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0024] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0027] It should be noted that, for the convenience of description, various directions that may be used in the following description are first defined. A first direction (Z direction) is defined parallel to the height direction of the insulating core, and an intersecting X direction and Y direction are defined in a plane perpendicular to the first direction. The X direction, the Y direction, and the Z direction may be perpendicular to each other. Among them, the second direction may be any direction in the XOY plane.

[0028] Figure 1A A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure is shown in FIG. Figure 1B for Figure 1A A schematic top view of a semiconductor device is shown. Figure 1A and Figure 1B The semiconductor device includes: an insulating core 1, a semiconductor column and a gate structure; the semiconductor column surrounds the insulating core 1, and the semiconductor column includes a source region 21, a channel region 22 and a drain region 23 along a first direction; the first direction is the height direction of the insulating core 1; the gate structure surrounds the channel region 22.

[0029] In some embodiments, the semiconductor device has a vertical semiconductor column and the semiconductor column has an annular channel region 22, and a source region 21 and a drain region 23 arranged at opposite ends of the channel region 22. And the gate structure surrounds the channel region 22, so that a new type of vertical transistor device can be provided. It should be noted that the positions of the source region and the drain region can be interchanged, the insulating core includes an insulating material, and the semiconductor column includes a semiconductor material.

[0030] The semiconductor device provided by the embodiment of the present disclosure can effectively control the thickness of the channel (reduce the size of the channel) by setting an insulating core in the semiconductor column, thereby enhancing the control ability of the gate over the channel, and then can fully control the device through a lower gate voltage, reducing the power consumption of the device. At the same time, due to the presence of the insulating core, the semiconductor device can achieve full depletion, that is, the charge in the semiconductor device is completely depleted, which can achieve faster switching speeds and smaller leakage currents, thereby improving device performance and further reducing power consumption. In addition, due to the presence of the insulating core, the interference between devices can be reduced, so that it has a higher ability to resist radio frequency interference.

[0031] The insulating materials and dielectric materials involved in the present disclosure can all be insulating materials with high dielectric constant (High-K, HK), for example, dielectric materials with dielectric constant K greater than or equal to 3.9, including but not limited to HK materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2); the semiconductor material can be at least one of single crystal silicon, amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon.

[0032] In some embodiments, the gate structure includes a gate dielectric layer 31 surrounding the channel region 22, and a gate layer 32 surrounding the gate dielectric layer 31; the side of the gate layer 32 away from the gate dielectric layer 31 includes a gate contact layer 33; the side of the source region 21 and the drain region 23 away from the channel region 22 include a source contact layer 24 and a drain contact layer 25 respectively; the materials of the gate contact layer 33, the source contact layer 24 and the drain contact layer 25 include metal silicide.

[0033] When the feature size of semiconductor process is reduced to below deep submicron, the size of the gate, source and drain regions of transistors continues to decrease, resulting in an increase in the equivalent series resistance of semiconductor devices, affecting the speed of the circuit. The conductive properties of metal silicide are between metal and silicon. By setting metal silicide on the gate, source and drain, the resistance of the gate and active area can be reduced, the RC delay can be reduced, the operating speed of semiconductor devices can be increased, and the equivalent series resistance of semiconductor devices can be improved, thereby improving the performance of integrated circuits.

[0034] In order to reduce the contact resistance of the source and the drain, metal silicide is formed on the source region and the drain region by reacting metal (eg, titanium Ti, cobalt Co, or nickel platinum alloy NiPt) with silicon to form metal silicide.

[0035] In some embodiments, the gate contact layer 33 may cover the surface of the gate layer 32 that is not in contact with the gate dielectric layer 31 , or may only cover a portion of the surface of the gate layer 32 .

[0036] The material of the metal silicide involved in the present disclosure may include, but is not limited to, at least one of titanium silicide (TiSi2), zirconium silicide (ZrSi2), tungsten silicide (WSi2), platinum silicide (PtSi) or cobalt silicide (CoSi or CoSi2). The material of the gate dielectric layer involved in the present disclosure may be selected from any one or more of silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO) and aluminum oxide (e.g., Al2O3). The gate dielectric layer may be a single-layer structure or a multi-layer structure, for example, it may include a two-layer structure formed by silicon oxide and hafnium oxide, wherein the silicon oxide layer is in contact with the channel region, and the hafnium oxide layer is in contact with the gate. The thickness of the gate dielectric layer may be set according to the actual electrical requirements, for example, it may be 2nm to 5nm.

[0037] In some embodiments, a dimension of the insulating core along a second direction is greater than or equal to 10 angstroms, and the second direction is perpendicular to the first direction.

[0038] In some embodiments, when the size d1 of the insulating core on the XOY plane is greater than or equal to 10 angstroms, full depletion of the channel can be achieved, power consumption of the semiconductor device can be reduced, and switching speed and radio frequency interference resistance can be improved.

[0039] In some embodiments, a dimension of the channel region along a second direction is less than or equal to 40 angstroms, and the second direction is perpendicular to the first direction.

[0040] In some embodiments, due to the presence of the insulating core, the dimension d2 of the channel region in the XOY plane can be reduced to less than 40 angstroms, thereby realizing a fully depleted vertical semiconductor device. It should be noted that the dimension of the channel region in the XOY plane refers to the ring width of the channel region, which can be understood as the thickness of the channel region; the dimension of the channel region along the Z direction is the length of the channel region.

[0041] In some embodiments, a dimension of the channel region along the second direction is less than or equal to 30 angstroms and greater than or equal to 10 angstroms.

[0042] In some embodiments, the dimension d2 of the channel region in the XOY plane can be reduced to a range of 30 angstroms to 10 angstroms, such as 15 angstroms, 20 angstroms, or 25 angstroms.

[0043] In some embodiments, a projection shape of the insulating core on a first plane includes a circle or a polygon, and the first plane is perpendicular to the first direction.

[0044] In some embodiments, the projection of the insulating core on the XOY plane can be a circle, a polygon or any shape. Since the semiconductor column surrounds the insulating core, the projection of the semiconductor column on the XOY plane is annular and the inner circumference of the projection of the semiconductor column matches the shape of the projection of the insulating core. The projected outer circumference of the semiconductor column can be different from or the same as the inner circumference projection of the semiconductor column. For example, the projection of the insulating core on the XOY plane and the inner circumference of the projection of the semiconductor column on the XOY plane are circular, and the outer circumference of the projection of the semiconductor column on the XOY plane is rectangular.

[0045] Figure 2 A schematic diagram of the steps of a method for preparing a semiconductor device provided in an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises the following steps:

[0046] 210: Providing a base structure; the base structure includes a substrate and a stacked structure, the stacked structure includes a first insulating layer, an initial gate layer, and a second insulating layer;

[0047] 220: An integrated structure is formed in the stacked structure, the integrated structure comprising an insulating core and a semiconductor column surrounding the insulating core; the semiconductor column comprises a source region, a channel region and a drain region along a first direction; the first direction is a height direction of the insulating core; an initial gate layer surrounds the integrated structure.

[0048] In some embodiments, the semiconductor device obtained by the preparation method can effectively control the thickness of the channel (reduce the size of the channel) by forming an insulating core in the semiconductor column, thereby enhancing the gate's control over the channel, and then can achieve full control of the device through a lower gate voltage, reducing device power consumption. At the same time, due to the presence of the insulating core, the semiconductor device can achieve full depletion, that is, the charge in the semiconductor device is completely depleted, which can achieve faster switching speeds and smaller leakage currents, thereby improving device performance and further reducing power consumption. In addition, due to the presence of the insulating core, interference between devices can be reduced, making it have a higher ability to resist radio frequency interference.

[0049] It should be understood that Figure 2 The steps shown are not exclusive, and other steps may be performed before, after, or between any steps in the shown operations.

[0050] FIG. 3A to FIG. 3I This is a schematic diagram of the structure of a semiconductor device at various stages in the method for preparing a semiconductor device provided in an embodiment of the present disclosure. It should be noted that: FIG. 3A to FIG. 3I This is a complete schematic diagram of the implementation process of the semiconductor device manufacturing method. The unmarked parts in some figures can be shared with each other. FIG. 3A to FIG. 3I , the preparation method of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0051] The deposition processes involved in the embodiments of the present disclosure include but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) and combinations thereof.

[0052] The etching processes involved in the embodiments of the present disclosure include, but are not limited to: a plasma dry etching process, a gas reaction dry etching process, a wet etching process, and a combination thereof.

[0053] See also Figure 3A , the base structure 300 can be formed by forming a stacked structure 320 on a substrate 310. The stacked structure 320 includes a first insulating layer 321, an initial gate layer 322, and a second insulating layer 323 formed sequentially on the substrate 310. The materials of the first insulating layer 321 and the second insulating layer 323 include insulating materials, and the material of the initial gate layer 322 includes semiconductor materials. It should be noted that the thicknesses of the first insulating layer 321, the initial gate layer 322, and the second insulating layer 323 may be the same, or different and neither is zero.

[0054] The disclosed embodiments do not specifically limit the constituent materials of the substrate. As an example, the substrate can be composed of semiconductor materials, insulating materials, conductor materials or any combination of their material types. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0055] In some embodiments, forming an integrated structure in a stacked structure includes: forming a first through hole penetrating the stacked structure, and forming the integrated structure through the first through hole.

[0056] See also FIG. 3B to FIG. 3CThe preparation method further includes the following steps: forming a first through hole 330 penetrating the stacked structure 320. In a specific example, a first mask layer (not shown) is formed on the upper surface of the base structure 300, and the first mask layer includes an opening corresponding to the first through hole. The substrate 310 is used as a stop layer, and an etching process is performed on the stacked structure 320 through the first mask layer to form the first through hole 330.

[0057] In some embodiments, before forming the integrated structure, the method further includes: replacing a portion of the initial gate layer with a gate dielectric layer through the first through hole, the gate dielectric layer surrounds the integrated structure, and the remaining initial gate layer surrounds the gate dielectric layer.

[0058] See also Figure 3B and Figure 3C , replacing part of the initial gate layer 322 with the gate dielectric layer 341 through the first through hole 330 specifically includes: laterally etching the initial gate layer 322 through the first through hole 330 to form a first transverse groove 340 surrounding the first through hole 330. It should be noted that the groove formed after laterally etching the initial gate layer 322 through the first through hole 330 is a whole, wherein the first through hole 330 and the first transverse groove 340 are different parts of the groove.

[0059] A gate dielectric layer 341 is formed in the first transverse groove 340, and the gate dielectric layer 341 surrounds the first through hole 330. In a specific example, the gate dielectric layer 341 can be formed by thermally oxidizing the surface of the initial gate layer exposed by the first transverse groove 340; in another specific example, the gate dielectric layer 341 can be formed in the first transverse groove 340 by a chemical vapor deposition process.

[0060] In some embodiments, after forming the gate dielectric layer, the process includes: forming an initial semiconductor column through a first through hole, the initial semiconductor column including an initial source region, an initial channel region and an initial drain region along a first direction; forming a second through hole passing through the initial semiconductor column, and forming an insulating core through the second through hole.

[0061] See also Figure 3D , semiconductor material is deposited into the first through hole 330 to form an initial semiconductor column. Specifically, the initial semiconductor column can be formed by an epitaxial growth process. For example, the epitaxial growth process can be molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG) or a combination thereof. In one embodiment, each of the initial source region, the initial channel layer region and the initial drain region in the initial semiconductor column can be formed in sequence by the same epitaxial growth process or different epitaxial growth processes. Among them, the initial source region and the initial drain region have similar doping concentrations and the same doping type, and the doping type of the initial channel region is different from that of the initial source region and the initial drain region.

[0062] The substrate 310 is used as a stop layer, and an etching process is performed on the initial semiconductor column to form a second through hole 350 and a semiconductor column surrounding the second through hole 350 ; wherein the semiconductor column includes a source region 331 , a channel region 332 , and a drain region 333 .

[0063] See also Figure 3E , an insulating material is deposited into the second through hole 350 to form an insulating core 351 , and the insulating core 351 and the semiconductor column form an integrated structure.

[0064] In some embodiments, the preparation method also includes: metallizing the side of the remaining initial gate layer away from the integrated structure to form a gate contact layer; the initial gate layer includes a semiconductor material; metallizing the side of the source region and the drain region away from the channel region to form a source contact layer and a drain contact layer; the materials of the gate contact layer, the source contact layer and the drain contact layer include metal silicide.

[0065] See also Figure 3F Before metallizing the remaining initial gate layer 322, the method also includes: using the initial gate layer 322 as a stop layer and performing an etching process on the second insulating layer 323 to expose the remaining initial gate layer. Specifically, the remaining second insulating layer 323 at least covers the lower portion of the side wall of the drain region 333 (the portion of the side wall of the drain region 333 close to the channel region 332) and the top surface of the gate dielectric layer 341 (the surface in contact with the second insulating layer 323).

[0066] See also Figure 3G The exposed surfaces of the remaining initial gate layer 322 and the drain region 333 are metallized to form a gate contact layer 361 and a drain contact layer 362, and the unmetallized portion of the remaining initial gate layer serves as a gate layer 322a.

[0067] See also Figure 3H The preparation method further includes: forming a gate contact structure and a drain contact structure on the gate contact layer 361 and the drain contact layer 362 respectively.

[0068] Specifically: Figure 3GA dielectric material is deposited on the top surface of the obtained structure to form a first dielectric layer 371, an etching process is performed on the first dielectric layer 371 to form a first contact hole exposing the gate contact layer 361 and the drain contact layer 362, and a conductive material is deposited in the first contact hole to form a first gate contact plug (Contact, CT) 371a and a first drain contact plug 371b. A dielectric material is deposited on the surface of the first dielectric layer 371 to form a second dielectric layer 372, an etching process is performed on the second dielectric layer 372 to form a second contact hole exposing the first gate contact plug 371a and the first drain contact plug 371b, and a conductive material is deposited in the second contact hole to form a second gate contact plug 372a and a second drain contact plug 372b. The first gate contact plug 371a and the second gate contact plug 372a constitute a gate contact structure, and the first drain contact plug 371b and the second drain contact plug 372b constitute a drain contact structure.

[0069] See also Figure 3H and Fig. 3I The preparation method further includes: forming a source contact layer 363 and forming a source contact structure on the source contact layer 363 .

[0070] Specifically, the second dielectric layer 372 is temporarily bonded to the carrier wafer 373 by a bonding material, the resulting structure is flipped over and the substrate 310 is peeled off. The bonding material includes an adhesive material, such as epoxy resin, polyimide, dry film, photosensitive polymer, etc. A dielectric material is deposited on the surface of the first insulating layer 321 to form a third dielectric layer 374, an etching process is performed on the third dielectric layer 374 to form a third contact hole exposing the source contact layer 363, and a conductive material is deposited in the third contact hole to form a first source contact plug 374a. A dielectric material is deposited on the surface of the third dielectric layer 374 to form a fourth dielectric layer 375, an etching process is performed on the fourth dielectric layer 375 to form a fourth contact hole exposing the first source contact plug 374a, and a conductive material is deposited in the fourth contact hole to form a second source contact plug 375a. The first source contact plug 374a and the second source contact plug 375a constitute a source contact structure.

[0071] In some embodiments, a dimension of the insulating core along a second direction is greater than or equal to 10 angstroms, and the second direction is perpendicular to the first direction.

[0072] In some embodiments, when the size d1 of the insulating core on the XOY plane is greater than or equal to 10 angstroms, full depletion of the channel of the semiconductor device can be achieved, power consumption of the semiconductor device can be reduced, and switching speed and radio frequency interference resistance can be improved.

[0073] In some embodiments, a dimension of the channel region along a second direction is less than or equal to 40 angstroms, and the second direction is perpendicular to the first direction.

[0074] In some embodiments, in a semiconductor device formed by the preparation method, the dimension d2 of the channel region in the XOY plane can be reduced to less than 40 angstroms, thereby realizing a fully depleted vertical semiconductor device.

[0075] In some embodiments, a dimension of the channel region along the second direction is less than or equal to 30 angstroms and greater than or equal to 10 angstroms.

[0076] In some embodiments, the dimension d2 of the channel region in the XOY plane can be reduced to a range of 30 angstroms to 10 angstroms, such as 15 angstroms, 20 angstroms, or 25 angstroms.

[0077] It should be noted here that the description of the above method for preparing a semiconductor device is similar to the description of the above semiconductor device embodiment, and has similar beneficial effects as the semiconductor device embodiment. For technical details not disclosed in the embodiment of the method for preparing a semiconductor device of the present disclosure, please refer to the description of the embodiment of the method for preparing a semiconductor device of the present disclosure for understanding.

[0078] The embodiments of the present disclosure provide a semiconductor device and a method for preparing the same. The semiconductor device includes: an insulating core, a semiconductor column and a gate structure; the semiconductor column surrounds the insulating core, and the semiconductor column includes a source region, a channel region and a drain region along a first direction; the first direction is the height direction of the insulating core; the gate structure surrounds the channel region. The semiconductor device provided by the embodiments of the present disclosure can effectively control the thickness of the channel (reduce the size of the channel) by arranging an insulating core in the semiconductor column, thereby enhancing the control ability of the gate over the channel, and then can achieve full control of the device through a lower gate voltage, thereby reducing the power consumption of the device. At the same time, due to the presence of the insulating core, the semiconductor device can achieve full depletion, that is, the charge in the semiconductor device is completely depleted, and faster switching speeds and smaller leakage currents can be achieved, thereby improving device performance and further reducing power consumption. In addition, due to the presence of the insulating core, interference between devices can be weakened, so that it has a higher ability to resist radio frequency interference.

[0079] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0080] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: insulating core, semiconductor pillar and gate structure; The semiconductor column surrounds the insulating core, and the semiconductor column includes a source region, a channel region and a drain region along a first direction; the first direction is a height direction of the insulating core; The gate structure surrounds the channel region.

2. The semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer surrounding the channel region, and a gate layer surrounding the gate dielectric layer; The side of the gate layer away from the gate dielectric layer includes a gate contact layer; the side of the source region and the drain region away from the channel region respectively include a source contact layer and a drain contact layer; the materials of the gate contact layer, the source contact layer and the drain contact layer include metal silicide.

3. The semiconductor device according to claim 1, wherein: A dimension of the insulating core along a second direction is greater than or equal to 10 angstroms, and the second direction is perpendicular to the first direction.

4. The semiconductor device according to claim 1, wherein: A dimension of the channel region along a second direction is less than or equal to 40 angstroms, and the second direction is perpendicular to the first direction.

5. The semiconductor device according to claim 1, wherein: A projection shape of the insulating core on a first plane includes a circle or a polygon, and the first plane is perpendicular to the first direction.

6. A method for preparing a semiconductor device, characterized in that: include: Providing a base structure; The base structure includes a substrate and a stacked structure, wherein the stacked structure includes a first insulating layer, an initial gate layer, and a second insulating layer; An integrated structure is formed in the stacked structure, the integrated structure comprising an insulating core and a semiconductor column surrounding the insulating core; the semiconductor column comprises a source region, a channel region and a drain region along a first direction; the first direction is a height direction of the insulating core; The initial gate layer surrounds the unitary structure.

7. The method according to claim 6, characterized in that The forming of an integrated structure in the stacked structure comprises: A first through hole is formed penetrating the stacked structure, and the integrated structure is formed through the first through hole.

8. The method according to claim 7, characterized in that Before forming the integrated structure, the method further comprises: A portion of the initial gate layer is replaced by a gate dielectric layer through the first through hole, the gate dielectric layer surrounds the integrated structure, and the remaining initial gate layer surrounds the gate dielectric layer.

9. The method according to claim 8, characterized in that After forming the gate dielectric layer, the method further comprises: Forming an initial semiconductor column through the first through hole, wherein the initial semiconductor column includes an initial source region, an initial channel region and an initial drain region along a first direction; A second through hole is formed through the initial semiconductor column, and the insulating core is formed through the second through hole.

10. The method according to claim 6, characterized in that The method further comprises: Performing metallization treatment on a side of the remaining initial gate layer away from the integrated structure to form a gate contact layer; the initial gate layer comprises a semiconductor material; Metallization treatment is performed on the sides of the source region and the drain region away from the channel region to form a source contact layer and a drain contact layer; the materials of the gate contact layer, the source contact layer and the drain contact layer include metal silicide.

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