Semiconductor device and manufacturing method thereof

Abstract

Gate dielectric materials and related methods for stacking device structures, such as complementary field effect transistors (CFETs), are disclosed herein. An exemplary method includes forming a two-dimensional (2D) dielectric material over a semiconductor channel layer. In some embodiments, the method further includes depositing a gate dielectric layer over the 2D dielectric material. In some examples, the method further includes forming a metal gate electrode over the gate dielectric layer. In various embodiments, a dipole is substantially formed within a 2D dielectric material, where the dipole is configured to modulate a threshold voltage (Vt) of the semiconductor device. The embodiment of the invention also discloses a semiconductor device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. To date, these goals have been achieved in large part by reducing IC size (e.g., by reducing the minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, this size reduction has also increased the complexity of the IC manufacturing process. Therefore, achieving continued advancements in IC devices and their performance requires similar advancements in IC manufacturing processes and technologies.

[0003] As an example, complementary field effect transistors (CFETs) have been introduced, which include a first transistor of a first conductivity type (e.g., n-type or p-type) vertically stacked on a second transistor of the opposite conductivity type, in an effort to provide the required density reduction for advanced IC technology nodes. However, the fabrication of such stacked device structures presents another set of challenges. Therefore, existing implementations are not satisfactory in all respects. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a two-dimensional (2D) dielectric material above a semiconductor channel layer; depositing a gate dielectric layer above the 2D dielectric material; and forming a metal gate electrode above the gate dielectric layer; wherein a dipole is substantially formed within the 2D dielectric material.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a stacked device structure, the stacked device structure comprising a first device vertically stacked above a second device, wherein the first device and the second device have corresponding first gate stacks and second gate stacks, and wherein forming at least one of the first gate stack and the second gate stack comprises: performing a channel release process to selectively remove a dummy layer from between adjacent channel layers, and forming a gap between adjacent channel layers, the gap exposing relative surfaces of adjacent channels; forming a two-dimensional (2D) dielectric material above the exposed relative surfaces of the adjacent channel layers, wherein the 2D dielectric material comprises a dipole inducing element, the dipole inducing element providing a dipole within the 2D dielectric material; and depositing a high-K gate dielectric above the 2D dielectric material.

[0006] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a semiconductor channel layer; a two-dimensional (2D) dielectric material, disposed above the semiconductor channel layer; a high-K dielectric layer, disposed above the 2D dielectric material; and a metal gate electrode, disposed above the high-K dielectric layer; wherein the 2D dielectric material comprises a dipole-inducing element, and the dipole-inducing element forms a dipole within the 2D dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A is a partial cross-sectional view of part or all of a stacked device structure according to various aspects of the present disclosure.

[0009] Figure 1B is a partial cross-sectional view of part or all of another stacked device structure according to various aspects of the present disclosure.

[0010] Figure 2A is a flowchart of part or all of a method for forming a gate structure of a transistor according to various aspects of the present disclosure.

[0011] Figure 2B , Figure 2C , Figure 2D and Figure 2E It shows that various aspects of the present disclosure can be used with Figure 2A The method correspondingly forms various gate structure embodiments.

[0012] Figure 2F Dipole profiles corresponding to embodiments of gate structures disclosed herein are shown according to some aspects of the present disclosure.

[0013] Figure 3 is a method for monolithically manufacturing a stacked device structure (e.g. Figure 1A A flowchart of a method for forming a stacked device structure) Figure 2A-2F The gate structure method.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H The stacked device structure according to various aspects of the present disclosure is in various manufacturing stages (e.g., Figure 3 and Figure 2A-2F A partial or complete cross-sectional view of a stage related to the method.

[0015] Figure 5 A method for sequentially manufacturing a stacked device structure (e.g. Figure 1B A flowchart of a method for forming a stacked device structure) Figure 2A-2F The gate structure method.

[0016] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G The stacked device structure according to various aspects of the present disclosure is in various manufacturing stages (e.g., Figure 5 and Figure 2A-2F A partial or complete cross-sectional view of a stage related to the method. DETAILED DESCRIPTION

[0017] The present invention generally relates to gate dielectric materials for stacked device structures, such as transistor stacks having n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs). More specifically, embodiments of the present disclosure relate to a two-dimensional (2D) gate dielectric material (e.g., 2D silicon oxide and / or 2D silicate) that provides threshold voltage (Vt) tuning and equivalent oxide thickness (EOT) reduction in stacked device structures.

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not meant to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first and second components are directly contacted and formed, and may also include an embodiment in which an additional component can be formed between the first and second components. In addition, in order to facilitate the discussion of the relationship between one feature and another feature in the present disclosure, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "below", "below", "above", "bottom", etc. and their derivatives (such as "horizontal", "downward", "upward", etc.) are used. Spatially relative terms are intended to cover different directions of devices including features. The present disclosure may also repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0019] In addition, when a number or a range of numbers is described using "about," "approximately," or the like, the term is intended to include numbers within a reasonable range that takes into account variations inherent in the manufacturing process as understood by a person of ordinary skill in the art. For example, a number or range of numbers encompasses a reasonable range that includes the described number, such as within + / -10% of the described number, based on known manufacturing tolerances for manufacturing features associated with the number. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.5 nm to 5.5 nm, and a person of ordinary skill in the art knows that the manufacturing tolerance associated with the deposited material layer is + / -10%. In addition, taking into account the differences inherent in any manufacturing process, when a device component is described as having a "basic" property and / or feature, the term is intended to capture the property and / or feature within the tolerance of the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" feature is intended to capture a feature that is approximately vertical and horizontal within a given tolerance of the manufacturing process used to manufacture such a feature, but is not mathematically or completely vertical and horizontal.

[0020] A stacked transistor structure can provide the desired density reduction for advanced integrated circuit (IC) technology nodes. The stacked transistor structure stacks a first transistor (i.e., an upper / top transistor) vertically on top of a second transistor (i.e., a lower / bottom transistor). When the first transistor and the second transistor have opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the stacked transistor structure provides a complementary field effect transistor (CFET). The first transistor and the second transistor are separated by an insulating layer, which is typically formed by replacing a sacrificial layer in the semiconductor layer stack with a dielectric layer during the processing of the semiconductor layer stack. For example, the semiconductor layer stack may include a sacrificial layer located between a first group of semiconductor layers and a second group of semiconductor layers, wherein the first group of semiconductor layers is processed to form a first transistor and the second group of semiconductor layers is processed to form a second transistor. After partially processing the semiconductor layer stack, forming the insulating layer may include removing the sacrificial layer to form a gap between the first group of semiconductor layers and the second group of semiconductor layers, and filling the gap with an insulating material (e.g., a dielectric material).

[0021] As an alternative to the bonding technique utilizing such a gap filling step, some techniques for stacked transistor structures utilize plasma activated wafer bonding to provide an insulating layer between the first transistor and the second transistor. In an exemplary plasma activated wafer bonding process, a first bonding dielectric layer may be formed on a first substrate, and a second bonding dielectric layer may be formed on a second substrate. Thereafter, a plasma activation process may be performed on each of the first and second bonding dielectric layers on the first substrate and the second substrate, respectively, to form a plasma activated surface thereon. The plasma activated surfaces on each of the first and second bonding dielectric layers on the first substrate and the second substrate may then be bonded by bringing the corresponding plasma activated surfaces into contact with each other. This technique eliminates the need to replace a sacrificial layer with a dielectric layer, which may eliminate seam formation in the insulating layer and reduce damage to the insulating layer and / or other device components that may be caused by the seams during a process utilizing gap filling.

[0022] In various embodiments, the transistor types for providing the first and / or second transistors of the stacked transistor structure may include planar transistors, fin field effect transistors (FinFETs), and / or full-ring gate (GAA) transistors including nanosheet transistors and nanowire transistors. Regardless of the specific type of transistor used, the gate structure of the transistor may include a high-K / metal gate structure. In some embodiments, the high-K / metal gate structure may include an interface layer (IL) formed above a semiconductor channel layer (e.g., a Si, SiGe, or Ge-based material layer), a high-K dielectric layer (e.g., an Hf-based dielectric layer, a Zr-based dielectric layer, or other high-K dielectric layer) formed above the IL, and a metal gate electrode formed above the high-K dielectric layer. As used and described herein, the high-K gate dielectric includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermally oxidized silicon (about 3.9). In some cases, the metal gate electrode may include a metal layer such as Ti, Al, W, Ta, a metal compound such as TaN, TiN, TiAl, WN, or other metal-containing material layer.

[0023] In various examples, the IL includes a silicon-containing dielectric material, such as amorphous SiOx (a-SiOx). As described above, the IL can be disposed between a semiconductor channel layer and a high-K dielectric layer. In at least some existing embodiments, a dipole-driven method can be used to modulate a transistor threshold voltage (Vt) by tuning the work function (WF) of the transistor. For example, a dipole-induced layer can be formed above the high-K dielectric layer, and the atoms of the dipole-induced layer can be driven into the high-K dielectric layer, so that a dipole can be formed at the interface between the high-K dielectric layer and the IL. The formed dipole will in turn modulate the transistor WF and Vt and help improve device performance. However, the dipole-driven method is performed using a high-temperature process that is not easy to control, which may result in a degradation of device performance. In addition to Vt tuning, a reduction in the equivalent oxide thickness (EOT) is also desirable for improving device performance. However, the thickness of the IL is difficult to scale down, at least in part because a reduction in the physical thickness of the IL (e.g., scaling down the thickness of the a-SiOx IL) may result in high gate leakage. In addition to the above challenges, dangling bonds at the interface between the IL (e.g., a-SiOx) and the underlying semiconductor channel layer (e.g., Si) may lead to high interface trap density, further degrading the device performance.

[0024] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all advantages must be discussed herein, and all embodiments do not require specific advantages. For example, the embodiments discussed herein include gate dielectric materials and related methods for stacked device structures (such as stacked transistor structures). In some embodiments, a two-dimensional (2D) dielectric material is disposed between a semiconductor channel layer and a high-K dielectric layer of a gate structure, substantially replacing the IL (e.g., a-SiOx) used in some existing applications. In various examples, the 2D dielectric material may include 2D silicon oxide and / or 2D silicate (e.g., c-SiOx, c-MSiOx, where "M" is a metal), which is a layered polymorph of silicon dioxide and has hexagonal crystal symmetry. Specifically, the 2D dielectric material disclosed herein provides Vt tuning and EOT scaling without compromising device performance. For example, the interface between the 2D dielectric material and the underlying semiconductor channel layer (e.g., Si) is substantially flat, thereby facilitating improved device performance. The crystalline structure of the 2D dielectric material, for example as opposed to the amorphous SiOx used in some prior embodiments, also provides enhanced device reliability. In various embodiments, the ultra-thin thickness of the 2D dielectric material provides a scalable EOT, further improving device performance. In addition, in some embodiments, the 2D dielectric material can be directly doped during the deposition process to form dipoles in a controllable manner (e.g., for WF and Vt tuning). Additional details of embodiments of the present disclosure are provided below, and additional benefits and / or other advantages will become apparent to those skilled in the art who benefit from the present disclosure.

[0025] As previously described, the transistor types for providing the first and / or second transistors of the stacked transistor structure may include planar transistors, FinFETs, and / or GAA transistors including nanosheet transistors and nanowire transistors. Although not limited to this, for the following discussion, various embodiments of using GAA transistors to provide the first and second transistors of the stacked transistor structure will be discussed. The disclosed stacked transistor structure can also provide a CFET, wherein the first transistor and the second transistor have opposite conductivity types (e.g., an n-type transistor and a p-type transistor). As described in more detail below and in some examples, the GAA transistor for implementing the CFET includes a gate structure having a high K / metal gate structure. In various embodiments, the high K / metal gate structure includes a 2D dielectric material (e.g., 2D silicon oxide and / or 2D silicate) formed above a semiconductor channel layer (e.g., a Si-based, SiGe-based, or Ge-based material layer), a high K dielectric layer (e.g., an Hf-based dielectric layer, a Zr-based dielectric layer, or other high K dielectric layer) formed above the 2D dielectric material, and a metal gate electrode formed above the high K dielectric layer.

[0026] Now referring to the accompanying drawings, Figure 1A A partial cross-sectional view of part or all of a stacked device structure 10A according to various aspects of the present disclosure is provided. The stacked device structure 10A is manufactured monolithically and can therefore be referred to as a monolithic stacked device structure. The stacked device structure 10A includes a device stack having an upper device 12U vertically stacked above a lower device 12L, a substrate 14, and an isolation structure 16A located between and separating the upper device 12U and the lower device 12L. The isolation structure 16A includes an isolation structure 17A and an isolation structure 18. In some embodiments, the upper device 12U and the lower device 12L are stacked front to back. For example, as further described below, the isolation structure 16A can bond and / or attach the back side of the upper device 12U to the front side of the lower device 12L, and the isolation structure 16A can be referred to as a bonding layer / structure. For clarity, Figure 1A It is simplified for better understanding of the inventive concepts of the present disclosure. Additional features may be added to the stacked device structure 10A, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the stacked device structure 10A.

[0027] exist Figure 1A In the embodiment, the upper device 12U and the lower device 12L each include at least one electrically functional device, such as an upper transistor 20U and a lower transistor 20L, respectively. Therefore, the stacked device structure 10A includes a transistor stack having a top transistor (e.g., transistor 20U) and a bottom transistor (e.g., transistor 20L) separated and / or electrically isolated from each other by an isolation structure 16A. In some embodiments, the lower transistor 20L and the upper transistor 20U are transistors of opposite conductivity types. For example, transistor 20L is a p-type transistor and transistor 20U is an n-type transistor, or vice versa. In such an embodiment, the lower transistor 20L and the upper transistor 20U form a CFET. In some embodiments, the lower transistor 20L and the upper transistor 20U are transistors of the same conductivity type. For example, transistor 20L and transistor 20U are both n-type transistors or both p-type transistors.

[0028] Device 12U includes various features and / or components, such as semiconductor layer 26U, semiconductor layer 26M, gate spacer 44, inner spacer 54, epitaxial source / drain 62U, contact etch stop layer (CESL) 70U, interlayer dielectric (ILD) layer 72U, gate dielectric 78U and gate electrode 80U (together forming gate stack 90U) and hard mask 92. Device 12L also includes various features and / or components, such as mesa 14' (e.g., extension of substrate 14), semiconductor layer 26L, semiconductor layer 26, substrate isolation structure, inner spacer 54, epitaxial source / drain 62L, CESL 70L, ILD layer 72L and gate dielectric 78L and gate electrode 80L (together forming gate stack 90L). Each gate stack 90U and each gate stack 90L are collectively referred to as a gate 90 of stacked device structure 10A, which can be a metal gate or a high-k / metal gate of each CFET. The gate stack 90U is separated from the gate stack 90L by the isolation structure 17A and the semiconductor layer 26M, and the epitaxial source / drain 62U is separated from the epitaxial source / drain 62L by the isolation member 18. In the stacked device structure 10B discussed below, the isolation structure 17B can provide electrical isolation of the channel and / or gate of the stacked device, and the isolation structure 18 can provide electrical isolation of the source / drain of the stacked device.

[0029] In the depicted embodiment, the lower transistor 20L is a GAA transistor. For example, the lower transistor 20L has two channels provided by a semiconductor layer 26L (also referred to as a channel layer or channel), which is suspended above the substrate 14 and extends between corresponding source / drains (e.g., epitaxial source / drain 62L). In some embodiments, the lower transistor 20L includes more or fewer channels (and therefore more or less semiconductor layers 26L). The transistor 20L also has a gate stack 90L disposed above its semiconductor layer 26L and between its epitaxial source / drain 62L, and an internal spacer 54 disposed between its gate stack 90L and its epitaxial source / drain 62L. Along the gate width direction (e.g., in the XZ plane), the gate stack 90L is located above the top semiconductor layer 26L, between the semiconductor layers 26L, and between the bottom semiconductor layer 26L and the substrate 14. Along the gate length direction (e.g., in the YZ plane), the gate stack 90L surrounds the semiconductor layer 26L. During operation of the GAA transistor, current can flow between semiconductor layer 26L and epitaxial source / drain 62L. Semiconductor layer 26M (also referred to as a dummy channel layer or dummy channel) is suspended above substrate 14 and extends between corresponding isolation structures 18, and isolation structure 17A is disposed between semiconductor layer 26M of device 12L / transistor 20L and semiconductor layer 26M of device 12U / transistor 20U.

[0030] In the depicted embodiment, the upper transistor 20U is also a GAA transistor. For example, the upper transistor 20U has two channels provided by a semiconductor layer 26U (also referred to as a channel layer or channel), which is suspended above the substrate 14 and extends between corresponding source / drains (e.g., epitaxial source / drain 62U). In some embodiments, the upper transistor 20U includes more or less channel / semiconductor layers 26U. The transistor 20U also has a gate stack 90U disposed above its semiconductor layer 26U and between its epitaxial source / drain 62U, a gate stack 90U disposed between corresponding gate spacers 44, an internal spacer 54 between its gate stack 90U and its epitaxial source / drain 62U, and a hard mask 92 disposed above the gate stack 90U. Along the gate width direction, the gate stack 90U is located above the top semiconductor layer 26U, between the semiconductor layers 26U, and between the bottom semiconductor layer 26U and the semiconductor layer 26M. Along the gate length direction, the gate stack 90U surrounds the semiconductor layer 26U. During operation of the GAA transistor, current may flow between the semiconductor layer 26U and the epitaxial source / drain 62U.

[0031] The monolithically manufactured stacked device structure 10A provides an isolation structure 16A having an isolation structure 17A and an isolation structure 18 between the channel region and the source / drain region of the device 12L and the device 12U, respectively. For example, the corresponding isolation structure 17A is located between the channel region of the lower transistor 20L and the channel region of the upper transistor 20U (for example, between their channels and / or gates), and the isolation structure 18 is located between the source / drain region of the lower transistor 20L and the source / drain region of the upper transistor 20U. In the depicted embodiment, the corresponding isolation structure 17A is located between the semiconductor layer 26M of the lower transistor 20L and the upper transistor 20U, and the isolation structure 18 is located between the epitaxial source / drain 62L of the lower transistor 20L and the epitaxial source / drain 62U of the upper transistor 20U. Therefore, the isolation structure 17A can be used as a channel isolation structure and / or a gate isolation structure, and the isolation structure 18 can be used as a source / drain isolation structure. The isolation structure 17A and the isolation structure 18 can include a single layer or multiple layers. Isolation structure 17A and isolation structure 18 include dielectric materials, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or combinations thereof). In some embodiments, isolation structure 17A may include a first portion having a first composition and a second portion having a second composition, wherein the second composition is different from the first composition. Isolation structure 17A and isolation structure 18 may include the same or different materials and / or configurations. In the depicted embodiment, the thickness of isolation structure 17A is less than the thickness of isolation structure 18, and isolation structure 17A differs from isolation structure 18 in configuration. In some embodiments, isolation structure 18 is formed by CESL 70L and a portion of ILD layer 72L, as shown.

[0032] The substrate 14, the semiconductor layer 26U, the semiconductor layer 267M, and the semiconductor layer 26L include elemental semiconductors such as silicon and / or germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiment, the substrate 14, the semiconductor layer 26U, the semiconductor layer 26M, and the semiconductor layer 26L include silicon. In some embodiments, the semiconductor layer 26U and the semiconductor layer 26L include different semiconductor materials, such as silicon and silicon germanium, respectively, or vice versa. In some embodiments, the substrate 14 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 14 (including the mesa 14' extending therefrom) may include various doped regions, such as a p-well and an n-well. The n-well is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-well is doped with a p-type dopant, such as boron, indium, other p-type dopants, or combinations thereof.

[0033] The gate spacer 44 is arranged along the sidewall of the upper portion of the gate stack 90U, the internal spacer 54 is arranged below the gate spacer 44 along the sidewall of the gate stack 90U and / or the gate stack 90L, and the fin / mesa spacer can be arranged along the sidewall of the mesa 14'. The internal spacer 54 is arranged between the semiconductor layer 26 and between the bottom semiconductor layer 26 and the mesa 14'. The gate spacer 44, the internal spacer 54 and the fin spacer include a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride or combinations thereof). The gate spacer 44, the internal spacer 44 and the fin spacer may include different materials and / or different configurations (e.g., different numbers of layers). In some embodiments, the gate spacer 44, the internal spacer 54, the fin spacer or a combination thereof has a multilayer structure. In some embodiments, the gate spacers 44 and / or the fin spacers include more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or a combination thereof. Each set of spacers may have a different composition.

[0034] The gate 90 is disposed between the epitaxial source / drain stacks, each of which includes a corresponding epitaxial source / drain 62U, 62L and an isolation structure 18 disposed therebetween. Depending on the configuration of their respective transistors, the epitaxial source / drain 62L and the epitaxial source / drain 62U may have the same or different compositions and / or materials. The epitaxial source / drain 62L and the epitaxial source / drain 62U may be doped with n-type dopants and / or p-type dopants. In some embodiments, the epitaxial source / drain 62L and / or the epitaxial source / drain 62U include silicon (e.g., Si:C epitaxial source / drain, Si:P epitaxial source / drain, or Si:C:P epitaxial source / drain) that may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments, epitaxial source / drain 62L and / or epitaxial source / drain 62U include silicon germanium or germanium, which may be doped with boron, other p-type dopants, or combinations thereof (e.g., Si:Ge:B epitaxial source / drain). In the depicted embodiment, epitaxial source / drain 62L includes silicon germanium doped with boron, and epitaxial source / drain 62U includes silicon doped with phosphorus. In some embodiments, epitaxial source / drain 62L and / or epitaxial source / drain 62U include more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may include the same or different materials and / or the same or different concentrations of dopants. In some embodiments, epitaxial source / drain 62L and / or epitaxial source / drain 62U include materials and / or dopants that achieve desired tensile and / or compressive stresses in adjacent channel regions (e.g., formed by semiconductor layer 26U and semiconductor layer 26L). As used herein, source / drain regions, epitaxial source / drain, epitaxial source / drain components, etc. may refer to the source of a device (e.g., the upper transistor 20U and / or the lower transistor 20L), the drain of a device (e.g., the upper transistor 20U and / or the lower transistor 20L), or the source and / or drain of multiple devices.

[0035] The ILD layer 72U and the ILD layer 72L include a dielectric material, such as silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed by tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene-based (BCB) materials, polyimide, other dielectric materials, or combinations thereof. In some embodiments, the ILD layer 72U and / or the ILD layer 72L include a dielectric material having a dielectric constant less than that of silicon dioxide. The CESL 70L and the CESL 70U include materials different from those of the ILD layer 72U and the ILD layer 72L, respectively. For example, in the case where the ILD layer 72U and the ILD layer 72L include a low-k dielectric material containing silicon and oxygen, the CESL 70L and the CESL 70U may include a material composed of silicon and nitrogen and / or carbon. In some embodiments, the ILD layer 72U, the ILD layer 72L, the CESL 70L, the CESL 70U, or a combination thereof may have a multi-layer structure.

[0036] The gate dielectric 78U and the gate dielectric 78L each include at least one gate dielectric layer. According to the embodiments disclosed herein, the gate dielectric 78U and / or the gate dielectric 78L include a 2D dielectric material (e.g., 2D silicon oxide and / or 2D silicate) 79U and / or 79L disposed above the corresponding semiconductor layer 26U, 26L. In some cases, both the gate dielectrics 78U and 78L include the same 2D dielectric material. In other cases, each of the gate dielectrics 78U and 78L includes a different 2D dielectric material. In some embodiments, the gate dielectric 78U and / or the gate dielectric 78L include a high-k dielectric layer formed above the 2D dielectric material 79U, 79L, which includes a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide (k≈3.9), such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-k dielectric materials or combinations thereof. For example, the gate dielectric 78U and / or the gate dielectric 78L include a hafnium-based oxide (e.g., HfO2) layer and / or a zirconium-based oxide (e.g., ZrO2) layer. In some embodiments, the 2D dielectric material and / or the high-k dielectric layer may have a multilayer structure.

[0037] The gate electrode 80U and the gate electrode 80L are respectively disposed above the gate dielectric 78U and the gate dielectric 78L. The gate electrode 80U and the gate electrode 80L each include at least one conductive gate layer. The conductive gate layer includes a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials or combinations thereof. In some embodiments, the gate electrode 80U and / or the gate electrode 80L include a work function layer. The work function layer is a conductive layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function). The work function layer includes a work function metal and / or its alloy, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN or a combination thereof. In some examples, the gate electrode 80U and / or the gate electrode 80L do not include a work function layer, but the 2D dielectric material 79U, 78L doped during the deposition process of the 2D dielectric material 79U, 79L can provide dipole formation and WF tuning. In some embodiments, the gate electrode 80U and / or the gate electrode 80L include a conductive body layer above the corresponding gate dielectric and / or work function layer. The body layer includes a conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other metals, their alloys or combinations thereof. In some embodiments, the gate electrode 80U and / or the gate electrode 80L include a barrier (blocking) layer on the corresponding work function layer and / or the gate dielectric layer. The barrier layer includes a material that prevents or eliminates diffusion and / or reaction of components between adjacent layers and / or promotes adhesion between adjacent layers (e.g., between the work function layer and the body layer). In some embodiments, the barrier layer includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other metal nitrides, or combinations thereof.

[0038] The hard mask 92 includes a material different from the ILD layer 72U and / or the subsequently formed ILD layer to achieve etching selectivity during the subsequent etching process. In some embodiments, the hard mask 92 includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, other silicon nitrides, other silicon carbides, or a combination thereof. In some embodiments, the hard mask 92 includes a metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HFO2), zirconium aluminum oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or a combination thereof.

[0039] Figure 1B A partial cross-sectional view of part or all of a stacked device structure 10B according to various aspects of the present disclosure is provided. The stacked device structure 10B is manufactured sequentially and may therefore be referred to as a sequential stacked device structure. Because the stacked device structure 10B is similar to the stacked device structure 10A in many respects, similar features of the stacked device structure 10B and the stacked device structure 10A are identified by the same reference numerals for the sake of clarity and simplicity. For example, the stacked device structure 10B includes a device stack disposed above a substrate 14 (e.g., an upper device 12U vertically stacked above a lower device 12L). The stacked device structure 10B includes an isolation structure 16B, rather than the isolation structure 16A, which is located between the upper device 12U and the lower device 12L and separates the upper device 12U from the lower device 12L. For example, as further described below, the isolation structure 16B may bond and / or attach the back side of the upper device 12U to the front side of the lower device 12L, and the isolation structure 16B may be referred to as a bonding layer / structure. For the sake of clarity, Figure 1B It is simplified for better understanding of the inventive concepts of the present disclosure. Additional features may be added to the stacked device structure 10B, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the stacked device structure 10B.

[0040] In the stacked device structure 10B, the lower device 12L and the upper device 12U each include at least one electrically functional device, such as a lower transistor 20L and an upper transistor 20U (which are configured as GAA transistors). The device 12U includes various features and / or components, such as a semiconductor layer 26U, a gate spacer 44U, an inner spacer 54U, an epitaxial source / drain 62U, a CESL 70U, an ILD layer 72U, a gate dielectric 78U, and a gate electrode 80U (which together form a gate stack 90U) and a hard mask 92U. The device 12L also includes various features and / or components, such as a mesa 14' (e.g., an extension of the substrate 14), a semiconductor layer 26L, a substrate isolation structure, a gate spacer 44L, an inner spacer 54L, an epitaxial source / drain 62L, a CESL 70L, an ILD layer 72L, and a gate dielectric 78L and a gate electrode 80L (which together form a gate stack 90L). The stacked device structure 10B may further include source / drain contacts, such as upper source / drain contacts disposed in the ILD layer 72U and on the epitaxial source / drain 62U, and lower source / drain contacts disposed in the ILD layer 72L and on the epitaxial source / drain 62L.

[0041] Because the stacked device structure 10B is manufactured sequentially, the isolation structure 16B is provided with the isolation structure 17B. The gate stack 90U is separated from the gate stack 90L by the isolation structure 17B, and the upper device 12U and / or the lower device 12L may not have the semiconductor layer 26M (eg, Figure 1A ), the epitaxial source / drain 62U is separated from the epitaxial source / drain 62L by the isolation structure 17B. Therefore, the isolation structure 17B is respectively located between the channel region and the source / drain region of the lower device 12L and the upper device 12U, and the isolation structure 17B can provide electrical isolation of the channel / gate and the source / drain of the stacked device. For example, the isolation structure 17B extends continuously between the channel region and the source / drain region of the lower transistor 20L and the upper transistor 20U without interruption. The isolation structure 17B may include a single layer or multiple layers. The isolation structure 17B includes a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbon, carbon nitride silicon oxynitride or combinations thereof). In some embodiments, the isolation structure 17B may include a first portion having a first component and a second portion having a second component, wherein the second component is different from the first component.

[0042] refer to Figure 2A, which shows a flowchart of part or all of a method 100 for forming a gate structure of a transistor according to various aspects of the present disclosure. The method 100 can be implemented in forming a gate structure for various types of transistors, such as a planar transistor, a FinFET, and / or a GAA transistor including a nanosheet transistor and a nanowire transistor. More specifically, in some embodiments, the method 100 can be implemented in forming a gate structure of a stacked transistor structure (e.g., the stacked device structure 10A and the stacked device structure 10B described above). Figure 2B , Figure 2C , Figure 2D and Figure 2E It shows that various aspects of the present disclosure can be used with Figure 2A The method 100 correspondingly forms various gate structure embodiments. Figure 2F Dipole profiles corresponding to embodiments of gate structures disclosed herein are shown according to some aspects of the present disclosure.

[0043] exist Figure 2A-2E In the method 100, at box 105, a semiconductor channel layer 150 is provided. The semiconductor channel layer 150 may include a Si-based, SiGe-based, or Ge-based material layer present in a planar transistor, a FinFET, and / or a GAA transistor including a nanosheet transistor and a nanowire transistor. In some cases, the semiconductor channel layer 150 may include a channel layer of a stacked transistor structure (e.g., a stacked device structure 10A and a stacked device structure 10B as described above). In the example shown, the semiconductor channel layer 150 includes a silicon channel layer. In some embodiments, the semiconductor channel layer 150 may be exposed (or provided, as shown in box 105 of the method 100) by a channel release process, in which a dummy semiconductor layer (e.g., SiGe) is selectively removed to form a gap between adjacent semiconductor channel layers (e.g., semiconductor channel layer 150).

[0044] exist Figure 2A-2E In the method 100 at block 110, the method 100 includes forming a 2D dielectric material 152 ( Figure 2B , Figure 2D ) or 2D dielectric material 162 ( Figure 2C , Figure 2E ), as described below. In some embodiments, the 2D dielectric material 152 ( Figure 2B , Figure 2D ) includes crystalline 2D silicon oxide (c-SiOx), 2D dielectric material 162 ( Figure 2C , Figure 2E) includes crystalline 2D silicates (c-MSiOx, where "M" is a metal). In various embodiments, the 2D dielectric materials 152, 162 have hexagonal crystal symmetry. It should also be noted that 2D silicon oxide is composed of X-membered rings, where X is between 3 and 9, does not form grain boundaries, and does not negatively affect device performance. For example, the structure of the 2D dielectric materials 152, 162 can be detected by appropriate metrology techniques, such as using electron diffraction, X-ray diffraction (XRD), Raman spectroscopy, transmission electron microscopy (TEM), scanning tunneling microscopy (STM), or other appropriate metrology techniques. In various embodiments, the thickness of the 2D dielectric materials 152, 162 is between about 0.5nm (e.g., for a double-layer structure) and about 2nm (e.g., for multiple 2D layers). In some embodiments, as Figure 2D and Figure 2E As shown, a buffer layer 165 (or adhesion layer 165) may be optionally formed on the semiconductor channel layer 150 before forming the 2D dielectric materials 152, 162. In this case, the 2D dielectric materials 152, 162 may then be formed over the buffer layer 165. In one example, the buffer layer 165 may include a crystalline oxide layer or a crystalline nitride layer, and may be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes.

[0045] Whether above the semiconductor channel layer 150 ( Figure 2B , Figure 2C ) or above the buffer layer 165 ( Figure 2D , Figure 2E ) to form 2D dielectric materials 152, 162. In various examples, various methods can be used to form 2D dielectric materials 152, 162, such as by growing directly on the semiconductor channel layer 150 (or by direct growth on the buffer layer 165) by CVD, ALD, PVD, or by growing on a separate substrate and then transferring to the semiconductor channel layer 150 (or to the buffer layer 165). In some cases, in order to enable the 2D dielectric materials 152, 162 to grow directly on the semiconductor channel layer 150 (or directly on the buffer layer 165), the amount of Si introduced during the deposition process should be carefully controlled. Controlling the amount of Si introduced during the deposition process also helps to avoid the formation of 3D silicon dioxide, which may be caused by the addition of too much Si during the deposition process. In some embodiments, the deposition temperature for forming the 2D dielectric materials 152, 162 can be between about 350-750 degrees Celsius. In other embodiments, the 2D dielectric materials 152, 162 may be first deposited at a lower temperature (eg, room temperature) and then annealed at a higher temperature (eg, between about 350-750 degrees Celsius).

[0046] When the 2D dielectric material 152 ( Figure 2B , Figure 2D ), the silicon source and the oxygen source may be used to co-deposit silicon and oxygen atoms on the semiconductor channel layer 150 (or the buffer layer 165) to form 2D silicon oxide (c-SiOx). As an example, Figure 2B (Right side) shows a ball-and-stick model of 2D silicon oxide (c-SiOx) formed on the semiconductor channel layer 150. As shown, the hexagonal crystal structure of the 2D silicon oxide (c-SiOx) includes silicon atoms 155A and oxygen atoms 157. In this example, a silicon atom top layer 155B of the crystal structure of the semiconductor channel layer 150 is also shown, wherein the 2D silicon oxide (c-SiOx) is bonded to the semiconductor channel layer 150. In various cases, the bonding between the 2D silicon oxide (c-SiOx) and the semiconductor channel layer 150 (or the buffer layer 165) may include covalent bonding and / or van der Waals bonding.

[0047] After forming the 2D silicon oxide (c-SiOx), in some embodiments, metal ions may be introduced into the 2D dielectric material 152 to form a dipole. As an alternative, a metal oxide, metal nitride, or other dipole inducing layer may be formed over the 2D dielectric material 152, and a thermal diffusion process (e.g., annealing) may be performed to drive ions from the dipole inducing layer into the 2D silicon oxide (c-SiOx), thereby forming a silicate and forming a dipole substantially within the silicate. According to some embodiments, the metal used to form the silicate may tend to position itself (bind) near one side of the 2D silicate (e.g., the top side or the bottom side of the 2D silicate) until substantially all available sites are occupied by the metal, thereby creating a controllable dipole, thereby providing a controllable Vt tuning of the transistor. As previously described, the formation of a dipole may be used to modulate the transistor Vt by tuning the work function (WF) of the transistor. In some cases, after the dipole is formed within the silicate, any remaining material of the dipole inducing layer may be removed from above the 2D dielectric material 152 prior to subsequent processing. For the avoidance of doubt, in some cases, if WF / Vt tuning is not required, the dipole formation step (e.g., including deposition of a dipole inducing layer and a thermal diffusion process above the 2D dielectric material 152) may be omitted. However, the implementation of the 2D dielectric material 152 will still provide enhanced device performance (e.g., due to enhanced EOT reduction, enhanced interface with the underlying semiconductor channel layer 150, and the crystal structure of the 2D dielectric material 152).

[0048] When the 2D dielectric material 162 (including crystalline 2D silicate (c-MSiOx, where "M" is a metal) is formed, for example, by one of the above methods Figure 2C , Figure 2E), a silicon source, an oxygen source, and a metal source may be used to co-deposit silicon, oxygen, and metal atoms over the semiconductor channel layer 150 (or buffer layer 165) to form a 2D silicate (c-MSiOx), where "M" is a metal. As an example, Figure 2C (Right) shows a ball-and-stick model of a 2D silicate (c-MSiOx, where "M" is a metal) formed above the semiconductor channel layer 150. As shown, the hexagonal crystal structure of the 2D silicate (c-MSiOx) includes silicon atoms 155, oxygen atoms 157, and metal atoms 159. In various cases, the metal atoms 159 may include a metal element suitable for inducing a dipole moment, such as La, Al, Sc, Y, Ti, Sr, Er, Mg, Ta, another dipole inducing layer, or a combination thereof. In some embodiments, the 2D silicate (c-MSiOx) is bonded to the semiconductor channel layer 150 (or buffer layer 165) by covalent bonds and / or van der Waals type bonds.

[0049] For example, by appropriately selecting deposition parameters associated with the deposition of the 2D dielectric material 162, the number and location of metal atoms 159 introduced by the metal source can be selectively adjusted to form dipoles within the silicate and selectively modulate the transistor Vt (e.g., by WF tuning). In some embodiments, the introduction of metal atoms 159 by the metal source is controlled by setting a prescribed dose during the deposition of the 2D silicate (c-MSiOx). This is in contrast to, for example, the introduction of metal ions into the 2D dielectric material 162 by a thermal diffusion process. According to some embodiments, the metal atoms 159 introduced into the 2D silicate (2D dielectric material 162) may tend to position themselves (join) near one side of the 2D dielectric material 162 (e.g., the top side or the bottom side of the 2D dielectric material 162) until substantially all available sites are occupied by metal, thereby generating a controllable dipole, thereby providing controllable Vt tuning of the transistor. In forming a 2D dielectric material 162 (c-MSiOx) including a crystalline 2D silicate (c-MSiOx) by co-depositing silicon atoms 155, oxygen atoms 157, and metal atoms 159 over the semiconductor channel layer 150 (or the buffer layer 165), Figure 2C , Figure 2E ), there is no need to perform a separate dipole formation step (eg, including depositing a dipole inducing layer on the 2D dielectric material 162 and a thermal diffusion process).

[0050] exist Figure 2A-2E In the method 100, at block 120, the method 100 includes forming a dielectric layer over the 2D dielectric material 152 ( Figure 2B , Figure 2D ) or above the 2D dielectric material 162 ( Figure 2C , Figure 2E) forms a high-K dielectric layer 154. The high-K dielectric layer 154 may include an Hf-based dielectric layer (e.g., HfO2), a Zr-based dielectric layer (e.g., ZrO2), or another suitable high-K dielectric layer. Generally, in various cases, the high-K dielectric layer 154 may include HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-K dielectric materials, or combinations thereof. In some embodiments, high-K dielectric layer 154 can be deposited by ALD, CVD, PVD, or another suitable deposition process. In some examples, high-K dielectric layer 154 can have a thickness of about 1-5 nm.

[0051] exist Figure 2A-2E In the method 100, at frame 125, a metal gate electrode 156 is formed over the high-K dielectric layer 154. The metal gate electrode 156 includes a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some cases, the metal gate electrode 156 can be formed using ALD, PVD, CVD, electron beam (e-beam) evaporation, and / or other suitable processes. In one example, the metal gate electrode 156 can have a thickness of about 0.5-5 nm. In some embodiments, the metal gate electrode 156 can optionally include a work function layer, as described above. However, in some cases, the metal gate electrode 156 does not include a work function layer, but relies on 2D dielectric materials 152, 162 to provide dipole formation and WF tuning, as described above. In some embodiments, before forming the metal gate electrode 156, a barrier (blocking) layer can be formed over the high-K dielectric layer 154. For example, such a barrier layer may include a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (eg, W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other metal nitrides, or combinations thereof.

[0052] Reference Figure 2F, shows a dipole profile 170 according to some embodiments, which may be formed as a result of method 100. For example, the dipole profile 170 may correspond to the number and location of metal atoms and / or metal ions within the 2D dielectric material 152, 162 that are responsible for forming the dipole. Therefore, the dipole profile 170 may also indicate the relative dipole strength within the 2D dielectric material 152, 162. Typically, the dipole profile 170 may be substantially disposed within the 2D dielectric material 152, 162. However, in various embodiments, the dipole profile 170 may not be located at the center of the 2D dielectric material 152, 162, but may move toward the overlying high-K dielectric layer 154 or toward the underlying semiconductor channel layer 150 (or underlying buffer layer 165). Thus, depending on various deposition parameters, the dipole profile 170 can be disposed closer to the top side or the bottom side of the 2D dielectric material 152, 162, such that the possible location of the peak of the dipole profile 170 is located within a space less than about 1 nm (e.g., where the spread Δd of the dipole profile 170 peak is less than about 1 nn). In some examples, the dipole profile 170 can be detected by a suitable metrology technique, such as using energy dispersive X-ray spectroscopy (EDS), electron energy loss spectroscopy (EELS), secondary ion mass spectroscopy (SIMS), or other suitable metrology methods.

[0053] It has been simplified for clarity. Figure 2A-2F , to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 100. Figure 2B-2F Add additional features and can be used in Figure 2B-2F Some of the features described below may be replaced, modified or eliminated in other embodiments.

[0054] Reference now Figure 3 , which shows a method for monolithically manufacturing a stacked device structure (such as Figure 1A Flowchart of a method 200 of forming a stacked device structure 10A) Figure 2A-2F The gate structure has been simplified for clarity. Figure 3 The method 200 of the present disclosure is provided to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after the method 200, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 200.

[0055] Figure 4A-4H is a partial or full cross-sectional view of a stacked device structure 10A at various stages of monolithic fabrication according to various aspects of the present disclosure, such as when implementing the formation Figure 2A-2F The gate structure method is Figure 3 For the sake of clarity, Figure 4A-4H It is simplified to better understand the inventive concepts of the present disclosure. Figure 4A-4H Additional steps may be provided before, during, and after the monolithic fabrication steps, and for Figure 4A-4H Additional embodiments of the monolithic manufacturing steps may move, replace, or eliminate some of the steps described. Figure 4A-4H Additional features can be added to the stacked device structure 10A, and can be Figure 4A-4H Some of the features described below may be replaced, modified, or eliminated in other embodiments of the stacked device structure 10A.

[0056] Reference Figure 4A and Figure 4B In an embodiment of block 205, manufacturing the stacked device structure 10A includes forming a superlattice structure on a substrate 14. Initially, a semiconductor layer stack 310L (e.g., for device 12L) is formed on the substrate 14. Thereafter, an intermediate sacrificial layer 310M is formed above the semiconductor layer stack 310L, and then a semiconductor layer stack 310 (e.g., for device 12U) is formed above the intermediate sacrificial layer 310M. The semiconductor stack 310L and the semiconductor stack 310U each include a corresponding semiconductor layer 26 and a corresponding semiconductor layer 315. The semiconductor layer 315 and the semiconductor layer 26 are stacked vertically (e.g., along the z-direction) from the top surface of the substrate 14 in a staggered and / or alternating configuration. The composition of the semiconductor layer 315 is different from the composition of the semiconductor layer 26 to achieve etching selectivity and / or different oxidation rates during processing. For example, the semiconductor layer 315 and the semiconductor layer 26 include different materials, composition atomic percentages, composition weight percentages, thicknesses, other characteristics, or combinations thereof to achieve the desired etching selectivity. In the depicted embodiment, semiconductor layer 26 includes silicon (e.g., to provide a channel layer for each device 12L, 12U), and semiconductor layer 315 includes silicon germanium. With such a composition, semiconductor layer 315 can have a first etch rate to an etchant, semiconductor layer 26 can have a second etch rate to an etchant, and the first etch rate and the second etch rate are different. As shown, the intermediate sacrificial layer 310M is used to vertically separate the semiconductor stack 310L from the semiconductor stack 310U. The intermediate sacrificial layer 310M can be composed of germanium and can have a different germanium content than the semiconductor layer 315. In some embodiments, the germanium content of the intermediate sacrificial layer 310M can be greater than the germanium content of the semiconductor layer 315, so that the entire intermediate sacrificial layer 310 can be selectively removed during the formation of the internal spacer, as described below.

[0057] After forming the superlattice structure (block 205), the method 200 continues to block 210 where a fin fabrication process is performed. Figure 4B and Figure 4C In an embodiment of block 210, a fin manufacturing process is performed to form fins 326 (also referred to as fin structures, fin elements, etc.) extending from the substrate 14. The fins 326 extend substantially parallel to each other along the x-direction, have a length in the x-direction, a width in the y-direction, and a height in the z-direction. Each fin 326 includes a substrate portion (e.g., a corresponding mesa 14'), a first semiconductor layer stack portion disposed on the substrate portion (e.g., a corresponding portion of the semiconductor layer stack 310L), an isolation portion disposed on the first semiconductor layer stack portion (e.g., a corresponding portion of the middle sacrificial layer 310M), and a second semiconductor layer stack portion disposed on the isolation portion (e.g., a corresponding portion of the semiconductor layer stack 310U). The fabrication of the fins 326 may include performing a photolithography process and / or an etching process to pattern the semiconductor layer stack precursor (e.g., the semiconductor layer stack 310U and the semiconductor layer stack 310L separated by the middle sacrificial layer 310M) and / or the substrate 14. In some embodiments, the fin 326 is formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer dielectric (SID) SADP process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch (LELELELE), a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof.

[0058] The method 200 proceeds to block 215 where a substrate isolation structure is formed. Figure 4C and Figure 4DIn the embodiment of block 215, a substrate isolation structure 328 is formed in the trench between the fins 326. The substrate isolation structure 328 fills the lower portion of the trench and surrounds a portion of the fin 326. The portion of the fin 326 extending above the top surface of the substrate isolation structure 328 may be referred to as a fin active region. The substrate isolation structure 328 electrically isolates the active device region and / or the passive device region. The substrate isolation structure 328 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, etc.), or a combination thereof. The substrate isolation structure 328 may have a multilayer structure. For example, the substrate isolation structure 328 may include a bulk dielectric (e.g., an oxide layer) on a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride, or a combination thereof). In another example, the substrate isolation structure 328 may include a bulk dielectric on a doped liner (e.g., a BSG liner and / or a PSG liner). The dimensions and / or characteristics of substrate isolation structure 328 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof. In the depicted embodiment, substrate isolation structure 328 may be an STI structure.

[0059] The substrate isolation structure 328 can be formed by depositing a liner layer (e.g., a dielectric layer) that partially fills the trench, depositing an oxide material on the liner layer that fills the remaining portion of the trench, performing a planarization process, and recessing and / or etching back the substrate isolation structure 328 so that the fin 326 protrudes therefrom. A planarization process (e.g., CMP) can be performed until the planarization stop layer is reached and exposed. In some embodiments, the planarization process removes the mask layer, any oxide material, any liner layer, or a combination thereof above the upper surface and / or top surface of the fin 326. The remaining portions of the liner layer and the oxide material can form the liner and the bulk dielectric of the substrate isolation structure 328, respectively.

[0060] The method 200 proceeds to block 220 where a dummy gate is formed and source / drain regions are defined. Figure 4D and Figure 4EIn one embodiment of the block 220, a dummy gate stack 330 is formed on a portion of the fin 326, a gate spacer 44 is formed along the sidewall of the dummy gate stack 130, and a source / drain recess 335 is defined. The dummy gate stack 330 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fin 326. For example, the dummy gate stack 330 extends along the y-direction, has a length in the y-direction, has a width in the x-direction, and has a height in the z-direction. In the XZ plane, the dummy gate stack 330 is disposed above the top of the channel region (C) of the fin 326 and / or the stacked device structure 10A, and the dummy gate stack 330 is disposed between the source / drain regions (S / D) of the fin 326 and / or the stacked device structure 10A. In the YZ plane, the dummy gate stack 330 may be disposed on the top and sidewalls of the fin 326, and the dummy gate stack 330 may wrap the channel region. The dummy gate stack 330 may include a dummy gate dielectric, a dummy gate electrode, a hard mask, other suitable layers (e.g., a capping layer, an interface layer, a diffusion layer, a barrier layer, etc.), or a combination thereof. The dummy gate dielectric includes a dielectric material, such as silicon oxide, a high-K dielectric material, other suitable dielectric materials, or a combination thereof. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon. The hard mask includes a suitable hard mask material, such as silicon nitride.

[0061] The source / drain recesses 335 may be formed by performing an etching process that removes the semiconductor layer stack 310U, the intermediate sacrificial layer 310M, and the semiconductor layer stack 310L in the source / drain of the fin 326, thereby exposing the mesas 14'. The etching process further removes some but not all of the mesas 14', so that the source / drain recesses 335 extend below the top surface of the substrate isolation structure 328. Each source / drain recess 335 has a corresponding sidewall formed by the corresponding remaining portion of the semiconductor layer stack 310U, the intermediate sacrificial layer 310M, and the semiconductor layer stack 310L in the channel region of the fin 326 and a bottom formed by the corresponding mesa 14'. In the depicted embodiment, after forming the source / drain recesses 335, each channel region includes an upper channel portion 340U (e.g., formed by the remainder of the semiconductor layer stack 310U) and a lower channel portion 340 (e.g., formed by the remainder of the semiconductor layer stack 310L) separated by a portion of the middle sacrificial layer 310M. In some embodiments, the etching process removes some but not all of the semiconductor layer stack 310L, and the source / drain recesses 335 have a bottom formed by the semiconductor layer 26 or the semiconductor layer 315. In some embodiments, the etching process stops at the mesa 14', and the source / drain recesses 335 do not extend below the substrate isolation structure 328. The etching process is a dry etch, a wet etch, other suitable etching, or a combination thereof. In some embodiments, the etching process is a multi-step etching process.

[0062] The method 200 continues at block 225 where internal spacers and epitaxial source / drain stacks are formed. Figure 4E and Figure 4F In one embodiment of block 225, an internal spacer 54 is formed below the gate spacer 44 along the sidewalls of the semiconductor layer 315. The internal spacer 54 displaces a portion of the semiconductor layer 315 below the gate spacer 44, separates the semiconductor layers 26 from each other, and separates the bottom semiconductor layer 26 from the mesa 14'. Forming the internal spacer 54 may include a first etching process, a deposition process, and a second etching process. The first etching process selectively etches the semiconductor layer 315, and the etching of the semiconductor layer 26 and the mesa 14' is negligible. The first etching process is configured to laterally etch the semiconductor layer 315 to reduce its length along the x-direction, thereby forming gaps between the semiconductor layers 26 and between the mesa 14' and the semiconductor layer 26, which separate adjacent semiconductor layers 26 and separate the mesa 14' from adjacent semiconductor layers 26. In some embodiments, the gaps extend laterally below the dummy gate stack 330. The deposition process forms a spacer layer that at least partially fills (and may completely fill) the gap, and the second etching process selectively etches the spacer layer, and the etching of the semiconductor layer 26 and the mesa 14' can be negligible, so that the remaining portion of the spacer layer forms the internal spacer 54. It should also be noted that the process used to form the internal spacer 54 is also used to remove the middle sacrificial layer 310M, and the spacer layer material (used to form the internal spacer 54) can also be formed in the empty space left by removing the middle sacrificial layer 310M to form the isolation structure 17A. In some embodiments, the internal spacer 54 and the isolation structure 17A include a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof. For example, the spacer layer may include a silicon nitride layer, a silicon carbonitride layer, a silicon carbon nitride oxide layer, a silicon carbon oxide layer, or a combination thereof.

[0063] In another embodiment of block 225, epitaxial source / drain stacks are formed in source / drain recesses 335 and dielectric layers (e.g., CESL 70U and ILD layer 72U) may be formed over the epitaxial source / drain stacks. Each epitaxial source / drain stack includes respective epitaxial source / drain 62U and 62L separated by respective source / drain isolation structures (e.g., CESL 70L and ILD layer 72L). The epitaxial source / drain 62L adjacent to the semiconductor layer 26 of the lower channel portion 340L may be formed by filling the bottom / lower portion of the source / drain recess 335 with one or more epitaxial semiconductor materials, filling the middle portion of the source / drain recess 335 with one or more dielectric materials (e.g., CESL 70L and ILD layer 72L) to form the isolation structure 18 adjacent to the isolation structure 17A (i.e., the trench isolation structure), and filling the top / upper portion of the source / drain recess 355 with one or more epitaxial semiconductor materials to form the epitaxial source / drain 62U adjacent to the semiconductor layer 26 of the upper channel portion 340U. The semiconductor layer 26 extending between the epitaxial source / drain 62U may be referred to as an upper semiconductor layer 26U, the conductor layer 26 extending between the epitaxial source / drain 62L may be referred to as a lower semiconductor layer 26L, and the insulating layer 26 extending between the isolation structures 18 may be referred to as an intermediate semiconductor layer 26M. Epitaxial source / drain 62L and epitaxial source / drain 62U are formed by any suitable epitaxial deposition and / or growth process. Isolation structure 18 can be formed by depositing CESL on epitaxial source / drain 62L, depositing an ILD layer on CESL, and etching back CESL and / or ILD layer to expose semiconductor layer 26 (e.g., semiconductor layer 26U) of upper channel portion 340U that will provide a channel for device 12U.

[0064] In the depicted embodiment, the isolation structure 16A is provided by the isolation structure 17A (i.e., the trench isolation structure and / or the gate isolation structure) and the isolation structure 18 (i.e., the source / drain isolation structure), which separates and / or electrically isolates the device 12L and the device 12U. The isolation structure 17A is disposed between the isolation structures 18. The isolation structure 18 extends to a distance above the dummy semiconductor layer (e.g., the semiconductor layer 26M thereof) of the channel portion 340U and a distance below the bottom active semiconductor layer (e.g., the bottom semiconductor layer 26U thereof) of the channel portion 34U, and the isolation structure 18 extends to a distance below the dummy semiconductor layer (e.g., the semiconductor layer 26M thereof) of the channel portion 340L and a distance above the top active semiconductor layer (e.g., the top semiconductor layer 26L thereof) of the channel portion 340L. The present disclosure contemplates other configurations of isolation structures 18 , such as isolation structures 18 disposed between isolation structures 17A but not between semiconductor layers 26M (ie, semiconductor layers 26M extend between respective epitaxial source / drains, but not isolation structures 18 ).

[0065] The method 200 proceeds to block 230 where the dummy gate stack is removed and a channel release process is performed. Figure 4F and Figure 4G In one embodiment of box 230, the dummy gate stack 330 is first removed to form a gate opening 337 (e.g., by a selective etching process). After the gate opening 337 is formed, the semiconductor layer 315 exposed by the formation of the gate opening 337 is selectively removed to form a gap / opening 339 between the semiconductor layers 26 and between the semiconductor layer 26 and the mesa 14' (e.g., by a selective etching process). According to embodiments disclosed herein, as a result of forming the gap / opening 339, the top semiconductor channel layer 26U and the bottom semiconductor channel layer 26L are exposed and are ready to subsequently form a gate structure thereon, wherein the gate structure includes a 2D dielectric material. Specifically, in some embodiments, a subsequently formed gate structure or portion thereof may fill the gap / opening 339 such that a portion of the gate structure may be formed around (e.g., surrounding) the top semiconductor channel layer 26U and the bottom semiconductor channel layer 26L.

[0066] The method 200 proceeds to block 235 where a gate structure including a 2D dielectric material is formed. For example, at block 235, Figure 2A The method 100 is used to form a gate structure for each of the devices 12L, 12U. Figure 4G and Figure 4HAfter exposing the semiconductor channel layers 26U, 26L, in one embodiment of block 235, a 2D dielectric material (e.g., 2D silicon oxide and / or 2D silicate) 79U is formed over the exposed surface of the top semiconductor channel layer 26U, and a 2D dielectric material (e.g., 2D silicon oxide and / or 2D silicate) 79L is formed over the exposed surface of the bottom semiconductor channel layer 26L. The 2D dielectric materials 79U, 79L may be formed as described above, and in some cases, the 2D dielectric materials 79U, 78L may be formed around (e.g., surrounding) a respective one of the top semiconductor channel layer 26U and the bottom semiconductor channel layer 26L. In various cases, the 2D dielectric materials 79U, 79L are not formed on the sidewall surfaces of the gate spacers 44 or on the sidewalls of the inner spacers 54, but are selectively formed on the exposed surfaces of the semiconductor channel layers 26U, 26L. In some embodiments, each of the 2D dielectric materials 79U, 79L may be the same. In other cases, each of the 2D dielectric materials 79U, 79L may be different. If the 2D dielectric materials 79U, 79L include 2D silicon oxide (c-SiOx), a dipole formation step (e.g., deposition of a dipole inducing layer and a thermal diffusion process on the 2D dielectric material) may be performed to form a silicate and substantially form a dipole within the silicate. If the 2D dielectric materials 79U, 79L include 2D silicates (c-MsiOx), a dipole may be formed within the silicate during deposition of the 2D silicate, and a separate dipole formation step may be omitted. In some embodiments, an optional buffer layer (e.g., buffer layer 165) may be formed above the semiconductor channel layer 26U, 26L before forming the 2D dielectric materials 79U, 79L. As previously described, the dipoles formed within the 2D dielectric materials 79U, 79L may be used to provide WF and Vt tuning of the devices 12L, 12U.

[0067] In another embodiment of block 235, after forming the 2D dielectric material 79U, 79L, still referring to Figure 4G and Figure 4HAs described above, a high-K dielectric layer is formed over the 2D dielectric materials 79U, 78L, and a metal gate electrode is formed on the high-K dielectric layer to complete the formation of the gate 90 that fills the gate opening 337 and the gap 339. In some embodiments, a planarization process may be performed to remove portions of the gate dielectric layer and / or portions of the gate electrode layer over the dielectric layer. Each gate 90 includes a corresponding gate 90L (e.g., a corresponding gate dielectric 78L, which includes a corresponding 2D dielectric material 79L, and a corresponding gate electrode 80L) and a corresponding gate 90U (e.g., a corresponding gate dielectric 78U, which includes a corresponding 2D dielectric material 79U, and a corresponding gate electrode 80U). The gate 90L is separated from the gate 90U by the intermediate dummy semiconductor layer 26M and the isolation structure 17A. In some embodiments, the gate 90L is separated from the gate 90U only by the isolation structure 17A. In the depicted embodiment, each channel region has two upper semiconductor layers 26U (which may be referred to as channel layers 26U) and two lower semiconductor layers 26L (which may be referred to as channel layers 26L). The channel layers 26U are stacked vertically along the z-direction and provide two channels for the transistor 20U, through which current can flow between the epitaxial source / drain 62U. The channel layers 26L are stacked vertically along the z-direction and provide two channels for the transistor 20L, through which current can flow between the epitaxial source / drain 62L. It will be appreciated that in other embodiments, each channel region of the channel layers 26, 26L may have a different number of channel layers (e.g., one, three, four, or five upper semiconductor layers 26U and one, three, four, or five lower semiconductor layers 26L).

[0068] In some embodiments, the gate 90U is recessed and / or etched back so that the top surface of the gate 90U is lower than the top surface of the ILD layer 72U, and a hard mask 92 (which may be referred to as a self-aligned contact (SAC) feature / structure) is formed on the gate 90U. The hard mask 92 includes a material different from the ILD layer 72U and / or a subsequently formed ILD layer to achieve etching selectivity during a subsequent etching process. In some embodiments, the hard mask 92 includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbides, or a combination thereof. In some embodiments, the hard mask 92 includes a metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HFO2), zirconium aluminum oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or a combination thereof. In some embodiments, the hard mask 92 includes an amorphous semiconductor material, such as amorphous silicon. In some embodiments, the hard mask 92 is formed by depositing a hard mask material to fill a recess formed on the gate 90U (e.g., a recess having sidewalls formed by the gate spacer 44 and a bottom formed by the recessed gate 90U) and planarizing the hard mask material.

[0069] The method 200 proceeds to block 240, where further processing is performed. For example, in some embodiments, fabricating the stacked device structure 10A may also include forming interconnects, such as gate contacts and / or source / drain contacts. For example, an upper source / drain contact may be formed in a dielectric layer (e.g., ILD layer 72U and / or CESL 70U) on the epitaxial source / drain 62U, and a lower source / drain contact may be formed on the epitaxial source / drain 62L. In some embodiments, a source / drain via may be formed that electrically connects the corresponding epitaxial source / drain 62U and the corresponding epitaxial source / drain 62L. In these embodiments, the source / drain via may be physically and / or electrically connected to an upper source / drain contact formed on the corresponding epitaxial source / drain 62U and a lower source / drain contact formed on the corresponding epitaxial source / drain 62L. Forming the source / drain contacts may include forming source / drain contact openings in the dielectric layer (or substrate 14) that expose the epitaxial source / drain 62U (or epitaxial source / drain 62L), and forming at least one conductive layer in the source / drain contact openings. In some embodiments, forming the source / drain contact openings includes forming a patterned mask layer (e.g., an etching mask) over the dielectric layer (or substrate), and etching the exposed portion of the dielectric layer. In some embodiments, forming at least one conductive layer in the source / drain contact openings includes forming a metal silicide layer over the epitaxial source / drain, depositing a barrier / liner layer that partially fills the source / drain contact openings, depositing a metal layer on the barrier / liner layer that fills the remaining portion of the source / drain contact openings, and performing a planarization process to remove portions of the barrier / liner layer and / or metal layer disposed over the top of the dielectric layer and / or gate structure. Thus, the source / drain contact may include a metal silicide layer, a barrier layer / liner layer, and a bulk metal layer, wherein the barrier / liner layer is located between the bulk metal layer and the dielectric layer (or substrate) and between the bulk metal layer and the metal silicide. In some embodiments, one or more insulating layers may be formed in the source / drain contact openings and processed to form contact spacers, such as dielectric layers and air gaps, along the sidewalls of the conductive portions of the source / drain contacts.

[0070] Reference now Figure 5 , which shows a method for sequentially manufacturing a stacked device structure (e.g. Figure 1B Flowchart of method 500 of stacked device structure 10B) that implements forming Figure 2A-2F The gate structure has been simplified for clarity. Figure 5 The method 500 of the present disclosure is provided to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after the method 500, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 500.

[0071] Figure 6A-6G is a partial or full cross-sectional view of a stacked device structure 10B at various sequential manufacturing stages according to various aspects of the present disclosure, for example, in the process of forming Figure 2A-2F The gate structure method is Figure 5 The method 500 is related to the following stages. For the sake of clarity, Figure 6A-6G It is simplified to better understand the inventive concepts of the present disclosure. Figure 6A-6G Additional steps may be provided before, during, and after the sequential manufacturing steps, and for Figure 6A-6G Additional embodiments of sequential manufacturing stages may move, replace or eliminate some of the steps described. Figure 6A-6G Additional features can be added to the stacked device structure 10B, and can be Figure 6A-6G Some of the features described below may be replaced, modified, or eliminated in other embodiments of the stacked device structure 10B.

[0072] Reference Fig. 6A , in one embodiment of box 505, manufacturing the stacked device structure 10B includes forming a first device, which may include the above-mentioned device 12L. Therefore, in some examples, as described above, the first device of box 505 can be substantially the same as the device 12L of the stacked device structure 10A. Forming device 12L may include forming a semiconductor layer stack on a corresponding substrate 14, and patterning the semiconductor layer stack (and substrate 14 in some embodiments) to form a fin extending from substrate 14. The semiconductor layer stack may be similar to semiconductor layer stack 310L. For example, the semiconductor layer stack may include a stacked first semiconductor layer (e.g., semiconductor layer 26) and a second semiconductor layer vertically (e.g., along the Z direction) in a staggered and / or alternating configuration from the top surface of substrate 14. The second semiconductor layer (e.g., a silicon germanium layer) may be similar to the above-mentioned semiconductor layer 315. The fin may be similar to fin 326. For example, the fin may include a patterned portion of the semiconductor layer stack and a patterned portion of the substrate 14 (i.e., the mesa 14'), as described above with reference to Figure 4C In some embodiments, forming device 12L may include forming a substrate isolation structure adjacent to and / or surrounding the lower portion of the fin, such as substrate isolation structure 328, as described above with reference to Figure 4D described.

[0073] Forming the device 12L may also include forming a dummy gate structure over the channel region of the fin, forming a source / drain recess in the source / drain region of the fin, and forming an internal spacer 54L. In some embodiments, forming the dummy gate structure includes forming at least one dummy gate layer (e.g., a dummy gate dielectric, a dummy gate electrode, and a hard mask layer) over the fin, patterning the at least one dummy gate layer to form a dummy gate stack, and forming a gate spacer 44L along the sidewalls of the dummy gate stack. The dummy gate stack and the gate spacer 44L may be similar to those described above with reference to Figure 4E The dummy gate stack 330 and gate spacer 44 are described. In some embodiments, forming the source / drain recess may include performing an etching process that selectively removes the first semiconductor layer and the semiconductor layer relative to the gate structure. The remaining portion of the first semiconductor layer of the fin (e.g., semiconductor layer 26) forms a channel layer 26L in the channel region, as described below and above with reference to Figure 4F In some embodiments, forming the inner spacers 54L includes laterally etching the second semiconductor layer to form gaps between the first semiconductor layers and between the first semiconductor layer and the mesas 14', and at least partially filling the gaps with a dielectric material (e.g., depositing and etching a dielectric layer), as described above with reference to Figure 4F described.

[0074] Forming the device 12L may also include forming epitaxial source / drain 62L in the source / drain recesses and forming a dielectric layer (eg, CESL 70L and ILD layer 72L) over the epitaxial source / drain 62L, as described above with reference to Figure 4F Forming the device 12L may also include removing the dummy gate stack (to form a gate opening) and performing a channel release process (to form a gap / opening between the semiconductor channel layers and between the semiconductor channel and the mesa 14'), as described above with reference to Figure 4G The formation of the device 12L may also include forming a gate structure including a 2D dielectric material. For example, after forming a gate opening and performing a channel release process, a 2D dielectric material (e.g., 2D silicon oxide and / or 2D silicate) 79L is formed on the exposed surface of the semiconductor channel layer 26L, as described above with reference to Figure 4G Forming the device 12L may also include forming a high-K dielectric layer on the 2D dielectric material 79L and forming a metal gate electrode on the high-K dielectric layer to complete the formation of the gate 90L filling the gate opening and the gap formed by the channel release process, as described above with reference to Figure 4HIn some embodiments, a planarization process is also performed to remove a portion of the gate dielectric layer and / or a portion of the gate electrode layer disposed on the gate dielectric layer. The gate dielectric layer and / or the gate electrode layer fills the gap so that the gate dielectric layer and / or the gate electrode layer can be formed around (e.g., surround) the semiconductor channel layer 26L. In some embodiments, forming the device 12L can also include forming a hard mask 92L (e.g., a SAC structure) on the gate 90L, as described above with reference to Figure 4H described.

[0075] In some embodiments, fabrication of device 12L may further include forming interconnects in device 12L, such as gate contacts and / or source / drain contacts. For example, source / drain contacts may be formed in a dielectric layer (e.g., ILD layer 72L and / or CESL 70L) on epitaxial source / drain 62L. Forming source / drain contacts may include forming source / drain contact openings in the dielectric layer that expose epitaxial source / drain 62L, and forming at least one conductive layer (e.g., metal) in the source / drain contact openings. In some embodiments, forming source / drain contact openings includes forming a patterned mask layer (e.g., an etch mask) on the dielectric layer and etching exposed portions of the dielectric layer. In some embodiments, forming at least one conductive layer in the source / drain contact opening includes forming a metal silicide layer on the epitaxial source / drain 62L, depositing a barrier / liner layer that partially fills the source / drain contact opening, depositing a metal layer on the barrier / liner layer that fills the remaining portion of the source / drain contact opening, and performing a planarization process to remove portions of the barrier / liner layer and / or metal layer disposed on top of the dielectric layer and / or gate structure. Thus, the source / drain contact may include a metal silicide layer, a barrier / liner layer, and a bulk metal layer, wherein the barrier / liner is between the bulk metal layer and the dielectric layer (e.g., CESL 70L) and between the bulk metal layer and the metal silicide. In some embodiments, one or more insulating layers may be formed in the source / drain contact opening and processed to form contact spacers, such as dielectric layers and air gaps, along the sidewalls of the conductive portions of the source / drain contacts.

[0076] After fabricating the device 12L, the method 500 continues to block 510 where the first device is bonded to a device precursor to fabricate a second device. Figure 6B In an embodiment of block 510, device 12L is bonded to a device precursor to fabricate a second device (device 12U). The device precursor of device 12U includes a semiconductor layer stack 610 disposed on a corresponding substrate 14. Semiconductor layer stack 610 includes semiconductor layer 26 and semiconductor layer 615 stacked vertically (e.g., along the z-direction) in a staggered and / or alternating configuration from a top surface of substrate 14. Semiconductor layer 615 (e.g., a silicon germanium layer) may be similar to semiconductor layer 315 described above.

[0077] like Figure 6B As shown, the device precursor of device 12U (e.g., its back side) is attached and / or bonded to device 12L (e.g., the front side). Attachment / bonding may include flipping the device precursor of device 12U, aligning device 12U and device 12L, contacting the device precursor of device 12AU to device 12L, and performing an annealing process to provide a stacked device structure. For example, under temperature, pressure, atmosphere, or a combination thereof, the bonding dielectric layer 620U of the device precursor of device 12U is brought into contact with the bonding dielectric layer 620L of device 12L (or vice versa) for a period of time to achieve bonding of the bonding dielectric layer 620U and the bonding dielectric layer 620L. In some embodiments, one or both of the bonding dielectric layer 620U and the bonding dielectric layer 620 may include a plasma-activated bonding dielectric layer. After bonding, device 12L is attached to and electrically isolated from the device precursor of device 12U by insulating / bonding layer 625, which includes bonding dielectric layer 620U and bonding dielectric layer 620L. Therefore, at this stage of processing, insulating / bonding layer 625 provides an isolation structure 16B of stacked device structure 10B, which electrically isolates and separates device 12L and device 12U. In some embodiments, the thickness of insulating / bonding layer 625 is approximately 10nm-100 microns. In some examples, the thickness of insulating / bonding layer 625 is approximately 1-100nm. In some cases, the thickness of insulating / bonding layer 625 is approximately 10-50nm. Figure 6C , and to facilitate the embodiment of block 510 , fabricating the stacked device structure 10B includes performing a thinning process to remove the substrate 14 and the top semiconductor layer 615 from the device precursor of the device 12U.

[0078] After bonding the first device to a device precursor for fabricating a second device, method 500 proceeds to block 515, where fabricating stacked device structure 10B includes forming a second device, which may include device 12U described above. Thus, in some examples, as previously described, forming the second device of block 515 may be substantially the same as forming device 12U of stacked device structure 10A.

[0079] refer to Figure 6C and Fig.6D, forming the device 12U may include patterning the semiconductor layer stack 610 to form a fin 626 extending from the isolation structure 16B, forming a dummy gate stack 630 above a portion of the fin 626, forming a gate spacer 44U along a sidewall of the dummy gate stack 630, and forming a source / drain recess 635. The dummy gate stack 630 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fin 626. For example, the dummy gate stack 630 extends along the y-direction, has a length in the y-direction, has a width in the x-direction, and has a height in the z-direction. In the XZ plane, the dummy gate stack 630 is disposed above the top of the channel region (C) of the fin 626 and / or the stacked device structure 10B, and the dummy gate stack 630 is disposed between the source / drain regions (S / D) of the fin 626 and / or the stacked device structure 10B. In the YZ plane, the dummy gate stack 630 may be disposed on the top and sidewalls of the fin 626, and the dummy gate stack 630 may wrap the channel region. The dummy gate stack 630 may be similar to the dummy gate stack 330, as described above with reference to Figure 4E For example, the dummy gate stack 630 may include a dummy gate dielectric, a dummy gate electrode, a hard mask, other suitable layers, or a combination thereof.

[0080] The source / drain recess 635 can be formed by performing an etching process that removes the semiconductor layer stack 610 in the source / drain region of the fin 626, thereby exposing the insulating / bonding layer 625 (e.g., its bonding dielectric layer 620U). Each source / drain recess 635 has a corresponding sidewall formed by the corresponding remaining portion of the semiconductor layer stack 610 in the channel region of the fin 626 and a bottom formed by the bonding dielectric layer 620U. In the depicted embodiment, after forming the source / drain recess 635, each channel region has a channel portion 640 formed by the remaining portion of the semiconductor layer stack 610. The channel portion 640 is separated from the channel portion / gate portion of the device 12L by the insulating / bonding layer 625. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process is a multi-step etching process.

[0081] Reference Fig.6D and Fig. 6E , forming the device 12U may also include forming an inner spacer 54U along the sidewall of the semiconductor layer 615 below the gate spacer 44U, as described above with reference to Figure 4F The epitaxial source / drain 62U is formed in the source / drain recess 635, as described above with reference to Figure 4F and forming a dielectric layer (eg, CESL70U and ILD layer 72U) over the epitaxial source / drain 62U, as described above with reference to Figure 4FThe epitaxial source / drain 62U is vertically disposed above the epitaxial source / drain 62L, and the epitaxial source / drain 62U may be electrically isolated from the epitaxial source / drain 62L and / or its source / drain contacts (e.g., source / drain contacts disposed in the ILD layer 72L and / or the CESL 70L, which may extend from the insulating / bonding layer 625 to the epitaxial source / drain 62L). The semiconductor layer 26 extending between the epitaxial source / drain 62U may be referred to as an upper semiconductor layer 26U. The dielectric layer may be formed by depositing the CESL 70U above the epitaxial source / drain 62U, depositing the ILD layer 72L above the CESL 70L, and performing a planarization process, which may be stopped when reaching the gate structure (e.g., the dummy gate stack 630).

[0082] refer to Fig. 6E and Fig. 6F , forming the device 12U may also include removing the dummy gate stack 630 to form a gate opening 637, followed by performing a channel release process to selectively remove the semiconductor layer 615, thereby forming a gap / opening 639 between the semiconductor layers 26U and between the semiconductor layer 26U and the insulating / bonding layer 625 (e.g., by a selective etching process), as described above with reference to Figure 4G According to the embodiments disclosed herein, as a result of forming the gap / opening 639, the semiconductor channel layer 26U of the device 12U is exposed and is ready to subsequently form a gate structure thereon, wherein the gate structure includes a 2D dielectric material. Specifically, in some embodiments, the subsequently formed gate structure or a portion thereof may fill the gap / opening 639, such that a portion of the gate structure may be formed around (e.g., surrounding) the semiconductor channel layer 26U of the device 12U.

[0083] Still refer to Fig. 6E and Fig. 6F , forming the device 12U may also include forming a gate structure including a 2D dielectric material. Figure 2AMethod 100 is used to form the gate structure of device 12U. After exposing the semiconductor channel layer 26U, a 2D dielectric material (e.g., 2D silicon oxide and / or 2D silicate) 79U is formed on the exposed surface of the semiconductor channel layer 26U. The 2D dielectric material 79U can be formed as described above, and in some cases, the 2D dielectric material 79U can be formed around (e.g., surrounding) the semiconductor channel layer 26U. In various cases, the 2D dielectric material 79U is not formed on the sidewall surface of the gate spacer 44U or the sidewall surface of the internal spacer 54U, but is selectively formed on the exposed surface of the semiconductor channel layer 26U. In some embodiments, the 2D dielectric material 79U can be the same as that used in the gate dielectric material of device 12L. In other cases, the 2D dielectric material 79U can be different from the dielectric material used in the gate dielectric of device 12L. If the 2D dielectric material 79U includes 2D silicon oxide (c-SiOx), a dipole forming step (e.g., deposition of a dipole inducing layer and a thermal diffusion process over the 2D dielectric material) may be performed to form a silicate and substantially form a dipole within the silicate. If the 2D dielectric material 79U includes a 2D silicate (c-MsiOx), a dipole may be formed within the silicate during deposition of the 2D silicate, and a separate dipole forming step may be omitted. In some embodiments, an optional buffer layer (e.g., buffer layer 165) may be formed over the semiconductor channel layer 26U prior to forming the 2D dielectric material 79U. As previously described, the dipole formed within the 2D dielectric material 79U (and within the 2D dielectric material 79L of the device 12L) may be used to provide WF and Vt tuning of the device.

[0084] Reference Fig. 6F and Figure 6G , forming device 12U may also include forming a high-K dielectric layer over 2D dielectric material 79U and forming a metal gate electrode over the high-K dielectric layer, as described above, to complete the formation of gate 90U filling gate opening 637 and gap 639. In some embodiments, a planarization process may be performed to remove portions of the gate dielectric layer and / or portions of the gate electrode layer over the dielectric layer. Gate 90U includes a corresponding gate dielectric 78U, which includes a corresponding 2D dielectric material 79U, and a corresponding gate electrode 80U. Gate 90U is separated from gate 90L by isolation structure 17B.

[0085] In some embodiments, forming the device 12U may further include forming a hard mask 92U (eg, a SAC structure) over the gate 90U, as described above with reference to Figure 4HIn some embodiments, fabricating the stacked device structure 10B may also include forming interconnects of the device 12U, such as gate contacts and / or source / drain contacts. For example, the source / drain contacts may be formed in a dielectric layer (e.g., ILD layer 72U and / or CESL 70U) on the epitaxial source / drain 62U, as described above with reference to Fig. 6A In some embodiments, a source / drain via may be formed that electrically connects the corresponding epitaxial source / drain 62U and the corresponding epitaxial source / drain 62L. In these embodiments, the source / drain via may be physically and / or electrically connected to a first source / drain contact formed on the corresponding epitaxial source / drain 62U and a second source / drain contact formed on the corresponding epitaxial source / drain 62L.

[0086] In the illustrated embodiment, the isolation structure 16B is provided by the isolation structure 17B, which separates and / or electrically isolates the channel regions and source / drain regions of the device 12U and the device 12L. For example, each channel region has two upper semiconductor layers 26U (upper channel layers) and two lower semiconductor layers 26L (lower channel layers) surrounded and / or wrapped by the gate 90U and the gate 90L, respectively, and the gate 90U is separated and / or electrically isolated from the gate 90L by the isolation structure 17B. The semiconductor layer 26U is stacked vertically along the Z direction and provides two channels for the transistor 20U, and the current can flow between the epitaxial source / drain 62U, and the semiconductor layer 26L is stacked vertically along the Z direction and provides two channels for the transistor 20L, and the current can flow between the epitaxial source / drain 62L through the channels. In addition, the epitaxial source / drain 62U may be separated and / or electrically isolated from the epitaxial source / drain 62L and / or its source / drain contacts (e.g., source / drain contacts disposed in the ILD layer 72L and / or the CESL 70L, which may extend from the insulating / bonding layer 625 to the epitaxial source / drain 62L) by the isolation structure 17B, wherein the isolation structure 17B is formed by the insulating / bonding layer 625. It should be understood that in other embodiments, each channel region of the channel layers 26U, 26L may have a different number of channel layers (e.g., one, three, four, or five upper semiconductor layers 26U and one, three, four, or five lower semiconductor layers 26L).

[0087] The devices and / or structures described herein, such as the stacked device structure 10A, the stacked device structure 10B, the device 12L, the device 12U, the transistor 20L, the transistor 20U, etc., may be included in a microprocessor, a memory, other IC devices, or a combination thereof. In some embodiments, the devices and / or structures described herein, such as the stacked device structure 10A, the stacked device structure 10B, the device 12L, the device 12U, the transistor 20L, the transistor 20U, etc., are part of an IC chip, a system on a chip (SoC), or a portion thereof, including various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal oxide semiconductor FETs (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other devices, or a combination thereof.

[0088] The various embodiments described herein provide several advantages over the prior art. It should be understood that not all advantages are necessarily discussed herein, all embodiments do not require specific advantages, and other embodiments may provide different advantages. As an example, the embodiments discussed herein include gate dielectric materials and related methods for stacked device structures (such as stacked transistor structures). In some embodiments, the 2D dielectric material is disposed between the semiconductor channel layer and the high-K dielectric layer of the gate structure. In various examples, the 2D dielectric material may include 2D silicon oxide and / or 2D silicate (e.g., c-SiOx, c-MSiOx, where "M" is a metal). Specifically, the 2D dielectric material disclosed herein provides Vt tuning and EOT reduction without compromising device performance. For example, the interface between the 2D dielectric material and the underlying semiconductor channel layer (e.g., Si) is substantially flat, thereby promoting improved device performance. The crystalline structure of the 2D dielectric material, for example, in contrast to the amorphous SiOx used in some existing embodiments, also provides enhanced device reliability. In various embodiments, the ultra-thin thickness of the 2D dielectric material provides a scalable EOT, further improving device performance. Furthermore, in some embodiments, 2D dielectric materials can be doped directly during deposition to form dipoles in a controllable manner (eg, for WF and Vt tuning). Additional benefits and / or other advantages will become apparent to those skilled in the art having the benefit of this disclosure.

[0089] Therefore, one embodiment of the present disclosure describes a method of manufacturing a semiconductor device, comprising: forming a two-dimensional (2D) dielectric material above a semiconductor channel layer; depositing a gate dielectric layer above the 2D dielectric material; and forming a metal gate electrode above the gate dielectric layer; wherein a dipole is substantially formed within the 2D dielectric material.

[0090] In some embodiments, the semiconductor device includes a monolithic stacked device structure having a first device vertically stacked above a second device, wherein the first device and the second device have corresponding first gate stacks and second gate stacks, and wherein at least one of the first gate stack and the second gate stack includes a 2D dielectric material disposed above a corresponding semiconductor channel layer, a gate dielectric layer disposed above the 2D dielectric material, and a metal gate electrode disposed above the gate dielectric layer.

[0091] In some embodiments, a semiconductor device includes a sequentially stacked device structure having a first device vertically stacked above a second device, wherein the first device and the second device have corresponding first gate stacks and second gate stacks, and wherein at least one of the first gate stack and the second gate stack includes a 2D dielectric material disposed above a corresponding semiconductor channel layer, a gate dielectric layer disposed above the 2D dielectric material, and a metal gate electrode disposed above the gate dielectric layer.

[0092] In some embodiments, the 2D dielectric material includes crystalline 2D silicon oxide (c-SiOx) or crystalline 2D silicate (c-MSiOx), and wherein "M" is a metal.

[0093] In some embodiments, the method further includes: forming a buffer layer over the semiconductor channel layer before forming the 2D dielectric material; and forming the 2D dielectric material over the buffer layer.

[0094] In some embodiments, the buffer layer includes a crystalline oxide layer or a crystalline nitride layer.

[0095] In some embodiments, the method further comprises: after forming the 2D dielectric material and before depositing the gate dielectric layer, performing a dipole forming step to form a dipole within the 2D dielectric material.

[0096] In some embodiments, the metal includes a dipole-inducing metallic element, and wherein a dipole within the 2D dielectric material is formed during formation of the 2D dielectric material.

[0097] In some embodiments, the gate dielectric layer includes a high-K dielectric layer.

[0098] In some embodiments, the 2D dielectric material is formed at a temperature between about 350-750 degrees Celsius.

[0099] In another embodiment, a method is discussed that includes forming a stacked device structure that includes a first device vertically stacked above a second device. In some embodiments, the first device and the second device have corresponding first gate stacks and second gate stacks. In some examples, forming at least one of the first gate stack and the second gate stack includes: performing a channel release process to selectively remove a dummy layer from between adjacent channel layers and forming a gap between adjacent channel layers, the gap exposing relative surfaces of adjacent channels; forming a two-dimensional (2D) dielectric material above the exposed relative surfaces of the adjacent channel layers, wherein the 2D dielectric material includes a dipole inducing element that provides a dipole within the 2D dielectric material. In some examples, forming at least one of the first and second gate stacks also includes: depositing a high-K gate dielectric above the 2D dielectric material.

[0100] In some embodiments, forming the 2D dielectric material includes forming the 2D dielectric material surrounding at least one of the adjacent channel layers.

[0101] In some embodiments, the 2D dielectric material includes crystalline 2D silicon oxide (c-SiOx) or crystalline 2D silicate (c-MSiOx), and wherein "M" is a metal.

[0102] In some embodiments, the method further includes: before forming the 2D dielectric material, forming a buffer layer over exposed opposing surfaces of the adjacent channel layer; and forming the 2D dielectric material over the buffer layer.

[0103] In some embodiments, the buffer layer includes a crystalline oxide layer or a crystalline nitride layer.

[0104] In some embodiments, the method further includes, after forming the 2D dielectric material and before depositing the high-K gate dielectric, performing a thermal diffusion process to form a dipole within the 2D dielectric material.

[0105] In some embodiments, the first device and the second device include gate-all-around (GAA) devices, and wherein the stacked device structure includes complementary field effect transistors (CFETs).

[0106] In another embodiment, a semiconductor device is discussed, comprising: a semiconductor channel layer, a two-dimensional (2D) dielectric material disposed above the semiconductor channel, a high-K dielectric layer disposed above the 2D dielectric material, and a metal gate electrode disposed above the high-K dielectric layer. In some embodiments, the 2D dielectric material includes a dipole inducing element that forms a dipole within the two-dimensional dielectric material. The dipole is used to modulate a threshold voltage (Vt) of the semiconductor device.

[0107] In some embodiments, the 2D dielectric material includes crystalline 2D silicon oxide (c-SiOx) or crystalline 2D silicate (c-MSiOx), and wherein "M" is a metal.

[0108] In some embodiments, a semiconductor device includes a stacked device structure having a first device vertically stacked above a second device, wherein the first device and the second device include corresponding first gate stacks and second gate stacks, and wherein at least one of the first gate stack and the second gate stack includes a 2D dielectric material disposed above a corresponding semiconductor channel layer, a high-K dielectric layer disposed above the 2D dielectric material, and a metal gate electrode disposed above the high-K dielectric layer.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a two-dimensional dielectric material over the semiconductor channel layer; depositing a gate dielectric layer over the two-dimensional dielectric material; as well as forming a metal gate electrode over the gate dielectric layer; Wherein the dipoles are substantially formed within the two-dimensional dielectric material.

2. The method according to claim 1, wherein: The semiconductor device includes a monolithic stacked device structure, the monolithic stacked device structure having a first device vertically stacked above a second device, wherein the first device and the second device have corresponding first gate stacks and second gate stacks, and wherein at least one of the first gate stack and the second gate stack includes the two-dimensional dielectric material disposed above the corresponding semiconductor channel layer, the gate dielectric layer disposed above the two-dimensional dielectric material, and the metal gate electrode disposed above the gate dielectric layer.

3. The method according to claim 1, wherein: The semiconductor device includes a sequential stacked device structure, the sequential stacked device structure having a first device vertically stacked above a second device, wherein the first device and the second device have corresponding first gate stacks and second gate stacks, and wherein at least one of the first gate stack and the second gate stack includes the two-dimensional dielectric material disposed above a corresponding semiconductor channel layer, the gate dielectric layer disposed above the two-dimensional dielectric material, and the metal gate electrode disposed above the gate dielectric layer.

4. The method according to claim 1, wherein: The two-dimensional dielectric material includes crystalline two-dimensional silicon oxide (c-SiOx) or crystalline two-dimensional silicate (c-MSiOx), and wherein "M" is a metal.

5. The method according to claim 4, wherein: The metal comprises a dipole inducing metallic element, and wherein the dipole within the two-dimensional dielectric material is formed during formation of the two-dimensional dielectric material.

6. The method according to claim 1, wherein: The two-dimensional dielectric material is formed at a temperature between about 350 degrees Celsius and 750 degrees Celsius.

7. A method for manufacturing a semiconductor device, comprising: forming a stacked device structure comprising a first device vertically stacked above a second device, wherein the first device and the second device have corresponding first and second gate stacks, and wherein forming at least one of the first and second gate stacks comprises: performing a channel release process to selectively remove the dummy layer from between adjacent channel layers and form a gap between the adjacent channel layers, the gap exposing opposite surfaces of the adjacent channels; forming a two-dimensional dielectric material over the exposed opposing surfaces of the adjacent channel layer, wherein the two-dimensional dielectric material includes a dipole-inducing element that provides a dipole within the two-dimensional dielectric material; and A high-K gate dielectric is deposited over the two-dimensional dielectric material.

8. The method according to claim 7, further comprising: before forming the two-dimensional dielectric material, forming a buffer layer over the exposed opposing surfaces of the adjacent channel layer; as well as The two-dimensional dielectric material is formed over the buffer layer.

9. The method according to claim 8, wherein: The buffer layer includes a crystalline oxide layer or a crystalline nitride layer.

10. A semiconductor device comprising: Semiconductor channel layer; A two-dimensional dielectric material is disposed above the semiconductor channel layer; a high-K dielectric layer disposed above the two-dimensional dielectric material; as well as A metal gate electrode, disposed above the high-K dielectric layer; The two-dimensional dielectric material includes a dipole-inducing element that forms a dipole within the two-dimensional dielectric material.

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