Semiconductor device

Abstract

The invention provides a semiconductor device capable of suppressing deterioration of characteristics. The semiconductor device includes: a substrate having a main surface and a back surface facing the main surface; a first FET group provided on the main surface and including a plurality of first source electrodes, a plurality of first drain electrodes, and a plurality of first gate electrodes arranged in a first direction; a second FET group that is provided on the main surface, overlaps the first FET group when viewed from a second direction intersecting the first direction, and includes a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes; a plurality of first gate pads provided on the main surface between the first FET group and the second FET group and electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes; a plurality of drain wires provided on the main surface alternately with the plurality of first gate pads between the first FET group and the second FET group, the plurality of drain wires electrically connecting the plurality of first drain electrodes and the plurality of second drain electrodes, respectively; and a drain pad electrically connected to the plurality of first drain electrodes such that the first FET group is disposed between the drain pad and the plurality of first gate pads.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] A field effect transistor (FET) having a source electrode, a gate electrode, and a drain electrode is known. Two FET groups having a plurality of FETs arranged in a parallel direction of the electrodes are arranged in the extending direction of the electrodes. A gate pad connected to the gate electrode and a drain pad connected to the drain electrode are provided between the FET groups (for example, Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 5-252036

[0006] Patent Document 2: U.S. Patent No. 11417746

[0007] However, since the gate pad and the drain pad are adjacent to each other, gate / drain parasitic capacitance is generated, and thus the characteristics of the FET are deteriorated. Summary of the invention

[0008] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics.

[0009] One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first FET group arranged on the main surface and comprising a plurality of first source electrodes, a plurality of first drain electrodes and a plurality of first gate electrodes arranged in a first direction; a second FET group arranged on the main surface, overlapping with the first FET group when viewed from a second direction intersecting the first direction, and comprising a plurality of second source electrodes, a plurality of second drain electrodes and a plurality of second gate electrodes; a plurality of first gate pads arranged on the main surface between the first FET group and the second FET group and electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes; a plurality of drain wirings arranged on the main surface between the first FET group and the second FET group alternately with the plurality of first gate pads, electrically connecting the plurality of first drain electrodes to the plurality of second drain electrodes, respectively; and a drain pad electrically connected to the plurality of first drain electrodes, so that the first FET group is configured between the drain pad and the plurality of first gate pads.

[0010] Effects of the Invention

[0011] According to the present disclosure, degradation of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a top view of the semiconductor device of Example 1.

[0013] Figure 2 1 is a top view of the semiconductor device of Example 1.

[0014] Figure 3 This is an enlarged top view of the semiconductor device of Example 1.

[0015] Figure 4 yes Figure 3 A-A section view.

[0016] Figure 5 yes Figure 3 B-B section view.

[0017] Figure 6 yes Figure 3 C-C section view.

[0018] Figure 7 yes Figure 3 D-D section view.

[0019] Figure 8 3 is a top view of the semiconductor device of Comparative Example 1.

[0020] Fig. 9 3 is a top view of a semiconductor device according to Comparative Example 2.

[0021] Fig.10 This is an enlarged top view of a semiconductor device according to Modification 1 of Embodiment 1.

[0022] Fig.11 It is a top view of a semiconductor device according to a second variation of the first embodiment.

[0023] Fig.12 It is a top view of a semiconductor device according to a third variation of the first embodiment.

[0024] Fig.13 It is a top view of a semiconductor device according to a fourth variation of the first embodiment.

[0025] Fig.14 It is a top view of a semiconductor device according to a fifth variation of the first embodiment.

[0026] Fig.15 It is a top view of the semiconductor device of Example 2.

[0027] Fig.16 yes Fig.15 Equivalent circuit diagram of .

[0028] Fig.17 It is a top view of a semiconductor device according to a first variation of the second embodiment.

[0029] Fig.18 yes Fig.17 Equivalent circuit diagram of .

[0030] Fig.19 3 is a top view of a semiconductor device of Comparative Example 3.

[0031] Description of reference numerals:

[0032] 10, 10a: substrate;

[0033] 10b: semiconductor layer;

[0034] 11a (first active region), 11b (second active region): active regions;

[0035] 12a (first source electrode), 12b (second source electrode): source electrodes;

[0036] 13a (first part, fourth part), 13b (second part, fifth part), 13c (third part, sixth part): source part;

[0037] 13: inactive area;

[0038] 14, 14a (first gate electrode), 14b (second gate electrode): gate electrodes;

[0039] 15a, 15b, 15c, 15d: gate portion;

[0040] 16a (first drain electrode), 16b (second drain electrode): drain electrodes;

[0041] 17a, 17b, 17c, 17d: drain portion;

[0042] 18, 18a (first gate wiring), 18b (second gate wiring), 19, 19a, 19b: gate wiring;

[0043] 20a, 20b: vias;

[0044] 21a, 21b, 21c: active part;

[0045] 22, 22a, 22b: source wiring;

[0046] 23a, 23b, 23c: wiring part;

[0047] 25: insulation layer;

[0048] 26: Drain wiring;

[0049] 26a, 26b, 26c: Partial;

[0050] 27a: gate metal layer;

[0051] 27b: wiring layer;

[0052] 28, 28a: metal layer;

[0053] 30a (first FET group), 30b (second FET group), 30c, 30d: FET group;

[0054] 31, 31a, 31b, 31c, 31d: FET;

[0055] 34 (first gate pad), 35 (second gate pad): gate pad;

[0056] 36: drain pad;

[0057] 42a, 42b: source pads;

[0058] 43a, 43b: connection wiring;

[0059] 44a, 44b: protection ring;

[0060] 50: Main side;

[0061] 51: back;

[0062] 52: packaging;

[0063] 53: base;

[0064] 54: frame;

[0065] 55a, 55b, 55c: capacitive components;

[0066] 56: dielectric substrate;

[0067] 57: electrode;

[0068] 58, 59: lead wire;

[0069] 60, 60a, 60b: semiconductor chip;

[0070] 62: matching circuit;

[0071] 63: High harmonic processing circuit;

[0072] 71, 72, 72a (third bonding line), 73 (first bonding line), 74 (second bonding line), 75 (first bonding line): bonding line;

[0073] 100, 101, 102, 103, 104, 105, 106, 107, 110, 112, 114: semiconductor devices. DETAILED DESCRIPTION

[0074] [Description of Embodiments of the Present Disclosure]

[0075] First, the contents of the embodiments of the present disclosure will be listed and described.

[0076] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first FET group provided on the main surface and having a plurality of first source electrodes, a plurality of first drain electrodes, and a plurality of first gate electrodes arranged in a first direction; a second FET group provided on the main surface and overlapping with the first FET group when viewed from a second direction intersecting the first direction, and having a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes; a plurality of first gate pads provided on the main surface between the first FET group and the second FET group and electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes; a plurality of drain wirings provided on the main surface between the first FET group and the second FET group alternately with the plurality of first gate pads and electrically connecting the plurality of first drain electrodes to the plurality of second drain electrodes respectively; and a drain pad electrically connected to the plurality of first drain electrodes, so that the first FET group is arranged between the drain pad and the plurality of first gate pads. Thus, gate / drain capacitance can be suppressed. Therefore, high frequency characteristics can be improved.

[0077] (2) In the above (1), there may be provided a back metal layer, the back metal layer being provided on the back surface and being electrically connected to the plurality of first source electrodes via a plurality of first via holes respectively overlapping the plurality of first source electrodes when viewed from the thickness direction of the substrate, and being electrically connected to the plurality of second source electrodes via a plurality of second via holes respectively overlapping the plurality of second source electrodes when viewed from the thickness direction of the substrate. Thus, the source inductance can be suppressed and the high frequency characteristics can be improved.

[0078] (3) In the above (1) or (2), the first FET group and the second FET group may be respectively provided in the first active region and the second active region of the main surface, and the plurality of first gate pads may be provided in the inactive region of the main surface deactivated and provided between the first active region and the second active region. Thus, the gate / source capacitance can be suppressed and the high frequency characteristics can be improved.

[0079] (4) In any of the above (1) to (3), the width of the plurality of drain wirings between the first FET group and the second FET group in the first direction may be smaller than the width of the plurality of first drain electrodes in the first direction and the width of the plurality of second drain electrodes in the first direction. This can suppress gate / drain capacitance and improve high-frequency characteristics.

[0080] (5) In any one of the above (1) to (4), a second gate pad may be provided on the main surface so that the second FET group is arranged between the second gate pad and the plurality of first gate pads, and is electrically connected to the plurality of second gate electrodes. Thus, bonding wires can be bonded at two locations.

[0081] (6) In any of the above (1) to (5), each of the plurality of first source electrodes may include: a first portion; and a second portion and a third portion, wherein the second portion and the third portion overlap with the first portion when viewed from the second direction, are disposed between the first portion and a corresponding first gate pad among the plurality of first gate pads, and are arranged in the first direction, and the first FET group includes a plurality of first gate wirings, each of the plurality of first gate wirings is disposed between the second portion and the third portion, and electrically connects at least one first gate electrode among the plurality of first gate electrodes to a corresponding first gate pad among the plurality of first gate pads. Thus, gate resistance can be suppressed and high-frequency characteristics can be improved.

[0082] (7) In the above (6), each of the plurality of second source electrodes may include: a fourth portion; and a fifth portion and a sixth portion, wherein the fifth portion and the sixth portion overlap with the fourth portion when viewed from the second direction, are disposed between the fourth portion and the plurality of first gate pads, and are arranged in the first direction, and the second FET group includes a plurality of second gate wirings, wherein each of the plurality of second gate wirings is disposed between the fifth portion and the sixth portion, and electrically connects at least one of the plurality of second gate electrodes to a corresponding first gate pad of the plurality of first gate pads. Thus, gate resistance can be suppressed and high-frequency characteristics can be improved.

[0083] (8) In any one of the above (1) to (7), a guard ring may be provided, the guard ring being electrically connected to the plurality of first source electrodes and the plurality of second source electrodes on the main surface and surrounding the first FET group and the second FET group, thereby shielding the first FET group and the second FET group.

[0084] (9) In any one of the above (1) to (8), the device may further include: a substrate; a semiconductor chip mounted on the substrate and having the substrate; a first bonding wire connected to each of the plurality of first gate pads and extending in the second direction; and a second bonding wire connected to the drain pad and extending in a direction opposite to the second direction. Thus, high-frequency signals are equally input to the first FET group and the second FET group.

[0085] (10) In the above (5), the device may also include: a base; a semiconductor chip mounted on the base and having the substrate; a first bonding wire connected to each of the plurality of first gate pads and extending in the second direction; a second bonding wire connected to the drain pad and extending in the direction opposite to the second direction; and a third bonding wire connected to the second gate pad and extending in the second direction. Thus, interference between different signals can be suppressed.

[0086] (11) In the above (10), the device may further include: a first capacitor mounted on the substrate, a first end of which is electrically connected to the substrate, and a second end of which is connected to the first bonding wire; and a second capacitor mounted on the substrate, a first end of which is electrically connected to the substrate, and a second end of which is connected to the third bonding wire. In this way, interference between different signals can be suppressed.

[0087] [Details of the embodiments of the present disclosure]

[0088] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0089] [Example 1]

[0090] The following description will be given by taking as an example a semiconductor device of an amplifier used for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a mobile communication base station. Figure 1 and Figure 2 FIG. 1 is a top view of the semiconductor device of Example 1. Figure 1 In FIG. 1 , the source electrode 12a, the source electrode 12b, the drain electrode 16a, and the drain electrode 16b are omitted. In addition, the details of the active region 11a and the active region 11b are omitted. Figure 2 In the top view of FIG. 1 , if the drain electrode 16a and the drain electrode 16b overlap with the drain wiring 26, it is difficult to see. Figure 2 In FIG. 1 , the drain wiring 26 is seen through, and a thick line indicating only the outer periphery of the drain wiring 26 is shown inside the drain electrodes 16a and 16b. In addition, the source wiring 22a and the source wiring 22b are not shown.

[0091] The thickness direction of the substrate 10 is set as the Z direction, the extending direction of the finger-shaped gate electrodes 14a and 14b is set as the Y direction (second direction), and the arrangement direction of the source electrode 12a, the gate electrode 14a and the drain electrode 16a is set as the X direction (first direction).

[0092] like Figure 1 and Figure 2As shown, in the semiconductor device 100 of the first embodiment, on the main surface 50 of the substrate 10, the FET group 30a (first FET group) and the FET group 30b (second FET group) are arranged in the Y direction. The FET group 30a and the FET group 30b each include a plurality of FETs 31 arranged in the X direction. The FETs 31 in the FET group 30a are provided on the active region 11a (first active region), and include a finger-shaped source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode) extending in the Y direction. The plurality of source electrodes 12a and the plurality of drain electrodes 16a are alternately arranged in the X direction. One of the plurality of gate electrodes 14a is arranged between one of the plurality of source electrodes 12a and one of the plurality of drain electrodes 16a in the X direction.

[0093] The FET 31 in the FET group 30b is provided on the active region 11b (second active region), and includes a finger-shaped source electrode 12b (second source electrode), a gate electrode 14b (second gate electrode), and a drain electrode 16b (second drain electrode) extending in the Y direction. The plurality of source electrodes 12b and the plurality of drain electrodes 16b are alternately provided in the X direction. One of the plurality of gate electrodes 14b is arranged between one of the plurality of source electrodes 12b and one of the plurality of drain electrodes 16b in the X direction. When viewed from the Y direction, the plurality of source electrodes 12b overlap with the plurality of source electrodes 12a, respectively, and the plurality of drain electrodes 16b overlap with the plurality of drain electrodes 16a, respectively.

[0094] Multiple gate pads 34 (first gate pads) overlap source electrodes 12a and 12b when viewed from the Y direction, are provided on the inactive region 13 of the main surface 50 between source electrodes 12a and 12b, and are electrically connected to gate electrodes 14a and 14b.

[0095] Gate wiring 18a (first gate wiring) and gate wiring 19a electrically connecting gate pad 34 and gate electrode 14a , and gate wiring 18b (second gate wiring) and gate wiring 19b electrically connecting gate pad 34 and gate electrode 14b are provided on main surface 50 .

[0096] The drain wiring 26 extends in the Y direction and is provided on the drain electrode 16a and the drain electrode 16b. The drain wiring 26 electrically connects the drain electrode 16a and the drain electrode 16b to the drain pad 36 to short-circuit them. The drain wiring 26 electrically connects the drain electrode 16a and the drain electrode 16b.

[0097] A plurality of drain wirings 26 and gate pads 34 are alternately provided on the main surface 50 between the corresponding drain electrodes 16 a and the corresponding drain electrodes 16 b .

[0098] When viewed from the Z direction, the via hole 20 a (first via hole) and the via hole 20 b (second via hole) overlap with the source electrode 12 a and the source electrode 12 b , respectively.

[0099] Figure 3 This is an enlarged top view of the semiconductor device of Example 1. Figure 4 to Figure 7 They are Figure 3 A-A sectional view, B-B sectional view, C-C sectional view and D-D sectional view.

[0100] like Figure 3 to Figure 7 As shown, the substrate 10 has a main surface 50 and a back surface 51 opposite to the main surface 50. The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. On the XY plane parallel to the X direction and the Y direction, the region of the semiconductor layer 10b deactivated by ion implantation or the like is an inactive region 13, and the region that is not deactivated (i.e., the region where a part of the substrate 10 is activated) is an active region 11a and an active region 11b. The active region 11a has active portions 21a to 21c. The source electrode 12a has source portions 13a to 13c. The gate electrode 14a has gate portions 15a to 15d. The drain electrode 16a has drain portions 17a to 17d. The source wiring 22a has wiring portions 23a to 23b.

[0101] The active portion 21a extends in the X direction. The active portion 21b and the active portion 21c are arranged in the X direction. The active portion 21a is provided with a FET 31a and a FET 31d. The active portion 21b and the active portion 21c are provided with a FET 31b and a FET 31c, respectively.

[0102] FET31a includes a source portion 13a, a gate portion 15a, and a drain portion 17a. The gate portion 15a is disposed between the source portion 13a and the drain portion 17a in the X direction. The source portion 13a, the gate portion 15a, and the drain portion 17a are arranged in this order in the + direction of the X direction.

[0103] FET31d includes a source portion 13a, a gate portion 15d, and a drain portion 17d. The gate portion 15d is disposed between the source portion 13a and the drain portion 17d in the X direction. The source portion 13a, the gate portion 15d, and the drain portion 17d are arranged in sequence in the - direction of the X direction. FET31a and FET31d share the source portion 13a.

[0104] FET31b includes a source portion 13b, a gate portion 15b, and a drain portion 17b. The gate portion 15b is disposed between the source portion 13b and the drain portion 17b in the X direction. When viewed from the Y direction, the source portion 13b is disposed inside the source portion 13a. That is, when viewed from the Y direction, the source portion 13b is not disposed outside the source portion 13a. When viewed from the Y direction, the drain portion 17b overlaps the drain portion 17a. The source portion 13b, the gate portion 15b, and the drain portion 17b are arranged in sequence in the + direction of the X direction.

[0105] FET31c includes a source portion 13c, a gate portion 15c, and a drain portion 17c. The gate wiring 18a is arranged between the source portion 13c and the source portion 13b, and the source portion 13c is arranged inside the source portion 13a when viewed from the Y direction. That is, when viewed from the Y direction, the source portion 13c is not arranged outside the source portion 13a. When viewed from the Y direction, the drain portion 17c overlaps with the drain portion 17d. In the X direction, the gate portion 15c is arranged between the source portion 13c and the drain portion 17c. The source portion 13c, the gate portion 15c, and the drain portion 17c are arranged in sequence in the - direction of the X direction.

[0106] Wiring portions 23a to 23c are provided in contact with source portions 13a to 13c, respectively. Wiring portion 23b electrically connects source portion 13b to wiring portion 23a. Wiring portion 23c electrically connects source portion 13c to wiring portion 23a. Thus, source portions 13a to 13c are electrically short-circuited and have the same potential.

[0107] Figure 3 The drain wiring 26 on the right side of the electrode electrically connects the drain portion 17 a and the drain portion 17 b to the drain pad 36 . Figure 3 The drain wiring 26 on the left side electrically connects the drain portion 17 d and the drain portion 17 c to the drain pad 36 .

[0108] A gate wiring 18a extending in the Y direction is provided on the inactive region 13 between the FET 31b and the FET 31c. The gate wiring 18a is provided inside the source portion 13a when viewed from the Y direction. That is, the gate wiring 18a is not provided outside the source portion 13a when viewed from the Y direction. The gate wiring 18a is electrically connected to the gate pad 34.

[0109] A gate wiring 19a extending in the X direction is provided on the inactive region 13 between the FET 31a and the FET 31b and between the FET 31d and the FET 31c. The gate wiring 19a intersects the wiring portion 23b and the wiring portion 23c without contact, and electrically connects the gate wiring 18a and the gate portions 15a to 15d. As a result, the gate portions 15a to 15d are electrically connected to the gate pad 34 via the gate wiring 18a and the gate wiring 19a, and are short-circuited to the same potential.

[0110] The gate wiring 18a and the gate pad 34 include a gate metal layer 27a provided on the substrate 10 and a wiring layer 27b provided on the gate metal layer 27a. The gate wiring 19a includes the gate metal layer 27a and does not include the wiring layer 27b.

[0111] The via hole 20a penetrates the substrate 10. The via hole 20a overlaps with the source portion 13a when viewed from the Z direction, and the via hole 20a is electrically connected to the source portion 13a. A metal layer 28 is provided on the back surface 51 of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20a. As a result, the metal layer 28 (back metal layer) is electrically connected to the source portion 13a via the via hole 20a and short-circuited, and becomes the same potential. The planar shape of the via hole 20a and the via hole 20b can be an ellipse, an oblong, a rounded quadrilateral or a circle.

[0112] The source potential (for example, a reference potential such as a ground potential) is supplied from the metal layer 28 to the source portion 13a via the metal layer 28a in the via 20a. Furthermore, the source potential is supplied from the wiring portion 23a to the source portion 13b and the source portion 13c via the wiring portion 23b and the wiring portion 23c, respectively. The gate potential (for example, a high-frequency signal and a gate bias voltage) is supplied from the gate pad 34 to the gate portions 15a to 15d via the gate wiring 18a and the gate wiring 19a. The drain bias voltage is supplied from the drain pad 36 to the drain portions 17a to 17d via the drain wiring 26. The high-frequency signal amplified in each FET 31a to 31d is output from the drain wiring 26 to the drain pad 36.

[0113] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the FET 31 is a GaNHEMT (Gallium Nitride High Electron Mobility Transistor), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0114] The source electrode 12a, the source electrode 12b, the drain electrode 16a, and the drain electrode 16b are metal films, such as titanium films and aluminum films from the substrate 10. The gate electrode 14a, the gate electrode 14b, and the gate metal layer 27a are metal films, such as nickel films and gold films from the substrate 10. The source wiring 22a, the source wiring 22b, the drain wiring 26, and the wiring layer 27b are, for example, gold layers, copper layers, or aluminum layers. The insulating layer 25 provided on the substrate 10 so as to cover the FET 31 is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0115] The width of the source portion 13a in the X direction is, for example, 50 μm to 150 μm. The width of the source portion 13b and the source portion 13c in the X direction is, for example, 5 μm to 20 μm. The gate length of the gate portions 15a to 15d in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain portions 17a to 17d in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 18a in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 19a in the Y direction is, for example, 3 μm to 20 μm. In order to reduce the gate resistance, the width of the gate wiring 18a in the X direction and the width of the gate wiring 19a in the Y direction are larger than the gate length, for example, more than twice the gate length. The gate width of the FETs 31a to 31d in the Y direction is, for example, 100 μm to 400 μm. The width of the via hole 20 a and the via hole 20 b in the X direction is, for example, 10 μm to 60 μm.

[0116] The width of the wiring portions 23a to 23c in the X direction is the same as or slightly smaller than the width of the source portions 13a to 13c in the X direction. The width of the drain wiring 26 in the X direction is the same as or slightly smaller than the width of the drain portions 17a to 17d in the X direction.

[0117] [Comparative Example 1]

[0118] Figure 8 is a top view of the semiconductor device of Comparative Example 1. Figure 8 As shown, in the semiconductor device 110 of Comparative Example 1, there is provided Figure 3 A FET group 30c including FET 31a and FET 31d is provided. A plurality of FET groups 30d including FET 31b and FET 31c are arranged in the Y direction. A gate pad 34 and a drain pad 36 are provided in such a manner that the FET group 30c and the plurality of FET groups 30d are arranged between the gate pad 34 and the drain pad 36. The gate wiring 18 is connected to the gate pad 34. Between the FET group 30c and the FET group 30d and between the plurality of FET groups 30d, the gate wiring 19 electrically connects the gate electrode 14 and the gate wiring 18.

[0119] In Comparative Example 1, the gate resistance between the gate electrode 14 and the gate pad 34 can be reduced by using the gate wiring 18 and the gate wiring 19. However, since the source wiring 22 becomes longer, the source inductance becomes larger. As a result, the high-frequency characteristics deteriorate. In addition, the gate electrode 14, which is a heat source, becomes denser, so the thermal resistance becomes higher.

[0120] [Comparative Example 2]

[0121] Fig. 9 is a top view of the semiconductor device of Comparative Example 2. Fig. 9 As shown, in the semiconductor device 112 of Comparative Example 2, a gate pad 34 is provided between the FET group 30a and the FET group 30b. The gate pad 34 is provided above the source wiring 22a, the source wiring 22b, and the drain wiring 26 in the Z direction.

[0122] In Comparative Example 2, the gate pad 34 is provided between the FET group 30a and the FET group 30b, and the vias 20a and 20b are provided on both sides of the FET group 30a and the FET group 30b, so that the source wiring 22a and the source wiring 22b can be shortened. Thus, the source inductance can be reduced. In addition, the distance between the gate electrode 14a and the gate electrode 14b, which are the heat source, becomes wider. Thus, the thermal resistance can be reduced.

[0123] However, in Comparative Example 2, when viewed from the Z direction, the gate pad 34 overlaps the source wiring 22a, the source wiring 22b, and the drain wiring 26. Therefore, the gate / drain capacitance and the gate / source capacitance increase, thereby deteriorating the high frequency characteristics.

[0124] [Description of Example 1]

[0125] According to Example 1, Figure 1 and Figure 2 As shown, the gate pad 34 is provided between the source electrode 12a and the source electrode 12b. The drain wiring 26 is provided alternately with the gate pad 34 between the drain electrode 16a and the drain electrode 16b.

[0126] Thus, the gate pad 34 does not overlap with the source wiring 22a, the source wiring 22b, and the drain wiring 26. Thus, compared with Comparative Example 2, the gate / drain capacitance and the gate / source capacitance can be suppressed. In addition, compared with Comparative Example 1, the source inductance can be suppressed. The FET group 30a is arranged between the drain pad 36 and the gate pad 34. Thus, as shown in Patent Documents 1 and 2, the gate / drain capacitance between the gate pad and the drain pad can be suppressed. By this, the high-frequency characteristics can be improved compared with Comparative Examples 1 and 2 and Patent Documents 1 and 2.

[0127] Furthermore, since the FET group 30 a and the FET group 30 b are separated from each other, the thermal resistance can be reduced compared with Comparative Example 1.

[0128] [simulation]

[0129] As an example, thermal simulation was performed in Example 1 and Comparative Example 1. In the simulation, 88 gate electrodes 14 were arranged in the X direction on the SiC substrate. In Example 1, the distance between the FET group 30a and the FET group 30b was set to 130 μm. As a result of the simulation, the maximum temperature of the upper surface of the SiC substrate in Example 1 and Comparative Example 1 was 120.1°C and 125.4°C, respectively. In this way, Example 1 has a lower thermal resistance than Comparative Example 1, and can reduce the maximum temperature.

[0130] like Figure 1 , Figure 4 as well as Figure 6 As shown, the metal layer 28 (back metal layer) is electrically connected to the plurality of source electrodes 12a and 12b through the plurality of via holes 20a and 20b, respectively. Thus, the source potential can be supplied to the source electrodes 12a and 12b, thereby suppressing the source inductance and improving the high frequency characteristics.

[0131] like Figure 1 As shown, a plurality of gate pads 34 are provided in the inactive region 13. This can suppress gate-source capacitance and improve high frequency characteristics.

[0132] like Figure 3 to Figure 7 As shown, the source electrode 12a includes a source portion 13a (first portion), a source portion 13b (second portion), and a source portion 13c (third portion). The source portion 13b and the source portion 13c overlap with the source portion 13a when viewed from the Y direction, and are provided between the source portion 13a and the gate pad 34. The gate wiring 18a is provided between the source portion 13b and the source portion 13c, and electrically connects the gate electrode 14a to the gate pad 34. Thus, the gate resistance in the FET group 30a can be reduced without increasing the size. Thus, the high frequency characteristics can be improved.

[0133] The source electrode 12b also includes a source portion 13a (fourth portion), a source portion 13b (fifth portion), and a source portion 13c (sixth portion). The gate wiring 18b is provided between the source portion 13b and the source portion 13c, and electrically connects the gate electrode 14b to the gate pad 34. Thus, the gate resistance in the FET group 30b can be reduced without increasing the size. Thus, the high frequency characteristics can be improved.

[0134] [Variation 1 of Example 1]

[0135] Fig.10 FIG. 1 is an enlarged top view of a semiconductor device according to a first variation of the first embodiment. Fig.10 As shown, in the semiconductor device 101 of the first modification of the first embodiment, in the FET group 30a, the gate portion 15a is separated from the gate portion 15b, and the gate portion 15d is separated from the gate portion 15c. The gate portion 15a and the gate portion 15d are electrically connected to the gate pad 34 via the gate wiring 19a and the gate wiring 18a. The gate portion 15b and the gate portion 15c are electrically connected to the gate pad 34 without passing through the gate wiring 18a and the gate wiring 19a. The other configurations are the same as those of the first embodiment, and the description thereof is omitted. As shown in the first modification of the first embodiment, it is sufficient that the gate portions of some of the gate portions 15a to 15d are electrically connected to the gate pad 34 via the gate wiring 18a and the gate wiring 19a.

[0136] [Variation 2 of Example 1]

[0137] Fig.11 FIG. 1 is a top view of a semiconductor device according to a second variation of the first embodiment. Fig.11As shown, in the semiconductor device 102 of the second variation of the first embodiment, the drain wiring 26 includes parts 26a to 26c. The part 26a and the part 26b are provided in the FET group 30a and the FET group 30b, respectively. The part 26c is a part between the FET group 30a and the FET group 30b. The width Wc of the part 26c in the X direction is narrower than the width Wa of the drain electrode 16a and the part 26a in the X direction and the width Wb of the drain electrode 16b and the part 26b in the X direction. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0138] According to the second variation of the first embodiment, the width Wc of the drain wiring 26 between the FET group 30a and the FET group 30b in the X direction is smaller than the width Wa of the drain electrode 16a and the portion 26a in the X direction and the width Wb of the drain electrode 16b and the portion 26b in the X direction. As a result, the distance between the gate pad 34 and the drain wiring 26 becomes longer, and the gate / drain capacitance can be suppressed. As a result, the high-frequency characteristics can be improved. The width Wc can be set to be less than 0.9 times the width Wa and the width Wb, can be set to be less than 0.8 times, and can be set to be less than 0.6 times. In the case where the lengths of the FET group 30a and the FET group 30b in the Y direction are substantially the same, as long as the width Wc is about 0.5 times the width Wa and the width Wb, the current density flowing through the portion 26c can be made the same as the current density of the portion of the portion 26a close to the drain pad 36. Therefore, the width Wc can be set to be more than 0.5 times the width Wa and the width Wb.

[0139] [Variation 3 of Example 1]

[0140] Fig.12 FIG. 1 is a top view of a semiconductor device according to a third variation of the first embodiment. Fig.12 As shown, in the semiconductor device 103 of the third modification of the first embodiment, a gate pad 35 (second gate pad) is provided in addition to the gate pad 34. The gate pad 35 is provided in such a manner that the FET group 30b is arranged between the gate pad 35 and the gate pad 34 on the main surface 50. The gate electrode 14b is directly electrically connected to the gate pad 35. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0141] According to the third modification of the first embodiment, by providing the gate pad 34 and the gate pad 35 , bonding wires can be bonded to the gate pads at two locations in the Y direction.

[0142] [Variation 4 of Example 1]

[0143] Fig.13 FIG. 4 is a top view of a semiconductor device according to a fourth variation of the first embodiment. Fig.13As shown, in the semiconductor device 104 of the fourth modification of the first embodiment, the gate wiring 18a, the gate wiring 18b, the gate wiring 19a and the gate wiring 19b are not provided. The planar shape of the source electrode 12a, the source electrode 12b, the source wiring 22a and the source wiring 22b is a rectangle. In this way, the semiconductor device 104 is a multi-finger FET. A gate pad 34 is provided between the FET group 30a and the FET group 30b. The other configurations are the same as those of the first embodiment, and their description is omitted.

[0144] In the modification 4 of the embodiment 1, compared with the embodiment 1, the gate wirings 18a, 18b, 19a and 19b are not provided, so the gate resistance is increased, but compared with the general multi-finger FET, the gate resistance can be suppressed and the high-frequency characteristics can be improved.

[0145] [Variation 5 of Example 1]

[0146] Fig.14 FIG. 1 is a top view of a semiconductor device according to a fifth variation of the first embodiment. Fig.14 As shown, in the semiconductor device 105 of the fifth modification of the first embodiment, the guard ring 44a and the guard ring 44b are provided on the main surface 50 so as to surround the FET group 30a and the FET group 30b. A plurality of drain pads 36 are provided corresponding to the drain wiring 26. The guard ring 44a is electrically connected to the source wiring 22a via the connection wiring 43a provided between the plurality of drain pads 36. The guard ring 44b is electrically connected to the source wiring 22b via the connection wiring 43b. The guard ring 44a and the guard ring 44b are electrically connected to the source pad 42a and the source pad 42b. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0147] In the variation 5 of the embodiment 1, the guard ring 44a and the guard ring 44b are electrically connected to the source electrode 12a and the source electrode 12b on the main surface 50, and surround the FET group 30a and the FET group 30b. Thus, the FET group 30a and the FET group 30b can be shielded. The guard ring 44a and the guard ring 44b can surround a part of the FET group 30a and the FET group 30b, but can also completely surround the FET group 30a and the FET group 30b. By setting the source pad 42a and the source pad 42b, the characteristics of the FET group 30a and the FET group 30b can be evaluated before the via 20a and the via 20b are formed. The drain pad 36 can be set as a whole, but it is also possible to set the connection wiring 43a by dividing it into a plurality of parts. A connection wiring electrically connected to the gate electrode 14b can be set between the source wiring 22b and the guard ring 44b. The connection wiring 43a and the connection wiring 43b may not be set.

[0148] In the first embodiment and its modified example, an example in which six FETs 31 are provided in the X direction is described, but eight or more FETs 31 may be provided in the X direction. An example in which two FETs 31 are provided in each of the FET groups 30a and 30b in the Y direction is described, but three or more FETs 31 may be provided in the Y direction.

[0149] In the first embodiment and its modified example, the drain portion 17a and the drain portion 17b (and the drain portion 17d and the drain portion 17c) electrically connected by the same drain wiring 26 are separated from each other in the inactive region 13. The plurality of drain portions 17a to 17d electrically connected by the drain wiring 26 may be connected to each other in the inactive region 13. In the FET 31, the source electrode 12a and the source wiring 22a may also be collectively referred to as a source electrode, and the drain electrode 16a and the drain wiring 26 may also be collectively referred to as a drain electrode.

[0150] [Example 2]

[0151] The second embodiment and its modified example are examples of semiconductor devices in which the semiconductor chips of the first embodiment and its modified example are mounted in a package. Fig.15 It is a top view of the semiconductor device of Example 2. Fig.16 yes Fig.15 The equivalent circuit diagram of Fig.15 , the cover of the package 52 is not shown.

[0152] like Fig.15 As shown, in the semiconductor device 106 of the second embodiment, the package 52 has a conductive substrate 53, a frame 54 and a cover on at least the upper surface. The substrate 53 is, for example, a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the substrate 53. The frame 54 and the cover are, for example, dielectric layers made of resins such as glass epoxy resin or ceramics. A semiconductor chip 60, a capacitive component 55a and a capacitive component 55b are mounted on the substrate 53. On the substrate 53, a frame 54 is provided in a manner surrounding the semiconductor chip 60, the capacitive component 55a and the capacitive component 55b. The cover is bonded to the upper surface of the frame 54 by an insulating adhesive such as a resin. The frame 54 and the cover seal the semiconductor chip 60 in the gap.

[0153] The planar shape of the frame 54 is roughly rectangular. A lead 58 (input lead) is provided on the - side of the frame 54 in the Y direction. A lead 59 (output lead) is provided on the + side of the frame 54 in the Y direction. The leads 58 and 59 are, for example, metal layers or metal plates such as copper. A high-frequency signal is input to the lead 58, and a high-frequency signal is output from the lead 59. The lead 58, the capacitive component 55a, the capacitive component 55b, the semiconductor chip 60, and the lead 59 are arranged in the Y direction.

[0154] The semiconductor chip 60 includes a substrate 10, a gate pad 34 and a drain pad 36 provided on the upper surface of the substrate 10, and a metal layer 28 provided on the back surface of the substrate 10 (see Figure 4 to Figure 7 ). The semiconductor chip 60 is the semiconductor device 100 to 105 of the first embodiment and its modified examples. The capacitive component 55a and the capacitive component 55b include a dielectric substrate 56, an electrode 57 provided on the upper surface of the dielectric substrate 56, and an electrode provided on the lower surface of the dielectric substrate 56. The electrode 57 and the electrode on the lower surface form a capacitor via the dielectric substrate 56. The dielectric substrate 56 is, for example, an aluminum oxide substrate or a barium titanate substrate. The electrode 57 is, for example, a metal layer such as a gold layer.

[0155] The bonding wire 71 electrically connects the lead 58 to the electrode 57 of the capacitive component 55a. The bonding wire 72 electrically connects the electrode 57 of the capacitive component 55a to the electrode 57 of the capacitive component 55b. The bonding wire 73 electrically connects the electrode 57 of the capacitive component 55b to the gate pad 34. The bonding wire 74 electrically connects the drain pad 36 to the lead 59.

[0156] like Fig.16 As shown, the source S of FETQ1 is grounded, the gate G is electrically connected to the lead 58 via the matching circuit 62, and the drain D is electrically connected to the lead 59. Inductors L1 to L3 are connected in series between the lead 58 and the gate G. A capacitor C1 is connected in a shunt to a node between the inductor L1 and the inductor L2, and a capacitor C2 is connected in a shunt to a node between the inductor L2 and the inductor L3. The inductors L1 to L3, the capacitor C1, and the capacitor C2 function as the matching circuit 62. An inductor L4 is connected between the drain D and the lead 59.

[0157] The high-frequency signal input to the lead 58 is input to the gate G via the matching circuit 62. The matching circuit 62 matches the impedance between the lead 58 and the gate G. The FET Q1 amplifies the high-frequency signal input to the gate G, and outputs the amplified high-frequency signal to the lead 59 via the inductor L4.

[0158] The inductors L1 to L4 correspond to the bonding wires 71 to 74 , respectively, and the capacitors C1 and C2 correspond to the capacitive component 55 a and 55 b , respectively.

[0159] In the second embodiment, the bonding wire 73 (first bonding wire) is connected to the gate pad 34 and extends in the - direction (second direction) of the Y direction. The bonding wire 74 (second bonding wire) is connected to the drain pad 36 and extends in the + direction (opposite direction of the second direction) of the Y direction. Figure 1 and Figure 2As shown in FIG. 1 , the high-frequency signal is input to the gate pad 34 between the FET group 30a and the FET group 30b, so the high-frequency signal is equally input to the FET group 30a and the FET group 30b. In particular, when the matching circuit 62 also processes the high-order harmonic signal, the wavelength of the high-order harmonic signal is shorter than the fundamental wave. Therefore, as in Comparative Example 1 Figure 8 As shown, even when the gate electrode 14 is long in the Y direction, harmonics may not be processed uniformly. In the second embodiment, since the matching circuit 62 is connected to the gate pad 34 between the FET group 30a and the FET group 30b, harmonics can be processed more uniformly.

[0160] [Variation 1 of Example 2]

[0161] Fig.17 It is a top view of a semiconductor device according to a first variation of the second embodiment. Fig.18 yes Fig.17 The equivalent circuit diagram of Fig.17 As shown, in the semiconductor device 107 of the first variation of the second embodiment, a capacitive component 55c is mounted on the substrate 53 between the capacitive component 55a and the semiconductor chip 60a. The semiconductor chip 60a is the semiconductor device 103 of the third variation of the first embodiment. The gate pad 34, the gate pad 35, and the drain pad 36 are provided on the substrate 10. The bonding wire 72a electrically connects the electrode 57 of the capacitive component 55a to the gate pad 35. The bonding wire 75 electrically connects the electrode 57 of the capacitive component 55c to the gate pad 34. The other configurations are the same as those of the second embodiment. Fig.15 same.

[0162] like Fig.18 As shown, an inductor L1 and an inductor L2a are connected in series between the lead 58 and the gate G. An inductor L5 and a capacitor C3 are connected in series between the node between the inductor L2a and the gate G and the ground. The inductor L1, the inductor L2a and the capacitor C1 function as a matching circuit 62. The inductor L5 and the capacitor C3 function as a harmonic processing circuit 63. The harmonic processing circuit 63 has a function of suppressing 2-fold or 3-fold waves. For example, the resonant frequency of the series resonant circuit of the inductor L5 and the capacitor C3 is set to the frequency of the harmonics. As a result, the harmonic signals in the harmonic signal input to the gate G flow to the ground, and the harmonics can be suppressed. The other structures are the same as those of Example 2. Fig.16 same.

[0163] [Comparative Example 3]

[0164] Fig.19 is a top view of the semiconductor device of Comparative Example 3. Fig.19As shown, in the semiconductor device 114 of the comparative example 3, the semiconductor chip 60b is the semiconductor device 110 of the comparative example 1. The gate pad 34 is not provided on the substrate 10, but a gate pad 35 is provided. The bonding wire 75 is connected to the gate pad 35. The other structures are the same as Fig.17 same.

[0165] The equivalent circuit of Comparative Example 3 is Fig.18 Since the bonding wire 72 a and the bonding wire 75 are connected to the same gate pad 35 , different signals such as the signal of the fundamental wave matching circuit 62 and the signal of the harmonic processing circuit 63 may interfere with each other.

[0166] In the modification 1 of the embodiment 2, the bonding wire 75 is connected to the gate pad 34, and the bonding wire 72a (third bonding wire) is connected to the gate pad 35. Thus, it is possible to suppress interference between different signals such as the signal of the matching circuit 62 of the fundamental wave and the signal of the harmonic processing circuit 63. The first end of the capacitor C3 (first capacitor) is electrically connected to the substrate 53, and the bonding wire 75 is connected to the second end. The first end of the capacitor C1 (second capacitor) is electrically connected to the substrate 53, and the bonding wire 72a is connected to the second end. Thus, the harmonic processing circuit 63 including the capacitor C3 and the bonding wire 75 can be formed, and the matching circuit 62 including the capacitor C1 and the bonding wire 72a can be formed. By connecting the harmonic processing circuit 63 to the gate pad 34, the harmonics can be uniformly processed.

[0167] The embodiments disclosed this time should be considered as illustrative in all aspects and not restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A substrate having a main surface and a back surface opposite to the main surface; A first FET group, provided on the main surface, comprising a plurality of first source electrodes, a plurality of first drain electrodes, and a plurality of first gate electrodes arranged in a first direction; A second FET group, provided on the main surface, overlapping with the first FET group when viewed from a second direction intersecting the first direction, and including a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes; a plurality of first gate pads, provided on the main surface between the first FET group and the second FET group, and electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes; a plurality of drain wirings, which are alternately provided on the main surface with the plurality of first gate pads between the first FET group and the second FET group, and electrically connect the plurality of first drain electrodes and the plurality of second drain electrodes, respectively; and The drain pad is electrically connected to the plurality of first drain electrodes, so that the first FET group is arranged between the drain pad and the plurality of first gate pads.

2. The semiconductor device according to claim 1, comprising: A back metal layer, wherein the back metal layer is arranged on the back side, and is electrically connected to the multiple first source electrodes via a plurality of first via holes that overlap with the multiple first source electrodes respectively when viewed from the thickness direction of the substrate, and is electrically connected to the multiple second source electrodes via a plurality of second via holes that overlap with the multiple second source electrodes respectively when viewed from the thickness direction of the substrate.

3. The semiconductor device according to claim 1 or 2, wherein: The first FET group and the second FET group are respectively arranged in a first active region and a second active region where the main surface is activated, and the plurality of first gate pads are arranged in an inactive region where the main surface is deactivated and arranged between the first active region and the second active region.

4. The semiconductor device according to claim 1 or 2, wherein: The width of the plurality of drain wirings between the first FET group and the second FET group in the first direction is smaller than the width of the plurality of first drain electrodes in the first direction and the width of the plurality of second drain electrodes in the first direction.

5. The semiconductor device according to claim 1 or 2, comprising: The second gate pad is provided on the main surface so that the second FET group is arranged between the second gate pad and the plurality of first gate pads, and is electrically connected to the plurality of second gate electrodes.

6. The semiconductor device according to claim 1 or 2, wherein: Each of the plurality of first source electrodes comprises: a first portion; and a second portion and a third portion, wherein the second portion and the third portion overlap with the first portion when viewed from the second direction, are disposed between the first portion and a corresponding first gate pad among the plurality of first gate pads, and are arranged in the first direction, The first FET group includes a plurality of first gate wirings, each of which is disposed between the second portion and the third portion and electrically connects at least one of the plurality of first gate electrodes to a corresponding first gate pad of the plurality of first gate pads.

7. The semiconductor device according to claim 6, wherein: Each of the plurality of second source electrodes comprises: a fourth portion; and a fifth portion and a sixth portion, wherein the fifth portion and the sixth portion overlap with the fourth portion when viewed from the second direction, are disposed between the fourth portion and the plurality of first gate pads, and are arranged in the first direction, The second FET group has a plurality of second gate wirings, each of which is arranged between the fifth portion and the sixth portion, electrically connecting at least one of the plurality of second gate electrodes to a corresponding first gate pad of the plurality of first gate pads.

8. The semiconductor device according to claim 1 or 2, comprising: A guard ring is electrically connected to the plurality of first source electrodes and the plurality of second source electrodes on the main surface and surrounds the first FET group and the second FET group.

9. The semiconductor device according to claim 1 or 2, comprising: substrate; a semiconductor chip mounted on the base and having the substrate; a first bonding wire connected to each of the plurality of first gate pads and extending in the second direction; as well as The second bonding wire is connected to the drain pad and extends in a direction opposite to the second direction.

10. The semiconductor device according to claim 5, comprising: substrate; a semiconductor chip mounted on the base and having the substrate; a first bonding wire connected to each of the plurality of first gate pads and extending in the second direction; a second bonding wire connected to the drain pad and extending in a direction opposite to the second direction; as well as The third bonding wire is connected to the second gate pad and extends in the second direction.

11. The semiconductor device according to claim 10, comprising: a first capacitor mounted on the substrate, with a first end thereof electrically connected to the substrate and a second end thereof connected to the first bonding wire; and The second capacitor is mounted on the substrate, has a first end electrically connected to the substrate, and has a second end connected to the third bonding wire.

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