Semiconductor device

Abstract

The invention relates to a semiconductor device. Provided is a highly reliable semiconductor device in which good characteristics are obtained for each of transistors having different characteristics. The semiconductor device includes: a first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second gate electrode facing the first semiconductor layer, the second gate electrode being supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode and between the first semiconductor layer and the second gate electrode; a second semiconductor layer that sandwiches the first gate electrode together with the first semiconductor layer; a third gate electrode that faces the second semiconductor layer on the opposite side from the first gate electrode with respect to the second semiconductor layer, and that overlaps the first gate electrode in plan view; and a second gate insulating layer between the second semiconductor layer and the third gate electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices in which transistors having different semiconductor materials as semiconductor layers are formed on the same substrate has been progressing. For example, transistors using polysilicon are used in transistors requiring high-speed operation, and transistors using oxide semiconductors are used in transistors requiring switching operation with less leakage current in the off state, thereby enabling transistors having different characteristics to be formed on the same substrate depending on the required functions.

[0003] Patent Document 1 discloses a display device in which transistors using silicon are formed in a driver circuit in a peripheral region, and transistors using oxide semiconductor are formed in a pixel circuit in a display region on the same substrate.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-128693 Summary of the invention

[0007] Problems to be solved by the invention

[0008] In one embodiment of the present invention, one of the objects is to provide a semiconductor device having high reliability and in which each of transistors having different characteristics exhibits good electrical characteristics.

[0009] Means for solving problems

[0010] A semiconductor device according to one embodiment of the present invention comprises: a first semiconductor layer; a first gate electrode opposite to the first semiconductor layer; a second gate electrode opposite to the first semiconductor layer and supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode and between the first semiconductor layer and the second gate electrode; a second semiconductor layer sandwiching the first gate electrode together with the first semiconductor layer; a third gate electrode opposite to the second semiconductor layer on the side opposite to the first gate electrode with respect to the second semiconductor layer and overlapping with the first gate electrode when viewed from above; and a second gate insulating layer between the second semiconductor layer and the third gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0012] Figure 2 This is a circuit configuration of a semiconductor device according to one embodiment of the present invention.

[0013] Figure 3 It is a plan view illustrating a semiconductor device according to one embodiment of the present invention.

[0014] Figure 4 It is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0015] Figure 5 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0016] Figure 6 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0017] Figure 7 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0018] Figure 8 It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0019] Description of Reference Numerals

[0020] 10: semiconductor device, 100: transistor, 101: substrate, 102: insulating layer, 110: semiconductor layer, 111, 112: channel region, 113, 114, 115: low resistance region, 120: gate insulating layer, 130, 140: gate electrode, 150, 160: electrode, 170: insulating layer, 171, 172: opening, 200: transistor, 210: semiconductor layer, 211: channel region, 213, 214: low resistance region, 220: gate insulating layer, 221, 222, 231: opening, 230: gate electrode, 250, 260: electrode, 259: conductive layer, 270: insulating layer, 271, 272: opening, 290: light shielding layer, 300: metal oxide layer, IN: input signal, OUT: output signal DETAILED DESCRIPTION

[0021] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is exemplary only. While maintaining the gist of the invention, the configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment is certainly included in the scope of the present invention. In order to make the description clearer, the accompanying drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same configuration as that described above with respect to the existing figure, and the detailed description is sometimes appropriately omitted.

[0022] In various embodiments of the present invention, the direction from the substrate toward the semiconductor layer is referred to as up or above. Conversely, the direction from the semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the description is made using the phrases such as up or below, but, for example, the up-and-down relationship between the substrate and the semiconductor layer may be configured in a different orientation than that shown in the figure. In the following description, for example, the description such as the semiconductor layer on the substrate is merely to illustrate the up-and-down relationship between the substrate and the semiconductor layer as described above, and other components may be configured between the substrate and the semiconductor layer. Up or down refers to the stacking order in a structure in which a plurality of layers are stacked, and in the case of the description of the second component being above the first component, it may also be a positional relationship in which the first component and the second component do not overlap when viewed from above. On the other hand, when described as the second component being vertically above the first component, it refers to a positional relationship in which the first component and the second component overlap when viewed from above.

[0023] In this specification, the expressions such as “α includes A, B or C”, “α includes any one of A, B and C”, and “α includes one selected from the group consisting of A, B and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. In addition, these expressions do not exclude the case where α includes other elements.

[0024] It should be noted that the configurations shown below can be combined with each other as long as no technical contradiction occurs.

[0025] [1. Cross-sectional structure of semiconductor device]

[0026] For an example of the structure of the semiconductor device 10 according to one embodiment of the present invention, refer to Figure 1 to Figure 3 Provide explanation. Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention. Figure 1 As shown, a semiconductor device 10 according to one embodiment of the present invention includes a transistor 100 provided on a substrate 101 and a transistor 200 provided above the transistor 100 .

[0027] Either an N-type transistor or a P-type transistor can be used as the transistor 100. In this embodiment, an example in which a top-gate P-type transistor using polysilicon as a semiconductor layer is used as the transistor 100 will be described.

[0028] Either an N-type transistor or a P-type transistor may be used as the transistor 200. In this embodiment, an example in which a double-gate N-type transistor using an oxide semiconductor in a semiconductor layer is used as the transistor 200 will be described.

[0029] In this embodiment, transistor 100 is a P-type transistor, and transistor 200 is an N-type transistor. Therefore, semiconductor device 10 constitutes a complementary metal oxide semiconductor (CMOS) circuit. However, one embodiment of the present invention is not limited to the above-mentioned CMOS circuit. For example, transistor 100 may also be an N-type transistor, and transistor 200 may also be a P-type transistor. Alternatively, one embodiment of the present invention may not be a CMOS circuit. That is, both transistors 100 and 200 may be N-type transistors, or both may be P-type transistors.

[0030] [1-1. Structure of Transistor 100]

[0031] The transistor 100 includes a semiconductor layer 110, a gate insulating layer 120, gate electrodes 130 and 140, and electrodes 150 and 160. An insulating layer 102 is provided on a substrate 101. The insulating layer 102 suppresses diffusion of impurities contained in the substrate 101 into the semiconductor layer 110. That is, the insulating layer 102 has a barrier property.

[0032] The semiconductor layer 110 is provided on the insulating layer 102. The semiconductor layer 110 is divided into channel regions 111, 112 and low resistance regions 113 to 115. Impurities (dopants) are mixed into the semiconductor layer 110 in the low resistance regions 113 to 115. Carriers are generated in the semiconductor layer 110 by the dopant. No dopant is mixed into the semiconductor layer 110 in the channel regions 111, 112, or a small amount of dopant is mixed into the semiconductor layer 110. That is, the dopant concentration of the low resistance regions 113 to 115 is higher than the dopant concentration of the channel regions 111, 112. When the material used for the semiconductor layer 110 is silicon and the transistor 100 is a P-type transistor, boron is used as a dopant. On the other hand, when the transistor 100 is an N-type transistor, phosphorus is used as a dopant.

[0033] The gate electrodes 130 and 140 are opposite to the semiconductor layer 110. Specifically, the gate electrode 130 is opposite to the semiconductor layer 110 in the channel region 111. The gate electrode 140 is opposite to the semiconductor layer 110 in the channel region 112. A gate insulating layer 120 is provided between the gate electrode 130 and the semiconductor layer 110, and between the gate electrode 140 and the semiconductor layer 110. The gate electrode 130 and the gate electrode 140 are provided in the same layer. That is, the gate electrode 130 and the gate electrode 140 are in contact with the gate insulating layer 120. In the D1 direction from the electrode 150 toward the electrode 160, the length of the gate electrode 140 is smaller than the length of the gate electrode 130. The gate electrode 130 is connected to the gate electrode 140, and the details will be described later. The same voltage as that of the gate electrode 130 is supplied to the gate electrode 140.

[0034] The channel regions 111, 112 and the low resistance regions 113 to 115 are arranged between the electrode 150 and the electrode 160 in the order of the low resistance region 113, the channel region 111, the low resistance region 114, the channel region 112, and the low resistance region 115. The electrode 150 is connected to the low resistance region 113, the electrode 160 is connected to the low resistance region 115, but no electrode is connected to the low resistance region 114. Therefore, when the channel regions 111 and 112 are both in the off state, the low resistance region 114 is in a floating state. As described above, the transistor 100 is controlled to be in the on state or the off state by the two gate electrodes 130 and 140. That is, the transistor 100 has a dual-gate structure.

[0035] In the above configuration, the semiconductor layer 110 is sometimes referred to as the "first semiconductor layer", the gate electrode 130 is sometimes referred to as the "first gate electrode", the gate electrode 140 is sometimes referred to as the "second gate electrode", and the gate insulating layer 120 is sometimes referred to as the "first gate insulating layer". In this case, the first gate electrode (gate electrode 130) and the second gate electrode (gate electrode 140) can be opposed to the first semiconductor layer (semiconductor layer 110). The same voltage as that of the first gate electrode (gate electrode 130) can be supplied to the second gate electrode (gate electrode 140). The first gate insulating layer (gate insulating layer 120) can be provided between the first semiconductor layer (semiconductor layer 110) and the first gate electrode (gate electrode 130), and between the first semiconductor layer (semiconductor layer 110) and the second gate electrode (gate electrode 140).

[0036] In a plan view, the channel region 111 overlaps with the gate electrode 130, and the channel region 112 overlaps with the gate electrode 140, as described in detail later. However, the transistor 100 is not limited to the above configuration. For example, a portion of the low resistance regions 113 to 115 may overlap with the gate electrodes 130 and 140 in a plan view.

[0037] A lightly doped drain (LDD) region may be provided between the channel regions 111 and 112 and the low resistance regions 113 to 115. The dopant concentration of the LDD region is higher than the dopant concentration of the channel regions 111 and 112 and lower than the dopant concentration of the low resistance regions 113 to 115. The LDD region is provided between the low resistance region 113 and the channel region 111, between the low resistance region 114 and the channel region 111, between the low resistance region 114 and the channel region 112, and between the low resistance region 115 and the channel region 112.

[0038] An insulating layer 170 is provided on the gate insulating layer 120 and the gate electrodes 130 and 140. The insulating layer 170 has openings 171 and 172. The opening 171 is an opening that reaches the semiconductor layer 110 in the low resistance region 113. The opening 172 is an opening that reaches the semiconductor layer 110 in the low resistance region 115.

[0039] The electrode 150 is disposed inside the opening 171 and is in contact with the semiconductor layer 110 in the low resistance region 113 . The electrode 160 is disposed inside the opening 172 and is in contact with the semiconductor layer 110 in the low resistance region 115 .

[0040] [1-2. Structure of transistor 200]

[0041] The transistor 200 includes a semiconductor layer 210 , a gate insulating layer 220 , a gate electrode 230 , and electrodes 250 and 260 .

[0042] The semiconductor layer 210 is provided on the insulating layer 170. The semiconductor layer 210 is divided into a channel region 211 and low resistance regions 213 and 214. A dopant is mixed into the semiconductor layer 210 in the low resistance regions 213 and 214. Carriers are generated in the semiconductor layer 210 by the dopant. No dopant is mixed into the semiconductor layer 210 in the channel region 211, or a small amount of dopant is mixed into the semiconductor layer 210. That is, the dopant concentration of the low resistance regions 213 and 214 is higher than the dopant concentration of the channel region 211. When the material used for the semiconductor layer 210 is an oxide semiconductor, phosphorus, boron, argon, etc. are used as the dopant.

[0043] When a polycrystalline oxide semiconductor described later is used as the semiconductor layer 210, the sheet resistance of the low resistance region can be reduced compared to a conventional amorphous oxide semiconductor. For example, the sheet resistance of the oxide semiconductor layer in the low resistance regions 213 and 214 is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less.

[0044] The gate electrode 230 is opposite to the semiconductor layer 210. Specifically, the gate electrode 230 is opposite to the semiconductor layer 210 in the channel region 211. A gate insulating layer 220 is provided between the gate electrode 230 and the semiconductor layer 210. The gate electrode 230 and the electrodes 150 and 160 are formed in the same layer. That is, the gate electrode 230 and the electrodes 150 and 160 are in contact with the upper surface of the gate insulating layer 220. In the gate insulating layer 220, openings 221 and 222 are provided at positions corresponding to the openings 171 and 172. The electrode 150 is provided inside the opening 221. The electrode 160 is provided inside the opening 222.

[0045] The gate electrode 230 is electrically connected to the gate electrode 130, and the details will be described later. That is, the gate electrode 230 is supplied with the same voltage as the gate electrode 130. The length of the gate electrode 230 is smaller than the length of the gate electrode 130 in the D1 direction.

[0046] In the above configuration, the semiconductor layer 210 is sometimes referred to as the "second semiconductor layer", the gate electrode 230 is sometimes referred to as the "third gate electrode", and the gate insulating layer 220 is sometimes referred to as the "second gate insulating layer". In this case, the second semiconductor layer (semiconductor layer 210) can sandwich the first gate electrode (gate electrode 130) together with the first semiconductor layer (semiconductor layer 110). The third gate electrode (gate electrode 230) can be opposed to the second semiconductor layer (semiconductor layer 210) on the opposite side to the first gate electrode (gate electrode 130) with respect to the second semiconductor layer (semiconductor layer 210). The second gate insulating layer (gate insulating layer 220) can be provided between the second semiconductor layer (semiconductor layer 210) and the third gate electrode (gate electrode 230).

[0047] In the above configuration, the electrode 150 is sometimes referred to as the "first electrode" and the electrode 160 is sometimes referred to as the "second electrode". The low resistance region 113 is sometimes referred to as the "first region" and the low resistance region 115 is sometimes referred to as the "second region". In this case, the first electrode (electrode 150) can be connected to the first region (low resistance region 113) of the first semiconductor layer (semiconductor layer 110). The second electrode (electrode 160) can be connected to the second region (low resistance region 115) of the first semiconductor layer (semiconductor layer 110) on the opposite side to the first electrode (electrode 150) with respect to the first gate electrode (gate electrode 130) and the second gate electrode (gate electrode 140). Furthermore, it is possible to connect the first region (low resistance region 113) and the second region (low resistance region 115) along a line ( Figure 3 AB line) cross-sectional observation ( Figure 1 In the cross-sectional view shown in FIG. 1 , the first gate electrode (gate electrode 130 ) and the second gate electrode (gate electrode 140 ) are separated.

[0048] In the above configuration, the electrode 250 is sometimes referred to as the "third electrode" and the electrode 260 is sometimes referred to as the "fourth electrode". The low resistance region 213 is sometimes referred to as the "third region" and the low resistance region 214 is sometimes referred to as the "fourth region". In this case, the third electrode (electrode 250) can be connected to the third region (low resistance region 213) of the second semiconductor layer (semiconductor layer 210). The fourth electrode (electrode 260) can be connected to the fourth region (low resistance region 214) of the second semiconductor layer (semiconductor layer 210) on the opposite side to the third electrode (electrode 250) with respect to the third gate electrode (gate electrode 230). Different voltages can be supplied to the second electrode (electrode 160) and the fourth electrode (electrode 260), respectively. The first electrode (electrode 150) and the third electrode (electrode 250) can be electrically connected. The first electrode (electrode 150) and the third gate electrode (gate electrode 230) can be the same layer.

[0049] The channel region 211 overlaps with the gate electrode 230 in a plan view, and the details will be described later. However, the transistor 200 is not limited to the above configuration. For example, a portion of the low resistance regions 213 and 214 may overlap with the gate electrode 230 in a plan view.

[0050] An insulating layer 270 is provided on the gate insulating layer 220 and the gate electrode 230. The insulating layer 270 is provided with openings 271 and 272. The opening 271 is an opening of the semiconductor layer 210 that reaches the upper surface of the electrode 150 and the low resistance region 213. In a plan view, the opening 271 overlaps with the pattern end of the electrode 150, and the details will be described later. The opening 272 is an opening of the semiconductor layer 210 that reaches the low resistance region 214.

[0051] The electrode 250 is disposed on the upper surface of the insulating layer 270 and inside the opening 271, and is in contact with the upper surface of the electrode 150 and the semiconductor layer 210 in the low resistance region 213. Since the pattern end of the electrode 150 is exposed through the opening 271, the electrode 250 is in contact with the pattern end. The electrode 260 is disposed on the upper surface of the insulating layer 270 and inside the opening 272, and is in contact with the semiconductor layer 210 in the low resistance region 214.

[0052] A light shielding layer 290 is provided on the transistor 200. The light shielding layer 290 is provided at least in a region covering the channel region 211 in a plan view. The light shielding layer 290 prevents external light incident on the semiconductor device 10 from above from reaching the semiconductor layer 210 in the channel region 211. External light incident on the semiconductor device 10 from below is blocked by the gate electrode 130, but a light shielding layer similar to the light shielding layer 290 may be provided under the transistor 100.

[0053] In this embodiment, the semiconductor device 10 constitutes a CMOS circuit including a P-type transistor 100 and an N-type transistor 200. A voltage Vdd is supplied to an electrode 160 of the transistor 100. A voltage Vss is supplied to an electrode 260 of the transistor 200. An input signal IN is supplied to the gate electrodes 130 and 140 of the transistor 100 and the gate electrode 230 of the transistor 200, and an output signal OUT in response to the input signal IN is output from the electrode 250 of the transistor 200 and / or the electrode 150 of the transistor 100.

[0054] [2. Circuit Configuration of Semiconductor Device]

[0055] Figure 2 This is a circuit configuration of a semiconductor device according to one embodiment of the present invention. Figure 2 As shown, transistor 100 and transistor 200 are connected in series between voltage Vdd and voltage Vss. Gate electrodes 130 and 140 of transistor 100 are connected to gate electrode 230 of transistor 200, and a common input signal IN is supplied to these gate electrodes. An output signal OUT is output from a node (electrodes 150 and 250) between transistor 100 and transistor 200.

[0056] [3. Planar Layout of Semiconductor Device]

[0057] Figure 3 It is a plan view illustrating a semiconductor device according to one embodiment of the present invention. Figure 1 The cross-section shown is Figure 3 The cross-sectional view of the AB line. Figure 3 The top view shown illustrates the layout of transistors 100 , 200 .

[0058] The semiconductor layer 110 has a long side in the D1 direction where the AB line extends. The gate electrode 130 and the gate electrode 140 cross the semiconductor layer 110 in the D2 direction. The gate electrode 130 and the gate electrode 140 are connected in a region that does not overlap with the semiconductor layer 110 when viewed from above. The D2 direction is a direction that intersects the D1 direction. Figure 1 In the example of FIG. 1 , the D2 direction is orthogonal to the D1 direction. However, the D2 direction may not be orthogonal to the D1 direction.

[0059] In the semiconductor layer 110, the region overlapping with the gate electrode 130 in a plan view is the channel region 111, and the region overlapping with the gate electrode 140 in a plan view is the channel region 112. On the other hand, in the semiconductor layer 110, the region not overlapping with any of the gate electrodes 130 and 140 in a plan view is the low resistance region 113 to 115. The region closer to B than the gate electrode 130 is the low resistance region 113. The region closer to A than the gate electrode 140 is the low resistance region 115. The region between the gate electrode 130 and the gate electrode 140 is the low resistance region 114.

[0060] The opening 171 is a region overlapping with the semiconductor layer 110 in a plan view, and is provided near the end portion close to B. The electrode 150 is provided in a region overlapping with the opening 171 in a plan view. The opening 172 is a region overlapping with the semiconductor layer 110 in a plan view, and is provided near the end portion close to A. The electrode 160 is provided in a region overlapping with the opening 172 in a plan view.

[0061] The semiconductor layer 210 has a long side in the D1 direction similarly to the semiconductor layer 110. The semiconductor layer 210 overlaps with the semiconductor layer 110 in a plan view. Specifically, the pattern of the semiconductor layer 210 is located inside the pattern of the semiconductor layer 110 in a plan view. That is, the entire outer edge of the pattern of the semiconductor layer 210 is surrounded by the outer edge of the pattern of the semiconductor layer 110. The gate electrode 230 crosses the semiconductor layer 210 in the D2 direction.

[0062] In the semiconductor layer 210, the region overlapping with the gate electrode 230 in a plan view is the channel region 211. On the other hand, in the semiconductor layer 210, the region not overlapping with the gate electrode 230 in a plan view is the low resistance region 213, 214. The region closer to B than the gate electrode 230 is the low resistance region 213. The region closer to A than the gate electrode 230 is the low resistance region 214.

[0063] The gate electrode 230 overlaps with the gate electrode 130 in a plan view. Specifically, the pattern of the gate electrode 230 is located inside the pattern of the gate electrode 130 in a plan view. At least in the region overlapping with the semiconductor layer 110 in a plan view, the pattern of the gate electrode 230 is located inside the pattern of the gate electrode 130. On the other hand, the gate electrode 230 does not overlap with the gate electrode 140 in a plan view. The gate electrode 140 may be provided in any region between the opening 171 and the opening 172 as long as it is a region other than the channel region 211.

[0064] Although Figure 1 Although not shown in the figure, in the insulating layer 170 and the gate insulating layer 220, as shown in FIG. Figure 3As shown, an opening 231 is provided. The gate electrode 230 is connected to the gate electrode 130 via the opening 231. Since the same voltage is supplied to the gate electrodes 130 and 230, the transistor 200 operates as a dual-gate transistor controlled by the top gate (gate electrode 230) and the bottom gate (gate electrode 130).

[0065] The opening 272 is provided in a region overlapping with the semiconductor layer 210 in a plan view. The opening 271 is provided in a region overlapping with the electrode 150 and the semiconductor layer 210 in a plan view and overlapping with the pattern end of the electrode 150. By making the opening 271 overlap with the pattern end of the electrode 150, Figure 1 As shown, the electrode 250 is in contact with both the electrode 150 and the semiconductor layer 210 .

[0066] [4. Functions of semiconductor devices]

[0067] like Figure 1 to Figure 3 As shown, transistor 100 is a dual-gate transistor controlled by gate electrodes 130 and 140. The dual-gate structure can reduce the voltage between the source and the drain adjacent to gate electrode 130 and the voltage between the source and the drain adjacent to gate electrode 140, thereby suppressing the reduction in reliability caused by hot carriers, etc. Furthermore, the dual-gate structure can reduce the electric field strength at each gate terminal, thereby suppressing the leakage current of transistor 100.

[0068] In the D1 direction, by making the length of the gate electrode 130 greater than the length of the gate electrode 230, the electric field generated in the channel region 211 of the transistor 200 can be made uniform by the gate electrode 130. In addition, light incident from the substrate 101 side can be prevented from reaching the semiconductor layer 210.

[0069] In order to obtain the effect of suppressing the reduction in reliability as described above, the low resistance region 114 is provided between the gate electrode 130 and the gate electrode 140, so that the length of the gate electrode 140 can be made smaller than the length of the gate electrode 130 in the D1 direction. Furthermore, based on the semiconductor device 10, the P-type transistor 100 and the N-type transistor 200 constituting the CMOS circuit can be stacked. In other words, the channel region 111 of the transistor 100 overlaps with the channel region 211 of the transistor 200 in a plan view. By having such a feature, the circuit size of the semiconductor device 10 can be reduced. That is, the semiconductor device 10 exerts the effect of suppressing the reduction in reliability while reducing the circuit size.

[0070] [5. Materials of Components of Semiconductor Device 10]

[0071] As the substrate 101, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 101 needs to be flexible, a substrate containing resin, such as a polyimide substrate, an acrylic resin substrate, a siloxane-based substrate, or a fluororesin substrate can be used as the substrate 101. When a substrate containing resin is used as the substrate 101, impurities can be introduced into the resin to improve the heat resistance of the substrate 101. In particular, when the semiconductor device 10 is a top-emitting display device, since the substrate 101 does not need to be transparent, impurities that deteriorate the transparency of the substrate 101 can also be used. When the semiconductor device 10 is used in an integrated circuit of a non-display device, as the substrate 101, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, or other substrates that are not light-transmitting can be used.

[0072] As the semiconductor layer 110 , for example, low-temperature polysilicon, amorphous silicon, or single crystal silicon can be used.

[0073] As the conductive layer including the gate electrodes 130, 140, 230 and the electrodes 150, 160, 250, 260, a general metal material can be used. For example, as the above-mentioned components, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. As the above-mentioned conductive layer, the above-mentioned materials can be used as a single layer or as a stacked layer.

[0074] As the insulating layer including the gate insulating layer 120, 220 and the insulating layer 102, 170, 270, a general insulating material can be used. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), Silicon Nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ), aluminum nitride (AlN x O y ) etc. As the above-mentioned insulating layer, the above-mentioned materials may be used as a single layer or as a stacked layer.

[0075] As the insulating layer 170, 270, an insulating layer having a function of releasing oxygen by heat treatment can be used. That is, an oxide insulating layer containing excessive oxygen can be used as the insulating layer 170, 270. The temperature of the heat treatment for releasing oxygen from the insulating layer 170, 270 is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the insulating layer 170, 270 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when, for example, a glass substrate is used as the substrate 101.

[0076] As the gate insulating layer 120, 220, an insulating layer with few defects can be used. For example, when the composition ratio of oxygen in the gate insulating layer 120, 220 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the gate insulating layer 120, 220 (hereinafter referred to as "other insulating layer"), the composition ratio of oxygen in the gate insulating layer 120, 220 is closer to the stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, silicon oxide (SiO2) is used in each of the gate insulating layer 120, 220 and the insulating layer 170, 270. x ), the oxygen composition ratio of the silicon oxide used as the gate insulating layers 120 and 220 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of the silicon oxide used as the insulating layers 170 and 270. For example, a layer in which no defects are observed when evaluating using the electron spin resonance method (ESR) may be used as the gate insulating layers 120 and 220.

[0077] The above SiO x N y and AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio less than that of nitrogen (x>y).

[0078] When an oxide semiconductor layer is used as the semiconductor layer 210, a metal oxide having semiconductor characteristics can be used as the oxide semiconductor layer. For example, as the semiconductor layer 210, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) can also be used. For example, as the semiconductor layer 210, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can also be used. However, the oxide semiconductor containing In, Ga, Zn and O used in this embodiment is not limited to the above composition. As the oxide semiconductor, an oxide semiconductor having a composition different from that described above can also be used. For example, in order to improve mobility, an oxide semiconductor layer having an In ratio greater than that described above can also be used. On the other hand, in order to increase the band gap and reduce the influence of light irradiation, an oxide semiconductor layer having a Ga ratio greater than that described above can also be used.

[0079] As the semiconductor layer 210, an oxide semiconductor containing two or more metals including indium (In) may be used. In this case, in the semiconductor layer 210, the ratio of the indium element to all metal elements may be 50% or more in terms of atomic ratio. As the semiconductor layer 210, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanide elements may also be used. As the semiconductor layer 210, other elements other than the above may also be used.

[0080] As the semiconductor layer 210, other elements may be added to the oxide semiconductor containing In, Ga, Zn and O, for example, metal elements such as Al and Sn may be added. In addition to the above-mentioned oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn and Zn (ITZO), an oxide semiconductor containing In and W, etc. may also be used as the semiconductor layer 210.

[0081] When the ratio of the indium element is large, the oxide semiconductor layer used as the semiconductor layer 210 is easily crystallized. As described above, in the oxide semiconductor layer, by using a material in which the ratio of the indium element to all metal elements is 50% or more, an oxide semiconductor layer having a polycrystalline structure can be obtained. The oxide semiconductor layer preferably contains gallium as another metal element other than indium. Gallium and indium belong to the same Group 13 element. Therefore, the crystallinity of the oxide semiconductor layer is not hindered by gallium, and the oxide semiconductor layer has a polycrystalline structure.

[0082] The oxide semiconductor layer can be formed using a sputtering method. The composition of the oxide semiconductor layer formed by the sputtering method depends on the composition of the sputtering target. Even in the case where the oxide semiconductor layer has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer are roughly the same. In this case, the composition of the metal element of the oxide semiconductor layer can be determined based on the composition of the metal element of the sputtering target.

[0083] In the case where the oxide semiconductor layer has a polycrystalline structure, the composition of the oxide semiconductor layer can also be determined by an X-ray diffraction (XRD) method. Specifically, based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method, the composition of the metal elements of the oxide semiconductor layer can be determined. Furthermore, the composition of the metal elements of the oxide semiconductor layer can also be determined by fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. However, the oxygen element contained in the oxide semiconductor layer varies depending on the process conditions of sputtering, etc., and therefore sometimes cannot be determined by these methods.

[0084] As described above, the oxide semiconductor layer may include an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure may be prepared using the Poly-OS (Poly-crystalline Oxide Semiconductor; polycrystalline oxide semiconductor) technology described later. In the following description, when distinguishing from an oxide semiconductor having an amorphous structure, an oxide semiconductor having a polycrystalline structure is sometimes described as Poly-OS for description.

[0085] It should be noted that a semiconductor other than an oxide semiconductor may be used as the semiconductor layer 210. In this case, the semiconductor used as the semiconductor layer 210 is made of a material different from that used in the semiconductor layer 110 or has a different composition. That is, the transistor 100 has characteristics different from those of the transistor 200.

[0086] A metal oxide layer 300 may also be provided between the insulating layer 170 and the semiconductor layer 210 (see Figure 4 In this case, the metal oxide layer may also be in contact with the semiconductor layer 210. As the metal oxide layer, a metal oxide containing aluminum as a main component is used. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y) or the like. "Metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% or more and 70% or more, 10% or more and 60% or more, or 30% or more and 50% or less of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0087] [6.Poly-OS technology]

[0088] As described above, the Poly-OS included in the oxide semiconductor layer used as the semiconductor layer 210 can be formed by using sputtering and heat treatment. Here, a method for forming the oxide semiconductor layer is described.

[0089] First, an oxide semiconductor layer is formed into a film by sputtering. The formed oxide semiconductor layer has an amorphous structure. Here, an amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement is observed. For example, when an oxide semiconductor layer having an amorphous structure is observed using an XRD method, no specific peak based on a crystal structure is obtained in the diffraction pattern. It should be noted that an oxide semiconductor layer having an amorphous structure sometimes has a short-range ordered structure in a tiny area. However, such an oxide semiconductor layer does not show the characteristics of Poly-OS and can therefore be classified as an oxide semiconductor layer having an amorphous structure.

[0090] In the Poly-OS technology, the oxide semiconductor layer is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor layer is formed is below 150°C, preferably below 100°C, and more preferably below 50°C. If the temperature of the substrate during the formation of the oxide semiconductor layer is high, microcrystals are easily generated in the formed oxide semiconductor. The oxygen partial pressure in the chamber during film formation is above 1% and below 10%, preferably above 1% and below 5%, and further preferably above 2% and below 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to the excess oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor layer becomes uneven, and an oxide semiconductor layer containing a large number of microcrystals is formed, or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0091] Next, the oxide semiconductor layer formed by sputtering is heat treated. The heat treatment is performed in the air, but the atmosphere of the heat treatment is not limited thereto. The temperature of the heat treatment is 300°C to 500°C, preferably 350°C to 450°C. The time of the heat treatment is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing the heat treatment, the oxide semiconductor layer having an amorphous structure is crystallized to form an oxide semiconductor layer containing Poly-OS.

[0092] [7. Features of Poly-OS]

[0093] Next, characteristics of an oxide semiconductor layer including Poly-OS used as the semiconductor layer 210 will be described below.

[0094] The oxide semiconductor layer has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer when being etched using an etchant for wet etching is very small. This means that the oxide semiconductor layer is hardly etched by the etchant. When the oxide semiconductor layer is etched using an etchant containing phosphoric acid as a main component at a temperature of about 40°C, the etching rate is less than 3nm / min, less than 2nm / min or less than 1nm / min. The proportion of phosphoric acid in the etchant is greater than 50%, greater than 60% or greater than 70%. In addition to phosphoric acid, nitric acid and acetic acid may also be included in the etchant. It should be noted that the above-mentioned temperature of about 40°C is the set temperature of the device for maintaining the etchant, and the actual temperature of the etchant is greater than 35°C and less than 45°C.

[0095] On the other hand, for an oxide semiconductor layer not including Poly-OS, for example, an oxide semiconductor layer having an amorphous structure before heat treatment, the etching rate when the oxide semiconductor layer is etched at a temperature of about 40° C. using an etchant containing phosphoric acid as a main component is greater than 100 nm / min.

[0096] When etching the oxide semiconductor layer including Poly-OS using a 0.5% hydrofluoric acid solution at room temperature (e.g., about 22° C.), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Here, room temperature refers to 25° C.±5° C. The actual temperature of the etching solution at this time is greater than 20° C. and less than 30° C.

[0097] On the other hand, when the oxide semiconductor layer not containing Poly-OS is etched using a 0.5% hydrofluoric acid solution at room temperature, the etching rate is 15 nm / min or more.

[0098] Here, an embodiment of the etching rate evaluation for the oxide semiconductor layer is shown in Table 1. In Table 1, the etching rates of each sample produced in a mixed acid etching solution and a 0.5% hydrofluoric acid solution are shown. As the mixed acid etching solution, "Mixed Acid AT-2F (product name)" of LASA Industries, Ltd. is used. The proportion of phosphoric acid in the mixed acid etching solution is about 65%. When etching each sample, the temperature of the mixed acid etching solution is about 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature. In Table 1, sample 1 is an oxide semiconductor layer containing Poly-OS, sample 2 is an oxide semiconductor layer having an amorphous structure before heat treatment, and sample 3 is an oxide semiconductor layer of indium gallium zinc oxide (IGZO) containing an indium ratio of less than 50%.

[0099] [Table 1]

[0100] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min

[0101] As shown in Table 1, for sample 1 (an oxide semiconductor layer containing Poly-OS), it is hardly etched using a mixed acid etching solution, and is only etched at 2 nm / min even using a 0.5% hydrofluoric acid solution. Compared with sample 2 (an oxide semiconductor layer having an amorphous structure before heat treatment), sample 1 has an etching rate of less than 1 / 100 in a mixed acid etching solution and an etching rate of less than about 1 / 10 in a 0.5% hydrofluoric acid solution. In addition, compared with sample 3 (an oxide semiconductor layer containing IGZO having an indium ratio of less than 50%), sample 1 has an etching rate of less than 1 / 100 in a mixed acid etching solution. That is, compared with samples 2 and 3, sample 1 is significantly superior in terms of etching resistance.

[0102] The excellent etching resistance of the oxide semiconductor layer containing Poly-OS is a property that cannot be obtained in the conventional oxide semiconductor having a polycrystalline structure produced under process conditions below 500° C. The detailed mechanism of the excellent etching resistance of the oxide semiconductor layer containing Poly-OS is not yet clear, but it is believed that Poly-OS has a polycrystalline structure different from the conventional one.

[0103] As described above, the etching rate of the oxide semiconductor layer containing Poly-OS in the etching solution is very low. Therefore, it is very difficult to pattern the oxide semiconductor layer. Therefore, in the case of forming an island-shaped oxide semiconductor layer, the oxide semiconductor layer having an amorphous structure before heat treatment is patterned into an island shape, and then heat treated to crystallize. Thus, an island-shaped oxide semiconductor layer containing Poly-OS can be formed.

[0104] [8. Method for Manufacturing Semiconductor Device 10]

[0105] Regarding a method for manufacturing a semiconductor device according to an embodiment of the present invention, refer to Figures 5 to 8 Provide explanation. Figures 5 to 8 The following is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the method for manufacturing the semiconductor device 10 described below, a configuration in which polysilicon is used as the semiconductor layer 110 and an oxide semiconductor (Poly-OS) is used as the semiconductor layer 210 is described.

[0106] like Figure 5 As shown, first, an insulating layer 102 and a semiconductor layer formed of polysilicon are formed on a substrate 101, and the semiconductor layer is processed by a photolithography process to form a semiconductor layer 110. Next, a gate insulating layer 120 is formed on the insulating layer 102 and the semiconductor layer 110. Next, a conductive layer is formed on the gate insulating layer 120, and the conductive layer is processed by a photolithography process to form gate electrodes 130 and 140 overlapping the semiconductor layer 110.

[0107] Next, using the gate electrodes 130 and 140 as masks, impurities are injected into the semiconductor layer 110 through the gate insulating layer 120. By injecting impurities, channel regions 111 and 112 and other low resistance regions 113 to 115 are formed. When the transistor 100 is a P-type transistor, boron is used as an impurity. On the other hand, when the transistor 100 is an N-type transistor, phosphorus is used as an impurity.

[0108] Next, an insulating layer 170 is formed on the gate insulating layer 120 and the gate electrodes 130 and 140. Next, an oxide semiconductor layer is formed on the insulating layer 170 and processed by a photolithography process to form the semiconductor layer 210. Next, a gate insulating layer 220 is formed on the insulating layer 170 and the semiconductor layer 210.

[0109] like Figure 6 As shown, the gate insulating layer 220 and the insulating layer 170 are processed by a photolithography process to form openings 171, 221 reaching the drain region (low resistance region 113) of the semiconductor layer 110, and openings 172, 222 reaching the source region (low resistance region 115) of the semiconductor layer 110. Next, a conductive layer is formed on the gate insulating layer 220 and inside the openings 171, 172, 221, 222. The formed conductive layer is processed by a photolithography process to form electrodes 150, 160 and a gate electrode 230.

[0110] Next, using the gate electrode 230 as a mask, impurities are implanted into the semiconductor layer 210 via the gate insulating layer 220. The implantation of impurities forms a channel region 211 and low resistance regions 213 and 214. The method of forming the low resistance regions 213 and 214 will be described in detail later.

[0111] like Figure 7 As shown, an insulating layer 270 is formed on the gate insulating layer 220 to cover the electrodes 150, 160 and the gate electrode 230. The gate insulating layer 220 and the insulating layer 270 are processed by a photolithography process to form openings 271 and 272 reaching the drain region (low resistance region 213) and the source region (low resistance region 214) of the semiconductor layer 210.

[0112] like Figure 8 As shown in FIG. 2 , a conductive layer 259 is formed on the insulating layer 270 and inside the openings 271 and 272. The formed conductive layer 259 is processed by a photolithography process to form Figure 1 Electrodes 250, 260 are shown.

[0113] [9. Method for forming low resistance regions 213 and 214]

[0114] use Figure 6 , the formation method of the drain region (low resistance region 213) and the source region (low resistance region 214) of the semiconductor layer 210 is described. Figure 6 As shown, on the semiconductor layer 210, after the gate insulating layer 220 and the gate electrode 230 are formed, ion implantation is performed on the semiconductor layer 210. For example, by ion implantation, boron (B) is implanted as an impurity element into the semiconductor layer 210. However, other impurity elements such as phosphorus (P) may be implanted into the semiconductor layer 210 instead of boron.

[0115] In a region where the gate electrode 230 is not provided, the impurity element reaches the semiconductor layer 210 through the gate insulating layer 220 . However, in a region where the gate electrode 230 is provided (channel region 211 ), the impurity element is blocked by the gate electrode 230 and thus does not reach the semiconductor layer 210 .

[0116] By the above-mentioned ion implantation, low resistance regions 213 and 214 into which impurity elements are implanted are formed in the semiconductor layer 210. In the semiconductor layer 210 in the low resistance regions 213 and 214, oxygen vacancies are formed by the implantation of impurity elements, so that the semiconductor layer 210 in this region has low resistance. It should be noted that in the oxide semiconductor layer including Poly-OS, the oxide semiconductor layer in the low resistance regions 213 and 214 into which impurity elements are implanted sometimes has crystallinity. This is also one of the characteristics of Poly-OS. In this case, the crystal structure of each oxide semiconductor layer in the low resistance regions 213 and 214 is the same as the crystal structure of the oxide semiconductor layer in the channel region 211.

[0117] The above manufacturing method exemplifies the manufacturing method using Poly-OS as the semiconductor layer 210 , but the manufacturing method of the semiconductor device 10 is not limited to the above method. For example, a manufacturing method in which an oxide semiconductor having an amorphous structure is formed as the semiconductor layer 210 may be used.

[0118] As the embodiments of the present invention, the embodiments described above can be appropriately combined and implemented as long as they are not contradictory. In addition, based on the embodiments, those skilled in the art can appropriately add, delete, or design changes to the components, or add, omit, or change the conditions of the processes, as long as they have the gist of the present invention, which is also included in the scope of the present invention.

[0119] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, effects that can be clearly seen from the description of this specification or effects that can be easily predicted by those skilled in the art are of course interpreted as effects brought about by the present invention.

Claims

1. A semiconductor device comprising: A first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second gate electrode which is opposed to the first semiconductor layer and is supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode and between the first semiconductor layer and the second gate electrode; a second semiconductor layer, which sandwiches the first gate electrode together with the first semiconductor layer; a third gate electrode facing the second semiconductor layer on the side opposite to the first gate electrode with respect to the second semiconductor layer and overlapping the first gate electrode in a plan view; and a second gate insulating layer between the second semiconductor layer and the third gate electrode.

2. The semiconductor device according to claim 1, wherein: The second semiconductor layer includes an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein: The second gate electrode does not overlap with the third gate electrode in a plan view.

4. The semiconductor device according to claim 3, further comprising: a first electrode connected to the first semiconductor layer in the first region; and a second electrode connected to the first semiconductor layer in the second region on the side opposite to the first electrode with respect to the first gate electrode and the second gate electrode, The first gate electrode and the second gate electrode are separated from each other in a cross-sectional view along a line connecting the first region and the second region.

5. The semiconductor device according to claim 4, wherein: The first gate electrode is connected to the second gate electrode in a region that does not overlap with the first semiconductor layer in a plan view.

6. The semiconductor device according to claim 5, further comprising: a first electrode connected to the first semiconductor layer in the first region; and a second electrode connected to the first semiconductor layer in the second region on the side opposite to the first electrode with respect to the first gate electrode and the second gate electrode, In a first direction connecting the first region and the second region, a length of the second gate electrode is smaller than a length of the first gate electrode.

7. The semiconductor device according to claim 6, wherein: The first gate electrode and the second gate electrode are in the same layer.

8. The semiconductor device according to claim 1, further comprising: a first electrode connected to the first semiconductor layer in the first region; and a second electrode connected to the first semiconductor layer in the second region on the side opposite to the first electrode with respect to the first gate electrode and the second gate electrode, In a first direction connecting the first region and the second region in cross-sectional view along a line connecting the first region and the second region, a length of the first gate electrode is greater than a length of the third gate electrode.

9. The semiconductor device according to claim 8, further comprising: a third electrode connected to the second semiconductor layer in the third region; and a fourth electrode connected to the second semiconductor layer in the fourth region on the side opposite to the third electrode with respect to the third gate electrode, supplying different voltages to the second electrode and the fourth electrode, respectively; The first electrode is electrically connected to the third electrode.

10. The semiconductor device according to claim 8, wherein The first electrode and the third gate electrode are in the same layer.

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