Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and an electronic device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a photoelectric conversion region and a transistor region, and forming a gate electrode on the semiconductor substrate of the transistor region; forming a dielectric layer on the surfaces of the semiconductor substrate and the gate electrode; forming a patterned hard mask layer on the surface of the dielectric layer on the photoelectric conversion region and the side wall of the gate electrode; etching the dielectric layer based on the hard mask layer to remove the dielectric layer formed on the top of the gate electrode and on the surface of the semiconductor substrate in the transistor region to obtain an offset side wall formed by the dielectric layer formed on the side wall of the gate electrode, and the protective layer is formed by the dielectric layer formed in the photoelectric conversion region. According to the invention, the semiconductor substrate can be prevented from being damaged in the process of forming the offset side wall.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] CMOS Image Sensor (CIS) is a semiconductor device that converts optical signals into electrical signals. It is widely used in mobile phones, digital cameras, security monitoring, medical impact and automotive electronics. It has the advantages of low power consumption, high integration, good compatibility and strong anti-noise ability.

[0003] CMOS image sensors usually include a transistor area and a photoelectric conversion area, each of which has different functions and together completes image capture and processing. Among them, the photoelectric conversion area is mainly responsible for capturing light signals and converting them into electrical signals, while the transistor area is mainly responsible for controlling the work of the photoelectric conversion area and processing the electrical signals.

[0004] When forming offset sidewalls on both sides of the gate electrode in the transistor area, a common practice is to form a photoresist layer in the photoelectric conversion area and use the photoresist layer as a mask to dry-etch the offset sidewalls in the transistor area. However, the photoresist has poor plasma resistance and cannot effectively resist the erosion of etching gas, so the protection of the photoelectric conversion area is insufficient, and the plasma in the dry etching process is also likely to damage the surface of the semiconductor substrate in the transistor area. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: Providing a semiconductor substrate, the semiconductor substrate comprising a photoelectric conversion region and a transistor region, wherein a gate electrode is formed on the semiconductor substrate in the transistor region; forming a dielectric layer on the surfaces of the semiconductor substrate and the gate electrode; forming a patterned hard mask layer on the surface of the dielectric layer located on the photoelectric conversion region and the sidewalls of the gate electrode; The dielectric layer is etched based on the hard mask layer to remove the dielectric layer formed on the top of the gate electrode in the transistor area and on the surface of the semiconductor substrate, thereby obtaining an offset side wall formed by the dielectric layer formed on the side wall of the gate electrode and a protective layer formed by the dielectric layer formed in the photoelectric conversion area.

[0007] In one embodiment, the forming of a patterned hard mask layer on the surface of the dielectric layer located on the sidewalls of the photoelectric conversion region and the gate electrode comprises: depositing a hard mask layer on the dielectric layer; forming a photoresist layer on the hard mask layer of the photoelectric conversion region; Using the photoresist layer as a mask, dry-etching the hard mask layer to remove the hard mask layer formed on the top of the gate electrode and on the surface of the semiconductor substrate in the transistor region to obtain the patterned hard mask layer; and The photoresist layer is removed.

[0008] In one embodiment, the dry etching further removes a portion of the dielectric layer.

[0009] In one embodiment, after depositing the hard mask layer and before forming the photoresist layer, the method further includes: A brush cleaning process is performed on the surface of the hard mask layer.

[0010] In one embodiment, etching the dielectric layer based on the hard mask layer includes: The dielectric layer is etched using a wet etching process.

[0011] In one embodiment, after etching the dielectric layer based on the hard mask layer, the method further includes: The hard mask layer is removed by a wet etching process.

[0012] In one embodiment, the dielectric layer includes a silicon oxide layer, and the hard mask layer includes a silicon nitride layer and / or a silicon oxynitride layer.

[0013] In one embodiment, after forming the offset spacer, the method further comprises: Lightly doped ions are implanted into the semiconductor substrate in the transistor region based on the offset spacer to form lightly doped drains on both sides of the gate electrode.

[0014] Another aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the method as described above.

[0015] Another aspect of an embodiment of the present invention provides an electronic device, wherein the electronic device includes the semiconductor device as described above.

[0016] According to the semiconductor device and its manufacturing method, and electronic device provided by the present invention, a patterned hard mask layer is formed on the dielectric layer, and the hard mask layer is used as a mask instead of the photoresist layer in the process of etching the dielectric layer to form an offset sidewall, which can not only avoid plasma damage to the semiconductor substrate surface of the transistor area, but also provide better protection for the photoelectric conversion area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0018] In the attached figure: Figure 1A to Figure 1B A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing various steps according to a method for manufacturing a semiconductor device in the related art is shown; Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention; FIG. 3A to FIG. 3F The cross-sectional schematic diagram shows a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0019] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0020] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0021] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0022] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] like Figure 1A and Figure 1BAs shown, the CMOS image sensor includes a photoelectric conversion region and a transistor region, which can be isolated by a shallow trench isolation structure 101, and a gate electrode 102 is formed on a semiconductor substrate 100 in the transistor region. When an offset spacer is formed on the sidewall of the gate electrode 102, a dielectric layer 103 covering the photoelectric conversion region and the transistor region is usually formed first, and then a photoresist layer 104 is formed on the dielectric layer 103 in the photoelectric conversion region, and then the dielectric layer 103 in the transistor region is etched using the photoresist layer 104 as a mask, thereby forming an offset spacer 103a on the sidewall of the gate electrode 102, which is used to protect the sidewall of the gate electrode 102 and form a self-alignment process for the subsequent lightly doped drain (LDD). The dielectric layer 103 in the photoelectric conversion region is retained due to the coverage of the photoresist layer 104, and serves as a protective layer 103b in the photoelectric conversion region.

[0025] In the above process flow, there are mainly the following two problems: first, the photoresist layer has poor plasma resistance and cannot effectively resist the erosion of the etching gas, so the protection of the photoelectric conversion area is insufficient; second, when the dielectric layer 103 of the transistor area is etched using a dry etching process, the plasma used for etching can easily damage the surface of the semiconductor substrate in the transistor area.

[0026] In view of the existence of the above technical problems, an embodiment of the present invention provides a method for preparing a semiconductor device. Figures 2 to 3F The method for preparing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. FIG. 3A to FIG. 3F The cross-sectional schematic diagram shows a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0027] First, execute step S201, such as Figure 3A As shown, a semiconductor substrate 300 is provided. The semiconductor substrate 300 includes a photoelectric conversion region and a transistor region. A gate electrode 302 is formed on the semiconductor substrate 300 in the transistor region.

[0028] The material of the semiconductor substrate 300 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI).

[0029] CMOS image sensors include pixel areas and logic areas. The pixel area includes a photoelectric conversion area and a pixel transistor area. The photoelectric conversion area is used to form a photodiode (PD). The photodiode is used for photoelectric conversion. When it is exposed to light, it will produce electron transitions and convert optical signals into electrical signals. The pixel transistor area is used to form pixel transistors. The pixel transistors are mainly used to control charge transfer, reset and signal readout in the photoelectric conversion area; pixel transistors are usually MOSFET transistors. The logic area is used to form logic transistors. Logic transistors are mainly used to realize more complex digital logic operations and signal processing; logic transistors are usually CMOS transistors.

[0030] It is understandable that the photoelectric conversion region of the embodiment of the present invention is the photoelectric conversion region in the pixel region, and the transistor region can be the pixel transistor region in the pixel region, or can be the logic region (or logic transistor region). Exemplarily, the photoelectric conversion region and the transistor region are isolated by a shallow trench isolation structure 301.

[0031] A gate electrode 302 is formed on the semiconductor substrate 300 in the transistor region. The material of the gate electrode 302 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer and a metal silicide layer. Exemplarily, a gate dielectric layer is also formed between the semiconductor substrate 300 and the gate electrode 302, and the gate dielectric layer includes a silicon oxide layer, which can be formed by a thermal oxidation growth process or a chemical vapor deposition process; the gate dielectric layer can also include a high-K gate dielectric layer, and its material can be selected from, for example, TiO2, Al2O3, ZrO2, HfO2, Ta2O5, La2O3, etc. Exemplarily, before forming the gate electrode 302, ion implantation can also be performed on the semiconductor substrate 300 in the photoelectric conversion region to form a pixel unit.

[0032] Next, step S202 is performed to form a dielectric layer 303 on the surfaces of the semiconductor substrate 300 and the gate electrode 302 .

[0033] Specifically, the dielectric layer 303 is formed on the upper surface of the semiconductor substrate 300 in the transistor region, the top and sidewalls of the gate electrode 302, the upper surface of the semiconductor substrate 300 in the photoelectric conversion region, and the upper surface of the shallow trench isolation structure 301. The dielectric layer 303 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric layer, etc. In one example, TEOS (tetraethyl orthosilicate) may be used as a precursor material to perform a chemical vapor deposition (CVD) process to form a silicon dioxide layer as the dielectric layer 303. After TEOS enters the reaction chamber, it decomposes into silicon dioxide and byproducts at high temperature, and silicon dioxide is deposited on the surface of the gate electrode 302 and the semiconductor substrate 300 to form a uniform film.

[0034] Illustratively, before forming the dielectric layer 303 , a pre-cleaning process may be performed to remove pollutants and natural oxides on the wafer surface, activate the chemical activity on the wafer surface, and improve the quality and adhesion of the deposited dielectric layer 303 .

[0035] Next, step S203 is performed to form a patterned hard mask layer 304 on the surface of the dielectric layer 303 located on the photoelectric conversion region and the sidewalls of the gate electrode 302 .

[0036] The material of the hard mask layer 304 is different from that of the dielectric layer 303, and there is a certain etching selectivity between the two. For example, when the dielectric layer 303 is a silicon oxide layer, the hard mask layer 304 can be a silicon nitride layer or a silicon nitride oxide layer.

[0037] like Figure 3A and Figure 3B As shown, the steps of forming the patterned hard mask layer 304 specifically include: first, depositing the hard mask layer 304 on the dielectric layer 303. The process used to deposit the hard mask layer 304 may include chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process and other commonly used deposition processes in the art.

[0038] For example, after depositing the hard mask layer 304 , the surface of the hard mask layer 304 may be scrubbed to remove particles and contaminants on the surface and to change the surface of the hard mask layer 304 from hydrophobic to hydrophilic, thereby improving the contact between the hard mask layer 304 and a subsequently formed photoresist layer.

[0039] Next, a photoresist layer 305 is formed on the hard mask layer 304 in the photoelectric conversion region. Specifically, the photoresist layer is spin-coated on the hard mask layer 304, and the photoresist layer is exposed and developed to form a window in the photoresist layer, which exposes the transistor region below.

[0040] Next, the hard mask layer 304 is dry etched using the photoresist layer 305 as a mask to remove the hard mask layer 304 formed on the top of the gate electrode 302 in the transistor area and on the surface of the semiconductor substrate 300, retaining the hard mask layer on the side wall of the gate electrode 302 and the hard mask layer 304 in the photoelectric conversion area as the above-mentioned patterned hard mask layer.

[0041] Among them, an anisotropic dry etching process can be used to etch the hard mask layer 304, and the etching direction is perpendicular to the surface of the semiconductor substrate 300. Exemplarily, the dry etching process may include plasma etching, which uses active free radicals in the plasma to chemically react with the material surface of the hard mask layer 304 to generate volatile products, thereby achieving etching. Alternatively, a reactive ion etching (RIE) process can be used to ionize the gas to form a plasma by applying a radio frequency electric field, and the ions bombard the surface of the hard mask layer 304 under the action of the electric field, and the active free radicals react chemically with the material of the hard mask layer 304 to perform etching. An ion beam etching (IBE) process can also be used to directly bombard the surface of the hard mask layer 304 with a high-energy ion beam, and perform etching through physical sputtering.

[0042] The dry etching process etches in the vertical direction, so in the transistor region, the hard mask layer 304 on the surface of the semiconductor substrate 300 and the hard mask layer 304 on the top of the gate electrode 302 are removed because they are perpendicular to the etching direction, while the hard mask layer 304 on the sidewall of the gate electrode 302 is retained because it is parallel to the etching direction. The hard mask layer 304 in the photoelectric conversion region is also retained because it is protected by the photoresist layer 305.

[0043] Furthermore, in the above-mentioned dry etching process, the dielectric layer 303 of a preset thickness can also be removed. Exemplarily, a dry etching process with high directivity and low etching selectivity can be used for etching, so as to simultaneously remove the hard mask layer 304 and part of the dielectric layer 303. By removing part of the dielectric layer 303 in the dry etching process, the etching time of the subsequent wet etching process can be reduced, and the side digging of the bottom of the offset sidewall can be avoided. For details, see the following.

[0044] Then, if Figure 3C As shown, the photoresist layer 305 is removed. Exemplarily, the photoresist layer 305 can be removed by an asher process, a wet stripping process, or a combination of the two. The asher process refers to decomposing the photoresist layer by oxidation through oxygen plasma, and the wet stripping process refers to dissolving the photoresist layer by chemical reagents such as sulfuric acid-hydrogen peroxide solution, organic solvent, alkaline solution, and ozone solution.

[0045] Next, execute step S204, such as Figure 3DAs shown, the dielectric layer 303 is etched based on the patterned hard mask layer 304 to remove the dielectric layer formed on the top of the gate electrode 302 in the transistor area and on the surface of the semiconductor substrate 300, thereby obtaining an offset sidewall 303a formed by the dielectric layer 303 formed on the sidewall of the gate electrode 302, and a protective layer 303b formed by the dielectric layer 303 formed in the photoelectric conversion area.

[0046] As mentioned above, in the previous process, the dielectric layer is etched using the photoresist layer located in the photoelectric conversion area as a mask. In order to remove the dielectric layer located on the top of the gate electrode and on the surface of the semiconductor substrate and retain the dielectric layer located on the sidewall of the gate electrode as an offset sidewall, an anisotropic dry etching process is required to ensure that the etching direction is perpendicular to the surface of the semiconductor substrate. Therefore, in order to ensure the directionality of the plasma during the etching process, it is necessary to bombard the dielectric layer with high-energy plasma, which is easy to cause plasma damage to the surface of the semiconductor substrate.

[0047] In the embodiment of the present invention, the dielectric layer 303 on the side wall of the gate electrode 302 and the dielectric layer 303 in the photoelectric conversion region are protected by a patterned hard mask layer 304, while the dielectric layer 303 on the top of the gate electrode 302 and the dielectric layer 303 on the surface of the semiconductor substrate 300 located in the device region are exposed to the outside, so that the dielectric layer 303 can be etched by an isotropic wet etching process, thereby avoiding damage to the surface of the semiconductor substrate 300 caused by the high-energy plasma used in dry etching; at the same time, the hard mask layer 304 can better shield the photoelectric conversion region than the photoresist layer, thereby avoiding ions penetrating the mask and being injected into the photoelectric conversion region to affect the performance of the image sensor.

[0048] For example, when the material of the dielectric layer 303 is silicon oxide and the material of the hard mask layer 304 is silicon nitride or silicon oxynitride, the etchant used in the wet etching process may include diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE).

[0049] Optionally, in addition to the wet etching process, the dry etching process may be used to etch the dielectric layer, and at the same time, the plasma bombardment energy may be reduced to avoid damage to the surface of the semiconductor substrate 300. Since the embodiment of the present invention reduces the requirement for etching directionality through the hard mask layer 304, reducing the plasma bombardment energy will not affect the morphology of the offset sidewall 303a finally formed.

[0050] When an isotropic etching process is used, the etching direction includes the horizontal direction in addition to the vertical direction. If the etching time is too long, the dielectric layer 303 may be etched laterally along the bottom of the hard mask layer 304, thereby generating a depression at the bottom of the offset sidewall 303a, i.e., side digging. In the embodiment of the present invention, the dielectric layer 303 of a preset thickness is removed in the previous dry etching process, thereby reducing the etching amount required for wet etching, reducing the wet etching time, and effectively avoiding the side digging phenomenon.

[0051] It should also be noted that, in the embodiment of the present invention, it is not required to completely remove the dielectric layer 303 on the top of the gate electrode 302 and the surface of the semiconductor substrate 300 in the device region, and a relatively thin dielectric layer 303 may be retained to protect the semiconductor substrate 300 and the gate electrode 302 in the subsequent ion implantation process. Exemplarily, the thickness of the retained dielectric layer 303 is not greater than 50 angstroms.

[0052] like Figure 3E As shown, after completing the wet etching of the dielectric layer 303, a wet etching process can also be used to remove the remaining hard mask layer 304. For example, a hot phosphoric acid solution can be used to remove the hard mask layer 304. Using a wet etching process to remove the hard mask layer 304 can avoid plasma damage to the surface of the semiconductor substrate 300.

[0053] Finally, if Figure 3F As shown, based on the offset spacer 303a, the semiconductor substrate 300 in the transistor region is lightly doped with ions to form a lightly doped drain 306 on both sides of the gate electrode 302. The lightly doped drain (LDD) can reduce the electric field peak near the drain by introducing a lightly doped region between the drain and the channel, thereby reducing the generation and injection of hot carriers, and by adjusting the doping distribution at the edge of the channel to form a gentler electric field gradient, thereby enhancing the control ability of the gate over the channel, alleviating the short channel effect, and being able to increase the breakdown voltage and reduce the leakage current.

[0054] During the lightly doped ion implantation process, due to the blocking effect of the offset sidewall 303a on the doped ions, there is a distance between the formed lightly doped drain 306 and the channel of the transistor device, and the doped ions will not reduce the width of the channel due to subsequent annealing diffusion. In addition, the thicker protective layer 303b of the photoelectric conversion region can protect the photoelectric conversion region from being contaminated by the LDD doped ions, and prevent the ion implantation process from causing damage to the surface of the semiconductor substrate 300 of the photoelectric conversion region.

[0055] So far, the process steps of the method for manufacturing a semiconductor device according to the first aspect of the present invention are completed. It can be understood that the method for manufacturing a semiconductor device in this embodiment not only includes the above steps, but also includes other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method in this embodiment. For example, main sidewalls can be formed on both sides of the offset sidewall 303a, and ion implantation can be performed on the semiconductor substrate based on the main sidewalls to form source and drain electrodes.

[0056] According to the manufacturing method of the semiconductor device provided by the embodiment of the present invention, a patterned hard mask layer is formed on the dielectric layer, and the hard mask layer is used as a mask instead of the photoresist layer in the process of etching the dielectric layer to form the offset sidewall, which can not only avoid plasma damage to the semiconductor substrate surface of the transistor area, but also provide better protection for the photoelectric conversion area.

[0057] An embodiment of the present invention further provides a semiconductor device, which can be manufactured by the method in the aforementioned embodiment, but is not limited thereto.

[0058] The semiconductor device of the present invention is introduced and described in detail below. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiments. For specific explanations and descriptions, reference can be made to the description in Embodiment 1.

[0059] Specifically, Figure 3F As shown, the semiconductor device of the embodiment of the present invention includes a semiconductor substrate 300, and the semiconductor substrate 300 includes a photoelectric conversion region and a transistor region. A gate electrode 302 is formed on the semiconductor substrate 300 in the transistor region; the photoelectric conversion region and the transistor region are isolated by a shallow trench isolation structure 301; offset sidewalls 303a are formed on both sides of the gate electrode 302, and lightly doped drains 306 are formed in the semiconductor substrate 300 on both sides of the offset sidewalls 303a; a protective layer 303b is formed on the surface of the semiconductor substrate 300 in the photoelectric conversion region.

[0060] The semiconductor device according to the embodiment of the present invention has similar advantages because it is manufactured by the above method.

[0061] The third aspect of the present invention further provides an electronic device in an embodiment, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0062] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0063] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a semiconductor substrate, the semiconductor substrate comprising a photoelectric conversion region and a transistor region, wherein a gate electrode is formed on the semiconductor substrate in the transistor region; forming a dielectric layer on the surfaces of the semiconductor substrate and the gate electrode; forming a patterned hard mask layer on the surface of the dielectric layer located on the photoelectric conversion region and the sidewalls of the gate electrode; The dielectric layer is etched based on the patterned hard mask layer to remove the dielectric layer formed on the top of the gate electrode in the transistor area and on the surface of the semiconductor substrate, thereby obtaining an offset sidewall formed by the dielectric layer formed on the side wall of the gate electrode and a protective layer formed by the dielectric layer formed in the photoelectric conversion area.

2. The manufacturing method according to claim 1, characterized in that The etching of the dielectric layer based on the patterned hard mask layer comprises: The dielectric layer is etched using a wet etching process.

3. The manufacturing method according to claim 2, characterized in that: After etching the dielectric layer based on the patterned hard mask layer, the method further includes: The hard mask layer is removed by a wet etching process.

4. The manufacturing method according to claim 1, characterized in that: The step of forming a patterned hard mask layer on the surface of the dielectric layer located on the photoelectric conversion region and the sidewalls of the gate electrode comprises: depositing a hard mask layer on the dielectric layer; forming a photoresist layer on the hard mask layer located in the photoelectric conversion region; Using the photoresist layer as a mask, dry-etching the hard mask layer to remove the hard mask layer formed on the top of the gate electrode and on the surface of the semiconductor substrate in the transistor region to obtain the patterned hard mask layer; and The photoresist layer is removed.

5. The manufacturing method according to claim 4, characterized in that: The dry etching also removes part of the dielectric layer.

6. The manufacturing method according to claim 4, characterized in that: After depositing the hard mask layer and before forming the photoresist layer, the method further includes: A brush cleaning process is performed on the surface of the hard mask layer.

7. The manufacturing method according to claim 1, characterized in that: The dielectric layer includes a silicon oxide layer, and the hard mask layer includes a silicon nitride layer and / or a silicon nitride oxide layer.

8. The manufacturing method according to claim 1, characterized in that: After forming the offset sidewall, the method further includes: Lightly doped ions are implanted into the semiconductor substrate of the transistor region based on the offset spacer to form lightly doped drains on both sides of the gate electrode.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to claim 9.

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