Photovoltaic cell and preparation method thereof

Abstract

The invention provides a photovoltaic cell and a preparation method thereof, relates to the technical field of photovoltaics, and aims to solve the technical problem that the yield of the photovoltaic cell is difficult to improve. The method comprises the steps that a substrate is provided, the substrate is provided with a first surface, and the first surface comprises a first area, a second area and a third area located between the first area and the second area; sequentially stacking a tunneling oxide layer, a first doped silicon-containing layer and a conductive layer on the first region; an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the second region; a tunneling oxide layer, a first doped silicon-containing layer, an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the third region; removing a part, opposite to the first sub-region and a part, opposite to the second sub-region, of the conductive layer step by step by adopting an etching method; wherein the first sub-region is a part, adjacent to the third region, of the first region; the second sub-region is a portion of the second region adjacent to the third region. According to the method, the battery yield can be improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a photovoltaic cell and a preparation method thereof. Background Art

[0002] The statements in this section merely provide background art related to the present invention and do not necessarily constitute prior art.

[0003] Heterojunction (HJT) cells are mainly composed of a PN heterojunction consisting of silicon and doped amorphous silicon. An intrinsic amorphous silicon passivation layer is embedded at the heterojunction interface, and then a layer of transparent conductive oxide (TCO) is prepared on both sides of the silicon wafer.

[0004] In recent years, back contact (BC) cell technology has been used to improve the photoelectric conversion performance of heterojunction cells. Specifically, all the cell grid electrodes are moved to the back of the cell, reducing the grid lines' shielding of sunlight, thereby improving the absorption efficiency of incident light and achieving higher conversion efficiency, forming a back contact heterojunction cell (HBC).

[0005] In the preparation process of HBC batteries, the P region and N region of the battery are both located on the back of the battery, and TCO needs to be prepared on the surfaces of both. Due to a certain height difference between the P region and the N region, accurate control cannot be performed during the preparation of TCO, resulting in a decrease in battery yield. Summary of the invention

[0006] The object of the present invention is to provide a photovoltaic cell and a method for preparing the same, so as to solve the technical problem that the cell yield is difficult to improve in the method for preparing the photovoltaic cell.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] In a first aspect, the present invention provides a method for preparing a photovoltaic cell, comprising:

[0009] Providing a substrate, the substrate having a first surface, the first surface including a first area, a second area, and a third area located between the first area and the second area;

[0010] A tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are sequentially stacked on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer are sequentially stacked on the third region; a conductive layer is stacked on the first doped silicon-containing layer in the first region and on the second doped silicon-containing layers in the second and third regions;

[0011] An etching method is used to stepwise remove the portion of the conductive layer opposite to the first sub-region and the portion opposite to the second sub-region; wherein the first sub-region includes at least one of the portion of the first region adjacent to the third region and at least a portion of the third region; and the second sub-region is the portion of the second region adjacent to the third region.

[0012] According to at least one embodiment of the present invention, the step of removing the portion of the conductive layer opposite to the first sub-region and the portion of the conductive layer opposite to the second sub-region in steps by an etching method includes:

[0013] The etching solution is applied step by step through a printing process to remove the portion of the conductive layer opposite to the first sub-region and the portion of the conductive layer opposite to the second sub-region.

[0014] According to at least one embodiment of the present invention, the printing process includes one or more of screen printing, laser transfer, and steel plate printing.

[0015] According to at least one embodiment of the present invention, a first screen is covered on a portion of the conductive layer opposite to the second region, wherein a hollow region of the first screen is opposite to the second sub-region;

[0016] A second screen is covered on a portion of the conductive layer opposite to the second area and / or the third area, wherein a hollow area of ​​the second screen is opposite to the first sub-area.

[0017] According to at least one embodiment of the present invention, the etching solution includes one or more of sulfuric acid and phosphoric acid; and / or,

[0018] The pH value of the etching solution ranges from 0 to 3.

[0019] According to at least one embodiment of the present invention, the width of the first sub-region ranges from 0.5 μm to 200 μm; and / or,

[0020] The width of the second sub-region ranges from 0.5 μm to 200 μm.

[0021] According to at least one embodiment of the present invention, the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the third region, further comprising:

[0022] A dielectric layer is stacked on the third region, wherein the dielectric layer is located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

[0023] According to at least one embodiment of the present invention, a tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region, comprising:

[0024] stacking the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer in sequence on the first surface;

[0025] The tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer on the second region are removed.

[0026] According to at least one embodiment of the present invention, the substrate has a second surface opposite to the first surface, and removing the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer on the second region includes:

[0027] Removing the dielectric layer on the second region by laser film opening, and removing the tunneling oxide layer and the first doped silicon-containing layer on the second region by chemical etching;

[0028] Forming a velvet structure on the second region and the second surface of the substrate respectively by a velvet treatment; or,

[0029] Removing the dielectric layer, the tunneling oxide layer and the first doped silicon-containing layer on the second region by laser film opening;

[0030] A textured structure is formed on the second region and the second surface of the substrate respectively through a texture making process.

[0031] According to at least one embodiment of the present invention, after forming a suede structure on the second region and the second surface of the substrate respectively, the method further includes:

[0032] stacking a passivation layer and an anti-reflection layer in sequence on the suede structure of the second surface;

[0033] When the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the second region, the method comprises:

[0034] The intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the textured structure in the second region.

[0035] According to at least one embodiment of the present invention, when the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the textured structure in the second region, the method includes:

[0036] stacking the intrinsic silicon-containing layer and the second doped silicon-containing layer in sequence on the textured structure of the second region, the dielectric layer of the third region, and the dielectric layer of the first region;

[0037] The intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region are removed.

[0038] According to at least one embodiment of the present invention, when removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the method includes:

[0039] removing the intrinsic silicon-containing layer and the second doped silicon-containing layer on the first region by laser film opening;

[0040] The dielectric layer on the first region is removed by alkali washing.

[0041] According to at least one embodiment of the present invention, after removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the preparation method further includes:

[0042] The conductive layer is stacked on the second doped silicon-containing layer in the second region, on the second doped silicon-containing layer in the third region, and on the first doped silicon-containing layer in the first region, and the conductive layer is an integrated structure.

[0043] In a second aspect, the present invention further provides a photovoltaic cell, comprising a substrate, wherein the substrate has a first surface, wherein the first surface comprises a first region, a second region, and a third region located between the first region and the second region;

[0044] A tunneling oxide layer, a first doped silicon-containing layer and a conductive layer are sequentially stacked on the first region; an intrinsic silicon-containing layer, a second doped silicon-containing layer and the conductive layer are sequentially stacked on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the third region, and the first doped silicon-containing layer and the second doped silicon-containing layer have opposite doping types;

[0045] The conductive layer has a first discontinuous structure on the first sub-region, and the conductive layer has a second discontinuous structure on the second sub-region, wherein the first sub-region includes at least one of a portion of the first region adjacent to the third region and at least a portion of the third region; and the second sub-region is a portion of the second region adjacent to the third region.

[0046] According to at least one embodiment of the present invention, the width of the first sub-region ranges from 0.5 μm to 200 μm; and / or,

[0047] The width of the second sub-region ranges from 0.5 μm to 200 μm.

[0048] According to at least one embodiment of the present invention, a portion of the second doped silicon-containing layer opposite to the third region is higher than a portion of the second doped silicon-containing layer opposite to the second region to form a height difference, and the height difference ranges from 0.5 μm to 8 μm.

[0049] According to at least one embodiment of the present invention, a step surface is formed between a portion of the second doped silicon-containing layer opposite to the third region and a portion of the second doped silicon-containing layer opposite to the second region, and a portion of the conductive layer is disposed on the step surface.

[0050] According to at least one embodiment of the present invention, the photovoltaic cell further includes a dielectric layer, which is stacked on the third region and located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

[0051] According to at least one embodiment of the present invention, the substrate is a p-type substrate or an n-type substrate.

[0052] According to at least one embodiment of the present invention, one of the first doped silicon-containing layer and the second doped silicon-containing layer is a p-type doped silicon-containing layer, and the other is an n-type doped silicon-containing layer.

[0053] According to at least one embodiment of the present invention, the substrate has a second surface opposite to the first surface, and a passivation layer and an anti-reflection layer are sequentially stacked on the second surface.

[0054] According to at least one embodiment of the present invention, the second region and the second surface of the substrate are respectively formed with a textured structure.

[0055] According to at least one embodiment of the present invention, the tunnel oxide layer is made of silicon oxide and has a thickness of 0.5 nm to 3 nm; and / or,

[0056] The first doped silicon-containing layer is made of n-type doped polysilicon and has a thickness of 30 nm to 300 nm; and / or,

[0057] The dielectric layer is made of at least one of silicon oxide, silicon nitride and silicon oxynitride; and / or,

[0058] The material of the intrinsic silicon-containing layer is at least one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or,

[0059] The material of the second doped silicon-containing layer is at least one of p-type doped microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or,

[0060] The material of the conductive layer includes at least one of transparent conductive metal oxide and transparent conductive metal nitride.

[0061] Among the one or more technical solutions provided in the exemplary embodiments of the present invention, at least one of the following beneficial effects can be achieved.

[0062] In the photovoltaic cell preparation method of the exemplary embodiment of the present invention, the first surface (back side) of the substrate is divided into a first region, a second region and a third region separating the two, wherein one of the first region and the second region may be a P region and the other may be an N region. Specifically, a tunneling oxide layer, a first doped silicon-containing layer and a conductive layer are sequentially stacked on the first region, an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the second region, and a tunneling oxide layer, a first doped silicon-containing layer, an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the third region. Thus, a height difference is inevitably formed between the P region and the N region, and a conductive layer is stacked on each region, and the conductive layer between the P region and the N region needs to be disconnected to prevent short circuit. The conductive layer is removed at a position close to both sides of the third region by an etching method, so as to separate the conductive layer between the P region and the N region. The positions on both sides of the third region are also the positions of the first sub-region and the second sub-region. The first sub-region is a small part of the first region adjacent to the third region, and the second sub-region is a small part of the second region adjacent to the third region.

[0063] Compared with the prior art that uses slurry etching printing to simultaneously etch the first sub-region, the second sub-region and the third region, due to the height difference between the P region and the N region and the different battery structures, the synchronous printing and etching of the above three regions will cause different forces on the printing screen in different regions, and the printing accuracy cannot be accurately controlled; while in the preparation method of the exemplary embodiment of the present invention, the etching on the first sub-region and the second sub-region is not synchronous, but one of the two regions is etched first, and then the other region is etched, and the third region is not etched. The step-by-step etching can overcome the etching offset problem caused by the height difference between the P region and the N region, and can also extend the service life of the screen.

[0064] In the preparation method of the exemplary embodiment of the present invention, part of the conductive layer is retained on the third area, so that the light inside the battery enters the low refractive index from the high refractive index, increasing the reflectivity of the internal light, thereby increasing the secondary absorption of light and improving the utilization rate of sunlight.

[0065] Furthermore, since the etching area does not include the third region, the etching area is smaller than that of the prior art, and the impact on the passivation layer below the conductive layer is smaller, thereby protecting the integrity of the passivation structure and reducing the impact on battery efficiency.

[0066] Compared with the prior art, which uses a laser film opening process to disconnect the conductive layer between the P region and the N region in an insulating manner, the preparation method of the exemplary embodiment of the present invention adopts a slurry etching process, which can avoid laser damage to the battery and increase the photoelectric conversion efficiency of the battery to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention, and these drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification;

[0068] Figure 1 is a schematic flow chart of a method for preparing a photovoltaic cell according to an embodiment of the present invention;

[0069] Figures 2 to 9 It is a schematic cross-sectional diagram of the corresponding process structure after each step in the photovoltaic cell preparation method according to an embodiment of the present invention is completed.

[0070] Reference numerals: 10, substrate; 11, first surface; 12, second surface; 11a, first velvet structure; 12a, second velvet structure;

[0071] 21. first doped silicon-containing layer; 22. tunneling oxide layer; 23. dielectric layer;

[0072] 31. Intrinsic silicon-containing layer; 32. Second doped silicon-containing layer;

[0073] 41. passivation layer; 42. anti-reflection layer;

[0074] 50. Conductive layer;

[0075] 61. First electrode; 62. Second electrode. DETAILED DESCRIPTION

[0076] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0077] The highest photoelectric conversion efficiency of HBC cells can reach 27.1%. Its P region and N region are located on the same side of the substrate, and the surface needs to be covered with a conductive layer, such as a TCO layer. In the HBC cell preparation process, the TCO layer needs to be disconnected at the junction of the P region and the N region for insulation. In the related art, the above-mentioned junction area is disconnected by laser grooving. This process will damage the functional layer under the TCO layer and reduce the photoelectric conversion efficiency of the battery. The use of etching slurry printing to disconnect the TCO layer in the above-mentioned junction area at one time will cause printing offset problems due to the height difference between the P region and the N region.

[0078] In response to the above problems, the photovoltaic cell preparation method provided by the exemplary embodiment of the present invention adopts a step-by-step etching method using a corrosive slurry to form discontinuous structures in the parts of the TCO layer adjacent to the boundary area in the P region and the N region in steps, thereby avoiding the printing offset problem caused by the height difference and reducing the area of ​​the etching area to minimize the impact on the cell's photoelectric conversion efficiency.

[0079] It should be noted that the photovoltaic cell preparation method provided by the exemplary embodiment of the present invention is not only applicable to HBC cells, but also applicable to other types of photovoltaic cells using BC cell technology.

[0080] Figure 1 is a schematic flow chart of a method for preparing a photovoltaic cell according to an embodiment of the present invention; Figures 2 to 9 1 is a schematic cross-sectional view of the process structure corresponding to each step in the photovoltaic cell preparation method according to the embodiment of the present invention. Figure 1 As shown, an exemplary embodiment of the present invention provides a method for preparing a photovoltaic cell, which may include the following steps:

[0081] Step 101: Provide a substrate 10, the substrate 10 having a first surface 11 and a second surface 12 opposite to each other, the first surface 11 including a first area E1, a second area E2 and a third area E3 located between the first area E1 and the second area E2, such as Figure 2 shown.

[0082] For example, the substrate 10 may be a silicon substrate, such as a p-type silicon substrate or an n-type silicon substrate. The following description takes the n-type silicon substrate as an example. The front side (light-receiving side) of the substrate 10 is the second surface 12, and the back side is the first surface 11.

[0083] It should be noted that Figure 2 The first surface 11 of the substrate 10 does not have only one set of the first region E1, the second region E2 and the third region E3, but may have a plurality of sets of the above regions.

[0084] For example, the first surface 11 may have a first area E1, a third area E3, a second area E2, a third area E3, a first area E1, a third area E3, and a second area E2 arranged in sequence, and reciprocatingly; or, the first surface 11 may have a first area E1, a third area E3, a second area E2, a third area E3, a second area E2, a third area E3, and a first area E1 arranged in sequence, and reciprocatingly, that is, there is a third area E3 between each group of areas.

[0085] Step 102: stacking a tunneling oxide layer 22, a first doped silicon-containing layer 21, and a conductive layer 50 in sequence on the first region E1; stacking an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 in sequence on the second region E2; and stacking a tunneling oxide layer 22, a first doped silicon-containing layer 21, an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 in sequence on the third region E3 to form a Figure 7 The structure shown.

[0086] Step 1021: Texturing and polishing are performed on the first surface 11 and the second surface 12 of the substrate 10 (silicon substrate) to form a tower base structure.

[0087] In practical applications, a velvet surface can be formed on both the first surface 11 and the second surface 12 of the substrate 10 by alkali washing, and dirt, impurities, metal ions, etc. on the surface of the substrate 10 can be removed by alkali washing for polishing. The alkaline etching solution used for the alkali washing can be potassium hydroxide, sodium hydroxide, etc. The tower base structure is the bottom structure remaining after the velvet surface is polished.

[0088] Step 1022: stacking a tunneling oxide layer 22, a first doped silicon-containing layer 21 and a dielectric layer 23 on the first surface 11 in sequence to form Figure 3 The structure shown.

[0089] The tunnel oxide layer 22 , the first doped silicon-containing layer 21 and the dielectric layer 23 may be deposited in sequence on the substrate 10 in a deposition manner over the entire area of ​​the first surface 11 .

[0090] The deposition process can be prepared by any one of vacuum evaporation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD), or a combination of multiple deposition methods.

[0091] An example is given for explanation in which an n region (negative region) is formed in the first region E1 , a p region (positive region) is formed in the second region E2 , and a spacer region between the p region and the n region is formed in the third region E3 .

[0092] Exemplarily, the tunneling oxide layer 22 is a silicon oxide layer, and its thickness can be 0.5nn~3.0nm, such as 0.7nm, 1nm, 1.5nm, 2nm, 2.5nm, etc. By reasonably controlling the thickness of the tunneling oxide layer 22, the probability of collecting majority carriers can be increased, thereby improving the photoelectric conversion efficiency of the battery.

[0093] Exemplarily, the first doped silicon-containing layer 21 is made of n-type doped polysilicon, and has a thickness of 30 nm to 300 nm, for example, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, etc.

[0094] Exemplarily, the material of the dielectric layer 23 is at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0095] Step 1023: remove the tunneling oxide layer 22, the first doped silicon-containing layer 21 and the dielectric layer 23 on the second region E2 to form Figure 4 The structure shown.

[0096] The tunnel oxide layer 22 , the first doped silicon-containing layer 21 and the dielectric layer 23 on the second region E2 are removed by a method combining one or more of laser stripping, chemical cleaning and etching.

[0097] For example, the dielectric layer 23 on the second area E2 is removed by laser opening, and the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second area E2 are removed by chemical etching; further, a velvet structure is formed on the second area E2 and the second surface 12 of the substrate 10 by velvet treatment.

[0098] Specifically, after the tunnel oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 are removed by alkaline corrosion, a first velvet structure 11a and a second velvet structure 12a are formed on the second region E2 and the second surface 12 of the exposed substrate 10 by texturing, respectively. The velvet structure may be in a pyramid shape. The chemical corrosion may include alkaline solution and acid solution, the alkaline solution may be sodium hydroxide, and the acid solution may be hydrofluoric acid and nitric acid. The chemical reagent used in the texturing treatment may also be alkaline solution.

[0099] In another optional embodiment, the dielectric layer 23, the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second area E2 are removed by laser film opening; and a velvet structure is formed on the second area E2 and the second surface 12 of the substrate 10 by texturing treatment.

[0100] The specific process of laser film opening (laser peeling) is to emit laser through a laser and bombard the surface with laser to remove the corresponding layer.

[0101] Step 1024a: stacking an intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32 on the first textured structure 11a of the second region E2, the dielectric layer 23 of the third region E3, and the dielectric layer 23 of the first region E1 in sequence to form Figure 5 The structure shown.

[0102] By chemical deposition, an intrinsic silicon-containing layer 31 is first deposited on the first textured structure 11 a of the second region E2 , the dielectric layer 23 of the third region E3 , and the dielectric layer 23 of the first region E1 , and then a second doped silicon-containing layer 32 is deposited.

[0103] Exemplarily, the material of the intrinsic silicon-containing layer 31 is at least one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide. For example, the intrinsic silicon-containing layer 31 is a single layer with the same performance or a multi-layer with different performance or a stacked or mixed silicon-containing film of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide.

[0104] Exemplarily, the second doped silicon-containing layer 32 is at least one of p-type doped microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide. For example, it is a single layer with the same performance or a multi-layer with different performance or a stacked or mixed silicon-containing film of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide or other thin film layers doped with boron.

[0105] Exemplarily, the thickness of the second doped silicon-containing layer 32 is 30 nm to 300 nm, such as 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, etc.

[0106] Step 1024b: stack the passivation layer 41 and the anti-reflection layer 42 in sequence on the suede structure of the second surface 12 to form Figure 5 The structure shown.

[0107] The passivation layer 41 is first deposited on the textured structure (second textured structure 12 a ) of the second surface 12 by chemical deposition, and then the anti-reflection layer 42 is deposited.

[0108] Exemplarily, the passivation layer 41 is one of an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a combination of an intrinsic silicon-containing layer 31 / a second doped silicon-containing layer 32, wherein the thickness of the intrinsic silicon-containing layer 31 is 1 nm to 15 nm, and the thickness of the second doped silicon-containing layer 32 is 0 to 15 nm.

[0109] Exemplarily, the material of the anti-reflection layer 42 is at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, and zinc oxide, and the thickness is 40nm to 200nm, for example, 60nm, 70nm, 80nm, 100nm, 150nm, 190nm, etc.

[0110] It should be noted that the step of forming the passivation layer 41 in this step can be performed simultaneously with the step of forming the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 in step 1024 , thereby shortening the process flow and simplifying the operation.

[0111] Step 1025: When removing the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32 and the dielectric layer 23 on the first region E1, the process includes: removing the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 on the first region E1 by laser film opening; removing the dielectric layer 23 on the first region E1 by alkali washing, and forming Figure 6 The structure shown.

[0112] In practical applications, on the first area E1, the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 are first removed by laser film opening; then the dielectric layer 23 is etched away by alkaline washing, such as sodium hydroxide, potassium hydroxide and other solutions to expose the first doped silicon-containing layer 21.

[0113] Step 1026: stack a conductive layer 50 on the second doped silicon-containing layer 32 in the second region E2, on the second doped silicon-containing layer 32 in the third region E3, and on the first doped silicon-containing layer 21 in the first region E1 to form a conductive layer 50. Figure 7 The structure shown.

[0114] In practical applications, the structure surface formed on the first surface 11 of the substrate 10 in step 1025 is formed into an integrally formed conductive layer 50 by chemical deposition.

[0115] The material of the conductive layer 50 includes at least one of transparent conductive metal oxide and transparent conductive metal nitride.

[0116] Specifically, the conductive layer 50 is a TCO film layer, which is a multilayer or stacked layer or mixture of one or more doped metal oxides or nitrides. The metal oxide may be indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride, and the metal nitride may be titanium nitride. The doping element may be indium, tin, calcium, aluminum, cadmium, zinc, cerium or fluorine.

[0117] Step 103: Use an etching method to remove the conductive layer 50 in steps, the portion opposite to the first sub-region E11 and the portion opposite to the second sub-region E22; wherein the first sub-region E11 is the portion of the first region E1 adjacent to the third region E3; the second sub-region E22 is the portion of the second region E2 adjacent to the third region E3, to form Figure 8 The structure shown.

[0118] In actual applications, the first sub-area E11 is a partial area on the first area E1, the width of which is substantially the same as the width of the third area E3, and the partial area is adjacent to the third area E3; the second sub-area E22 is a partial area on the second area E2, the width of which is substantially the same as the width of the third area E3, and the partial area is adjacent to the third area E3; that is, the first sub-area E11 and the second sub-area E22 are respectively located on both sides of the third area E3.

[0119] Exemplarily, the width of the first sub-region E11 ranges from 0.5 μm to 200 μm, for example, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 130 μm, 150 μm, 170 μm, 190 μm, etc.

[0120] Exemplarily, the width of the second sub-region E22 ranges from 0.5 μm to 200 μm, for example, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 130 μm, 150 μm, 170 μm, 190 μm, etc.

[0121] The etching method uses an etching solution to corrode the conductive layer 50 to form a first discontinuous structure and a second discontinuous structure on both sides of the third area E3, so that the conductive layer 50 on the first area E1 is electrically insulated from the conductive layer 50 on the third area E3, and the conductive layer 50 on the second area E2 is electrically insulated from the conductive layer 50 on the third area E3, that is, the conductive layer 50 on the first area E1 is electrically insulated from the conductive layer 50 on the second area E2.

[0122] Exemplarily, the material of the etching paste may be sulfuric acid, phosphoric acid, etc., and the pH value is 0-3.

[0123] Exemplarily, the printing process is a combination of one or more of screen printing, laser transfer, steel plate printing, etc., and a similar graphic scheme can be achieved.

[0124] Specifically, the etching method uses a printing process to apply the etching paste on the first sub-region E11 or the second sub-region E22 to etch the corresponding conductive layer 50. In the step-by-step etching method, two screens can be used, and the etching paste is first applied to one sub-region using the first screen, and then the etching paste is applied to the other sub-region using the second screen.

[0125] Specifically, both the first screen and the second screen have hollow areas, and the hollow areas are aligned with the corresponding first sub-area E11 or second sub-area E22, and the etching paste is scraped on the first sub-area E11 or second sub-area E22 through the hollow areas using a scraper, and the corresponding conductive layer 50 is corroded to form a discontinuous structure for electrical insulation. Exemplarily, the first screen and the second screen can be the same or different, depending on the actual sub-area to be etched.

[0126] The order of etching the conductive layer 50 in the first sub-region E11 and the second sub-region E22 is not critical.

[0127] In other embodiments, the first sub-region E11 may be the portion of the first region E1 adjacent to the third region E3, or may be a part or all of the third region E3, or may be a part of the third region E3 and the portion of the first region E1 adjacent to the third region E3; or may be the entire third region E3 and the portion of the first region E1 adjacent to the third region E3.

[0128] Therefore, the step-by-step etching method is adopted to avoid the problem that the printing precision cannot be accurately controlled due to the height difference between the first area E1 and the second area E2 in the synchronous etching method (using the same screen to print the strong acid slurry simultaneously in the first sub-area E11, the second sub-area E22 and the third area E3). At the same time, it also avoids the problem that the height difference causes different forces in synchronous printing and the service life of the screen is short.

[0129] Compared with laser grooving to disconnect the conductive layer 50 on the first region E1 and the second region E2 , the screen printing etching has less influence on the passivation structure under the conductive layer 50 , thereby having less influence on the battery efficiency.

[0130] Furthermore, the step-by-step etching retains the conductive layer 50 on the third region E3, and the etching area is smaller, thereby protecting the integrity of the passivation structure.

[0131] At the same time, the conductive layer 50 is retained on the third area E3, so that the light inside the battery enters the low refractive index from the high refractive index, increasing the reflectivity of the internal light, thereby increasing the secondary absorption of light and improving the utilization rate of sunlight. Retaining the dielectric layer 23 on the third area E3 can also increase the reflectivity of the internal light of the battery, which is conducive to improving the utilization rate of sunlight.

[0132] In some other embodiments, when the first sub-region E11 includes a part or the whole of the third region E3, a portion of the conductive layer 50 opposite to the third region E3 is partially or completely etched away.

[0133] The portion of the second doped silicon-containing layer 32 opposite to the third region E3 is higher than the portion of the second doped silicon-containing layer 32 opposite to the second region E2 to form a height difference, and the height difference ranges from 0.5 μm to 8 μm. For example, the height difference is 0.7 μm, 1 μm, 3 μm, 5 μm, 7 μm, etc.

[0134] As can be seen from the above, a step surface is formed between the portion of the second doped silicon-containing layer 32 opposite to the third region E3 and the portion of the second doped silicon-containing layer 32 opposite to the second region E2, and the step surface is roughly perpendicular to the distribution direction from the first region E1 to the second region E2. The present invention uses a step-by-step etching method, and the coating area of ​​the etching paste avoids the step surface. The conductive layer 50 will be deposited on the step surface during the formation process. Therefore, the step surface will retain a portion of the conductive layer 50.

[0135] Step 104: Form metal electrodes on the structures in the first area E1 and the second area E2 respectively, forming Fig. 9 The structure shown.

[0136] In practical applications, a first electrode 61 is disposed on the conductive layer 50 on the first area E1 , and a second electrode 62 is disposed on the conductive layer 50 on the second area E2 .

[0137] The corresponding metal electrodes are prepared on the first area E1 and the second area E2 by printing electrode paste. For example, one end of the first electrode 61 is located outside the conductive layer 50, and the other end is located inside the corresponding conductive layer 50; one end of the second electrode 62 is located outside the conductive layer 50, and the other end is located inside the corresponding conductive layer 50, thereby forming a photovoltaic cell.

[0138] Exemplarily, when the first doped silicon-containing layer 21 is a boron-doped silicon-containing layer, the first electrode 61 is a positive electrode, and correspondingly, the second electrode 62 is a negative electrode.

[0139] In some embodiments, when the first doped silicon-containing layer 21 is a phosphorus-doped silicon-containing layer, the first electrode 61 is a negative electrode, and correspondingly, the second electrode 62 is a positive electrode.

[0140] Exemplarily, the first electrode 61 and the second electrode 62 may be a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, or a nickel / copper / silver multilayer electrode, or a stack of several of them.

[0141] like Figure 8 As shown, an exemplary embodiment of the present invention provides a photovoltaic cell, which is manufactured using the photovoltaic cell manufacturing method of the above embodiment.

[0142] like Fig. 9As shown, an exemplary embodiment of the present invention further provides a photovoltaic cell, including a substrate 10 . The substrate 10 has a first surface 11 . The first surface 11 includes a first area E1 , a second area E2 , and a third area E3 located between the first area E1 and the second area E2 .

[0143] The first region E1 is stacked with a tunneling oxide layer 22, a first doped silicon-containing layer 21, and a conductive layer 50; the second region E2 is stacked with an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50; the third region E3 is stacked with a tunneling oxide layer 22, a first doped silicon-containing layer 21, an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50. The first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 have opposite doping types.

[0144] The conductive layer 50 on the first area E1 has a first discontinuous structure on the first sub-area E11, and the conductive layer 50 on the second area E2 has a second discontinuous structure on the second sub-area E22, wherein the first sub-area E11 includes at least one of a portion of the first area E1 adjacent to the third area E3 and at least a portion of the third area E3; and the second sub-area E22 is a portion of the second area E2 adjacent to the third area E3.

[0145] The conductive layer on the first region E1 and the second region E2 forms a first discontinuous structure in the first sub-region E11 and a second discontinuous structure in the second sub-region E22, thereby forming electrical isolation of regions with opposite polarities. Compared with the complete discontinuous structure across the third region E3 on the conductive layer to achieve electrical isolation, the screen offset problem of the printed etching paste caused by the height difference between the third region E3 and the second region E2 can be overcome. When the first sub-region E11 includes a part of the third region E3 or does not include the third region E3, the relative part of the conductive layer 50 and the third region E3 is retained, so that when etching to form the discontinuous structure, the etching area is smaller, so that the integrity of the passivation structure under the conductive layer can be protected, thereby having a smaller impact on the battery efficiency.

[0146] In some embodiments, the width of the first sub-region E11 ranges from 0.5 μm to 200 μm, for example, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 130 μm, 150 μm, 170 μm, 190 μm, etc.

[0147] In some embodiments, the width of the second sub-region E22 ranges from 0.5 μm to 200 μm, for example, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 130 μm, 150 μm, 170 μm, 190 μm, etc.

[0148] In some embodiments, the portion of the second doped silicon-containing layer 32 opposite to the third region E3 is higher than the portion of the second doped silicon-containing layer 32 opposite to the second region E2 to form a height difference, and the height difference ranges from 0.5 μm to 8 μm. For example, the height difference is 0.7 μm, 1 μm, 3 μm, 5 μm, 7 μm, etc.

[0149] In some embodiments, a step surface is formed between the portion of the second doped silicon-containing layer 32 opposite to the third region E3 and the portion of the second doped silicon-containing layer 32 opposite to the second region E2, and a portion of the conductive layer 50 is disposed on the step surface. The step surface is higher than the side surface of the second region. In this way, the conductive layer 50 on the step surface does not need to be removed, which reduces the process difficulty and improves the etching accuracy.

[0150] In some embodiments, the photovoltaic cell further includes a dielectric layer 23 , which is stacked on the third region E3 and located between the first doped silicon-containing layer 21 and the intrinsic silicon-containing layer 31 .

[0151] Retaining the dielectric layer 23 on the third area E3 can increase the internal light reflectivity of the cell, which is beneficial to improving the utilization rate of sunlight. For example, when light is incident from the front of the solar cell, it is reflected by the dielectric layer 23 and enters the substrate 10 again, thereby improving the utilization rate of sunlight.

[0152] In some embodiments, the substrate 10 is one of a p-type substrate 10 or an n-type substrate 10 .

[0153] In some embodiments, one of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 is a p-type doped silicon-containing layer, and the other is an n-type doped silicon-containing layer.

[0154] In some embodiments, the substrate 10 has a second surface 12 opposite to the first surface 11 , and a passivation layer 41 and an anti-reflection layer 42 are sequentially stacked on the second surface 12 .

[0155] In some embodiments, the second area E2 and the second surface 12 of the substrate 10 are respectively formed with a textured structure.

[0156] In some embodiments, the tunnel oxide layer 22 is made of silicon oxide and has a thickness of 0.5 nm to 3 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm.

[0157] In some embodiments, the first doped silicon-containing layer 21 is made of n-type doped polysilicon and has a thickness of 30 nm to 300 nm, such as 30 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm.

[0158] In some embodiments, the dielectric layer 23 is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0159] In some embodiments, the material of the intrinsic silicon-containing layer 31 is at least one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0160] In some embodiments, the material of the second doped silicon-containing layer 32 is at least one of p-type doped microcrystalline silicon, nano silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0161] In some embodiments, the material of the conductive layer 50 includes at least one of a transparent conductive metal oxide or a transparent conductive metal nitride.

[0162] The technical advantages of the above photovoltaic cell over the prior art are the same as the advantages of the above photovoltaic cell preparation method, which will not be repeated here.

[0163] The present invention also provides the following technical solutions:

[0164] Technical Solution 1. A method for preparing a photovoltaic cell, comprising:

[0165] Providing a substrate, the substrate having a first surface, the first surface including a first area, a second area, and a third area located between the first area and the second area;

[0166] A tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are sequentially stacked on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer are sequentially stacked on the third region; a conductive layer is stacked on the first doped silicon-containing layer in the first region and on the second doped silicon-containing layers in the second and third regions;

[0167] An etching method is used to stepwise remove the portion of the conductive layer opposite to the first sub-region and the portion opposite to the second sub-region; wherein the first sub-region includes at least one of the portion of the first region adjacent to the third region and at least a portion of the third region; and the second sub-region is the portion of the second region adjacent to the third region.

[0168] Technical Solution 2. According to the preparation method of Technical Solution 1, the step of removing the portion of the conductive layer corresponding to the first sub-region and the portion corresponding to the second sub-region in steps by an etching method comprises:

[0169] The etching solution is applied step by step through a printing process to remove the portion of the conductive layer opposite to the first sub-region and the portion of the conductive layer opposite to the second sub-region.

[0170] Technical Solution 3. According to the preparation method described in Technical Solution 2, the printing process includes one or more of screen printing, laser transfer, and steel plate printing.

[0171] Technical Solution 4. According to the preparation method described in Technical Solution 3, the etching method specifically comprises: placing a first screen cover on the portion of the conductive layer opposite to the second area, wherein the hollow area of ​​the first screen is opposite to the second sub-area;

[0172] A second screen is covered on a portion of the conductive layer opposite to the first area and / or the third area, wherein a hollow area of ​​the second screen is opposite to the first sub-area.

[0173] Technical Solution 5. According to the preparation method described in Technical Solution 2, the etching solution includes one or more of sulfuric acid and phosphoric acid; and / or,

[0174] The pH value of the etching solution ranges from 0 to 3.

[0175] Technical Solution 6. According to the preparation method described in Technical Solution 2, the width of the first sub-region ranges from 0.5 μm to 200 μm; and / or,

[0176] The width of the second sub-region ranges from 0.5 μm to 200 μm.

[0177] Technical Solution 7. According to the preparation method of Technical Solution 1, the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the third region, and further comprising:

[0178] A dielectric layer is stacked on the third region, wherein the dielectric layer is located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

[0179] Technical Solution 8. According to the preparation method described in Technical Solution 7, a tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region, comprising:

[0180] stacking the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer in sequence on the first surface;

[0181] The tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer on the second region are removed.

[0182] Technical Solution 9. According to the preparation method of Technical Solution 8, the substrate has a second surface opposite to the first surface, and the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer on the second region are removed, comprising:

[0183] Removing the dielectric layer on the second region by laser film opening, and removing the tunneling oxide layer and the first doped silicon-containing layer on the second region by chemical etching;

[0184] Forming a velvet structure on the second region and the second surface of the substrate respectively by a velvet treatment; or,

[0185] Removing the dielectric layer, the tunneling oxide layer and the first doped silicon-containing layer on the second region by laser film opening;

[0186] A textured structure is formed on the second region and the second surface of the substrate respectively through a texture making process.

[0187] Technical Solution 10. According to the preparation method of Technical Solution 9, after forming the suede structure on the second region and the second surface of the substrate respectively, the method further comprises:

[0188] stacking a passivation layer and an anti-reflection layer in sequence on the suede structure of the second surface;

[0189] When the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the second region, the method comprises:

[0190] The intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the textured structure in the second region.

[0191] Technical Solution 11. According to the preparation method of Technical Solution 10, when the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the textured structure of the second region, the method comprises:

[0192] stacking the intrinsic silicon-containing layer and the second doped silicon-containing layer in sequence on the textured structure of the second region, the dielectric layer of the third region, and the dielectric layer of the first region;

[0193] The intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region are removed.

[0194] Technical Solution 12. According to the preparation method of Technical Solution 11, when removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the method comprises:

[0195] removing the intrinsic silicon-containing layer and the second doped silicon-containing layer on the first region by laser film opening;

[0196] The dielectric layer on the first region is removed by alkali washing.

[0197] Technical Solution 13. According to the preparation method of Technical Solution 11, after removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the preparation method further includes:

[0198] The conductive layer is stacked on the second doped silicon-containing layer in the second region, on the second doped silicon-containing layer in the third region, and on the first doped silicon-containing layer in the first region, and the conductive layer is an integrated structure.

[0199] Technical Solution 14. A photovoltaic cell, comprising a substrate, the substrate having a first surface, the first surface comprising a first region, a second region, and a third region located between the first region and the second region;

[0200] A tunneling oxide layer, a first doped silicon-containing layer and a conductive layer are sequentially stacked on the first region; an intrinsic silicon-containing layer, a second doped silicon-containing layer and the conductive layer are sequentially stacked on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the third region, and the first doped silicon-containing layer and the second doped silicon-containing layer have opposite doping types;

[0201] The conductive layer has a first discontinuous structure on the first sub-region, and the conductive layer has a second discontinuous structure on the second sub-region, wherein the first sub-region includes at least one of a portion of the first region adjacent to the third region and at least a portion of the third region; and the second sub-region is a portion of the second region adjacent to the third region.

[0202] Technical Solution 15. According to the photovoltaic cell of Technical Solution 14, the width of the first sub-region ranges from 0.5 μm to 200 μm; and / or,

[0203] The width of the second sub-region ranges from 0.5 μm to 200 μm.

[0204] Technical Solution 16. According to the photovoltaic cell described in Technical Solution 14, the portion of the second doped silicon-containing layer opposite to the third region is higher than the portion of the second doped silicon-containing layer opposite to the second region and forms a height difference, and the height difference ranges from 0.5 μm to 8 μm.

[0205] Technical Solution 17. According to the photovoltaic cell described in Technical Solution 16, a step surface is formed between the portion of the second doped silicon-containing layer opposite to the third region and the portion of the second doped silicon-containing layer opposite to the second region, and a portion of the conductive layer is arranged on the step surface.

[0206] Technical Solution 18. According to the photovoltaic cell described in Technical Solution 14, the photovoltaic cell also includes a dielectric layer, and the dielectric layer is stacked on the third region and located between the first doped silicon-containing layer and the intrinsic silicon-containing layer.

[0207] Technical Solution 19. According to the photovoltaic cell described in Technical Solution 14, the substrate is one of a p-type substrate or an n-type substrate.

[0208] Technical Solution 20. According to the photovoltaic cell described in Technical Solution 14, one of the first doped silicon-containing layer and the second doped silicon-containing layer is a p-type doped silicon-containing layer, and the other is an n-type doped silicon-containing layer.

[0209] Technical Solution 21. According to the photovoltaic cell of Technical Solution 15, the substrate has a second surface opposite to the first surface, and a passivation layer and an anti-reflection layer are stacked in sequence on the second surface.

[0210] Technical Solution 22. According to the photovoltaic cell described in Technical Solution 21, the second region and the second surface of the substrate are respectively formed with a velvet structure.

[0211] Technical Solution 23. According to the photovoltaic cell of Technical Solution 21, the tunneling oxide layer is made of silicon oxide and has a thickness of 0.5 nm to 3 nm; and / or,

[0212] The first doped silicon-containing layer is made of n-type doped polysilicon and has a thickness of 30 nm to 300 nm; and / or,

[0213] The dielectric layer is made of at least one of silicon oxide, silicon nitride and silicon oxynitride; and / or,

[0214] The material of the intrinsic silicon-containing layer is at least one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or,

[0215] The material of the second doped silicon-containing layer is at least one of p-type doped microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or,

[0216] The material of the conductive layer includes at least one of transparent conductive metal oxide and transparent conductive metal nitride.

[0217] It should be understood by those skilled in the art that the above embodiments are only for the purpose of clearly illustrating the present invention, and are not intended to limit the scope of the present invention. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present invention.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: include: Providing a substrate, the substrate having a first surface, the first surface including a first area, a second area, and a third area located between the first area and the second area; A tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are sequentially stacked on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer are sequentially stacked on the third region; a conductive layer is stacked on the first doped silicon-containing layer in the first region and on the second doped silicon-containing layers in the second and third regions; An etching method is used to stepwise remove the portion of the conductive layer opposite to the first sub-region and the portion opposite to the second sub-region; wherein the first sub-region includes at least one of the portion of the first region adjacent to the third region and at least a portion of the third region; and the second sub-region is the portion of the second region adjacent to the third region.

2. The preparation method according to claim 1, characterized in that: The step of removing the portion of the conductive layer opposite to the first sub-region and the portion of the conductive layer opposite to the second sub-region in steps by using an etching method comprises: The etching solution is applied step by step through a printing process to remove the portion of the conductive layer opposite to the first sub-region and the portion of the conductive layer opposite to the second sub-region.

3. The preparation method according to claim 2, characterized in that: The printing process includes one or more of screen printing, laser transfer, and steel plate printing.

4. The preparation method according to claim 3, characterized in that: The etching method specifically comprises: placing a first screen cover on a portion of the conductive layer opposite to the second region, wherein a hollow region of the first screen is opposite to the second sub-region; A second screen is covered on a portion of the conductive layer opposite to the first area and / or the third area, wherein a hollow area of ​​the second screen is opposite to the first sub-area.

5. The preparation method according to claim 2, characterized in that: The etching solution includes one or more of sulfuric acid and phosphoric acid; and / or, The pH value of the etching solution ranges from 0 to 3.

6. The preparation method according to claim 2, characterized in that: The width of the first sub-region ranges from 0.5 μm to 200 μm; and / or, The width of the second sub-region ranges from 0.5 μm to 200 μm.

7. The preparation method according to claim 1, characterized in that: The tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the third region, and further comprising: stacking a dielectric layer on the third region, wherein the dielectric layer is located between the first doped silicon-containing layer and the intrinsic silicon-containing layer; Preferably, a tunneling oxide layer and a first doped silicon-containing layer are sequentially stacked on the first region, comprising: stacking the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer in sequence on the first surface; removing the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer on the second region; Preferably, the substrate has a second surface opposite to the first surface, and removing the tunneling oxide layer, the first doped silicon-containing layer and the dielectric layer on the second region comprises: Removing the dielectric layer on the second region by laser film opening, and removing the tunneling oxide layer and the first doped silicon-containing layer on the second region by chemical etching; Forming a velvet structure on the second region and the second surface of the substrate respectively by a velvet treatment; or, Removing the dielectric layer, the tunneling oxide layer and the first doped silicon-containing layer on the second region by laser film opening; Forming a velvet structure on the second region and the second surface of the substrate respectively through a velvet treatment; Preferably, after forming the suede structure on the second region and the second surface of the substrate respectively, the method further comprises: stacking a passivation layer and an anti-reflection layer in sequence on the suede structure of the second surface; When the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the second region, the method comprises: stacking the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer in sequence on the textured structure of the second region; Preferably, when the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the textured structure of the second region, the method comprises: stacking the intrinsic silicon-containing layer and the second doped silicon-containing layer in sequence on the textured structure of the second region, the dielectric layer of the third region, and the dielectric layer of the first region; removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region; Preferably, when removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the method includes: removing the intrinsic silicon-containing layer and the second doped silicon-containing layer on the first region by laser film opening; removing the dielectric layer on the first region by alkali washing; Preferably, after removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the preparation method further includes: The conductive layer is stacked on the second doped silicon-containing layer in the second region, on the second doped silicon-containing layer in the third region, and on the first doped silicon-containing layer in the first region, and the conductive layer is an integrated structure.

8. A photovoltaic cell, characterized in that: A substrate having a first surface, wherein the first surface comprises a first region, a second region, and a third region located between the first region and the second region; A tunneling oxide layer, a first doped silicon-containing layer and a conductive layer are sequentially stacked on the first region; an intrinsic silicon-containing layer, a second doped silicon-containing layer and the conductive layer are sequentially stacked on the second region; the tunneling oxide layer, the first doped silicon-containing layer, the intrinsic silicon-containing layer, the second doped silicon-containing layer and the conductive layer are sequentially stacked on the third region, and the first doped silicon-containing layer and the second doped silicon-containing layer have opposite doping types; The conductive layer has a first discontinuous structure on the first sub-region, and the conductive layer has a second discontinuous structure on the second sub-region, wherein the first sub-region includes at least one of a portion of the first region adjacent to the third region and at least a portion of the third region; and the second sub-region is a portion of the second region adjacent to the third region.

9. The photovoltaic cell according to claim 8, characterized in that: The width of the first sub-region ranges from 0.5 μm to 200 μm; and / or, The width of the second sub-region ranges from 0.5 μm to 200 μm.

10. The photovoltaic cell according to claim 8, characterized in that: A portion of the second doped silicon-containing layer opposite to the third region is higher than a portion of the second doped silicon-containing layer opposite to the second region and forms a height difference, and a value range of the height difference is 0.5 μm to 8 μm; Preferably, a step surface is formed between a portion of the second doped silicon-containing layer opposite to the third region and a portion of the second doped silicon-containing layer opposite to the second region, and a portion of the conductive layer is disposed on the step surface; Preferably, the photovoltaic cell further comprises a dielectric layer, which is stacked on the third region and located between the first doped silicon-containing layer and the intrinsic silicon-containing layer; Preferably, the substrate is a p-type substrate or an n-type substrate; Preferably, one of the first doped silicon-containing layer and the second doped silicon-containing layer is a p-type doped silicon-containing layer, and the other is an n-type doped silicon-containing layer; Preferably, the substrate has a second surface opposite to the first surface, and a passivation layer and an anti-reflection layer are sequentially stacked on the second surface; Preferably, the second region and the second surface of the substrate are respectively formed with a suede structure; Preferably, the tunnel oxide layer is made of silicon oxide and has a thickness of 0.5 nm to 3 nm; and / or, The first doped silicon-containing layer is made of n-type doped polysilicon and has a thickness of 30 nm to 300 nm; and / or, The dielectric layer is made of at least one of silicon oxide, silicon nitride and silicon oxynitride; and / or, The material of the intrinsic silicon-containing layer is at least one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or, The material of the second doped silicon-containing layer is at least one of p-type doped microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or, The material of the conductive layer includes at least one of transparent conductive metal oxide and transparent conductive metal nitride.

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