Manufacturing method of back contact battery, back contact battery and battery assembly

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a manufacturing method of a back contact cell, the back contact cell and a cell assembly, and the manufacturing method comprises the following steps: S2, sequentially forming a first semiconductor layer and a mask layer on the back surface of a silicon wafer; s3, performing opening etching for the first time on the back surface obtained in the step S2 to form a second semiconductor opening region; s4, cleaning through texturing; s5, sequentially forming a passivation layer and an anti-reflection layer on the front surface of the silicon wafer, wherein the anti-reflection layer comprises carbon-doped silicon nitride; s6, annealing oxidation is carried out so as to at least oxidize part of the anti-reflection layer; s7, removing the winding plating layer on the back surface, and then cleaning the opening area of the second semiconductor by adopting an HF-containing solution; the mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%; and S8, depositing a second semiconductor layer on the back surface. The stability of the battery manufacturing process can be ensured, and the solution cost is reduced; meanwhile, the passivation effect of the second semiconductor layer is improved, and the cell efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a method for manufacturing a back contact battery and a back contact battery and a battery assembly. Background Art

[0002] The existing back-contact battery post-texturing process includes forming a first semiconductor layer on a silicon wafer, then opening an opening to form a second semiconductor opening area, and then performing texturing and cleaning, followed by depositing a passivation layer and an anti-reflection layer on the front of the silicon wafer. After the passivation layer and the anti-reflection layer are formed on the front of the silicon wafer, there will be a certain amount of plating on the back, which needs to be cleaned by wet chemistry to ensure that there is no residual plating layer and laser-scratched damage layer on the surface of the second semiconductor opening area. At the same time, the first semiconductor layer must be prevented from being damaged by solution corrosion in the cleaning solution. Therefore, the wet chemical cleaning solution must not be too corrosive, otherwise the second semiconductor opening area will not be cleaned properly, and it must not be too corrosive, otherwise the first semiconductor layer will be easily damaged during the cleaning process, resulting in passivation and conductivity being affected. In short, there is currently a problem of unstable cleaning leading to unstable battery process and inability to take into account battery efficiency.

[0003] CN118658933A discloses a method for preparing a back contact battery, which includes oxygen annealing after depositing a passivation layer, then cleaning the generated plating layer, and then depositing an anti-reflection layer. This method anneals the passivation layer with oxygen, which will cause hydrogen in the amorphous silicon to overflow, resulting in poor passivation performance, and cannot solve the problem of unstable battery process.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defect of the prior art that the post-texturing process of the back-contact battery cannot take into account both the stability of the battery process and the battery efficiency, and to provide a manufacturing method for a back-contact battery and its back-contact battery and battery assembly, which can ensure the stability of the battery process and reduce the solution cost; at the same time, it is beneficial to improve the passivation effect of the second semiconductor layer and improve the battery efficiency.

[0006] In order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing a back contact battery, comprising the following steps: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, forming a texture surface at least on the second semiconductor opening region by texturing and cleaning, and then performing or not performing a step of removing the mask layer; S5, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer, wherein the anti-reflection layer comprises carbon-doped silicon nitride; S6, then performing annealing oxidation to oxidize at least part of the anti-reflection layer, and during the annealing oxidation process, controlling the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride; S7, removing the back side coating, and then using a HF-containing solution to clean the second semiconductor opening region; the mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%; S8. Depositing a second semiconductor layer on the back side.

[0007] In some preferred embodiments of the present invention, the oxygen doping concentration of the oxidized portion of the carbon-doped silicon nitride in S6 is 1×10 20 cm -3 -9×10 21 cm -3 .

[0008] Preferably, the total thickness D0 of the carbon-doped silicon nitride is 30-80 nm, and / or the carbon doping concentration of the carbon-doped silicon nitride is 1×10 18 cm -3 -9×10 19 cm -3 .

[0009] In some preferred embodiments of the present invention, the anti-reflection layer in S5 further includes an inner film layer arranged between the passivation layer and the carbon-doped silicon nitride, and the inner film layer is selected from silicon nitride and / or silicon oxynitride, wherein the thickness of the silicon nitride is 50-100nm, and / or the ratio of the thickness of silicon nitride to that of carbon-doped silicon nitride is 1:(0.3-1.6).

[0010] In some preferred embodiments of the present invention, the passivation layer in S5 comprises at least one film layer selected from the group consisting of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide.

[0011] In some preferred embodiments of the present invention, the passivation layer in S5 comprises a silicon oxide film layer and an aluminum oxide film layer deposited in sequence, the thickness of the silicon oxide film layer is 1-2 nm, and the thickness of the aluminum oxide film layer is 3-10 nm.

[0012] In some preferred embodiments of the present invention, the annealing oxidation conditions in S6 include: introducing a mixed gas containing oxygen and protective gas during annealing, the volume flow ratio of oxygen to protective gas in the mixed gas containing oxygen and protective gas is (0.033-0.30):1, and the flow rate of the protective gas is 2000-90000sccm.

[0013] In some preferred embodiments of the present invention, the annealing and oxidation conditions in S6 include: an annealing temperature of 700-950° C., an annealing pressure of 100-800 mbar, and an annealing time of 15-80 min.

[0014] In some preferred embodiments of the present invention, the annealing and oxidation process in S6 includes: controlling the furnace temperature to be 200-700°C, introducing a protective gas to increase the temperature from the furnace temperature to the annealing temperature, and introducing a mixed gas containing oxygen and protective gas when the temperature reaches the set annealing temperature.

[0015] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack of a second tunneling silicon oxide layer and a second doped polysilicon layer.

[0016] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer.

[0017] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic hydrogenated amorphous silicon layer is reduced to 2-5 nm, and the thickness of the second doped silicon layer is reduced to 5-10 nm.

[0018] In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-250°C.

[0019] In some preferred embodiments of the present invention, the cleaning conditions in S7 include: a treatment temperature of 20° C.-30° C., and a cleaning time of 30-300 s.

[0020] In some preferred embodiments of the present invention, the method for manufacturing a back contact battery further comprises: S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S10, depositing a conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0021] In a second aspect, the present invention provides a back contact cell, which is manufactured by the manufacturing method of the back contact cell according to the first aspect, wherein the back contact cell comprises a silicon wafer and a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, wherein the anti-reflection layer comprises carbon-doped silicon nitride, wherein the carbon-doped silicon nitride contained in the anti-reflection layer is at least partially doped with oxygen and the thickness D1 of the oxygen-doped part is 10%-60% of the total thickness D0 of the carbon-doped silicon nitride, and the oxygen doping concentration of the oxygen-doped part of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 .

[0022] In a third aspect, the present invention provides a battery assembly comprising the back-contact battery described in the second aspect.

[0023] Beneficial effects: The present invention adopts the above-mentioned technical scheme, especially performs appropriate partial annealing and oxidation on the carbon-doped silicon nitride of the anti-reflection layer, which not only improves the corrosion resistance of the front anti-reflection layer in subsequent cleaning solutions, but also the coating layer of the second semiconductor opening area on the back and the local velvet peak body silicon in the opening area will undergo oxidation reaction during the annealing and oxidation process, so that the concentration of the S7 cleaning solution can be reduced (the HF mass concentration is reduced by 60%-98% compared with the existing process) and the corrosion destructiveness can be greatly reduced, thereby avoiding damage to the first semiconductor layer in the cleaning solution, ensuring the stability of the battery process, and reducing the solution cost; at the same time, the local velvet peak body silicon in the second semiconductor opening area is oxidized in the oxygen of annealing oxidation to form an oxide layer, and the oxide layer will be quickly removed in the subsequent cleaning solution. After removal, the pyramid velvet surface of the second semiconductor opening area will be more rounded and the interface state will be cleaner, which is beneficial to improving the passivation effect of the second semiconductor layer and improving the battery efficiency. Compared with the process of oxygen annealing of the front passivation layer in the prior art, the present invention performs appropriate partial annealing and oxidation on the carbon-doped silicon nitride of the anti-reflection layer, which can make the hydrogen ions in the anti-reflection layer enter the interface between the passivation layer and the silicon wafer, further repair the dangling bonds of the interface, and improve the passivation level of the front film layer; at the same time, during the annealing process, the carbon-doped silicon nitride is partially oxidized and there are non-oxidized parts and oxidized parts, and the corrosion rate is greatly different. After oxidation, the corrosion rate of the oxidized part will be significantly accelerated. Retaining a certain non-oxidized layer can resist solution corrosion, improve the corrosion resistance of the non-oxidized part in the anti-reflection layer, improve its corrosion resistance in the solution, and help improve the performance of the battery and the stability of the process. Under the same conditions, if the carbon-doped silicon nitride is replaced by silicon nitride or silicon oxynitride, considering the light absorption effect, the refractive index of the silicon nitride or silicon oxynitride of the outer layer is small, then the difference in its corrosion rate between oxygen and non-oxidized is not obvious, and both are easily corroded, so it is not easy to control the retained thickness and cannot resist solution corrosion.

[0024] Among them, the present invention specifically controls the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride, which is beneficial to the full oxidation of the second semiconductor opening area on the back side, and further beneficial to improving the passivation effect of the second semiconductor layer. At the same time, in the subsequent cleaning process, the carbon-doped silicon nitride of the front anti-reflection layer can be at least partially retained, playing the best anti-reflection role, thereby improving the battery efficiency.

[0025] In a preferred embodiment of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer. Since the second semiconductor opening area has a good rounded velvet effect and a clean state after oxidation, it is beneficial to the passivation of the intrinsic hydrogenated amorphous silicon layer. The film thickness of the second semiconductor layer can be reduced by 10%-20% compared with the prior art, which is beneficial to reducing the parasitic absorption of the second semiconductor layer and improving the current density of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0028] Figure 2 This is a SEM image of the unoxidized sharp velvet surface of the back pyramid velvet in one embodiment of the present invention.

[0029] Figure 3 This is a SEM picture of the rounded pyramid velvet surface on the back side after annealing and oxidation in one embodiment of the present invention.

[0030] Description of Reference Numerals Silicon wafer 1, first tunneling silicon oxide layer 2, N-type doped polysilicon layer 3, passivation layer 5, silicon nitride 6.1, carbon-doped silicon nitride 6.2, intrinsic hydrogenated amorphous silicon layer 7, P-type doped amorphous silicon layer 8, transparent conductive film layer 9, metal electrode 10. Second semiconductor opening region W2, first semiconductor opening region W1, isolation trench W3. DETAILED DESCRIPTION

[0031] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0032] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0033] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0034] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0035] In a first aspect, the present invention provides a method for manufacturing a back contact battery, comprising the following steps: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, forming a texture surface at least on the second semiconductor opening region by texturing and cleaning, and then performing or not performing a step of removing the mask layer; S5, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer; the anti-reflection layer comprises carbon-doped silicon nitride; S6, then performing annealing oxidation to oxidize at least part of the anti-reflection layer, and during the annealing oxidation process, controlling the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride; S7, removing the back side coating, and then using a HF-containing solution to clean the second semiconductor opening region; the mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%; S8. Depositing a second semiconductor layer on the back side.

[0036] During the annealing and oxidation process, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer is controlled to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride. For example, it can be 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 25%, 27%, 30%, 32%, 35%, 37%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, 59%, 60% and the range between any two point values. In some specific embodiments, it can be preferably 10%-55%, and more preferably 18%-55%.

[0037] The thickness of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer of the present invention is obtained by testing the thickness change of the film layer before and after etching in an HF solution of S7.

[0038] The mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%, for example, it can be 0.1%, 0.2%, 0.5%, 0.7%, 1.0%, 1.2%, 1.5%, 1.7%, 1.9%, 2% and the range between any two points.

[0039] The texturing cleaning in S4 of the present invention can also form a texturing surface on the front side of the silicon wafer. The mask layer can be removed or not in S4, which can be selected according to actual needs. The method of removing the mask layer can refer to the prior art and will not be repeated here.

[0040] In the present invention, the carbon-doped silicon nitride is the corresponding film layer of the outermost layer of the anti-reflection layer. The total thickness of the carbon-doped silicon nitride refers to the thickness of the carbon-doped silicon nitride formed in S5.

[0041] Preferably, the oxygen doping concentration of the oxidized portion of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 The use of partially carbon-doped silicon nitride with an appropriate oxygen doping concentration is more conducive to ensuring sufficient oxygen content so that both the front and back sides are fully oxidized.

[0042] Further preferably, the total thickness D0 of the carbon-doped silicon nitride is 30-80 nm, for example, it can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm and the range between any two point values, for example, 30-70 nm can be preferred.

[0043] In the present invention, the carbon doping concentration of carbon-doped silicon nitride is preferably 1×10 18 cm -3 -9×10 19 cm -3 .

[0044] The present invention uses carbon-doped silicon nitride with a suitable thickness and / or a suitable carbon doping concentration, which is more conducive to taking into account both corrosion resistance and optical properties.

[0045] In some preferred embodiments of the present invention, the anti-reflection layer in S5 further comprises an inner film layer disposed between the passivation layer and the carbon-doped silicon nitride, the inner film layer being selected from silicon nitride and / or silicon oxynitride. The inner film layer may be a single film layer or a stacked layer comprising silicon nitride and silicon oxynitride.

[0046] Further preferably, the thickness of the inner film layer is 50-100 nm.

[0047] Further preferably, the thickness ratio of the inner film layer to the carbon-doped silicon nitride is 1:(0.3-1.6), preferably 1:(0.3-1.2). Using a combination of silicon nitride and carbon-doped silicon nitride with a suitable thickness ratio as the anti-reflection layer is more conducive to improving the current density of the battery.

[0048] In some preferred embodiments of the present invention, the passivation layer in S5 comprises at least one film layer selected from the group consisting of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide.

[0049] In some preferred embodiments of the present invention, the passivation layer in S5 comprises a silicon oxide film layer and an aluminum oxide film layer deposited in sequence. Further preferably, the thickness of the silicon oxide film layer is 1-2 nm, and the thickness of the aluminum oxide film layer is 3-10 nm. The preferred combination of the silicon oxide film layer and the aluminum oxide film layer of the present invention is used as the passivation layer, which is more conducive to improving the passivation level of the battery.

[0050] In some preferred embodiments of the present invention, the annealing and oxidation conditions in S6 include: a mixed gas containing oxygen and protective gas is introduced during annealing, and the volume flow ratio of oxygen to protective gas in the mixed gas containing oxygen and protective gas is (0.033-0.30): 1, preferably (0.10-0.30): 1. The use of oxygen and protective gas with a suitable low flow ratio is more conducive to controlling the uniformity of annealing and oxidation.

[0051] More preferably, the flow rate of the protective gas is 2000-90000 sccm. The protective gas may be, for example, an inert gas such as argon or helium, or a protective gas that does not participate in the reaction such as nitrogen.

[0052] In some preferred embodiments of the present invention, the annealing and oxidation conditions in S6 include: an annealing temperature of 700-950° C. and an annealing time of 15-80 min.

[0053] In some preferred embodiments of the present invention, the annealing and oxidation conditions in S6 include: the annealing pressure is 100-800 mbar.

[0054] In some preferred embodiments of the present invention, the annealing oxidation process in S6 includes: controlling the furnace temperature to be 200-700°C, introducing a protective gas to increase the temperature from the furnace temperature to the annealing temperature, and introducing a mixed gas containing oxygen and protective gas when the temperature reaches the set annealing temperature. The furnace temperature refers to the temperature of the furnace body when entering the furnace.

[0055] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack of a second tunneling silicon oxide layer and a second doped polysilicon layer. The thickness of the second doped polysilicon layer can be, for example, 10-90 nm.

[0056] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer. The thickness of the first tunneling silicon oxide layer and the first doped polysilicon layer and their corresponding doping concentrations can refer to the corresponding ranges of the prior art, and can be used in the present invention. For example, the thickness of the first tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 80-150 nm, and the effective doping concentration is 1×10 19 cm -3 -9×10 20 cm -3 .

[0057] One of the first doped polysilicon layer and the second doped silicon layer or the second doped polysilicon layer in the second semiconductor layer is N-type and the other is P-type. The second doped silicon layer may be, for example, amorphous silicon or microcrystalline silicon doped accordingly. The effective doping concentration of the second doped silicon layer or the second doped polysilicon layer may refer to the range of the prior art, for example, the effective doping concentration may be 1×10 18 cm -3 -9×10 19 cm -3 .

[0058] In the present invention, the thickness of the mask layer may be, for example, 50-100 nm, and the type of the mask layer may be, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, or nitrogen-containing polysilicon.

[0059] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer. The use of a jointly passivated semiconductor layer in conjunction with the manufacturing method of the present invention is more conducive to improving the conversion efficiency of the battery.

[0060] Further preferably, the thickness of the intrinsic hydrogenated amorphous silicon layer is reduced to 2-5 nm, and the thickness of the second doped silicon layer is reduced to 5-10 nm. The present invention can ensure the efficiency of the battery and the stability of its battery process while using a thinner second semiconductor layer, while reducing the parasitic absorption of the second semiconductor layer, which is conducive to improving the current density of the battery.

[0061] The second semiconductor layer can be formed by referring to the prior art method, for example, it can be deposited by plate CVD method, which can be used in the present invention. In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-250° C. The present invention can deposit the second semiconductor layer at a lower temperature, which is more conducive to improving the passivation effect of the second semiconductor layer.

[0062] The method of removing the back winding coating in S7 of the present invention can refer to the prior art. For example, HF acid solution can be used to remove the back winding coating. The removal conditions are: temperature of 20-50°C and time of 15-300s. As long as the target winding coating is removed, it can be used.

[0063] In some preferred embodiments of the present invention, the cleaning conditions in S7 include: a treatment temperature of 20° C.-30° C., and a cleaning time of 30-300 s.

[0064] The manufacturing method of the present invention may also include other conventional steps. In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes: S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S10, depositing a conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0065] In a second aspect, the present invention provides a back-contact battery, which is manufactured by the method for manufacturing a back-contact battery according to the first aspect.

[0066] The back contact cell of the present invention comprises a silicon wafer and a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, the anti-reflection layer comprises carbon-doped silicon nitride, the carbon-doped silicon nitride contained in the anti-reflection layer is at least partially doped with oxygen, and the thickness D1 of the oxygen-doped part is 10%-60% of the total thickness D0 of the carbon-doped silicon nitride. The oxygen-doped anti-reflection layer of the present invention can reduce the concentration of the cleaning solution used for cleaning the second semiconductor opening area on the back side during manufacturing (HF mass concentration is reduced by 60%-98% compared with the existing process) and greatly reduce the corrosion damage, thereby avoiding damage to the first semiconductor layer in the cleaning solution, ensuring higher battery efficiency and battery process stability.

[0067] Preferably, the oxygen doping concentration of the oxygen-doped portion of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 .

[0068] Preferably, the back contact cell of the present invention further comprises a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer. Both ends of the second semiconductor layer extend outwards to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region not covering the second semiconductor layer is provided on the back side of the first semiconductor layer, and a second semiconductor opening region is formed between adjacent first semiconductor layers, and the second semiconductor opening region is arranged at intervals from the first semiconductor opening region and the region between them is a spacing region; in the spacing region, a mask layer is provided between the first semiconductor layer and the second semiconductor layer or no mask layer is provided.

[0069] Preferably, in the present invention, the back-contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is provided on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0070] In a third aspect, the present invention provides a battery assembly, comprising the back-contact battery described in the second aspect. The battery assembly can be any form of assembly such as a battery module containing the back-contact battery of the present invention.

[0071] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0072] Example 1 A back contact battery, such as Figure 1 As shown, the manufacturing method is as follows: S1, double-sided polishing and cleaning of silicon wafer 1 (N-type single crystal silicon wafer); S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer 1: The first semiconductor layer includes a first tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3 (i.e., a first doped polysilicon layer). The mask layer is silicon nitride and has a thickness of 70 nm. The first tunneling silicon oxide layer 2 has a thickness of 1.5 nm, and the N-type doped polysilicon layer 3 has a thickness of 120 nm and an effective doping concentration of 2×10 20 cm -3 .

[0073] S3, etching an opening on the back side of the silicon wafer 1 for the first time to form a second semiconductor opening region W2; S4, performing texturing and cleaning on the second semiconductor opening area W2 on the front and back sides of the silicon wafer 1, and during the texturing and cleaning process, the mask layer on the back side of the silicon wafer 1 is also removed by the final cleaning solution; S5, forming a passivation layer 5 and an anti-reflection layer on the front side of the silicon wafer 1 in sequence: The passivation layer 5 is a combination of a silicon oxide film layer and an aluminum oxide film layer deposited in sequence, the thickness of the silicon oxide film layer is 1.5 nm, and the thickness of the aluminum oxide film layer is 6 nm; The anti-reflection layer is a stacked combination of silicon nitride 6.1 and carbon-doped silicon nitride 6.2 deposited in sequence, wherein the thickness of silicon nitride 6.1 is 60 nm, the thickness D0 of carbon-doped silicon nitride 6.2 is 60 nm, and the carbon doping concentration is 5.6×10 19 cm -3 ; After conversion, the thickness ratio of silicon nitride 6.1 and carbon-doped silicon nitride 6.2 is 1:1.

[0074] S6, then annealing and oxidation: The annealing temperature is 800°C. The gas introduced during annealing is a mixed gas containing oxygen and nitrogen, wherein the flow ratio of oxygen to nitrogen is 0.15:1, the flow rate of nitrogen is 10000sccm, and the annealing pressure is 500mbar. The furnace temperature during annealing is 600°C. When the temperature rises from the furnace temperature to the annealing temperature, nitrogen is introduced to increase the temperature. When the temperature reaches the set temperature for annealing, a mixed gas containing oxygen and nitrogen is introduced again. The annealing time is 30 minutes. During annealing, the thickness D1 of the oxidized part of the top carbon-doped silicon nitride 6.2 on the front side is controlled to be 20% of the total thickness D0 of the top carbon-doped silicon nitride 6.2. The oxygen doping concentration of the oxidized part of the top carbon-doped silicon nitride 6.2 is 1.3×10 20 cm -3 After annealing and oxidation, the texture of the second semiconductor opening region W2 is as follows: Figure 3 As shown, compared with the unoxidized Figure 2 , more rounded; S7, removing the back side coating, and then cleaning the second semiconductor opening area W2; wherein, the second semiconductor opening area W2 is cleaned with an HF solution, the mass concentration of HF in the HF solution is 2%, the remainder is deionized water, the treatment temperature is 25°C, and the cleaning time is 100s; S8. Deposit a second semiconductor layer on the back of the silicon wafer 1 by plate CVD at a deposition temperature of 230°C. The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer 7 and a P-type doped amorphous silicon layer 8 (i.e., a second doped silicon layer). The thickness of the intrinsic hydrogenated amorphous silicon layer 7 is 5 nm, the thickness of the P-type doped amorphous silicon layer 8 is 10 nm, and the effective doping concentration is 1.4×10 19 cm -3 .

[0075] S9, performing a second etching opening on the second semiconductor layer on the back side of the silicon wafer 1 to form a first semiconductor opening region W1; S10, depositing a transparent conductive film layer 9 (ITO) on the back side of the silicon wafer 1; S11, performing a third etching opening on the transparent conductive film layer 9 on the back side of the silicon wafer 1 to form an isolation groove W3; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0076] S12 , forming metal electrodes 10 on the corresponding outer surfaces of the first semiconductor opening region W1 and the second semiconductor opening region W2 on the back side of the silicon wafer 1 .

[0077] Example 2 The process is carried out with reference to Example 1, except that during the annealing and oxidation process of S6, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer is controlled so that the thickness D1 is 60% of the total thickness D0 of the carbon-doped silicon nitride. The process parameters that need to be adjusted to meet this condition are: extending the annealing and oxidation time to 65 minutes.

[0078] Example 3 The method is carried out in accordance with Example 1, except that the total deposition thickness D0 of the S5 carbon-doped silicon nitride is adjusted to 80 nm, the thickness of the oxidized portion remains unchanged, and the thickness ratio of silicon nitride to carbon-doped silicon nitride is calculated to be 1:1.33. The process parameters that need to be adjusted to meet the thickness condition are: extending the coating time by 25%.

[0079] Example 4 The method was carried out in accordance with Example 1, except that the flow rate of methane during the deposition of S5-doped carbonitride was adjusted to make the carbon doping concentration 8.2×10 19 cm -3 .

[0080] Example 5 The method is carried out in accordance with Example 1, except that the oxygen flow rate in the annealing oxidation is adjusted so that the volume flow ratio of oxygen to nitrogen is 0.09:1. In this case, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer is controlled during the annealing oxidation process so that the thickness D1 is 12% of the total thickness D0 of the carbon-doped silicon nitride, and the oxygen doping concentration of the oxidized portion of the carbon-doped silicon nitride is 1.3×10 20 cm -3 .

[0081] Example 6 The method is carried out in accordance with Example 1, except that the second semiconductor layer is adjusted to be a second tunneling silicon oxide layer with a thickness of 1.2 nm and a second tunneling silicon oxide layer with a thickness of 50 nm and a boron doping concentration of 1.9×10 19 cm -3 A stack of P-type doped polysilicon layers.

[0082] Comparative Example 1 The method is carried out in accordance with Example 1, except that the annealing oxidation of S6 is not performed, and the unoxidized suede surface of the second semiconductor opening region is as follows: Figure 2 As shown; and the mass concentration of HF in the HF solution in S7 is 10%.

[0083] Comparative Example 2 The process is carried out in accordance with Example 1, except that in the annealing oxidation process of S6, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer is controlled to be 85% of the total thickness D0 of the carbon-doped silicon nitride. The process parameters that need to be adjusted to meet this condition are: extending the oxidation time to 122 min.

[0084] Comparative Example 3 The process is carried out with reference to Example 1, except that the timing of introducing the annealing oxidation is different. Specifically, the annealing oxidation of S6 is carried out after forming the passivation layer, and then the anti-reflection layer is deposited.

[0085] Test Case The back contact cells obtained in the above-mentioned embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. Among them, the various performance indicators of each embodiment and comparative example were converted with embodiment 1 as the reference benchmark, and the data of embodiment 1 was normalized to 1.000. Other examples were converted based on embodiment 1, such as the anti-reflection layer thickness uniformity of comparative example 1 / the anti-reflection layer thickness uniformity of embodiment 1 was 3.619. Among them, the test method for the uniformity of the anti-reflection layer thickness is: the film thickness of any silicon wafer is tested at 5 locations (four locations around the silicon wafer and a total of five locations at the center) by an ellipsometer, and the uniformity test value = (maximum film thickness-minimum film thickness) / (maximum film thickness+minimum film thickness). The smaller the test value of the anti-reflection layer thickness uniformity, the better its uniformity and the more stable the battery process.

[0086] Table 1

[0087] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can obtain an anti-reflection layer with a more uniform thickness, which is beneficial to ensure the stability of the battery process and reduce the solution cost; at the same time, it is beneficial to improve the passivation effect of the second semiconductor layer and improve the battery efficiency.

[0088] Furthermore, according to Example 1 and Examples 2-6, it can be seen that the adoption of the preferred solution of the present invention is more conducive to improving the battery efficiency and the stability of the battery manufacturing process.

[0089] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for manufacturing a back contact battery, characterized in that: The steps include: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, forming a texture surface at least on the second semiconductor opening region by texturing and cleaning, and then performing or not performing a step of removing the mask layer; S5, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer, wherein the anti-reflection layer comprises carbon-doped silicon nitride; S6, then performing annealing oxidation to oxidize at least part of the anti-reflection layer, and during the annealing oxidation process, controlling the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride; S7, removing the back side coating, and then using a HF-containing solution to clean the second semiconductor opening area; The mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%; S8. Depositing a second semiconductor layer on the back side.

2. The method for manufacturing a back contact battery according to claim 1, characterized in that: The oxygen doping concentration of the oxidized part of the carbon-doped silicon nitride in S6 is 1×10 20 cm -3 -9×10 21 cm -3 and / or, The total thickness D0 of the carbon-doped silicon nitride in S5 is 30-80 nm; and / or, The carbon doping concentration of carbon-doped silicon nitride in S5 is 1×10 18 cm -3 -9×10 19 cm -3 .

3. The method for manufacturing a back contact battery according to claim 2, characterized in that: The anti-reflection layer in S5 further comprises an inner film layer disposed between the passivation layer and the carbon-doped silicon nitride, wherein the inner film layer is selected from silicon nitride and / or silicon oxynitride, wherein: The thickness of the inner film layer is 50-100 nm, and / or the ratio of the thickness of the inner film layer to that of the carbon-doped silicon nitride is 1:(0.3-1.6).

4. The method for manufacturing a back contact battery according to any one of claims 1 to 3, characterized in that: The passivation layer in S5 includes at least one film layer selected from amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide.

5. The method for manufacturing a back contact battery according to claim 4, characterized in that: The passivation layer in S5 includes a silicon oxide film layer and an aluminum oxide film layer deposited in sequence, wherein the thickness of the silicon oxide film layer is 1-2 nm, and the thickness of the aluminum oxide film layer is 3-10 nm.

6. The method for manufacturing a back contact battery according to any one of claims 1 to 3, characterized in that: The annealing and oxidation conditions in S6 include: during annealing, a mixed gas containing oxygen and protective gas is introduced, the volume flow ratio of oxygen and protective gas in the mixed gas containing oxygen and protective gas is (0.033-0.30): 1, and the flow rate of the protective gas is 2000-90000 sccm; and / or, The annealing and oxidation conditions in S6 include: annealing temperature of 700-950° C., annealing pressure of 100-800 mbar, and annealing time of 15-80 min.

7. The method for manufacturing a back contact battery according to claim 1, characterized in that: The annealing and oxidation process in S6 includes: controlling the furnace temperature to be 200-700°C, introducing a protective gas to increase the temperature from the furnace temperature to the annealing temperature, and introducing a mixed gas containing oxygen and protective gas when the temperature reaches the set annealing temperature.

8. The method for manufacturing a back contact battery according to claim 1, characterized in that: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack of a second tunneling silicon oxide layer and a second doped polysilicon layer; And / or, the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic hydrogenated amorphous silicon layer is reduced to 2-5 nm, and the thickness of the second doped silicon layer is reduced to 5-10 nm; And / or, the deposition temperature of the second semiconductor layer is 150-250°C.

10. The method for manufacturing a back contact battery according to claim 1, characterized in that: The cleaning conditions in S7 include: a treatment temperature of 20°C-30°C and a cleaning time of 30-300s; And / or, the method for manufacturing a back contact battery further comprises: S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S10, depositing a conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

11. A back contact battery, characterized in that: The back contact cell is made by the manufacturing method of any one of claims 1 to 10, wherein the back contact cell comprises a silicon wafer and a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, the anti-reflection layer comprises carbon-doped silicon nitride, the carbon-doped silicon nitride contained in the anti-reflection layer is at least partially doped with oxygen, and the thickness D1 of the oxygen-doped part is 10%-60% of the total thickness D0 of the carbon-doped silicon nitride, and the oxygen doping concentration of the oxygen-doped part of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 .

12. A battery assembly, characterized in that: Comprising a back contact cell as claimed in claim 11.

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