Solar cell, photovoltaic module and preparation method of solar cell

Abstract

The invention provides a solar cell, a photovoltaic module and a preparation method of the solar cell. The solar cell includes a substrate having a first surface and a second surface disposed opposite to each other in a thickness direction; the tunneling layer is arranged on the first surface; the polycrystalline silicon doping layer is arranged on one side, away from the substrate, of the tunneling layer; and the conductive layer is arranged on one side, deviating from the substrate, of the polycrystalline silicon doping layer. According to the invention, while passivation is ensured, electrical contact is improved, parasitic absorption is reduced, contact resistance is reduced, and battery efficiency is improved to the greatest extent.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a method for preparing the solar cell. Background Art

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that convert sunlight directly into electrical energy. As they are green and environmentally friendly products that do not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In the related technology, the tunnel oxide layer passivation contact cell is a solar cell based on the principle of selective carriers. It has an N-type silicon substrate cell structure, and forms a passivation contact structure by preparing an ultra-thin silicon oxide tunnel layer on the back of the cell and depositing a doped polysilicon layer, which effectively reduces surface recombination and metal contact recombination, thereby improving the conversion efficiency of the cell.

[0004] However, the above-mentioned tunnel oxide layer passivation contact cell has the problem of not being able to achieve the desired passivation effect while reducing parasitic absorption. Summary of the invention

[0005] The embodiments of the present application provide a solar cell, a photovoltaic module and a method for preparing the solar cell, which can better achieve the passivation effect while reducing parasitic absorption and improving battery efficiency.

[0006] In a first aspect, an embodiment of the present application provides a solar cell, comprising:

[0007] A substrate having a first surface and a second surface arranged opposite to each other in a thickness direction;

[0008] A tunneling layer, disposed on the first surface;

[0009] a polysilicon doped layer, disposed on a side of the tunneling layer away from the substrate; and

[0010] The conductive layer is arranged on a side of the polysilicon doped layer away from the substrate.

[0011] In one embodiment, the thickness of the polysilicon doped layer ranges from 30 nm to 100 nm.

[0012] In one embodiment, the polysilicon doping layer is doped with phosphorus, and the doping concentration of the phosphorus is in the range of 10 18 cm -3 -10 22 cm -3 .

[0013] In one embodiment, the thickness of the conductive layer ranges from 30 nm to 100 nm.

[0014] In one of the embodiments, the conductive layer includes graphene or transparent conductive oxide.

[0015] In one embodiment, the conductive layer is a whole layer structure;

[0016] The orthographic projection of the conductive layer on the substrate covers the orthographic projection of the polysilicon doped layer on the substrate.

[0017] In one of the embodiments, the conductive layer includes a plurality of discontinuous structures;

[0018] Along a direction perpendicular to the thickness direction of the substrate, a plurality of discontinuous structures are arranged at intervals.

[0019] In one of the embodiments, it further includes a first passivation layer and a first electrode, wherein the first passivation layer is disposed on a side of the conductive layer facing away from the substrate;

[0020] The first electrode is disposed on the first passivation layer and is electrically connected to the conductive layer.

[0021] In one embodiment, the invention further comprises an emitter, a second electrode and a second passivation layer, wherein the emitter is arranged on the second surface, and the second passivation layer is arranged on a side of the emitter away from the substrate;

[0022] The second electrode is disposed on the second passivation layer and is electrically connected to the emitter.

[0023] In one embodiment, the thickness of the substrate is in the range of 100-150 μm; and / or the thickness of the emitter is in the range of 0.1-2 μm; and / or the thickness of the tunneling layer is in the range of 0.5-2 nm.

[0024] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell, the method comprising:

[0025] Providing a substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other in a thickness direction;

[0026] forming a tunneling layer and a polysilicon doped layer stacked on each other on the first surface, wherein the polysilicon doped layer is located on a side of the tunneling layer away from the substrate;

[0027] A conductive layer is formed on a side of the polysilicon doped layer facing away from the substrate.

[0028] In one embodiment, before the step of forming a tunneling layer and a polysilicon doping layer stacked on each other on the first surface, the step further includes:

[0029] forming a suede structure on the first surface and the second surface respectively;

[0030] Forming emitter materials on the first surface and the second surface after the texture treatment respectively;

[0031] The substrate on the first surface is etched to remove the emitter material plated around one side of the first surface and the side surface of the substrate, so as to form an emitter on the second surface.

[0032] In one embodiment, forming a polysilicon doped layer includes:

[0033] A tunneling material layer and a phosphorus-doped amorphous silicon material layer are sequentially stacked on the first surface;

[0034] Annealing the amorphous silicon material layer to form a polycrystalline silicon material layer;

[0035] The amorphous silicon material layer and the tunneling material layer deposited on one side of the second surface of the substrate are removed to form the tunneling layer and the polysilicon doped layer on the first surface.

[0036] In one embodiment, forming a conductive layer includes:

[0037] A whole layer of conductive material is formed on the side of the polysilicon doped layer facing away from the substrate, and the conductive material layer plated around one side of the second surface and the side surface of the substrate is removed to form the conductive layer, the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the polysilicon doped layer on the substrate.

[0038] In one embodiment, forming a conductive layer includes:

[0039] forming a whole conductive material layer on a side of the polysilicon doped layer away from the substrate;

[0040] The conductive material layer plated around one side of the second surface and the side surface of the substrate is removed, and the conductive material layer in the non-electrode pattern area on one side of the first surface is removed to form a plurality of discontinuous structures, and the plurality of discontinuous structures are arranged at intervals along a direction perpendicular to the thickness direction of the substrate.

[0041] In one embodiment, the preparation method further comprises:

[0042] A first passivation layer is formed on the polysilicon doped layer and the conductive layer in the electrode contact area.

[0043] A second passivation layer is formed on a side of the emitter facing away from the substrate.

[0044] In one embodiment, the preparation method further comprises:

[0045] forming a first electrode on the first passivation layer, wherein the first electrode is electrically connected to the conductive layer;

[0046] A second electrode is formed on the second passivation layer, and the second electrode is electrically connected to the emitter.

[0047] In a third aspect, an embodiment of the present application provides a photovoltaic component, including a solar cell.

[0048] The solar cell, photovoltaic module and the method for preparing the solar cell provided by the embodiment of the present application include a polysilicon doped layer and a conductive layer, and the conductive layer is arranged on the side of the polysilicon doped layer away from the substrate. In this way, on the one hand, the present application helps to reduce the thickness of the polysilicon doped layer, thereby avoiding the problem that an overly thick polysilicon doped layer will introduce more impurities and defect energy levels, resulting in large parasitic absorption; on the other hand, by setting a conductive layer, the present application helps to avoid the difficulty of achieving high-concentration doping in an overly thin polysilicon doped layer, thereby reducing the problem of penetration during the diffusion process, and is also conducive to ensuring contact with the metal electrode and reducing contact resistance; on the other hand, the conductive layer has almost no absorption of light in the near-infrared band, and the parasitic absorption is small. Therefore, while ensuring passivation, the present application helps to improve electrical contact, reduce parasitic absorption and reduce contact resistance, thereby maximizing battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 A schematic diagram of the structure of a solar cell provided in an embodiment of the present application;

[0051] Figure 2 Another schematic diagram of the structure of a solar cell provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of the process of preparing a solar cell provided in an embodiment of the present application.

[0053] Reference numerals:

[0054] 100, solar cell; 110, substrate; 111, first surface; 112, second surface; 120, tunneling layer; 130, polysilicon doped layer; 140, conductive layer; 141, discontinuous structure; 150, first passivation layer; 160, first electrode; 170, emitter; 180, second electrode; 190, second passivation layer. DETAILED DESCRIPTION

[0055] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0056] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0057] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0058] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0059] In the related art, a tunneling oxide layer passivated contact cell includes an N-type silicon substrate, a silicon oxide tunneling layer and a doped polysilicon layer are arranged on the side of the N-type silicon substrate close to the backlight surface of the cell, and the silicon oxide tunneling layer is located between the doped polysilicon layer and the N-type silicon substrate.

[0060] However, the current thickness of the doped polysilicon layer is about 100nm or more. An overly thick doped polysilicon layer will introduce more impurities, such as metal ions, oxygen, carbon, etc. These impurities form energy levels in the material. When the energy of the incident light matches these energy levels, it will be absorbed by the impurities, resulting in greater parasitic absorption, reducing the number of photons reaching the effective area, causing optical losses, and affecting the efficiency improvement of the battery. If the thickness of the doped polysilicon layer is reduced, the thinned doped polysilicon layer is not conducive to achieving a high doping concentration, and will face the problem of doped polysilicon layer expansion, causing serious leakage of the battery. At the same time, the low doping concentration will increase the contact resistance at the connection with the back electrode after metallization.

[0061] To solve the above problems, the embodiments of the present application provide a method for preparing a solar cell, a photovoltaic module and a solar cell thereof, which helps to improve electrical contact, reduce parasitic absorption and reduce contact resistance while ensuring passivation, thereby maximizing battery efficiency.

[0062] The specific structure of the solar cell provided in the embodiment of the present application will be described below with reference to the drawings.

[0063] The embodiment of the present application provides a solar cell 100 , and the solar cell 100 may be a tunnel oxide passivating contact cell (TOPCON for short) or the like.

[0064] Reference Figure 1 and Figure 2 As shown, the solar cell 100 includes a substrate 110, wherein the substrate 110 can provide support for the film layers to be formed subsequently. The substrate 110 can be used to receive incident light and generate photogenerated carriers.

[0065] For example, refer to Figure 1 and Figure 2 As shown, the substrate 110 may have a thickness in the thickness direction (ie Figure 1 and Figure 2 The solar cell 100 includes a first surface 111 and a second surface 112 that are relatively arranged in a direction Z in the solar cell 100, and at least one of the first surface 111 and the second surface 112 can be used to receive sunlight. In the embodiment of the present application, the second surface 112 is used to receive sunlight as an example, that is, the second surface 112 is close to the light-facing surface of the solar cell 100, and the first surface 111 is close to the backlight surface of the solar cell 100.

[0066] For example, the substrate 110 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon and polycrystalline silicon. The present application embodiment is described by taking single crystal silicon as an example.

[0067] Exemplarily, the doping type of the substrate 110 may be N-type doping, which may be achieved by doping N-type ions, and the N-type ions may include at least one of phosphorus, arsenic, and antimony. Alternatively, the doping type of the substrate 110 may be P-type doping, which may be achieved by doping P-type ions, and the P-type ions may include at least one of aluminum and boron. The embodiment of the present application is described by taking the doping type of the substrate 110 as N-type doping as an example.

[0068] In some embodiments, at least one of the first surface 111 and the second surface 112 may have a velvet structure. The velvet structure may be a pyramid velvet, an etched pit velvet, etc. The velvet structure has a lower reflectivity to incident light, and thus has a higher absorption rate to incident light, so that the photoelectric conversion efficiency of the solar cell 100 is higher.

[0069] Exemplarily, the thickness of the substrate 110 may be in the range of 100-150 μm, for example, the thickness of the substrate 110 may be set to 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm or any value between 100-150 μm according to actual needs, which is not limited in this embodiment.

[0070] In this way, on the one hand, the problem that the thickness of the substrate 110 is less than 100μm and is too thin, resulting in insufficient absorption of sunlight and reduced photoelectric conversion efficiency can be avoided. At the same time, it is helpful to avoid the problem that the battery thickness is too thin, resulting in voltage drop and overall battery performance degradation, and it helps to improve the structural stability of the battery. On the other hand, it can avoid the problem that an overly thick battery cannot allow sunlight to penetrate to the bottom well, reducing light absorption and conversion efficiency, and it can also avoid the problem that an overly thick battery will cause the internal temperature to rise, resulting in battery failure or damage.

[0071] Continue to refer to Figure 1 and Figure 2 As shown, the solar cell 100 includes a tunneling layer 120, which is arranged on the first surface 111. The majority carriers (electrons) can pass through the tunneling layer 120 through the tunneling effect. The tunneling layer 120 can also block minority carriers (holes), thereby achieving selective collection of carriers, preventing electrons and holes from recombining, reducing surface recombination efficiency, and improving open circuit voltage.

[0072] Exemplarily, the material of the tunneling layer 120 may be a dielectric material, such as at least one of silicon oxide, magnesium fluoride, silicon oxide, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide.

[0073] Exemplarily, the thickness of the tunneling layer 120 may range from 0.5 to 2 nm. For example, the thickness of the tunneling layer 120 may be set to 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.5 nm, 1.8 nm, 2 nm, or any value between 0.5 and 2 nm according to actual needs. This embodiment does not limit this.

[0074] In this way, on the one hand, the tunneling layer 120 can be prevented from being too thin, less than 0.5 nm, so as to improve the tunneling effect of the tunneling layer 120. On the other hand, by setting the thickness of the tunneling layer 120 to not more than 2 nm, the thickness of the tunneling layer 120 is small, and the energy band barrier between the tunneling layer 120 and the substrate 110 can be ignored, which is beneficial to the transmission of carriers.

[0075] In order to solve the problem of large parasitic absorption and increased contact resistance in the related art, in the embodiment of the present application, reference is made to Figure 1 and Figure 2 As shown, the solar cell 100 includes a polysilicon doped layer 130 and a conductive layer 140 . The polysilicon doped layer 130 is disposed on a side of the tunneling layer 120 away from the substrate 110 , and the conductive layer 140 is disposed on a side of the polysilicon doped layer 130 away from the substrate 110 .

[0076] In this way, during the preparation of the solar cell 100, the polysilicon doping layer 130 can attract impurities in the substrate 110 and impurities introduced during the process into the polysilicon doping layer 130, thereby reducing impurities and defects in the substrate 110. Exemplarily, the doping type of the polysilicon doping layer 130 can be N-type doping.

[0077] In the embodiment of the present application, a polysilicon doped layer 130 is superimposed on a conductive layer 140. In this way, the thickness of the polysilicon doped layer 130 can be thinned, thereby avoiding the problem that an excessively thick polysilicon doped layer 130 will introduce more impurities and defect energy levels, resulting in greater parasitic absorption.

[0078] In addition, by providing the conductive layer 140, on the one hand, it helps to avoid the problem of penetration during the diffusion process due to the difficulty in achieving high-concentration doping in the overly thin polysilicon doping layer 130; on the other hand, it helps to ensure contact with the metal electrode and reduce contact resistance; on the other hand, the conductive layer 140 has almost no absorption of light in the near-infrared band and has low parasitic absorption.

[0079] Therefore, the present application adopts the method of superimposing the polysilicon doped layer 130 with the conductive layer 140, which can reduce the thickness and doping concentration of the polysilicon doped layer 130, so as to achieve the passivation effect while reducing parasitic absorption, improving electrical contact, reducing contact resistance, and maximizing battery efficiency.

[0080] In some embodiments, the thickness of the polysilicon doping layer 130 may range from 30 nm to 100 nm. For example, the thickness of the polysilicon doping layer 130 may be set to 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any value between 30 nm and 100 nm according to actual needs.

[0081] When the thickness of the polysilicon doping layer 130 is less than 30 nm, the thickness of the polysilicon doping layer 130 is too thin. A too thin polysilicon doping layer 130 is not conducive to achieving a high doping concentration because it will face the problem of penetration during the diffusion process, thereby causing serious leakage of the battery; and a low doping concentration will increase the contact resistance after metallization.

[0082] When the thickness of the polysilicon doping layer 130 is greater than 100 nm, the thickness of the polysilicon doping layer 130 is too thick. The excessively thick polysilicon doping layer 130 will introduce more impurities, resulting in more serious parasitic absorption, causing optical loss and affecting the efficiency improvement of the battery.

[0083] Therefore, in this embodiment, by limiting the thickness range of the polysilicon doping layer 130 to between 30-100 nm, it is helpful to reduce the thickness and doping concentration of the polysilicon doping layer 130, so as to achieve the passivation effect while reducing parasitic absorption, improving electrical contact, reducing contact resistance, and maximizing battery efficiency.

[0084] In some embodiments, the thickness of the polysilicon doping layer 130 can range from 40 to 80 nm. For example, the thickness of the polysilicon doping layer 130 can be set to 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or any value between 40 and 80 nm according to actual needs, which is not limited in this embodiment.

[0085] In some embodiments, the polysilicon doping layer 130 may be doped with phosphorus, and the doping concentration of the phosphorus may range from 10 18 cm -3 -10 22 cm -3 .

[0086] Among them, phosphorus is a doping element widely used in semiconductor materials. In the polysilicon doping layer 130, the incorporation of phosphorus enhances the conductivity of the polysilicon doping layer 130. The incorporation of phosphorus can accelerate the movement of electrons in polysilicon, thereby improving its conductivity; at the same time, the incorporation of phosphorus can reduce the energy gap of polysilicon and enhance the range of its absorption spectrum.

[0087] The present embodiment does not limit the doping concentration of phosphorus, which can be selected according to actual needs. 18 cm -3 -10 22 cm -3 In this way, on the one hand, it can be avoided that when the phosphorus doping concentration is too high, the conductivity of the polysilicon doping layer 130 is too strong, which makes the device easy to short-circuit or damage during operation; on the other hand, it can be avoided that when the phosphorus doping concentration is too low, the conductivity of the polysilicon doping layer 130 is insufficient, which affects the working efficiency of the device. Therefore, when the phosphorus doping concentration is moderate, the conductivity of the polysilicon doping layer 130 will be improved, which is conducive to the transmission of current and the performance of the device.

[0088] In some embodiments, the thickness of the conductive layer 140 may range from 30 nm to 100 nm. For example, the thickness of the conductive layer 140 may be set to 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm or any value between 30 nm and 100 nm according to actual needs, which is not limited in this embodiment.

[0089] In this way, on the one hand, it can be avoided that when the thickness of the conductive layer 140 is too thin, the conductivity will be reduced. At the same time, although the single-layer conductive layer has a higher elastic modulus and tensile strength, as the number of layers increases, the multi-layer conductive layer may be more prone to interlayer slip when bent, thereby reducing its overall mechanical properties. On the other hand, it can be avoided that when the thickness of the conductive layer 140 is too thick, the production cost is high. At the same time, it is beneficial to avoid the introduction of impurities and defects in the production process, thereby maximizing the performance and application effect of the conductive layer 140.

[0090] In some embodiments, the conductive layer 140 may include graphene or a transparent conductive oxide.

[0091] Exemplarily, when the material of the conductive layer 140 is graphene, on the one hand, graphene has high electrical conductivity, and plating graphene on the polysilicon doped layer 130 can significantly improve the conductivity of the composite material and reduce the contact resistance with the metal electrode, thereby improving the current transmission efficiency of the electronic device; on the other hand, graphene has high thermal conductivity, and plating graphene on the polysilicon doped layer 130 can effectively improve the heat dissipation performance of the composite material; on the other hand, there are no dangling bonds at the interface of graphene, which can greatly reduce the recombination loss at the interface; on the other hand, graphene has relatively weak absorption of light, which helps to improve the secondary absorption of light and reduce parasitic absorption.

[0092] Exemplarily, the material of the conductive layer 140 may include a transparent conductive oxide, for example, may include at least one of indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium aluminum zinc oxide (GAZO), tin oxide (SnO2), antimony tin oxide (ATO), fluorine tin oxide (FTO), cerium indium oxide (ICO), and aluminum indium oxide (IWO). This embodiment is not limited to this.

[0093] In some embodiments, reference Figure 1 As shown, the conductive layer 140 may be a whole layer structure; wherein the orthographic projection of the conductive layer 140 on the substrate 110 covers the orthographic projection of the polysilicon doped layer 130 on the substrate 110 .

[0094] It should be noted that orthographic projection refers to projecting a structure from a direction perpendicular to the substrate 110 (usually the vertical direction) to obtain a two-dimensional profile of the structure on the plane of the substrate 110. The projection of the conductive layer 140 on the substrate 110 completely covers the projection of the polysilicon doped layer 130 on the substrate 110, that is, the conductive layer 140 is located above the polysilicon doped layer 130 in space, and its area is large enough to completely cover the polysilicon doped layer 130.

[0095] Exemplarily, the conductive layer 140 can be provided as a whole layer, and the polysilicon doped layer 130 can be provided as a whole layer, so that the conductive layer 140 has a larger setting area, which is beneficial to improving the conductive effect of the conductive layer 140; in addition, the conductive layer 140 covers the polysilicon doped layer 130 to ensure good electrical connection, and at the same time helps to prevent the polysilicon doped layer 130 from being affected by the external environment.

[0096] In some embodiments, reference Figure 2 As shown, the conductive layer 140 may include a plurality of discontinuity structures 141 ; along a direction perpendicular to the thickness direction of the substrate 110 , the plurality of discontinuity structures 141 are arranged at intervals.

[0097] For example, refer to Figure 1 As shown, the solar cell 100 may have a first direction X and a second direction Z, wherein the second direction Z may be the thickness direction of the substrate 110, and the first direction X may be any two directions perpendicular to the thickness direction of the substrate 110, for example, the first direction X may be the width direction of the solar cell 100, or may be the length direction of the solar cell 100. The length, width, thickness, etc. in this embodiment are only for the convenience of description and do not mean any limitation on the size. For example, the width may be greater than, equal to, or less than the length. The direction of the solar cell 100 may be consistent with the direction of the film layer such as the substrate 110.

[0098] There is no limitation on the number of discontinuous structures 141. For example, the number of discontinuous structures 141 may be two, three or more. In this embodiment, the conductive layer 140 is mainly described as including two discontinuous structures 141. The two discontinuous structures 141 are arranged at intervals along the first direction X.

[0099] In this way, by setting the conductive layer 140 to multiple discontinuous structures 141 and arranging them at intervals, on the one hand, the overall area of ​​the conductive layer 140 can be reduced, thereby reducing the thermal effect and improving the stability of the device under high current density or high temperature conditions; on the other hand, the discontinuous structures 141 are connected to the metal electrodes respectively. This design can optimize the flexibility and reliability of the electrical connection.

[0100] In some embodiments, reference Figure 1 and Figure 2 As shown, the solar cell 100 includes a first passivation layer 150 and a first electrode 160 . The first passivation layer 150 is disposed on a side of the conductive layer 140 facing away from the substrate 110 . The first electrode 160 is disposed on the first passivation layer 150 and is electrically connected to the conductive layer 140 .

[0101] Exemplarily, the first passivation layer 150 can be a stacked film composed of oxide and nitride, wherein the material of the first passivation layer 150 includes oxide, for example, the material of the first passivation layer 150 includes aluminum oxide, and the surface of the aluminum oxide film facing the substrate 110 has a high fixed negative charge density, and these negative charges can generate a built-in electric field, which can repel electrons (minority carriers) from approaching the first surface 111 of the substrate 110, thereby reducing the recombination of electrons on the surface, and exhibiting good field passivation characteristics.

[0102] Exemplarily, the material of the first passivation layer 150 includes nitride, for example, the material of the first passivation layer 150 includes silicon nitride, and the silicon nitride film can play a hydrogen passivation role. The silicon nitride film contains a large amount of hydrogen, and these hydrogen atoms can diffuse to the first surface 111 of the substrate 110, and combine with the dangling bonds of the first surface 111 to form a stable Si-H bond, thereby reducing the number of dangling bonds of the first surface 111 of the substrate 110, reducing the defects of the first surface 111 of the substrate 110, reducing the interface state density, and reducing the surface recombination of carriers. In addition, the passivation effect of silicon nitride is good, which can improve the passivation effect of the first passivation layer 150, which is conducive to improving the open circuit voltage and improving the efficiency of the solar cell 100.

[0103] The first electrode 160 can collect and transmit photogenerated carriers, thereby realizing the conversion of solar energy into electrical energy. Exemplarily, the material of the first electrode 160 can include metal materials such as silver, copper, titanium, iron, and gold.

[0104] Exemplarily, there may be a plurality of first electrodes 160, and the plurality of first electrodes 160 are arranged at intervals along the first direction X. Thus, the spaced arrangement of the plurality of first electrodes 160 can improve the carrier transmission path, reduce energy loss during transmission, and improve the overall photoelectric conversion efficiency.

[0105] In some embodiments, reference Figure 1 and Figure 2 As shown, the solar cell 100 includes an emitter 170 , a second electrode 180 and a second passivation layer 190 . The emitter 170 is arranged on the second surface 112 , and the second passivation layer 190 is arranged on the side of the emitter 170 facing away from the substrate 110 ; the second electrode 180 is arranged on the second passivation layer 190 and is electrically connected to the emitter 170 .

[0106] Exemplarily, the emitter 170 may be a boron emitter. For example, the emitter 170 may be formed by performing a boron diffusion process on the second surface 112 of the substrate 110. The emitter 170 and the substrate 110 may form a PN junction to achieve conversion of light energy into electrical energy.

[0107] Exemplarily, the thickness of the emitter 170 ranges from 0.1 to 2 μm. For example, the thickness of the emitter 170 can be set to 0.1 μm, 0.2 μm, 0.5 μm, 2 μm or any value between 0.1 and 2 μm according to actual needs, which is not limited in this embodiment.

[0108] Exemplarily, the second passivation layer 190 may be a stacked film composed of oxide and nitride, and its principle is similar to that of the first passivation layer 150 , which will not be described in detail.

[0109] The second electrode 180 can collect and transmit photogenerated carriers, thereby realizing the conversion of solar energy into electrical energy. Exemplarily, the material of the second electrode 180 can include metal materials such as silver, copper, titanium, iron, and gold, which is not limited in this embodiment.

[0110] The photovoltaic module provided in the embodiments of the present application is described below.

[0111] The embodiment of the present application further provides a photovoltaic module, which may include the solar cell 100 in the above embodiment. There may be at least one solar cell 100 in the photovoltaic module. The embodiment of the present application is described by taking the case where there are multiple solar cells 100 in the photovoltaic module as an example, and the multiple solar cells 100 together constitute a battery string layer.

[0112] In some embodiments, the photovoltaic module may include a first encapsulation member and a second encapsulation member located on both sides of the battery string layer, and the first encapsulation member and the second encapsulation member encapsulate the battery string layer to protect the battery string layer. The first encapsulation member and the second encapsulation member may include an encapsulation adhesive layer and a cover plate, the encapsulation adhesive layer is located on the side of the cover plate facing the battery string layer, the cover plate can protect the battery string layer, and the encapsulation adhesive layer can be used to connect the cover plate and the battery string layer.

[0113] The following is an explanation of the method for preparing a solar cell provided in the embodiment of the present application, which can be used to prepare the solar cell in the above embodiment. Figure 3 As shown, the preparation method may include:

[0114] S100: providing a substrate, wherein the substrate has a first surface and a second surface arranged opposite to each other along a thickness direction.

[0115] For example, the thickness of the substrate 110 may be in the range of 100-150 μm.

[0116] S200: forming a tunneling layer and a polysilicon doping layer stacked on each other on a first surface, wherein the polysilicon doping layer is located on a side of the tunneling layer facing away from the substrate.

[0117] Among them, the deposition of the tunneling layer 120 and the polysilicon doped layer 130 is carried out simultaneously to form a mutually stacked structure. On the one hand, the stacked structure can improve the photoelectric conversion efficiency of the solar cell 100, and can reduce parasitic absorption losses, further improving the utilization rate of light; on the other hand, the tunneling layer 120 and the polysilicon doped layer 130 jointly form a passivation contact structure, which can effectively passivate the surface of the silicon wafer and reduce the capture of carriers by the surface, thereby improving the performance of the battery.

[0118] Exemplarily, a tunneling layer 120 and a polysilicon doping layer 130 stacked on each other are deposited on the first surface 111. For example, the deposition process may include an atomic layer deposition process (atomic layer deposition, referred to as ALD), a physical vapor deposition process (physical vapor deposition, referred to as PVD) or a chemical vapor deposition process (chemical vapor deposition, referred to as CVD), etc. Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which will not be described in detail.

[0119] For example, the doping type of the polysilicon doping layer 130 may be N-type doping.

[0120] Exemplarily, the thickness of the polysilicon doping layer 130 can be between 30-100 nm, which helps to reduce the thickness and doping concentration of the polysilicon doping layer 130, so as to achieve the passivation effect while reducing parasitic absorption, improving electrical contact, reducing contact resistance, and maximizing battery efficiency. The thickness of the polysilicon doping layer 130 can be set to 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm or any value between 30-100 nm according to actual needs.

[0121] In this way, during the preparation of the solar cell 100 , the polysilicon doping layer 130 can attract impurities in the substrate 110 and impurities introduced during the process into the polysilicon doping layer 130 , thereby reducing impurities and defects in the substrate 110 .

[0122] S300: forming a conductive layer on a side of the polysilicon doped layer facing away from the substrate.

[0123] Exemplarily, the conductive layer 140 is deposited on the polysilicon doped layer 130 . For example, the conductive layer 140 may be prepared by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

[0124] For example, the conductive layer 140 may include graphene or transparent conductive oxide.

[0125] Exemplarily, the thickness of the conductive layer 140 can be between 30-100 nm. In this way, on the one hand, when the thickness of the conductive layer 140 is too thin, the conductivity will be reduced. At the same time, although the single-layer conductive layer 140 has a high elastic modulus and tensile strength, as the number of layers increases, the multi-layer conductive layer 140 may be more prone to interlayer slip when bent, thereby reducing its overall mechanical properties. On the other hand, when the thickness of the conductive layer 140 is too thick, the problem of high production cost can be avoided. At the same time, it is beneficial to avoid the introduction of impurities and defects in the production process, thereby maximizing the performance and application effect of the conductive layer 140.

[0126] In some embodiments, before the step of forming a tunneling layer and a polysilicon doped layer stacked on the first surface, the method may further include:

[0127] forming a suede structure on the first surface and the second surface respectively;

[0128] Forming emitter materials on the first surface and the second surface after the texture treatment respectively;

[0129] The substrate on the first surface is etched to remove the emitter material plated around one side of the first surface and the side surface of the substrate, so as to form an emitter.

[0130] Exemplarily, at least one of the first surface 111 and the second surface 112 of the substrate 110 may be textured to form a textured structure. Taking the second surface 112 of the substrate 110 as an example, at least a portion of the second surface 112 may be textured.

[0131] For example, the velvet structure can be prepared by wet chemical etching, for example, an alkaline solution can be used for velvet preparation, such as a NaOH solution, or chemical etching, laser etching, mechanical method, plasma etching, etc. can be used to prepare the velvet structure.

[0132] Exemplarily, the first surface 111 and the second surface 112 may be subjected to boron diffusion treatment to form an emitter material. Exemplarily, a chemical etching method may be used to remove the emitter material plated around the side of the first surface 111 and the side of the substrate 110 to form an emitter 170 on the side of the second surface 112. The emitter 170 and the substrate 110 may form a PN junction to achieve conversion of light energy into electrical energy.

[0133] In some embodiments, forming a polysilicon doping layer may include:

[0134] A tunneling material layer and a phosphorus-doped amorphous silicon material layer are sequentially stacked on the first surface;

[0135] Annealing the amorphous silicon material layer to form a polycrystalline silicon material layer;

[0136] The amorphous silicon material layer and the tunnel material layer deposited on one side of the second surface of the substrate are removed to form a tunnel layer and a polysilicon doped layer on the first surface.

[0137] Exemplarily, after forming the stacked tunneling material layer and the phosphorus-doped amorphous silicon material layer, the amorphous silicon material layer is annealed, which is beneficial for attracting impurities in the substrate 110 into the polysilicon material layer under high temperature process conditions.

[0138] For example, the annealing temperature may be between 800-1000° C., and the annealing time may be between 1-3 hours.

[0139] Exemplarily, after annealing the amorphous silicon material layer, the amorphous silicon material layer and the tunneling material layer coated on the second surface 112 of the substrate 110 are removed, so that only the tunneling layer 120 and the polysilicon doped layer 130 are retained on the first surface 111 .

[0140] For example, the amorphous silicon material layer can be removed by wet etching using an alkaline solution, such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) solution. This method can efficiently remove the amorphous silicon material layer while causing less damage to the substrate 110 .

[0141] For example, the tunneling material layer can be removed by etching using an acid solution containing hydrofluoric acid (HF). HF has a strong corrosiveness to silicon oxide and can quickly remove the tunneling layer 120.

[0142] For example, the amorphous silicon material layer and the tunneling material layer may be removed by plasma etching technology; or, for a thicker wrapping layer, a chemical mechanical polishing technology may be used to remove it. This embodiment does not limit this.

[0143] In the embodiment of the present application, forming a conductive layer may include the following two implementation methods.

[0144] In some embodiments, forming a conductive layer may include: forming a whole conductive material layer on the side of the polysilicon doped layer facing away from the substrate, and removing the conductive material layer plated around the second side and the side surface of the substrate to form a conductive layer.

[0145] In this way, by removing the conductive material layer plated on one side of the second surface 112 and the side of the substrate 110, the negative impact of the plated part on the device performance can be avoided. The conductive layer 140 is set as a whole layer, so that the setting area of ​​the conductive layer 140 is larger, which is beneficial to improving the conductive effect of the conductive layer 140.

[0146] The orthographic projection of the conductive layer 140 on the substrate 110 covers the orthographic projection of the polysilicon doped layer 130 on the substrate 110, ensuring good contact between the conductive layer 140 and the polysilicon doped layer 130, while helping to prevent the polysilicon doped layer 130 from being affected by the external environment.

[0147] In some embodiments, forming a conductive layer may include: forming a whole layer of conductive material layer on the side of the polysilicon doped layer facing away from the substrate; removing the conductive material layer plated around the second side and the side of the substrate, and removing the conductive material layer in the non-electrode pattern area on the first side to form a plurality of discontinuous structures, wherein the plurality of discontinuous structures are arranged at intervals along a direction perpendicular to the thickness direction of the substrate.

[0148] For example, the conductive material layer in the non-electrode pattern area on one side of the first surface 111 can be removed by laser. In this way, laser technology can achieve high-precision material removal and can remove only the conductive material layer in the specified area without damaging the underlying base material.

[0149] For example, the conductive material layer plated on one side of the second surface 112 and the side surface of the substrate 110 may be removed by pickling.

[0150] By setting the conductive layer 140 to multiple discontinuous structures 141 and arranging them at intervals, on the one hand, the overall area of ​​the conductive layer 140 can be reduced, thereby reducing the thermal effect and improving the stability of the device under high current density or high temperature conditions; on the other hand, the discontinuous structures 141 are connected to the metal electrodes respectively. This design can optimize the flexibility and reliability of the electrical connection.

[0151] In some embodiments, the preparation method may further include: forming a first passivation layer on the polysilicon doping layer and the conductive layer in the electrode contact region; and forming a second passivation layer on a side of the emitter facing away from the substrate.

[0152] Exemplarily, the materials of the first passivation layer 150 and the second passivation layer 190 may include aluminum oxide or silicon nitride, the principle of which has been explained and will not be repeated. In addition, since aluminum oxide or silicon nitride has a good passivation effect, after removing the polysilicon doped layer 130, aluminum oxide or silicon nitride can be directly passivated, thereby improving the passivation effect of the first passivation layer 150 and the second passivation layer 190, which is conducive to increasing the open circuit voltage.

[0153] In some embodiments, the preparation method may further include: forming a first electrode on the first passivation layer, the first electrode being electrically connected to the conductive layer; and forming a second electrode on the second passivation layer, the second electrode being electrically connected to the emitter.

[0154] Exemplarily, when forming the first electrode 160, it may include forming a first initial electrode on the side of the conductive layer 140 facing away from the substrate 110. For example, the first initial electrode may be formed by screen printing of low-temperature silver paste, and then the first initial electrode may be sintered at low temperature to form the first electrode 160. For example, the temperature of the low-temperature sintering may be 400° C. Since the conductive layer 140 is provided, a low-temperature sintering method may be adopted, and the temperature of the low-temperature sintering is relatively low, which is conducive to reducing the damage of the sintering to the solar cell 100.

[0155] Illustratively, when forming the second electrode 180 , the second initial electrode may be formed by screen printing, and the second initial electrode may be sintered at a high temperature and laser-assisted sintered to form the second electrode 180 .

[0156] Exemplarily, the preparation process of the first electrode 160 and the second electrode 180 may also include laser transfer, electroplating or thermal evaporation.

[0157] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0158] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A substrate having a first surface and a second surface arranged opposite to each other in a thickness direction; A tunneling layer, disposed on the first surface; A polysilicon doped layer, disposed on a side of the tunneling layer away from the substrate; as well as The conductive layer is arranged on a side of the polysilicon doped layer away from the substrate.

2. The solar cell according to claim 1, characterized in that The thickness of the polysilicon doping layer ranges from 30 nm to 100 nm.

3. The solar cell according to claim 1, characterized in that The polysilicon doping layer is doped with phosphorus, and the doping concentration of the phosphorus element ranges from 10 18 cm -3 -10 22 cm -3 .

4. The solar cell according to claim 1, characterized in that The thickness of the conductive layer ranges from 30 to 100 nm.

5. The solar cell according to claim 1, characterized in that: The conductive layer includes graphene or transparent conductive oxide.

6. The solar cell according to any one of claims 1 to 5, characterized in that: The conductive layer is a whole layer structure; The orthographic projection of the conductive layer on the substrate covers the orthographic projection of the polysilicon doped layer on the substrate.

7. The solar cell according to any one of claims 1 to 5, characterized in that: The conductive layer includes a plurality of discontinuous structures; Along a direction perpendicular to the thickness direction of the substrate, a plurality of discontinuous structures are arranged at intervals.

8. The solar cell according to any one of claims 1 to 5, characterized in that: It also includes a first passivation layer and a first electrode, wherein the first passivation layer is disposed on a side of the conductive layer away from the substrate; The first electrode is disposed on the first passivation layer and is electrically connected to the conductive layer.

9. The solar cell according to any one of claims 1 to 5, characterized in that: It also includes an emitter, a second electrode and a second passivation layer, wherein the emitter is arranged on the second surface, and the second passivation layer is arranged on a side of the emitter away from the substrate; The second electrode is disposed on the second passivation layer and is electrically connected to the emitter.

10. The solar cell according to claim 9, characterized in that: The thickness of the substrate is in the range of 100-150 μm; and / or the thickness of the emitter is in the range of 0.1-2 μm; and / or the thickness of the tunneling layer is in the range of 0.5-2 nm.

11. A method for preparing a solar cell, characterized in that: The preparation method comprises: Providing a substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other in a thickness direction; forming a tunneling layer and a polysilicon doped layer stacked on each other on the first surface, wherein the polysilicon doped layer is located on a side of the tunneling layer away from the substrate; A conductive layer is formed on a side of the polysilicon doped layer facing away from the substrate.

12. The preparation method according to claim 11, characterized in that: Before the step of forming a tunneling layer and a polysilicon doped layer stacked on each other on the first surface, the method further includes: forming a suede structure on the first surface and the second surface respectively; Forming emitter materials on the first surface and the second surface after the texture treatment respectively; The substrate on the first surface is etched to remove the emitter material plated around one side of the first surface and the side surface of the substrate, so as to form an emitter on the second surface.

13. The preparation method according to claim 12, characterized in that: Forming a polysilicon doped layer, comprising: A tunneling material layer and a phosphorus-doped amorphous silicon material layer are sequentially stacked on the first surface; Annealing the amorphous silicon material layer to form a polycrystalline silicon material layer; The amorphous silicon material layer and the tunneling material layer plated on one side of the second surface of the substrate and the side surface of the substrate are removed to form the tunneling layer and the polysilicon doping layer on the first surface.

14. The preparation method according to claim 13, characterized in that: Forming a conductive layer, comprising: A whole layer of conductive material is formed on the side of the polysilicon doped layer facing away from the substrate, and the conductive material layer plated around one side of the second surface and the side surface of the substrate is removed to form the conductive layer, the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the polysilicon doped layer on the substrate.

15. The preparation method according to claim 13, characterized in that: Forming a conductive layer, comprising: forming a whole conductive material layer on a side of the polysilicon doped layer away from the substrate; The conductive material layer plated around one side of the second surface and the side surface of the substrate is removed, and the conductive material layer in the non-electrode pattern area on one side of the first surface is removed to form a plurality of discontinuous structures, and the plurality of discontinuous structures are arranged at intervals along a direction perpendicular to the thickness direction of the substrate.

16. The preparation method according to claim 14 or 15, characterized in that: The preparation method further comprises: forming a first passivation layer on the polysilicon doped layer and the conductive layer in the electrode contact region; A second passivation layer is formed on a side of the emitter facing away from the substrate.

17. The preparation method according to claim 16, characterized in that: The preparation method further comprises: forming a first electrode on the first passivation layer, wherein the first electrode is electrically connected to the conductive layer; A second electrode is formed on the second passivation layer, and the second electrode is electrically connected to the emitter.

18. A photovoltaic module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 10.

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