LED epitaxial wafer for improving lighting effect attenuation and preparation method thereof

Abstract

The invention relates to the technical field of LEDs, in particular to an LED epitaxial wafer for improving lighting effect attenuation and a preparation method of the LED epitaxial wafer. The LED epitaxial wafer sequentially comprises an N-type GaAs substrate, an N-type GaAs buffer layer, a DBR reflecting layer, an N-type high-temperature-resistant diffusion layer, an N-type limiting layer, a first reverse doping layer, a multi-quantum well light-emitting layer, a second reverse doping layer, a P-type limiting layer, a P-type transition layer and a P-type window layer from bottom to top. According to the invention, the AlGaInP structure is inserted between the DBR reflecting layer and the N-type limiting layer, a special PH3 gradual change growth mode is adopted, and reverse doping layer structures are designed on the side close to the N type and the side close to the P type, so that the problem of light effect attenuation caused by impurities in a high-temperature and large-current environment can be effectively inhibited, and the obtained LED has excellent light attenuation resistance and aging resistance, and is suitable for large-scale production. And the luminance and the reliability are high.

Description

Technical Field

[0001] The invention relates to the technical field of LEDs, and in particular to an LED epitaxial wafer for improving light efficiency attenuation and a preparation method thereof. Background Art

[0002] LEDs made of quaternary AlGaInP materials are widely used in display screens, scene lighting, stage backgrounds, automotive systems and other fields. As the application scenarios gradually increase and the use conditions become more and more stringent, high-brightness AlGaInP red LEDs need to maintain good brightness stability and reliability under extreme conditions of high temperature and high current. However, as the chip size continues to shrink, conventional AlGaInP red LEDs in the industry cannot achieve good aging performance against high temperature and high current. For example, patent number CN201610276669 proposes a method of improving the aging performance against high current by adopting a segmented doped multi-spectrum DBR reflective layer and reducing the P-type semiconductor doping layer adjacent to the transition layer. However, as the chip size shrinks to less than 4.0mil×4.0mil, the above scheme will experience aging failure. The main reason is that the junction temperature of the LED itself increases, and the non-radiative recombination at a higher current density intensifies. In addition, the negative impact of impurity defects in a high-temperature working environment begins to dominate, resulting in severe brightness attenuation.

[0003] Similarly, conventional AlGaInP LED epitaxial structures (such as Figure 1 As shown in the figure, although it includes N-type GaAs substrate 1, N-type GaAs buffer layer 2, distributed Bragg reflector (DBR) 3, N-type confinement layer 4, multi-quantum well light-emitting layer 5, P-type confinement layer 6, P-type transition layer 7, and P-type window layer 8 from bottom to top, the DBR material on the side of the N-type doped layer cannot provide good current expansion under high temperature working environment and high current density. If the N-type doping is adjusted, it will cause serious carrier leakage and impurity diffusion, and more impurities will be introduced into the multi-quantum well light-emitting layer, reducing the luminous efficiency and causing the luminous brightness of the small-sized LED chip to continue to decay. At the same time, the P-type dopant in the P-type confinement layer is very easy to diffuse to the multi-quantum well light-emitting layer and transition layer at high temperature, causing the electron-hole pairs to be captured by deep energy levels, reducing the probability of radiation recombination, thereby affecting the luminous efficiency.

[0004] Therefore, it is of great significance to develop an AlGaInP red LED epitaxial wafer that can improve the light efficiency attenuation under high temperature and high current conditions. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention provides an LED epitaxial wafer with improved light efficiency decay and a preparation method thereof, which are used to improve the problem of light efficiency decay of LEDs in high temperature and high current working environments.

[0006] The first object of the present invention is to provide an LED epitaxial wafer with improved light efficiency attenuation, wherein the LED epitaxial wafer comprises, from bottom to top, an N-type GaAs substrate, an N-type GaAs buffer layer, a DBR reflective layer, an N-type high temperature resistant diffusion layer, an N-type confinement layer, a first reverse doping layer, a multi-quantum well light emitting layer, a second reverse doping layer, a P-type confinement layer, a P-type transition layer, and a P-type window layer; The material of the N-type high temperature resistant diffusion layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P, where the value range of x1 is 0.6~0.8.

[0007] The present invention adopts (Al x1 Ga 1-x1 ) 0.5 In 0.5 The design of the P insertion layer, taking advantage of the fact that the electron mobility of the AlGaInP material is between that of the DBR reflective layer material and the N-type confinement layer AlInP, improves the current expansion capability of the LED chip and avoids problems such as device heating and brightness attenuation caused by current crowding during high current operation. At the same time, a reverse doping layer structure is designed between the N-type confinement layer and the non-doped light-emitting layer, and between the P-type confinement layer and the light-emitting layer, which can effectively prevent the diffusion of carriers into the multi-quantum well light-emitting layer during high temperature and high current operation to cause deep energy level defects, offset the diffusion effect of impurity elements, and further improve the LED's anti-light decay performance under high temperature and high current.

[0008] Furthermore, the thickness of the N-type high temperature resistant diffusion layer is 200nm-250nm, the dopant is SiH4, and the doping concentration is 0.5×10 18 cm -3 ~1×10 18 cm -3 .

[0009] Furthermore, the material of the first reverse doping layer is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P, thickness is 40nm~60nm, where the value range of x2 is 0.7~0.8. This layer uses CCl4 as P-type dopant to provide P-type carriers, and the doping concentration is 0.2×10 17 cm -3 ~0.5×10 17 cm -3 .

[0010] Furthermore, the material of the second reverse doping layer is (Al x3 Ga1-x3 ) 0.5 In 0.5 P, with a thickness of 60nm to 80nm, where the value range of x3 is 0.7 to 0.8. This layer uses DETe as an N-type dopant to provide N-type carriers, and the doping concentration is 0.5×10 17 cm -3 ~1.0×10 17 cm -3 .

[0011] This technical solution uses opposite impurity doping on both the N-type side and the P-type side, which can offset the original doping characteristics. That is, when the electrons on the N-type side of the LED chip diffuse to the multi-quantum well light-emitting layer at high temperature, they will be captured by the holes in the first reverse doping layer, thereby offsetting the diffusion of the electrons; similarly, when the holes on the P-type side diffuse to the multi-quantum well light-emitting layer, they will be offset by the electrons in the second reverse doping layer to reduce the diffusion concentration, inhibit the diffusion effect of the impurity elements, and thus improve the LED's anti-light decay performance under high temperature and high current.

[0012] Furthermore, the DBR reflective layer is made of AlAs / Al 0.45 Ga 0.55 The AlAs material grows alternately in a periodic structure. The thickness of AlAs in each periodic structure is 44nm to 48nm. 0.45 Ga 0.55 The thickness of As is 57nm to 62nm. 0.45 Ga 0.55 The number of periodic cycles of As alternating growth is 15 to 20 pairs, where the dopant in the AlAs material is SiH4 with a doping concentration of 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , Al 0.45 Ga 0.55 The dopant in the As material is SiH4, and the doping concentration is 2.0×10 18 cm -3 ~3.0×10 18 cm -3 .

[0013] Furthermore, the material of the N-type limiting layer is Al 0.5 In 0.5 P, thickness is 300nm~500nm, dopant is SiH4, doping concentration is 1×10 18 cm -3 ~2×10 18 cm -3 ; The material of the P-type limiting layer is Al0.5 In 0.5 P, thickness is 500nm~900nm, dopant is Cp2Mg, doping concentration is 0.7×10 18 cm -3 ~1×10 18 cm -3 .

[0014] The second object of the present invention is to provide a method for preparing an LED epitaxial wafer with improved light efficiency attenuation, wherein an N-type GaAs buffer layer, a DBR reflective layer, an N-type high temperature resistant diffusion layer, an N-type confinement layer, a first reverse doping layer, a multi-quantum well light emitting layer, a second reverse doping layer, a P-type confinement layer, a P-type transition layer, and a P-type window layer are sequentially grown on an N-type GaAs substrate using an MOCVD device; The N-type high temperature resistant diffusion layer is grown in a gradual manner using a Group V source material PH3; The first reverse doping layer is between the multi-quantum well light-emitting layer and the N-type confinement layer and is doped with a P-type dopant, and the second reverse doping layer is between the multi-quantum well light-emitting layer and the P-type confinement layer and is doped with an N-type dopant.

[0015] The present invention adopts a special PH3 gradient method to grow an N-type high temperature resistant diffusion layer, so as to achieve the purpose of continuous gradient of the molar ratio of the group V source and the group III metal source of the layer material, and adjust the incorporation of the doping material in the lattice, thereby inhibiting the light efficiency attenuation caused by the diffusion of impurities to the light-emitting layer under high temperature environment, improving the light efficiency attenuation while improving the high temperature anti-aging performance of the LED chip. At the same time, by designing a reverse doping layer structure, the electrons diffused by the N-type and the holes diffused by the P-type are captured and offset, and the diffusion effect of the impurity elements is inhibited, thereby further improving the high temperature and high current anti-light decay performance of the LED.

[0016] Furthermore, the growth step of the N-type high temperature resistant diffusion layer is as follows: setting the temperature of the reaction chamber to 730°C ± 10°C, introducing TMAl, TMGa, TMIn, and PH3 into the DBR reflective layer, and growing (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, and SiH4 is used as N-type dopant with a doping concentration of 0.5×10 18 cm -3 ~1×10 18 cm -3 , where the value range of x1 is 0.6~0.8, the initial PH3 flow rate of growth is 800sccm, and then gradually changes to 1300sccm, and the gradual change rate of PH3 flow rate is 2.0sccm / nm~2.5sccm / nm.

[0017] Furthermore, the growth step of the first reverse doping layer is: setting the temperature of the reaction chamber to 700°C ± 10°C, introducing TMAl, TMGa, TMIn, and PH3 into the N-type confinement layer, and growing (Al2O3) with a thickness of 40nm to 60nm. x2 Ga1 -x2 ) 0.5 In 0.5 P material, and CCl4 is used as a P-type dopant to provide P-type carriers, with a doping concentration of 0.2×10 17 cm -3 ~0.5×10 17 cm -3 , where the value range of x2 is 0.7~0.8.

[0018] Furthermore, the growth step of the second reverse doping layer is: setting the temperature of the reaction chamber to 730°C ± 10°C, introducing TMAl, TMGa, TMIn, and PH3 into the multi-quantum well light-emitting layer, and growing (Al x3 Ga1 -x3 ) 0.5 In 0.5 P material, and DETe is used as N-type dopant to provide N-type carriers, with a doping concentration of 0.5×10 17 cm -3 ~1.0×10 17 cm -3 , where the value range of x3 is 0.7~0.8.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention inserts an N-type high temperature resistant diffusion layer between the DBR reflective layer and the N-type limiting layer, and uses the characteristics of the AlGaInP material electron mobility between the DBR reflective material and the N-type limiting layer AlInP to improve the current expansion capability of the LED chip under high temperature and high current. At the same time, a special PH3 gradient growth method is adopted to make the molar ratio of the V group source to the III group source continuously change gradually, and adjust the incorporation of the doping material in the lattice, thereby inhibiting the light efficiency attenuation caused by the diffusion of impurities to the light-emitting layer under high temperature environment. It can effectively avoid the problem of brightness attenuation caused by device heating caused by current crowding in harsh working conditions.

[0020] 2. The present invention introduces a first reverse doping layer between the N-type confinement layer and the multi-quantum well light-emitting layer, and introduces a second reverse doping layer between the P-type confinement layer and the multi-quantum well light-emitting layer. The two reverse doping layers use impurity doping types opposite to the corresponding space charge regions. The design of this reverse doping layer structure can effectively capture and offset N-type diffused electrons and P-type diffused holes, inhibit the diffusion effect of impurity elements, and thus improve the anti-light decay performance of the LED under high temperature and high current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the structure of a conventional AlGaInP-based LED epitaxial wafer; Figure 2 This is a schematic diagram of the structure of an LED epitaxial wafer of the present invention; Figure 3 The graph is a comparison of the brightness of the LED of the present invention and a conventional LED when lit up versus current.

[0022] Description of the numbers in the schematic diagram: 1. N-type GaAs substrate; 2. N-type GaAs buffer layer; 3. DBR reflective layer; 4. N-type confinement layer; 5. Multi-quantum well light-emitting layer; 6. P-type confinement layer; 7. P-type transition layer; 8. P-type window layer; 9. N-type high-temperature resistant diffusion layer; 10. First reverse doping layer; 11. Second reverse doping layer. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present application.

[0025] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0026] See also Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] In one embodiment of the present invention, an LED epitaxial wafer with improved light efficiency attenuation is provided, and its structural schematic diagram is shown in FIG. Figure 2 As shown, the LED epitaxial wafer includes, from bottom to top, an N-type GaAs substrate 1, an N-type GaAs buffer layer 2, a DBR reflective layer 3, an N-type high temperature resistant diffusion layer 9, an N-type confinement layer 4, a first reverse doping layer 10, a multi-quantum well light-emitting layer 5, a second reverse doping layer 11, a P-type confinement layer 6, a P-type transition layer 7, and a P-type window layer 8.

[0028] In some embodiments, the thickness of the N-type GaAs buffer layer material is 100 nm to 200 nm, the dopant is SiH4, and the doping concentration is 3.0×10 18 cm -3 ~5.0×10 18 cm -3 .

[0029] In some embodiments, the DBR reflective layer is made of AlAs / Al 0.45 Ga 0.55 The AlAs material grows alternately in a periodic structure. The thickness of AlAs in each periodic structure is 44nm to 48nm. 0.45 Ga 0.55 The thickness of As is 57nm to 62nm. 0.45 Ga 0.55 The number of cyclic pairs of As alternate growth is 15 to 20 pairs, where the dopant in the AlAs material layer is SiH4 with a doping concentration of 1.0×10 18 cm -3 ~2.0×10 18 cm-3 , Al 0.45 Ga 0.55 The dopant in the As material layer is SiH4, and the doping concentration is 2.0×10 18 cm -3 ~3.0×10 18 cm -3 .

[0030] Furthermore, the N-type high temperature resistant diffusion layer material is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P, thickness is 200nm~250nm. The value range of Al component x1 is 0.6~0.8, and the doping concentration is 0.5×10 18 cm -3 ~1×10 18 cm -3 The N-type dopant used in this layer is SiH4. x1 Ga 1-x1 ) 0.5 In 0.5 The design of the P insertion layer, taking advantage of the fact that the electron mobility of the AlGaInP material is between that of the DBR reflective layer material and the N-type limiting layer AlInP, improves the current expansion capability of the LED chip and avoids the problem of current congestion during high current operation causing device heating and brightness attenuation.

[0031] In some embodiments, the N-type confinement layer material is Al 0.5 In 0.5 P, thickness is 300nm~500nm, dopant is SiH4, doping concentration is 1×10 18 cm -3 ~2×10 18 cm -3 .

[0032] In some embodiments, the first counter doping layer material is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P, thickness is 40nm~60nm, x2 value range is 0.7~0.8, the doping concentration of this layer is 0.2×10 17 cm -3 ~0.5×10 17 cm -3, CCl4 is used as a P-type dopant to provide P-type carriers. The growth position of the first reverse doping layer is between the N-type confinement layer and the multi-quantum well light-emitting layer. That is, when the LED chip is at high temperature, a P-type dopant is used below the multi-quantum well light-emitting layer. The holes provided by the P-type dopant can capture electrons on the N-type side and diffuse to the multi-quantum well light-emitting layer, effectively avoiding deep energy level defects, thereby improving the anti-light decay performance.

[0033] In some embodiments, the multi-quantum well light-emitting layer is a quantum well / barrier structure with 15 to 20 pairs, wherein the materials of the quantum well layer / barrier layer are AlGaInP; specifically, the material of the quantum well layer is (Al y1 Ga 1-y1 ) 0.5 In 0.5 P, the thickness of the single quantum well layer is 3nm~5nm, the value range of y1 is 0.05~0.07; the material of the quantum barrier layer is (Al y2 Ga 1-y2 ) 0.5 In 0.5 P, the thickness of a single quantum barrier layer is 6nm to 8nm, the value range of y2 is 0.7 to 0.8, and the quantum wells / barriers are all non-doped.

[0034] In some embodiments, the second counter doping layer material is (Al x3 Ga 1-x3 ) 0.5 In 0.5 P, thickness is 60nm~80nm, the value range of x3 is 0.7~0.8, and the doping concentration of this layer is 0.5×10 17 cm -3 ~1.0×10 17 cm -3 , DETe is used as an N-type dopant to provide N-type carriers. The growth position of the second reverse doping layer is between the P-type confinement layer and the light-emitting layer. Similarly, an N-type dopant is used above the multi-quantum well light-emitting layer, and the electrons provided by the N-type dopant can offset the diffusion of holes on the P-type side to the multi-quantum well light-emitting layer, thereby improving the anti-light decay performance.

[0035] In some embodiments, the P-type confinement layer material is Al 0.5 In 0.5 P, thickness is 500nm~900nm, dopant is Cp2Mg, doping concentration is 0.7×10 18 cm -3 ~1×10 18 cm -3 .

[0036] In some embodiments, the P-type transition layer material is (Al x4 Ga 1-x4 )0.5 In 0.5 P, thickness is 20nm~40nm, dopant is Cp2Mg, doping concentration is 2×10 18 cm -3 ~3×10 18 cm -3 , the value range of x4 is 0.2~0.3.

[0037] In some embodiments, the material of the P-type window layer is GaP, the thickness is 3000nm to 4000nm, the dopant is CP2Mg, and the doping concentration is 1×10 18 cm -3 ~5×10 18 cm -3 .

[0038] In another embodiment, the present invention also provides a method for preparing an LED epitaxial wafer with improved light efficiency attenuation, using MOCVD equipment to sequentially grow an N-type GaAs buffer layer, a DBR reflective layer, an N-type high temperature resistant diffusion layer, an N-type confinement layer, a first reverse doping layer, a multi-quantum well light emitting layer, a second reverse doping layer, a P-type confinement layer, a P-type transition layer, and a P-type window layer on an N-type GaAs substrate. Specifically, the method comprises the following steps: (1) The MOCVD was depressurized to 50 mbar in a pure H2 atmosphere, and the reaction chamber temperature was set to 400°C. The N-type GaAs substrate was then transferred to the reaction chamber through a robot transfer bin, and then the temperature was quickly raised to 700°C and maintained at 700°C for 5 min to 8 min. (2) Growth of N-type GaAs buffer layer: The reaction chamber temperature was set to 700°C ± 10°C, TMGa and AsH3 were introduced, and GaAs buffer layer material with a thickness of 100nm to 200nm was grown. SiH4 was used as the N-type dopant with a doping concentration of 3×10 18 cm -3 ~5×10 18 cm -3 ; (3) Growth of DBR reflective layer: The reaction chamber temperature was set to 700°C ± 10°C, TMAl and AsH3 were introduced, and SiH4 was introduced as N-type dopant to grow AlAs material with a thickness of 44nm to 48nm and a doping concentration of 1×10 18 cm -3 ~2×10 18 cm -3 Then TMGa is introduced to grow Al with a thickness of 57nm to 62nm. 0.45 Ga 0.55 As material, dopant is SiH4, doping concentration is 2×10 18 cm -3~3×10 18 cm -3 The above AlAs and Al 0.45 Ga 0.55 As growth combination forms the first pair of DBR reflective layers, and then repeats the cycle for 14 to 19 pairs of combined structures; (4) Growth of N-type high temperature diffusion resistance: Set the reaction chamber temperature to 730℃±10℃, introduce TMAl, TMGa, TMIn, and PH3 into the DBR reflective layer, and grow (Al) with a thickness of 200nm~250nm x1 Ga 1-x1 ) 0.5 In 0.5 P material. The value range of component x1 is 0.6~0.8. The N-type dopant used in this layer is SiH4 with a doping concentration of 0.5×10 18 cm -3 ~1×10 18 cm -3 The initial PH3 flow rate of this layer growth is 800 sccm, and then gradually changes to 1300 sccm, and the rate of gradual change of PH3 flow rate is 2.0 sccm / nm~2.5 sccm / nm; (5) Growth of N-type confinement layer: Set the reaction chamber temperature to 730℃±10℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 300nm to 500nm. 0.5 In 0.5 P material, doping concentration is 1×10 18 cm -3 ~2×10 18 cm -3 , N-type dopant is SiH4; (6) Growth of the first reverse doping layer: Set the reaction chamber temperature to 700℃±10℃, introduce TMAl, TMGa, TMIn, and PH3 into the N-type confinement layer, and grow (Al) with a thickness of 40nm to 60nm. x2 Ga 1-x2 ) 0.5 In 0.5 P material, the value range of component x2 is 0.7~0.8. This layer uses CCl4 as P-type dopant to provide P-type carriers, and the doping concentration is 0.2×10 17 cm -3 ~0.5×10 17 cm -3 ; (7) Growth of multi-quantum well light-emitting layer: Set the temperature of the reaction chamber to 700℃±20℃, introduce TMGa, TMAl, TMIn, and PH3, and grow quantum wells and quantum barriers respectively (Al y1 Ga1-y1 ) 0.5 In 0.5 P、(Al y2 Ga 1-y2 ) 0.5 In 0.5 P material. The thickness of the single quantum well layer is 3nm to 5nm, and the value range of y1 is 0.05 to 0.07. The thickness of the single quantum barrier layer is 6nm to 8nm, and the value range of y2 is 0.7 to 0.8. The number of periods is 15 pairs to 20 pairs, and the light-emitting region is non-doped; (8) Growth of the second reverse doping layer: Set the temperature of the reaction chamber to 730℃±10℃, introduce TMAl, TMGa, TMIn, and PH3 into the light-emitting layer, and grow (Al x3 Ga 1-x3 ) 0.5 In 0.5 P material, the value range of component x3 is 0.7~0.8. This layer uses DETe as N-type dopant to provide N-type carriers, and the doping concentration is 0.5×10 17 cm -3 ~1.0×10 17 cm -3 ; (9) Growth of P-type confinement layer: Set the reaction chamber temperature to 730°C ± 10°C, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 500nm to 900nm. 0.5 In 0.5 P material, dopant is Cp2Mg, doping concentration is 0.7×10 18 cm -3 ~1×10 18 cm -3 ; (10) Growth of P-type transition layer: Set the reaction chamber temperature to 730℃±20℃, introduce TMGa, TMAl, TMIn, and PH3, and grow (Al) with a thickness of 20nm to 40nm. x4 Ga 1-x4 ) 0.5 In 0.5 P material, dopant is Cp2Mg, doping concentration is 2×10 18 cm -3 ~3×10 18 cm -3 , the value range of x4 is 0.2~0.3; (11) Growth of P-type window layer: The reaction chamber temperature was set to 690°C ± 20°C, TMGa and PH3 were introduced, and GaP material with a thickness of 3000nm to 4000nm was grown. CP2Mg was used as the P-type dopant with a doping concentration of 1×1018 cm -3 ~5×10 18 cm -3 ; (12) Wafer removal: After the growth is completed, the temperature of the MOCVD reaction chamber is lowered to 110°C, and then the pressure is adjusted to 1000 mbar. The reaction chamber is opened and the epitaxial wafer is removed.

[0039] In order to further illustrate the present invention, the present invention is described in detail below in conjunction with specific embodiments.

[0040] Example 1 A method for preparing an LED epitaxial wafer with improved light efficiency attenuation, specifically comprising the following steps: (1) The MOCVD was depressurized to 50 mbar in a pure H2 atmosphere, and the reaction chamber temperature was set to 400°C. The N-type GaAs substrate was then transferred to the reaction chamber through a robot transfer bin, and then the temperature was quickly raised to 700°C and maintained at 700°C for 6 minutes. (2) Growth of N-type GaAs buffer layer: The reaction chamber temperature was set to 700°C, TMGa and AsH3 were introduced, and a GaAs buffer layer material with a thickness of 200 nm was grown. SiH4 was used as the N-type dopant with a doping concentration of 5×10 18 cm -3 ; (3) Growth of DBR reflective layer: The reaction chamber temperature was set to 700°C, TMAl and AsH3 were introduced, and SiH4 was introduced as N-type dopant to grow AlAs material with a thickness of 44 nm and a doping concentration of 1×10 18 cm -3 Then TMGa was introduced to grow Al with a thickness of 57nm. 0.45 Ga 0.55 As material, dopant is SiH4, doping concentration is 2×10 18 cm -3 The above AlAs and Al 0.45 Ga 0.55 As growth combination forms the first pair of DBR reflective layers, and then repeats the cycle 15 for the combined structure; (4) Growth of N-type high temperature diffusion resistance: Set the reaction chamber temperature to 730°C, introduce TMAl, TMGa, TMIn, and PH3 into the DBR reflective layer, and grow (Al) with a thickness of 200nm. 0.6 Ga 0.4 ) 0.5 In 0.5 P material. The N-type dopant used in this layer is SiH4, with a doping concentration of 1×10 18 cm -3The initial PH3 flow rate of this layer growth is 800sccm, and then gradually changes to 1300sccm, and the rate of PH3 flow rate change is 2.5sccm / nm; (5) Growth of N-type confinement layer: Set the reaction chamber temperature to 730°C, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 500 nm. 0.5 In 0.5 P material, doping concentration is 1×10 18 cm -3 , N-type dopant is SiH4; (6) Growth of the first reverse doping layer: Set the reaction chamber temperature to 700°C, introduce TMAl, TMGa, TMIn, and PH3 into the N-type confinement layer, and grow a 40nm thick (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P material, this layer uses CCl4 as a P-type dopant to provide P-type carriers, and the doping concentration is 0.5×10 17 cm -3 ; (7) Growth of multi-quantum well light-emitting layer: The temperature of the reaction chamber is set to 700°C, and TMGa, TMAl, TMIn, and PH3 are introduced. The quantum wells and quantum barriers grown are (Al 0.05 Ga 0.95 ) 0.5 In 0.5 P、(Al 0.7 Ga 0.3 ) 0.5 In 0.5 P material. The thickness of a single quantum well layer is 4nm, the thickness of a single quantum barrier layer is 6nm, the number of periods is 15 pairs, and the light-emitting region is non-doped; (8) Growth of the second reverse doping layer: The reaction chamber temperature was set to 730°C, and TMAl, TMGa, TMIn, and PH3 were introduced into the light-emitting layer to grow a 80nm thick (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P material. This layer uses DETe as an N-type dopant to provide N-type carriers, with a doping concentration of 0.5×10 17 cm -3 ; (9) Growth of P-type confinement layer: Set the reaction chamber temperature to 730°C, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 600 nm. 0.5 In 0.5 P material, dopant is Cp2Mg, doping concentration is 1×10 18 cm-3 ; (10) Growth of P-type transition layer: Set the reaction chamber temperature to 730°C, introduce TMGa, TMAl, TMIn, and PH3, and grow a 40nm thick (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P material, dopant is Cp2Mg, doping concentration is 3×10 18 cm -3 ; (11) Growth of P-type window layer: The reaction chamber temperature was set to 690°C, TMGa and PH3 were introduced, and GaP material with a thickness of 4000 nm was grown. CP2Mg was used as the P-type dopant with a doping concentration of 2×10 18 cm -3 ; (12) Wafer removal: After the growth is completed, the temperature of the MOCVD reaction chamber is lowered to 110°C, and then the pressure is adjusted to 1000 mbar. The reaction chamber is opened and the epitaxial wafer is removed.

[0041] Comparative Example 1 A conventional AlGaInP LED epitaxial wafer is prepared by conventional methods, and its structural schematic diagram is shown in FIG. Figure 1 shown.

[0042] Test example 1. The LED obtained in Example 1 and the LED obtained in Comparative Example 1 were subjected to chip aging lighting test under high temperature (115°C) and high current (40mA) conditions. The chip size was 3.8mil×3.8mil, and the results were shown in Table 1. From the results in Table 1, it can be seen that the brightness attenuation of the conventional LED reached 19.2% after 48 hours of lighting, and the brightness attenuation was 42.8% after 1000 hours; while the brightness attenuation of the LED of the present invention was only 3.7% after 1000 hours of lighting.

[0043] Table 1 High temperature and high current aging lighting test results

[0044] 2. The LED obtained in Example 1 and the LED obtained in Comparative Example 1 were lit up, and the curves of brightness changing with current were compared. The results are as follows: Figure 3 The results show that the LED prepared in the embodiment of the present invention has better anti-light efficiency decay performance than conventional LEDs under high current, and can still maintain good luminous brightness and reliability as the current increases, which is significantly improved compared with conventional LEDs.

[0045] In summary, the present invention utilizes the characteristic that the electron mobility of AlGaInP material is between that of DBR reflective layer material and N-type limiting layer AlInP, inserts AlGaInP structure between the two, improves the current expansion capability of LED chip, can effectively avoid the problems such as device heating and brightness attenuation caused by current crowding during high current operation, and adopts a special PH3 gradient growth method to adjust the incorporation of doping material in the lattice, and inhibit the diffusion of impurities into the light-emitting layer under high temperature environment to cause light efficiency attenuation; at the same time, a reverse doping layer structure is designed near the N-type side and the P-type side, which can effectively prevent the diffusion of carriers into the multi-quantum well light-emitting layer to cause deep energy level defects during high temperature and high current operation, offset the diffusion effect of impurity elements, thereby further improving the anti-light decay performance of LED under high temperature and high current, and the obtained LED has excellent anti-light attenuation performance and anti-aging performance, high luminous brightness and reliability, and is suitable for high temperature and high current working conditions.

[0046] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An LED epitaxial wafer for improving light efficiency attenuation, characterized in that: The LED epitaxial wafer includes, from bottom to top, an N-type GaAs substrate, an N-type GaAs buffer layer, a DBR reflective layer, an N-type high temperature resistant diffusion layer, an N-type confinement layer, a first reverse doping layer, a multi-quantum well light emitting layer, a second reverse doping layer, a P-type confinement layer, a P-type transition layer, and a P-type window layer; The material of the N-type high temperature resistant diffusion layer is (Al x1 Ga 1-x1 ) 0.5 In 0.5 P, where the value range of x1 is 0.6~0.

8.

2. The LED epitaxial wafer for improving light efficiency decay according to claim 1, characterized in that: The thickness of the N-type high temperature resistant diffusion layer is 200nm-250nm, the dopant is SiH4, and the doping concentration is 0.5×10 18 cm -3 ~1×10 18 cm -3 .

3. The LED epitaxial wafer with improved light efficiency decay according to claim 1, characterized in that: The material of the first reverse doping layer is (Al x2 Ga 1-x2 ) 0.5 In 0.5 P, thickness is 40nm~60nm, where the value range of x2 is 0.7~0.

8. This layer uses CCl4 as P-type dopant to provide P-type carriers, and the doping concentration is 0.2×10 17 cm -3 ~0.5×10 17 cm -3 .

4. The LED epitaxial wafer with improved light efficiency decay according to claim 1, characterized in that: The material of the second reverse doping layer is (Al x3 Ga 1-x3 ) 0.5 In 0.5 P, with a thickness of 60nm to 80nm, where the value range of x3 is 0.7 to 0.

8. This layer uses DETe as an N-type dopant to provide N-type carriers, and the doping concentration is 0.5×10 17 cm -3 ~1.0×10 17 cm -3 .

5. The LED epitaxial wafer with improved light efficiency decay according to claim 1, characterized in that: The DBR reflective layer is made of AlAs / Al 0.45 Ga 0.55 The AlAs material grows alternately in a periodic structure. The thickness of AlAs in each periodic structure is 44nm to 48nm. 0.45 Ga 0.55 The thickness of As is 57nm to 62nm. 0.45 Ga 0.55 The number of periodic cycles of As alternating growth is 15 to 20 pairs, where the dopant in the AlAs material is SiH4 with a doping concentration of 1.0×10 18 cm -3 ~2.0×10 18 cm -3 , Al 0.45 Ga 0.55 The dopant in the As material is SiH4, and the doping concentration is 2.0×10 18 cm -3 ~3.0×10 18 cm -3 .

6. The LED epitaxial wafer with improved light efficiency decay according to claim 1, characterized in that: The material of the N-type confinement layer is Al 0.5 In 0.5 P, thickness is 300nm~500nm, dopant is SiH4, doping concentration is 1×10 18 cm -3 ~2×10 18 cm -3 ; The material of the P-type confinement layer is Al 0.5 In 0.5 P, thickness is 500nm~900nm, dopant is Cp2Mg, doping concentration is 0.7×10 18 cm -3 ~1×10 18 cm -3 .

7. A method for preparing an LED epitaxial wafer with improved light efficiency decay according to any one of claims 1 to 6, characterized in that: Using MOCVD equipment, an N-type GaAs buffer layer, a DBR reflective layer, an N-type high temperature resistant diffusion layer, an N-type confinement layer, a first reverse doping layer, a multi-quantum well light-emitting layer, a second reverse doping layer, a P-type confinement layer, a P-type transition layer, and a P-type window layer are sequentially grown on an N-type GaAs substrate; The N-type high temperature resistant diffusion layer is grown in a gradual manner using a Group V source material PH3; The first reverse doping layer is between the multi-quantum well light-emitting layer and the N-type confinement layer and is doped with a P-type dopant, and the second reverse doping layer is between the multi-quantum well light-emitting layer and the P-type confinement layer and is doped with an N-type dopant.

8. The method for preparing an LED epitaxial wafer with improved light efficiency decay according to claim 7, characterized in that: The growth steps of the N-type high temperature resistant diffusion layer are as follows: setting the temperature of the reaction chamber to 730°C ± 10°C, introducing TMAl, TMGa, TMIn, and PH3 into the DBR reflective layer, and growing (Al) with a thickness of 200nm to 250nm. x1 Ga 1-x1 ) 0.5 In 0.5 P material, and SiH4 is used as N-type dopant with a doping concentration of 0.5×10 18 cm -3 ~1×10 18 cm -3 , where the value range of x1 is 0.6~0.8, the initial PH3 flow rate of growth is 800sccm, and then gradually changes to 1300sccm, and the gradual change rate of PH3 flow rate is 2.0sccm / nm~2.5sccm / nm.

9. The method for preparing an LED epitaxial wafer with improved light efficiency decay according to claim 7, characterized in that: The growth step of the first reverse doping layer is: setting the temperature of the reaction chamber to 700°C ± 10°C, introducing TMAl, TMGa, TMIn, and PH3 into the N-type confinement layer, and growing (Al) with a thickness of 40nm to 60nm. x2 Ga1 -x2 ) 0.5 In 0.5 P material, and CCl4 is used as a P-type dopant to provide P-type carriers, with a doping concentration of 0.2×10 17 cm -3 ~0.5×10 17 cm -3 , where the value range of x2 is 0.7~0.

8.

10. The method for preparing an LED epitaxial wafer with improved light efficiency decay according to claim 7, characterized in that: The growth step of the second reverse doping layer is: setting the temperature of the reaction chamber to 730°C ± 10°C, introducing TMAl, TMGa, TMIn, and PH3 into the multi-quantum well light-emitting layer, and growing (Al) with a thickness of 60nm to 80nm. x3 Ga1 -x3 ) 0.5 In 0.5 P material, and DETe is used as N-type dopant to provide N-type carriers, with a doping concentration of 0.5×10 17 cm -3 ~1.0×10 17 cm -3 , where the value range of x3 is 0.7~0.8.

Images