Array substrate, light-emitting substrate and display device

Abstract

The invention discloses an array substrate, a light-emitting substrate and a display device, and belongs to the field of display. The array substrate comprises a substrate body (900), a first conductive layer (100) and a second conductive layer (200) which are insulated from each other are arranged on the substrate body (900) in a stacked mode, and the array substrate further comprises a plurality of light-emitting element terminal sets (10) arranged on the second conductive layer (200) in an array mode and used for being connected with light-emitting elements. A plurality of sensor terminal sets (30) located on the second conductive layer 200 (200) are further arranged and used for being connected with sensors, and the sensors are used for sensing the light-emitting elements so that the light-emitting conditions of the surrounding light-emitting elements can be rapidly and effectively monitored, various parameters such as the light-emitting elements can be adjusted more precisely in time, and it is ensured that the performance of the light-emitting elements is stable.

Description

[0001] The present disclosure is a divisional application. The application number of the original application is 202180000440.5, the application date is March 10, 2021, and the name of the invention is “Array substrate, light-emitting substrate and display device”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a light-emitting substrate and a display device. Background Art

[0003] MiniLED, also known as sub-millimeter light-emitting diode, has a grain size of approximately 100 to 300um, while MicroLED has a grain size of less than 100um. Currently, the research and development of MiniLED and MicroLED applications in the backlight and display fields is constantly deepening in order to achieve products of better quality.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide an array substrate, a light-emitting substrate and a display device.

[0006] According to one aspect of the present disclosure, an array substrate is provided, comprising a base substrate, on which a first conductive layer and a second conductive layer insulated from each other are stacked, wherein the array substrate further comprises:

[0007] A plurality of array-arranged light-emitting element terminal groups are provided on the second conductive layer and are used for coupling with the light-emitting elements;

[0008] A plurality of sensor terminal groups are provided on the second conductive layer and are used to couple with sensors; the orthographic projection of the sensor terminal group on the substrate substrate does not overlap with the orthographic projection of the light emitting element terminal group on the substrate substrate; the sensor terminal group includes an input terminal and an output terminal; the corresponding sensor includes an input pin and an output pin, the input terminal is used to be electrically connected to the input pin, and the output terminal is used to be electrically connected to the output pin;

[0009] A first signal line group, provided in the first conductive layer, electrically connected to the sensor terminal group, and used to drive the sensor to perform sensing;

[0010] A second signal line group, provided in the first conductive layer, electrically connected to the light emitting element terminal group, and used for driving the light emitting element to emit light;

[0011] A plurality of first leads; wherein the first leads connect the output terminal of one of the two adjacent sensor terminal groups with the input terminal of the other sensor terminal group.

[0012] In an exemplary embodiment of the present disclosure, the first leads include first column leads extending along a column direction and first row leads extending along a row direction, each of the first column leads is arranged in the first conductive layer, each of the first row leads is arranged in the second conductive layer, and the first column leads and the first row leads are electrically connected through a via.

[0013] In an exemplary embodiment of the present disclosure, at least one of the first leads includes one first column lead and two first row leads, the two first row leads respectively extend from the output terminal and the input terminal of two adjacent sensor terminal groups along the row direction, and the two first row leads are electrically connected to the first column leads through vias at the same time.

[0014] In an exemplary embodiment of the present disclosure, first-column lead wires connecting sensor terminal groups located in the same column are arranged along the column direction.

[0015] In an exemplary embodiment of the present disclosure, the sensor terminal group further includes a power supply terminal; the corresponding sensor further includes a power supply pin, and the power supply terminal is used to be electrically connected to the power supply pin;

[0016] The first signal line group includes a power signal line; the power terminal is electrically connected to the power signal line;

[0017] The power signal line and the first column lead are arranged side by side and at intervals.

[0018] In an exemplary embodiment of the present disclosure, m×n sensors are connected in series in an S-shaped manner, row by row and column by column; wherein m and n are both integers; m is the number of rows of sensors connected in series, and n is the number of columns of sensors connected in series.

[0019] In an exemplary embodiment of the present disclosure, in two adjacent sensors of the m×n sensors sequentially connected in series in an S-shape, column by column and row by row, an output pin of one of the sensors is electrically connected to an input pin of the other sensor through the first lead.

[0020] In an exemplary embodiment of the present disclosure, the first signal line group includes an input signal line and an output signal line;

[0021] Among all the sensors connected in series, the input terminal of the sensor terminal group corresponding to the sensor at one end is connected to the input signal line, and the output terminal of the sensor terminal group corresponding to the sensor at the other end is connected to the output signal line.

[0022] According to another aspect of the present disclosure, there is provided a light-emitting substrate, comprising:

[0023] The array substrate described above;

[0024] A light emitting element coupled to the light emitting element terminal group of the array substrate;

[0025] The sensor is coupled to the sensor terminal group of the array substrate.

[0026] According to yet another aspect of the present disclosure, a display device is provided, comprising the light-emitting substrate described above.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0029] Figure 1 This is a schematic diagram of a local structure of a mini LED array substrate disclosed in the present invention;

[0030] Figure 2 for Figure 1 A partial enlarged schematic diagram of the middle M area;

[0031] Figure 3 is a schematic diagram of the arrangement of light-emitting units;

[0032] Figure 4 It is a structural schematic diagram of a sensor terminal group;

[0033] Figure 5 for Figure 4 Schematic diagram of the cross section along the AA direction;

[0034] Figure 6 A schematic diagram of the arrangement of a sensor terminal group and a signal line;

[0035] Figure 7 Shows Figure 6 A schematic structural diagram of a first conductive layer;

[0036] Figure 8 An arrangement of signal lines of a sensor terminal group in one embodiment is shown;

[0037] Fig. 9 Shows Figure 8 A schematic diagram of a local structure of an array substrate;

[0038] Fig.10 for Fig. 9 A partial enlarged schematic diagram of the middle M area;

[0039] Fig.11 for Fig. 9 A schematic diagram of the structure of a sensor terminal group;

[0040] Fig.12 Shows Fig. 9 A schematic diagram of a wiring method of the first conductive layer in FIG.

[0041] Fig.13 shows a schematic structural diagram of a first lead;

[0042] Fig.14 Another embodiment of the signal line arrangement of the sensor terminal group is shown;

[0043] Fig.15 Shows Fig.14 A schematic diagram of a local structure of an array substrate;

[0044] Fig.16 for Fig.14 A schematic diagram of the structure of a sensor terminal group;

[0045] Fig.17 Shows Fig.14 A wiring method of the first conductive layer in;

[0046] Fig.18 Shows Fig.14 Schematic diagram of the transmission path of input signal and output signal;

[0047] Fig.19 A partial structural schematic diagram of an array substrate in another embodiment is shown;

[0048] Fig. 20 for Fig.19 A partial enlarged schematic diagram of the middle M area;

[0049] Fig.21 for Fig.19 A schematic diagram of the structure of a sensor terminal group;

[0050] Fig. 22 for Fig.19 The middle M area includes a partial enlarged schematic diagram of the capacitor terminal group;

[0051] Fig.23 A schematic diagram of the structure of a capacitor terminal group.

[0052] Description of reference numerals:

[0053] 100, first conductive layer; 200, second conductive layer; 300, insulating layer; 400, insulating layer; 900, substrate; 10, light emitting element terminal group; 11, anode terminal; 12, cathode terminal; 101, light emitting unit; 20, drive circuit terminal group; 21, input terminal; 22, power supply terminal; 23, output terminal; 24, first common voltage terminal; 30, sensor terminal group; 31, input terminal; 32, output terminal; 33, power supply terminal; 34, second common voltage terminal; 40, capacitor terminal group; 41. First capacitor terminal; 42. Second capacitor terminal; 101. Input signal line; 102. Output signal line; 103. Power signal line; 104. First common voltage signal line; 105. First lead; 1051. First column lead; 1052. First row lead; 106. Second lead; 107. Third lead; 108. Fourth lead; 201. Second common voltage signal line; 202. Drive voltage signal line; 203. Power line; 204. Source address line; 205. Common voltage signal line auxiliary line; 5. Grooving. DETAILED DESCRIPTION

[0054] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations provided by embodiments of the present disclosure and are not necessarily drawn to scale.

[0055] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0056] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0057] The disclosed embodiment provides an array substrate, on which a light-emitting element can be bound to serve as a backlight source of a Mini-LED display device. The array substrate can also be bound to a sensor to sense the light-emitting performance of the light-emitting element, so as to facilitate monitoring of the light-emitting condition of the backlight source.

[0058] In the embodiments of the present disclosure, Figure 1 This is a schematic diagram of a local structure of a mini LED array substrate disclosed in the present invention. Figure 2 for Figure 1 A partial enlarged schematic diagram of the middle M area. Figure 3 It is a structural diagram of a sensor terminal group. Figure 4 for Figure 3 Schematic diagram of the cross section along the AA axis. Figure 1-Figure 4 The Mini-LED array substrate includes a base substrate 900, a first conductive layer 100, and a second conductive layer 200. The first conductive layer 100 is disposed on one side of the base substrate 900, and the second conductive layer 200 is disposed on the side of the first conductive layer 100 away from the base substrate 900. An insulating layer 300 is disposed between the first conductive layer 100 and the second conductive layer 200, and an insulating layer 400 is disposed above the second conductive layer. An opening area is disposed on the insulating layer 400 to expose the terminal.

[0059] In the disclosed embodiment, the first conductive layer 100 is used to arrange various signal lines, including a first signal line group for driving the sensor, and a second signal line group for emitting light from the light-emitting element. In some embodiments, a sputtering process can be used to sequentially form a stacked structure of MoNb / Cu / MoNb, wherein the bottom layer MoNb is used to improve adhesion, the top layer MoNb is used for anti-oxidation, and the middle layer Cu is used as the main part of the signal line, and the material has the characteristics of low resistivity. At the same time, the width and thickness of the signal line can be further increased to further reduce the resistance of the signal line. In other embodiments, the middle layer Cu can be formed by an electroplating process, then the bottom layer can be made of MoNiTi as a seed layer by a sputtering process to increase the nucleation density of metal Cu grains during electroplating, and finally the anti-oxidation layer MoNiTi or MoNb is formed by a sputtering process.

[0060] The second conductive layer 200 is provided with a plurality of light emitting element terminal groups 10 coupled to the light emitting element. The second conductive layer 200 is also provided with a plurality of sensor terminal groups 30 connected to the sensor. The sensor terminal groups 30 are distributed between the light emitting element terminal groups 10, and the orthographic projection of the sensor terminal groups 30 on the substrate substrate does not overlap with the orthographic projection of the light emitting element terminal groups 10 on the substrate substrate. The second conductive layer 200 can be sequentially formed into a stacked structure of MoNb / Cu / CuNi by a sputtering process, wherein the bottom layer MoNb is used to improve adhesion, and the top layer surface adopts CuNi to take into account both anti-oxidation and solid crystal firmness.

[0061] It should be noted that the light emitting element terminal group 10 of the present disclosure is used to electrically connect the light emitting element to the second signal line group on the base substrate. The light emitting element can be bound to the array substrate by welding, so the light emitting element terminal group 10 can be a pad group. The light emitting element can also be directly prepared on the base substrate by a film forming process, so the light emitting element terminal group 10 can also be an electrode group that performs a conductive function. Similarly, the sensor terminal group 30 of the present disclosure can also be a pad group or an electrode group.

[0062] Providing sensors on the array substrate can quickly and effectively monitor the light emission of surrounding light-emitting elements, so as to timely and more precisely adjust various parameters such as current, voltage, brightness, etc. of the light-emitting elements to ensure stable performance of each light-emitting element.

[0063] The sensor can be of various types according to its function. For example, the sensor can be a temperature sensor to detect the temperature of the surrounding light-emitting elements and adjust the voltage, current and other parameters in time to avoid system insensitivity caused by overheating, or circuit burnout caused by excessive voltage and current. The sensor can also be a photosensitive sensor to detect the brightness of the surrounding light-emitting elements and adjust the brightness of each light-emitting element in time to make the light brightness of each light-emitting element consistent and stable. In one embodiment, the sensor can be an integrated sensor integrated on a chip, which is bound to the array substrate through the sensor terminal group 30.

[0064] The array substrate in the embodiment of the present disclosure is further described in detail below:

[0065] refer to Figure 1 and Figure 2, multiple light-emitting elements are arranged in an array, and a light-emitting unit 101 includes 4 light-emitting elements connected in series, wherein the light-emitting element electrically connected to the driving voltage signal line 202 is used as the starting point of the series connection of the 4 light-emitting elements, and the light-emitting element electrically connected to the control circuit is used as the end point of the series connection of the 4 light-emitting elements. The 4 light-emitting elements are driven by a control circuit. Therefore, a fourth lead 108 is also provided in the second conductive layer 200 of the array substrate, and the fourth lead 108 connects the 4 light-emitting element terminal groups 10 in sequence so that the 4 light-emitting elements are connected in series into a light-emitting unit 101. It should be noted that in the embodiment provided in the embodiment of the present disclosure, the number of light-emitting elements in each light-emitting unit is not limited, and can be any number such as 5, 6, 7, 8, etc., but not limited to 4. At the same time, the light-emitting element can be an LED or any other form of light-emitting element.

[0066] In some examples, in specific implementations, combined with Figure 1 As shown, the light-emitting elements in the same light-emitting unit 101 are sequentially connected to form a polygon. For example, when the light-emitting unit 101 includes 4 light-emitting elements, the 4 light-emitting elements can be sequentially connected to form a quadrilateral. Two sides of the quadrilateral can be parallel to the row direction, and the other two sides can be parallel to the column direction. Alternatively, two sides of the quadrilateral can also have an angle with the row direction, and the other two sides can also have an angle with the column direction. Therefore, the four light-emitting element terminal groups 10 in each light-emitting unit 101 are also arranged in a corresponding shape.

[0067] Correspondingly, the positions of the light emitting element terminal groups 10 corresponding to the four light emitting elements in a light emitting unit 101 are connected to each other to obtain a polygon (as shown by the dashed box X in the figure), specifically, a parallelogram. It is understandable that the vertices of the quadrilateral can be the geometric center of each light emitting element terminal group 10. It should be noted here that Figure 2 The dashed box X and Figure 1 The difference between the dashed box and Figure 2 The dotted frame X in the middle is used to indicate the location of the light emitting element terminal group 10. Figure 1 The dashed box in the middle only roughly depicts the division method of the light-emitting unit 101. In some examples, in a specific implementation, in the light-emitting units 101 adjacent in the row direction, the light-emitting elements located at the same position in each light-emitting unit 101 can be arranged roughly on the same straight line along the row direction. Further, in the light-emitting units adjacent in the column direction, the light-emitting elements located at the same position in each light-emitting unit 101 can be arranged roughly on a straight line along the column direction. Therefore, each light-emitting element terminal group 10 in the row direction and the column direction is also arranged according to the corresponding rule.

[0068] Further, among the four light-emitting element terminal groups 10 connected in series, the fourth lead 108 between any two light-emitting element terminal groups 10 connected in series through the fourth lead 108 includes a plurality of sub-segments extending along the row direction and / or the column direction. The fourth lead composed of a plurality of sub-segments along the row and column directions is easy to manufacture, and can reduce the probability of a short circuit between two terminals in the same light-emitting element terminal group, and reduce the risk of a fourth lead disconnection caused by a step difference between a signal line in the first conductive layer and a gap between adjacent signal lines. Figure 2 The fourth lead 108 of the upper left light emitting element terminal group 10 extends to the lower left light emitting element terminal group 10 along the column direction, the row direction, and the column direction in sequence.

[0069] refer to Figure 2 In one embodiment, the light emitting element terminal group 10 includes two terminals, one is an anode terminal 11, and the other is a cathode terminal 12. The anode terminal 11 is connected to an anode pin of the light emitting element, and the cathode terminal 12 is connected to another cathode pin of the light emitting element.

[0070] The light-emitting element of the present invention is driven by a control circuit to emit light, so the array substrate of the present invention is also provided with a drive circuit terminal group 20. Similar to the light-emitting element and the sensor, the drive circuit can also be integrated in the chip and bound to the array substrate by welding, so the drive circuit terminal group 20 can be a pad group, and can also be directly prepared on the base substrate by a film forming process, so the drive circuit terminal group 20 can also be an electrode group that performs a conductive function. It can be understood that the orthographic projection of the drive circuit terminal group 20 on the base substrate does not overlap with the orthographic projection of the light-emitting element terminal group 10 and the sensor terminal group 30 on the base substrate.

[0071] In one embodiment, the control circuit for driving the light-emitting element to emit light can be a microchip. The size of the microchip (e.g., length) can be in the order of tens or hundreds of microns, and the chip area is about tens of thousands of square microns or hundreds of square microns or even smaller, which is similar to the size of Mini-LED. It has the characteristics of miniaturization and is easy to integrate into the array substrate 10 (e.g., bound and coupled to the surface of the array substrate 10), which simplifies the overall structure and is conducive to achieving lightness and thinness. Each control circuit directly drives a light-emitting unit 101, avoiding the problems of complex operation and easy flickering of the row scanning control method. In addition, the driving circuit 110 has a small number of ports, a small number of required signals, a simple control method, a simple wiring method, and a low cost.

[0072] Figure 1 and Figure 2Also shown is the structure of a drive circuit terminal group 20 coupled to the drive circuit, the drive circuit terminal group 20 includes four terminals, namely an input terminal 21 for connecting to the Di pin of the drive circuit, a power supply terminal 22 for connecting to the Pwr pin of the drive circuit, an output terminal 23 for connecting to the Out pin of the drive circuit, and a common voltage terminal 24 for connecting to the Gnd pin of the drive circuit.

[0073] refer to Figure 1 and Figure 2 , a second signal line group for driving the light-emitting element to emit light is provided in the first conductive layer 100, and the second signal line group includes a second common voltage signal line 201, a driving voltage signal line 202, a power line 203, and a source address line 204; the above-mentioned input terminal 21 is configured to receive a first input signal, and the first input signal is, for example, an address signal, for selecting the driving circuit of the corresponding address. For example, the first input signal can be the 8-bit starting address information transmitted from the source address line 204, and the address of the first driving circuit corresponding to it can be known by parsing the address signal. The power terminal 22 is configured to receive a second input signal, and the second input signal is, for example, a power line carrier communication signal from the power line 203. The second input signal not only provides electrical energy for the driving circuit, but also transmits communication data to the driving circuit, and the communication data can be used to determine the light-emitting duration of the corresponding light-emitting unit, thereby controlling its visual light-emitting brightness. The output terminal 23 is configured to output a relay signal to the next-level driving circuit in a cascade relationship in a first time period, and the relay signal includes address information. By parsing the address signal, the address of the corresponding driving circuit can be known; the output terminal 23 is also configured to form a signal loop for the corresponding light-emitting unit in a second time period, so that the light-emitting unit can emit a corresponding brightness. The common voltage terminal 24 is configured to receive a common voltage signal, such as a ground signal from the second common voltage signal line 201. In the embodiment of the present disclosure, the above-mentioned second common voltage signal line 201, the driving voltage signal line 202, the power line 203, and the source address line 204 all extend in the column direction and are arranged at intervals in the row direction.

[0074] Combination Figure 1 As shown, the arrangement of four light-emitting elements and a driving circuit in a light-emitting unit 101 is used as a repeating unit, and the array substrate may include a plurality of repeating units, and adjacent repeating units are arranged at intervals and periodically arranged along the row direction and the column direction. In this way, a light-emitting unit group can be repeatedly arranged as a repeating unit. For example, in the plurality of light-emitting units arranged in the column direction, the relative positions of the plurality of light-emitting elements and the driving circuit in each light-emitting unit can be substantially the same; and in the light-emitting units arranged in the row direction, the relative positions of the plurality of light-emitting elements and the driving circuit in two adjacent light-emitting units can be arranged in a centrally symmetrical manner.

[0075] like Figure 2 As shown, the drive circuit terminal group 20 is located outside the quadrilateral (shown by the dotted box X in the figure) obtained by sequentially connecting the positions of the four light-emitting element terminal groups 10 connected in series, so as to facilitate the wiring design of the fourth lead 108 and minimize the influence of the drive circuit on the light emission of the light-emitting element. It can be understood that when each light-emitting unit includes n×m light-emitting element terminal groups, the positions of the multiple light-emitting element terminal groups located at the outermost sides of the light-emitting unit can be sequentially connected to obtain a polygon, and the drive circuit terminal group 20 is located outside the polygon. Here, the positions of the outermost light-emitting element terminal groups in the light-emitting unit refer to the geometric centers of the above-mentioned light-emitting element terminal groups; the non-outermost light-emitting element terminal groups in the light-emitting unit are located inside the aforementioned polygon.

[0076] For ease of description, the light emitting units 101 in the array substrate are labeled according to the arrangement of rows and columns according to coordinates. For example, there are a total of P rows and Q columns of light emitting units 101 on the array substrate, and the light emitting unit 101 in the ath row and bth column can be mapped to the coordinates (a, b), 1≤a≤P, 1≤b≤Q, and P, Q, a, and b are all positive integers. Figure 3 Schematic diagram showing the arrangement structure and coordinates of some light emitting units 101 .

[0077] In one embodiment, the locations of the drive circuit terminal groups corresponding to the four light-emitting units 101 with coordinates (a, b), (a+1, b), (a, b+1), and (a+1, b+1) are connected in sequence to obtain a convex quadrilateral, such as a parallelogram, specifically, a rectangle or a square. Obviously, each convex quadrilateral is composed of two triangles, and the two triangles are composed of the locations of the three drive circuit terminal groups 20 in the four light-emitting units 101.

[0078] In some embodiments, each parallelogram may be composed of two isosceles triangles or regular triangles, and the isosceles triangles or regular triangles are composed of the positions of three drive circuit terminal groups 20 in the four light-emitting units 101. When each parallelogram is composed of two regular triangles, the distances between the drive circuit terminal groups 20 can be close. It should be noted that the "isosceles triangle" and "regular triangle" described here are idealized descriptions. In actual products, due to the influence of process and equipment accuracy, the general shape can be an isosceles triangle or regular triangle.

[0079] In some embodiments, reference Figure 1-Figure 3, the drive circuit terminal group 20 in the light-emitting unit (1, 1), the drive circuit terminal group 20 in the light-emitting unit (1, 2), and the drive circuit terminal group 20 in the light-emitting unit (2, 1) are respectively located at the three vertices of a triangle, for example, they can be the three vertices of a first triangle. The drive circuit terminal group 20 in the light-emitting unit (2, 1), the drive circuit terminal group 20 in the light-emitting unit (1, 2), and the drive circuit terminal group 20 in the light-emitting unit (2, 2) can be respectively located at the three vertices of a triangle, for example, they can be the three vertices of a second triangle. The drive circuit terminal group 20 in the light-emitting unit (2, 1), the drive circuit terminal group 20 in the light-emitting unit (2, 2), and the drive circuit terminal group 20 in the light-emitting unit (3, 1) can be respectively located at the three vertices of a triangle, for example, they can be the three vertices of a third triangle. The drive circuit terminal group 20 in the light-emitting unit (3, 1), the drive circuit terminal group 20 in the light-emitting unit (2, 2), and the drive circuit terminal group 20 in the light-emitting unit (3, 2) can be respectively located on three vertices of a triangle, for example, on the three vertices of a fourth triangle. The drive circuit terminal group 20 in the light-emitting unit (1, 2), the drive circuit terminal group 20 in the light-emitting unit (1, 3), and the drive circuit terminal group 20 in the light-emitting unit (2, 3) can be respectively located on the three vertices of a triangle, for example, on the three vertices of a fifth triangle; the drive circuit terminal group 20 in the light-emitting unit (2, 3), the drive circuit terminal group 20 in the light-emitting unit (1, 2), and the drive circuit terminal group 20 in the light-emitting unit (2, 2) can be respectively located on the three vertices of a triangle, for example, on the three vertices of a sixth triangle; the drive circuit terminal group 20 in the light-emitting unit (1, 3), the drive circuit terminal group 20 in the light-emitting unit (1, 4), and the drive circuit terminal group 20 in the light-emitting unit (2, 3) can be respectively located on the three vertices of a triangle, for example, on the three vertices of a seventh triangle.

[0080] Among them, the line connecting the centroids of any two adjacent triangles in the row direction or column direction is parallel to the row direction or column direction. For example, the line connecting the centroid of the first triangle and the centroid of the third triangle is parallel to the column direction; and the line connecting the centroid of the second triangle and the centroid of the fourth triangle is also parallel to the column direction. The line connecting the centroid of the first triangle, the centroid of the fifth triangle, and the centroid of the seventh triangle is parallel to the row direction; and the line connecting the centroid of the second triangle and the centroid of the sixth triangle is parallel to the row direction.

[0081] The arrangement rules of other drive circuit terminal groups 20 are the same as above, and so on, which will not be described in detail here.

[0082] The arrangement of the drive circuit terminal group 20 corresponding to the multiple light-emitting units 101 on the array substrate can be designed according to the above rules, which will not be described in detail here. In some examples, in the specific implementation, along the row direction, the arrangement of the light-emitting element terminal group 10 and the drive circuit terminal group 20 corresponding to a light-emitting unit is used as a repeating unit, and the array substrate may include multiple repeating units, and the adjacent repeating units are arranged at intervals and arranged periodically along the row direction. In this way, a light-emitting unit can be repeatedly arranged as a repeating unit to form an array substrate. In this way, the relative positions of the multiple light-emitting element terminal groups 10 and the drive circuit terminal groups 20 in each light-emitting unit arranged in the row and column directions can be basically the same.

[0083] refer to Figure 4 , is a schematic diagram of the structure of a sensor terminal group 30, the sensor terminal group 30 includes an R for connecting to the sensor x Pin 31 is connected to the input terminal for the sensor T x Pin connected to output terminal 32, used to connect to the sensor's V + A power supply terminal 33 connected to the pin, and a common voltage terminal 34 for connecting to the Gnd pin of the sensor.

[0084] Figure 5 for Figure 4 In the cross-sectional schematic diagram along the AA direction, a first signal line group for driving the sensor for sensing is provided in the first conductive layer 100, and the first signal line group includes an input signal line 101, an output signal line 102, a power signal line 103 and a first common voltage signal line 104. The above signal lines extend in the column direction and are arranged in the row direction. The input terminal 31 is electrically connected to the input signal line 101, the output terminal 32 is electrically connected to the output signal line 102, the power terminal 33 is electrically connected to the power signal line 103, and the common voltage terminal 34 is electrically connected to the first common voltage signal line 104.

[0085] The first common voltage signal line 104 and the second common voltage signal line 201 both provide a ground voltage, so the second common voltage signal line 201 and the first common voltage signal line 104 can be combined into one signal line, thereby providing a common voltage signal to the sensor and the driving circuit at the same time without increasing the number of signal lines.

[0086] The sensor provided by the embodiment of the present disclosure can be used to sense temperature. For example, the sensor includes a thermistor, which uses the voltage change between its base and emitter to sense temperature change; it also includes an analog-to-digital conversion unit to convert an analog signal representing the voltage change into a digital signal; further, it can also include a signal processor such as denoising and filtering to further process the digital signal, so that the corresponding temperature change measurement value converted from the digital signal is more accurate; by comparing the measured value of the temperature change with the standard value, the cause of the temperature change can be determined, such as the line problem such as the current in the temperature area to be measured or the packaging problem in the temperature area to be measured; by adjusting or repairing different problems, the effect of temperature monitoring and improving product yield can be achieved.

[0087] The sensor terminal group 30 may be located at the gap between two adjacent light emitting units, such as Figure 2 In other embodiments, the sensor terminal group 30 may also be located between the light emitting element terminal groups 10 in the light emitting unit, as long as the area where the light emitting unit is located can be sensed. Regardless of the arrangement, multiple sensor terminal groups 30 may be arranged in an array along the row direction and the column direction on the array substrate, so that the sensor can monitor the temperature of light emitting units in different areas.

[0088] The number of sensors is designed according to the sensing accuracy requirements of the array substrate, and may be multiple or only one. Correspondingly, the number of the sensor terminal group 30 is also one or more.

[0089] In the present disclosure, in order to achieve more accurate inspection and regulation, the number of sensor terminal groups 30 is multiple and distributed in the gaps between the light-emitting units. Figure 6 As an example, it is a schematic diagram of an arrangement of sensor terminal groups 30 and signal lines, and the figure schematically shows a structure in which 15 sensor terminal groups 30 are evenly arranged in a manner of 3 rows and 5 columns on an array substrate.

[0090] It is understandable that the number and arrangement of the sensor terminal group 30 are not unique. Each sensor can sense the light-emitting elements around it. In order to ensure that the sensing data is helpful to monitor the actual performance of the light-emitting elements, the number and position of the sensors can be set according to the number and range of the light-emitting elements that each sensor can sense, so that all the sensing ranges of the sensors can just cover all the light-emitting elements without repeated sensing. Figure 6The sensor terminal groups are distributed in the row direction and the column direction, and the sensor terminal groups in each row or column are located on the same straight line, and the intervals between two adjacent sensor terminal groups are the same, so that the test is more accurate. In other embodiments, according to the test requirements, the sensors in each row or column can also be arranged in other forms, for example, the sensors in each row or column are not located on the same straight line, as long as the sensing purpose can be achieved.

[0091] The connection relationship of the sensors is described below. The array substrate may have N sensors, where N is greater than or equal to 1 and is an integer.

[0092] In some cases, N sensors are cascaded with each other, that is, the T x Pin and R of the (n+1)th sensor x pins are connected, and the R x The pin is connected to the input signal line 101, and the T x The pin is connected to the output signal line 102, and n is an integer greater than 1 and less than N-1. x The pin is connected to the input signal line 101 through the input terminal 31 in the sensor terminal group corresponding to the sensor, and is used to receive the input signal; the output pin T of the Nth level sensor x The output terminal 32 in the corresponding sensor terminal group is connected to the output signal line 102 to transmit the sensor sensed signal to the external circuit. The input signal is generated based on a communication protocol to perform a series of configurations and settings on the sensors at each level: in the power-on stage, the input signal is configured to assign address information to the first-level sensor to the N-th-level sensor in turn; in the initial configuration stage, the input signal is configured to sequentially specify the sensing accuracy and sensing range of the first-level sensor to the N-th-level sensor for physical quantities (such as temperature); in the sensing stage, the input signal is configured to specify the x-th-level sensor to perform the sensing function and output the corresponding sensing signal. It can be understood that in the sensing stage, only one sensor performs the sensing function at a time, and the other sensors at each level can be equivalent to (N-1) resistors connected in series with the sensor performing the sensing function, so as to realize the sensing at a specific position of the array substrate. Therefore, in the sensing stage, the input signal can be configured to sequentially specify the sensors at each level to perform the sensing function, so as to obtain the sensing signals at all positions on the array substrate.

[0093] In some cases, the N sensors may also be independent of each other. In order to avoid too many signal lines and complicated overall wiring, the sensors in the same column may be connected to the same power signal line 103, the same input signal line 101 and the same output signal line 102. xThe pin is connected to the input signal line 101 through the input terminal 31 in the sensor terminal group corresponding to the sensor, and is used to receive the input signal; the output pin T of each sensor x The output terminal 32 in the corresponding sensor terminal group is connected to the output signal line 102 to transmit the signal sensed by the sensor to the external circuit. Each sensor is pre-set with address information, and the address information of each sensor is different. The input signal is generated based on a communication protocol to configure and set each sensor. In the initial configuration stage, the input signal with address information is configured to specify the sensing accuracy and sensing range of the corresponding sensor for the physical quantity (such as temperature); in the sensing stage, the input signal with address information is configured to specify a certain sensor to perform a sensing function and output a corresponding sensing signal. It can be understood that in the sensing stage, only one sensor performs the sensing function at a time, and other sensors connected to the same input signal line 101 and the same output signal line 102 as the sensor performing the sensing function do not work, so that sensing at a specific position of the array substrate can be achieved. Therefore, in the sensing stage, the input signal can be configured to sequentially specify sensors at different positions to perform the sensing function, so that sensing signals at all positions on the array substrate can be obtained.

[0094] In one embodiment, reference Figure 1-Figure 7 ,in, Figure 6 correspond Figure 1 The arrangement of the sensor terminal group 30 and the signal lines in the array substrate, Figure 7 Shows Figure 6 The structure of the first conductive layer 100 is shown in FIG. As shown in the figure, the number of input signal lines 101 is equal to the number of sensor terminal groups 30 in the row direction, and the number of output signal lines 102 is also equal to the number of sensor terminal groups 30 in the row direction. In the column direction, the input terminals 31 of each sensor terminal group 30 located in the same column are connected to the same input signal line 101, and the output terminals 32 of each sensor terminal group 30 located in the same column are connected to the same output signal line 102. In other words, only one input signal line 101 and one output signal line 102 are provided in each column, thereby reducing the number of input signal lines 101 and output signal lines 102.

[0095] In another embodiment, reference Figure 8-Figure 12 , Figure 8 The signal line arrangement of the sensor terminal group 30 in this embodiment is shown. Fig. 9 FIG. 1 shows a partial structural diagram of the array substrate of this embodiment. Fig.10 for Fig. 9 A partial enlarged schematic diagram of the middle M area. Fig.11 for Fig. 9FIG. 1 is a schematic structural diagram of a sensor terminal group 30 . Fig.12 Shows Figure 8 The wiring method of the first conductive layer 100 in FIG. As shown in the figure, the number of input signal lines 101 is equal to the number of sensor terminals in the row direction, and the number of output signal lines 102 is equal to the number of sensor terminals in the row direction. In the column direction, in two adjacent sensor terminal groups 30 located in the same column, the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30; in each sensor terminal group 30 located in the same column, the input terminal 31 of the first sensor terminal group 30 is connected to an input signal line 101, and the output terminal 32 of the last sensor terminal group 30 is connected to an output signal line 102, so that all sensors in each column are connected in series, and the signal used to configure the sensor can be transmitted to each sensor in the same column.

[0096] For example, in the structure shown in the figure, the input terminal 31 of the sensor terminal group 30 in the bottom row of the first column is connected to the input signal line 101, and its output sub-terminal 32 is connected to the input terminal 31 of the sensor terminal group 30 in the second to last row of the column, and the input terminal 31 of the sensor terminal group 30 in the second to last row of the column is connected to the input terminal 31 of the sensor terminal group 30 in the third to last row of the column. According to this rule, the output terminal 32 of the sensor terminal group 30 in the top row of the first column is connected to the output signal line 102, so that the sensors in the first column can be connected in series. According to the same rule, the sensor terminal groups 30 in each column are connected so that the sensors in each column can be connected in series. Based on this series connection form, each column is only provided with one input signal line 101 and one output signal line 102, and the input signal line 101 and the output signal line 102 only need to be respectively provided above and below the array substrate, and can be connected to the array substrate binding area through edge routing, without having to run through the entire array substrate from top to bottom. Figure 5 The wiring method shown further reduces the space occupied by the lines.

[0097] In this embodiment, since the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30 in two adjacent sensor terminal groups 30 , the two input terminals can be connected by providing a lead wire in the second conductive layer 200 .

[0098] In one embodiment, reference Fig.13, the array substrate further includes a plurality of first leads 105, the first leads 105 connecting the output terminals and input terminals of two adjacent sensor terminal groups 30. The first leads 105 include first column leads 1051 extending in the column direction and first row leads 1052 extending in the row direction, each first column lead 1051 is provided in the first conductive layer 100, each first row lead 1052 is provided in the second conductive layer 200, and the first column leads 1051 and the first row leads 1052 are electrically connected through vias. Taking the first lead 105 shown in the figure as an example, the first lead 105 includes a first column lead 1051 and two first row leads 1052, the two first row leads 1052 extend horizontally from the output terminal and the input terminal respectively, and the two first row leads 1052 are electrically connected to the longitudinal first column lead 1051 through vias at the same time, so that the output terminals and input terminals of two adjacent sensor terminal groups 30 are electrically connected. Fig.13 (a) shows the case where the first column lead 1051 and the first row lead 1052 do not cross each other, Fig.13 (b) shows the situation where the first column lead 1051 and the first row lead 1052 cross each other.

[0099] In this embodiment, the first column leads 1051 connected to the sensor terminal groups 30 in the same column are arranged along the column direction, so that all the first column leads 1051 occupy the least space in the column direction.

[0100] In yet another embodiment, reference Figure 14-17 , Fig.14 The signal line arrangement of the sensor terminal group 30 in this embodiment is shown. Fig.15 FIG. 1 shows a partial structural diagram of the array substrate of this embodiment. Fig.15 A partial enlarged schematic diagram of the middle M area Fig.10 same, Fig.16 for Fig.14 FIG. 1 is a schematic structural diagram of a sensor terminal group 30 . Fig.17 Shows Fig.14The wiring method of the first conductive layer 100 in the array substrate. As shown in the figure, the number of input signal lines 101 and the number of output signal lines 102 are both 1. In the column direction, in two adjacent sensor terminal groups 30 located in the same column, the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30. In other words, all sensors in each column are connected in series. Further, in two adjacent columns of sensor terminal groups 30, the output terminal 32 of one column of the sensor terminal group 30 located in the first row or the last row is electrically connected to the input terminal 31 of the other column of the sensor terminal group 30 located in the first row or the last row, so that all sensors are connected in series. In all sensor terminal groups 30 connected in series, the input terminal 31 of the first sensor terminal group 30 is connected to the input signal line 101, and the output terminal 32 of the last sensor terminal group 30 is connected to the output signal line 102, so that the signal used to configure the sensor can be transmitted to all sensors on the array substrate.

[0101] Fig.17 A schematic diagram of the transmission path of the input signal and the output signal corresponding to this embodiment is shown, Fig.18 The figure schematically shows a structure in which 15 sensor terminal groups 30 are arranged in an array on an array substrate in the form of 3 rows and 5 columns, and the 15 points A, B, C, ..., M, N, O represent 15 sensors respectively; each small square in the figure represents a light-emitting unit, each small square on the horizontal axis represents a column of light-emitting units, and each small square on the vertical axis represents a row of light-emitting units. All light-emitting units are arranged in an array in rows and columns, and the sensor terminal group 30 has no overlap with the orthographic projection of the light-emitting unit on the array. Fig.18 The coordinate values ​​next to the letters in are used to indicate the position of the terminal sensor on the array substrate. For example, A(8.5, 38.5) indicates that the sensor terminal A is located between the 8th and 9th columns of light-emitting units, and between the 38th and 39th rows of light-emitting units.

[0102] In some embodiments, the m×n sensors are connected in series in an S-shaped manner, row by row, or the m×n sensors are numbered in a Z-shaped manner, row by row, and column by column. Fig.18As shown, when m=3 and n=5, sensor A is connected to the input signal line 101 through the input terminal 31 of the corresponding sensor terminal group 30, and then sensor A and each sensor in the same column are connected in series in sequence, for example, sensor A, sensor B, and sensor C are connected in series in sequence; then sensor C is connected in series with the most adjacent sensor D in the same row; sensor D and each sensor in the same column are connected in series in sequence, for example, sensor D, sensor E, and sensor F are connected in series in sequence; and so on, sensor O is connected to the output signal line 102 through the output terminal 32 of the corresponding sensor terminal group 30, so as to realize the series connection of 15 sensor groups 30. Based on this series connection form, at least one input signal line 101 and one output signal line 102 are required to be set on the array substrate, and the input signal line 101 and the output signal line 102 only need to be connected to the first and last two sensors of the multiple sensors that are in a series connection relationship, respectively, without having to run through the entire array substrate from top to bottom. Compared with this series connection form, Figure 6 The connection method between the sensor terminal groups corresponding to the multiple sensors and the signal lines shown can greatly reduce the number of signal lines, thereby saving the wiring space of the array substrate. In this embodiment, since the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30 in two adjacent sensor terminal groups 30, the two terminals can be connected by providing a lead wire on the second conductive layer 200.

[0103] In one embodiment, reference Fig.16 , the array substrate further includes a plurality of first leads 105, the first leads 105 connecting the output sub-terminals and the input sub-terminals of two adjacent sensor terminal groups 30. The first leads 105 include first column leads 1051 extending in the column direction and first row leads 1052 extending in the row direction, each first column lead 1051 is provided in the first conductive layer 100, each first row lead 1052 is provided in the second conductive layer 200, and the first column leads 1051 and the first row leads 1052 are electrically connected through vias. Taking the first lead 105 shown in the figure as an example, the first lead 105 includes a first column lead 1051 and two first row leads 1052, the two first row leads 1052 extend horizontally from the output sub-terminal and the input sub-terminal respectively, and the two first row leads 1052 are electrically connected to the longitudinal first column lead 1051 through vias at the same time, so that the output terminals 32 and the input terminals 31 of the two adjacent sensor terminal groups 30 are electrically connected. Fig.16 (a) shows the case where the first column lead 1051 and the first row lead 1052 do not cross each other, Fig.16 (b) shows the situation where the first column lead 1051 and the first row lead 1052 cross each other.

[0104] In this embodiment, the first column leads 1051 connected to the sensor terminal groups 30 in the same column are arranged along the column direction, so that all the first column leads 1051 occupy the least space in the column direction.

[0105] refer to Figure 6 , Figure 8 , Fig.14 In these embodiments, the number of power signal lines 103 is equal to the number of sensor terminals in the row direction; in the column direction, the power terminals 33 of each sensor terminal group 30 in the same column are connected to the same power signal line 103, thereby reducing the number of power signal lines 103. Since the power signal line 103 extends along the column direction, the power terminal 33 can be connected to the power signal line 103 by providing a horizontal lead in the second conductive layer 200. Figure 7 , Fig.12 , Fig.17 In the structure shown, the power signal line 103 and the first column lead 1051 are arranged side by side, and a sufficient distance should be reserved between the two to avoid mutual interference of signals.

[0106] Similarly, reference Figure 6 , Figure 8 , Fig.14 In these embodiments, the number of first common voltage signal lines 104 is also equal to the number of sensor terminal groups 30 in the row direction; in the column direction, the common voltage terminals 34 of each sensor terminal group 30 in the same column are connected to the same first common voltage signal line 104 (that is, the second common voltage signal line 201), thereby reducing the number of common voltage signal lines.

[0107] In one embodiment, the array substrate further includes a common voltage signal line auxiliary line 205 disposed in the second conductive layer 200, and the common voltage signal line auxiliary line 205 is electrically connected to the first common voltage signal line through a via hole, so as to increase the signal transmission path through two layers of routing and improve the signal transmission strength. Figure 19-21 , Fig.19 FIG. 1 shows a partial structural diagram of the array substrate of this embodiment. Fig. 20 for Fig.19 A partial enlarged schematic diagram of the middle M area. Fig.21Schematic diagram of the structure of a sensor terminal group 30 in this embodiment. The figure shows an exemplary wiring method of a common voltage signal line auxiliary line 205. The common voltage signal line is in a grid shape and covers the gaps between the adjacent light-emitting units. In the thickness direction of the array substrate, the common voltage signal line auxiliary line 205 of this embodiment is located above the driving voltage signal line 202. Since the sensor terminal and the common voltage signal line auxiliary line 205 are both located in the second conductive layer 200, the common voltage sub-terminal 34 can be directly connected to the common voltage signal line auxiliary line 205. In other embodiments, the common voltage signal line auxiliary line 205 can also be in other shapes, and the present disclosure does not specifically limit this.

[0108] The terminal groups 30 of the above-mentioned structures and the corresponding connected signal lines all need to occupy the wiring space of the array substrate. In one embodiment, the orthographic projections of the sensor terminal group 30, the light-emitting element terminal group 10, and the drive circuit terminal group 20 on the base substrate at least partially overlap with the orthographic projections of the second signal line group on the base substrate, so as to save wiring space. Furthermore, the orthographic projections of the sensor terminal group 30 on the base substrate and the orthographic projections of the light-emitting element terminal group 10 and the drive circuit terminal group 20 on the base substrate are respectively located in the orthographic projections of different signal lines in the second signal line group on the base substrate. Specifically, in the case Figure 1 , Fig. 9 , Fig.15 In the illustrated embodiment, the light emitting element terminal group 10 occupying most of the space has its orthographic projection on the base substrate 900 overlapping with the orthographic projection of the wider second common voltage signal line 201, the orthographic projection of the driving circuit terminal group 20 on the base substrate also overlaps with the orthographic projection of the second common voltage signal line 201, and the orthographic projection of the sensor terminal group 30 on the base substrate 900 overlaps with the orthographic projection of the driving voltage signal line 202, thereby saving wiring space.

[0109] For the above-mentioned input signal line 101, output signal line 102, power signal line 103, and first lead 105, each signal line corresponding to each column of sensor terminal group 30 is located between a second common voltage signal line 201 and a driving voltage signal line 202. In order to make the best use of the existing space for wiring, the edge of the second common voltage signal line 201 or the driving voltage signal line 202 can be appropriately grooved. If there are at least two signal lines that are adjacent in the column direction and extend along the column direction, and there is an overlapping area in their orthographic projections on any straight line parallel to the column direction, the position of the groove can correspond to the overlapping area, so that the at least two adjacent signals can obtain a larger wiring space, thereby improving the utilization rate of the substrate. Reference Fig.16(b), it can be understood that, since there is an overlapping area in the orthographic projections of two adjacent first column leads 1051 extending longitudinally on any straight line parallel to the column direction, the size of the portion of the two first column leads 1051 corresponding to the overlapping area in the row direction is relatively wide (including the line width of a single first column lead 1051 and the spacing between adjacent first column leads 1051 in the row direction). By providing a groove 5 on the left side of the second common voltage signal line 201 (i.e., the position corresponding to the overlapping area), the portion of the two first column leads 1051 corresponding to the overlapping area can correspond to a larger space in the row direction. The shape of the groove 5 includes but is not limited to the rectangle in the figure, and the size or position of the groove 5 can be designed according to the routing method of the size of each signal line or lead, and this application does not specifically limit it.

[0110] In one embodiment, reference Fig.23 The array substrate further includes a plurality of capacitor terminal groups 40, which are arranged on the second conductive layer 200 and are used for binding capacitors. The capacitor terminal group 40 includes a first capacitor terminal 41 and a second capacitor terminal 42. The first capacitor terminal 41 is interconnected with the power terminal 33, and the second capacitor terminal 42 is interconnected with the common voltage terminal 34, thereby reducing the noise generated by the sensor and making the overall electrical stability of the array substrate more stable.

[0111] Fig. 22 for Fig.18 The middle M area includes a partial enlarged schematic diagram of the capacitor terminal group 40, Fig.23 Schematic diagram of a structure of the capacitor terminal group 40. The array substrate further includes a second lead 106 and a third lead 107 provided on the second conductive layer 200, one end of the second lead 106 is connected to the first capacitor terminal 41, and the other end is connected to the power signal line 103 through a via hole, and one end of the third lead 107 is connected to the first capacitor terminal 41, and the other end is connected to the power terminal 33 of the sensor terminal group 30.

[0112] like Fig.23As shown, in this embodiment, since the common voltage signal line auxiliary line 205 is arranged on the second conductive layer 200, the common voltage terminal 34 is directly connected to the common voltage signal line auxiliary line 205, therefore, the second capacitor terminal 42 of the capacitor terminal group 40 is also connected to the common voltage signal line auxiliary line 205, that is, electrically connected to the first common voltage signal line 104, so as to conduct the static electricity generated near the capacitor to the common voltage signal line, and avoid the static electricity discharge from damaging the array substrate. It should be noted that the common voltage terminal 34, the second capacitor terminal 42 and the common voltage signal line auxiliary line are all arranged on the second conductive layer 200. It can be understood that the common voltage signal line auxiliary line 205 and other signal lines arranged on the second conductive layer need to be covered by an insulating layer to prevent the line from being oxidized and affecting the electrical performance; and the upper surface of each terminal arranged on the second conductive layer needs to be electrically connected to the components, so it is exposed. Therefore, the common voltage terminal 34 and the second capacitor terminal 42 can also be regarded as part of the common voltage signal line auxiliary line 205.

[0113] It should be noted that the “extending along the direction” and “extending along the column direction” mentioned in the present disclosure refer to the overall direction of the signal line along the row direction or column direction, which may allow local bending to avoid other circuit structures or tilting within the range of process errors, and is not limited to a standard straight line.

[0114] The array substrate provided in the embodiment of the present disclosure can be used as a substrate with a light-emitting function by installing a light-emitting device, and can also be further applied to a display device as a backlight unit.

[0115] After the light-emitting elements, sensors, and driver chips are installed on the array substrate of the present disclosure, a hemispherical microstructure can be made above the light-emitting elements, sensors, and driver chips to protect the above structures from being scratched during production and transportation. Specifically, the microstructure above the light-emitting element is a light-transmitting material, which can further have an optical shaping effect on the emitted light of the light-emitting element, such as improving the light efficiency or increasing the light output at a positive viewing angle, while the microstructure above the sensor and driver chip can be made of a transparent material or a material with a light-absorbing effect, which is not limited here.

[0116] The embodiment of the present invention further provides a display device, which includes the array substrate in the above embodiment. Since the display device includes the above array substrate, it has the same beneficial effects, and the present invention will not be repeated here.

[0117] The present invention does not impose any specific restrictions on the applicability of the display device, which can be any product or component with a flexible display function, such as a television, a laptop computer, a tablet computer, a wearable display device, a mobile phone, a car display, a navigation, an e-book, a digital photo frame, an advertising light box, etc.

[0118] Those skilled in the art will readily appreciate other embodiments provided by the embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations provided by the embodiments of the present disclosure, which follow the general principles provided by the embodiments of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are intended to be exemplary only, and the true scope and spirit provided by the embodiments of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a base substrate, on which a first conductive layer and a second conductive layer insulated from each other are stacked, wherein the array substrate further comprises: A plurality of array-arranged light-emitting element terminal groups are provided on the second conductive layer and are used for coupling with the light-emitting elements; A plurality of sensor terminal groups are provided on the second conductive layer and are used to couple with sensors; the orthographic projection of the sensor terminal group on the substrate substrate does not overlap with the orthographic projection of the light emitting element terminal group on the substrate substrate; the sensor terminal group includes an input terminal and an output terminal; the corresponding sensor includes an input pin and an output pin, the input terminal is used to be electrically connected to the input pin, and the output terminal is used to be electrically connected to the output pin; A first signal line group, provided in the first conductive layer, electrically connected to the sensor terminal group, and used to drive the sensor to perform sensing; A second signal line group, provided in the first conductive layer, electrically connected to the light emitting element terminal group, and used for driving the light emitting element to emit light; A plurality of first leads; wherein the first leads connect the output terminal of one of the two adjacent sensor terminal groups with the input terminal of the other sensor terminal group.

2. The array substrate according to claim 1, characterized in that: The first leads include first column leads extending along the column direction and first row leads extending along the row direction. Each of the first column leads is arranged in the first conductive layer, each of the first row leads is arranged in the second conductive layer, and the first column leads and the first row leads are electrically connected through vias.

3. The array substrate according to claim 2, characterized in that: At least one of the first leads includes one first column lead and two first row leads, the two first row leads extend from the output terminal and the input terminal of two adjacent sensor terminal groups along the row direction respectively, and the two first row leads are electrically connected to the first column lead through vias at the same time.

4. The array substrate according to claim 2, characterized in that: The first column leads connecting the sensor terminal groups located in the same column are arranged along the column direction.

5. The array substrate according to claim 2, characterized in that: The sensor terminal group further includes a power terminal; the corresponding sensor further includes a power pin, and the power terminal is used to be electrically connected to the power pin; The first signal line group includes a power signal line; the power terminal is electrically connected to the power signal line; The power signal line and the first column lead are arranged side by side and at intervals.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The m×n sensors are connected in series in an S-shaped manner, row by row and column by column; wherein m and n are both integers; m is the number of rows of the sensors connected in series, and n is the number of columns of the sensors connected in series.

7. The array substrate according to claim 6, characterized in that: In two adjacent sensors of the m×n sensors sequentially connected in series in an S-shape, column by column and row by row, an output pin of one of the sensors is electrically connected to an input pin of the other sensor through the first lead.

8. The array substrate according to claim 6, characterized in that: The first signal line group includes an input signal line and an output signal line; Among all the sensors connected in series, the input terminal of the sensor terminal group corresponding to the sensor at one end is connected to the input signal line, and the output terminal of the sensor terminal group corresponding to the sensor at the other end is connected to the output signal line.

9. A light-emitting substrate, characterized in that: include: The array substrate according to any one of claims 1 to 8; A light emitting element coupled to the light emitting element terminal group of the array substrate; The sensor is coupled to the sensor terminal group of the array substrate.

10. A display device, characterized in that: Comprising the light-emitting substrate as described in claim 9.

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