Large scale independent tester system

Abstract

Apparatuses, systems, methods, and computer program products for a large scale independent tester system 100, 300, 400, 500 are disclosed. An apparatus includes a controller 102, 302, a substrate 104, 106, 110, 112, 402, a device interface board 110, a plurality of tester modules 126a-n, 406a-n, and / or one or more interface buses 118 mounted on the substrate 104, 106, 110, 112, 402. One or more components (326, 328, 330, 332, 334, 412, 414, 416, 418) for the tester modules (126a-n, 406a-n) are mounted on the device interface board (110). The tester modules (126a-n, 406a-n) are configured to perform both independent function tests and parameter tests. One or more interface buses 118 are in communication with the controller 102, 302, the plurality of tester modules 126a-n, 406a-n, and / or the device interface board 110 to provide one or more of power and communication links.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuits, and more particularly to a tester system for semiconductor integrated circuit devices. Background Art

[0002] Since its birth, semiconductor chip testing in the form of wafers has not changed much. For example, a general automatic test equipment (ATE) tester can be used to test a specific product chip or die on a wafer by contacting the die or device under test (DUT) on the wafer with a probe to complete electrical testing, etc. After the test is completed, the wafer chuck can move down and disconnect the contact between the DUT and the probe, move to the next die and repeat the process until all the dies on the wafer are tested. General ATE may be very expensive, take up a lot of space, and it is difficult to provide different temperature environments for testing. Such conventional wafer-level test methods need to be changed, especially for large batches of chips and small chips. Summary of the invention

[0003] An apparatus for a large-scale independent tester system is disclosed. In one embodiment, the apparatus includes a controller. In some embodiments, the apparatus includes a substrate. In another embodiment, the apparatus includes a device interface board. In certain embodiments, the apparatus includes a plurality of tester modules mounted on the substrate. In some embodiments, one or more components for testing are mounted on the device interface board. In one embodiment, one or more tester modules are configured to perform independent functional and / or parametric tests. In certain embodiments, one or more interface buses communicate with the controller, the plurality of tester modules, and / or the device interface board, thereby providing one or more of power and communication links.

[0004] Other devices for large-scale independent tester systems are disclosed. In one embodiment, the device includes a controller. In another embodiment, the device includes a tester wafer. In some embodiments, the device includes a device interface board. In certain embodiments, the device includes multiple independent tester dies of the tester wafer. In some embodiments, one or more components of the tester die are mounted on the device interface board. In one embodiment, the tester die is configured to perform independent functional tests and / or parameter tests. In another embodiment, one or more interface buses communicate with the controller and / or multiple independent tester dies to provide one or more of power and communication links to the controller and / or multiple independent tester dies.

[0005] A system for a large-scale independent tester system is disclosed. In one embodiment, the system includes a first temperature-controlled chuck. In another embodiment, the system includes a substrate that is coupled to the first temperature-controlled chuck. In certain embodiments, the system includes a device interface board coupled to the substrate. In some embodiments, the system includes a plurality of independent tester resource sites configured to perform independent functional tests and / or parameter tests. In one embodiment, the independent tester resource sites are disposed on one or more substrates and the device interface board. In certain embodiments, the system includes one or more interface buses that communicate with a plurality of independent tester resource sites, thereby providing one or more of power and a communication link to the independent tester resource sites. In yet another embodiment, the system includes a controller that communicates with a plurality of independent tester resource sites via one or more interface buses. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to readily understand the advantages of the invention, the invention briefly described above will be described in more detail with reference to specific embodiments illustrated in the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the invention and are not, therefore, to be considered limiting of its scope, and the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0007] Figure 1 is a schematic block diagram illustrating one embodiment of a large-scale independent tester system;

[0008] Figure 2 is a schematic block diagram illustrating one embodiment of a tester wafer for a large-scale stand-alone tester system;

[0009] Figure 3 is a schematic block diagram illustrating a certain embodiment of a large-scale independent tester system;

[0010] Figure 4A is a schematic block diagram illustrating yet another embodiment of a large-scale independent tester system;

[0011] Figure 4B is a schematic block diagram illustrating one embodiment of a tester module for a large-scale standalone tester system;

[0012] Figure 4C is a schematic block diagram illustrating yet another embodiment of a tester module for a large-scale standalone tester system;

[0013] Figure 5 is a schematic block diagram illustrating one embodiment of a large-scale independent tester system;

[0014] Figure 6is a schematic block diagram illustrating one embodiment of a probe card and a device under test wafer for a large-scale standalone tester system;

[0015] Fig. 7A is a schematic block diagram illustrating one embodiment of a chuck for a large-scale stand-alone tester system;

[0016] Figure 7B is a schematic block diagram illustrating yet another embodiment of a chuck for a large-scale stand-alone tester system;

[0017] Figure 7C is a schematic block diagram illustrating a certain embodiment of a chuck for use in a large-scale stand-alone tester system;

[0018] Fig.7D is a schematic block diagram illustrating another embodiment of a chuck for a large-scale stand-alone tester system; and

[0019] Figure 8 is a diagram illustrating a schematic flow chart of one embodiment of a method for a large-scale standalone tester system. DETAILED DESCRIPTION

[0020] Throughout this specification, references to "one embodiment", "embodiment" or similar language mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment. Therefore, unless otherwise expressly provided, the phrases "in one embodiment", "in an embodiment" and similar language throughout this specification may but do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments". Unless otherwise expressly stated, the terms "include", "comprise", "have" and their variants mean "including but not limited to". Unless otherwise expressly provided, the list of items listed does not imply that any or all items are mutually exclusive and / or mutually inclusive. Unless otherwise expressly provided, the terms "one", "an" and "the" also refer to "one or more".

[0021] In addition, the features, advantages and characteristics of the described embodiments may be combined in any suitable manner. Those skilled in the relevant art will recognize that these embodiments may be practiced without one or more specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments may be recognized in certain embodiments.

[0022] Through the following description and the appended claims, these features and advantages of the embodiments will become more apparent, or can be understood by the practice of the embodiments as set forth below. As will be appreciated by those skilled in the art, aspects of the present invention may be implemented as systems, methods and / or computer program products. Therefore, aspects of the present invention may take the form of completely hardware embodiments, completely software embodiments (including firmware, resident software, microcode, etc.) or embodiments of combined software and hardware aspects, which are generally referred to herein as "circuits", "modules" or "systems". In addition, aspects of the present invention may take the form of a computer program product implemented in one or more computer-readable media on which program code is implemented.

[0023] Many of the functional units described in this specification are labeled as modules in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit (including custom very large scale integration ("VLSI") circuits or gate arrays, off-the-shelf semiconductors (such as logic chips, transistors, or other discrete components)). A module may also be implemented in a programmable hardware device (such as a field programmable gate array ("FPGA"), programmable array logic, programmable logic device, etc.).

[0024] Modules may also be implemented in software so as to be executed by various types of processors. For example, a module of identified program code may include one or more physical or logical blocks of computer instructions that may be organized, for example, as objects, procedures, or functions. However, the executable code of the identified module need not be physically located together, but may include different instructions stored in different locations that, when logically combined together, constitute the module and achieve the stated purpose of the module.

[0025] In fact, the module of program code can be a single instruction or multiple instructions, and can even be distributed on several different code segments, distributed in different programs and distributed across several storage devices. Similarly, operating data can be identified and illustrated in this article within the module, and can be implemented in any suitable form and organized in the data structure of any suitable type. Operating data can be collected as a single data set, or can be distributed on different locations (including on different storage devices), and can exist at least partially as an electronic signal on a system or network. In the case where a module or part of a module is implemented in software, the program code can be stored and / or propagated on one or more computer-readable media.

[0026] The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0027] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing devices. A non-exhaustive list of more particular examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory ("RAM"), a read-only memory ("ROM"), an erasable programmable read-only memory ("EPROM" or flash memory), a static random access memory ("SRAM"), a portable compact disc read-only memory ("CD-ROM"), a digital versatile disk ("DVD"), a memory stick, a floppy disk, a mechanical encoding device (such as a punched card or a raised structure in a groove on which instructions are recorded) and any suitable combination of the foregoing. As used herein, a computer-readable storage medium itself should not be interpreted as a transient signal (such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire).

[0028] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network, and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0029] The computer-readable program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture ("ISA") instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, wherein the one or more programming languages ​​include object-oriented programming languages, such as Smalltalk, C++, etc., and conventional process programming languages, such as "C" programming languages ​​or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network (including a local area network ("LAN") or a wide area network ("WAN")), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit comprising, for example, a programmable logic circuit, a field programmable gate array ("FPGA"), or a programmable logic array ("PLA") may execute computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit, thereby performing various aspects of the present invention.

[0030] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0031] Such computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium, which may instruct a computer, a programmable data processing device, and / or other devices to operate in a particular manner, so that the computer-readable storage medium in which the instructions are stored includes an article of manufacture containing instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0032] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other apparatus to perform a series of operational steps on the computer, other programmable device, or other apparatus to produce a computer-implemented process, such that the instructions executed on the computer, other programmable device, or other apparatus implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0033] The schematic flow chart diagrams and / or schematic block diagrams in the accompanying drawings illustrate the possible architectures, functions and operations of the devices, systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the schematic flow chart diagrams and / or schematic block diagrams may represent a module, segment or part of a code, including one or more executable instructions of a program code for implementing (one or more) specified logical functions.

[0034] It should also be noted that in some alternative implementations, the functions annotated in the blocks may not appear in the order annotated in the figure. For example, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. Other steps and methods may be envisioned that are equivalent in function, logic, or effect to one or more blocks or portions thereof of the illustrated figures.

[0035] Although various arrow types and line types can be used in flow charts and / or block diagrams, it should be understood that various arrow types and line types do not limit the scope of the corresponding embodiments. In fact, some arrows or other connectors can be used to indicate only the logical flow of the depicted embodiments. For example, an arrow can indicate a waiting or monitoring period of unspecified duration between the enumerated steps of the depicted embodiments. It should also be noted that each block of the diagram of the block diagram and / or flow chart and the combination of the blocks in the diagram of the block diagram and / or flow chart can be implemented by a combination of a dedicated hardware-based system or dedicated hardware and program code that performs a specified function or action.

[0036] As used herein, a list with the conjunction "and / or" includes any single item in the list or a combination of items in the list. For example, a list of A, B, and / or C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C. As used herein, a list using the term "one or more" includes any single item in the list or a combination of items in the list. For example, one or more of A, B, and C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C. As used herein, a list using the term "one of..." includes one and only one of any single item in the list. For example, "one of A, B, and C" includes only A, only B, or only C, and excludes a combination of A, B, and C. As used herein, "a member selected from the group consisting of A, B, and C" includes one and only one of A, B, or C, and excludes a combination of A, B, and C. As used herein, “a member selected from the group consisting of A, B, and C, and combinations thereof” includes only A, B, C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C.

[0037] The terms "chip," "die," "die under test" (DUT), and "dielet" are often used herein. Each of these terms may be used interchangeably, although DUT may be used to mean a die under test and a dielet may include a die used in 3D multi-die packaging applications, etc.

[0038] Some wafer sorters are bulky and may have a temperature control system to heat the device under test and / or the test head. The test head may be a plurality of printed circuit boards (PCBs) with various functions (such as power supplies, pin electronics, controllers, etc.). The test signals generated by these PCBs may reach the DUT via a maze of device interface boards and / or probe cards. Such wafer sorters may be bulky, costly, and / or have a heavy tester channel load for the DUT. In an embodiment with a heavy tester channel load, the output of the DUT may be overdesigned to drive only the tester channel. Such testers may be able to test a limited number of DUTs with independent pin electronics but with shared control. When testing a large number of DUTs, the heat generated by the DUT and the tester module itself may heat the DUT environment. In some embodiments, smaller and / or more easily managed thermal control equipment may be advantageous.

[0039] Figure 1One embodiment of a large-scale independent tester system 100 is depicted. In the depicted embodiment, the system 100 includes a controller 102, one or more chucks 104 (e.g., a tester chuck 104a, a device under test chuck 104b, etc.), a tester wafer 106 having a plurality of independent tester dies 126a-n coupled to a device interface board 110 via one or more conductive bumps 108, a probe card 112, one or more vertical probes 114, a device under test wafer 116 having a plurality of DUT dies 116a-n, one or more interface buses 118, one or more coolant channels 120, one or more heaters 122 and / or temperature sensing buses 122, and one or more vacuum devices 124. In some embodiments, the controller 102 communicates with one or more of the above components of the system 100.

[0040] One or more of the test functions described herein for the tester dies 126a-n may be built using the process technology of the tester wafer 106. For example, bipolar CMOS (BICMOS) technology may allow certain analog components used by automatic test equipment (ATE) to be built on the tester wafer 106. In some embodiments, wafer-level repair techniques (such as fuse blowing and / or one or more additional metal mask steps for connecting proven good components on one or more of the tester dies 126a-n) may enable the test wafer 106 to include most or all working tester dies 126a-n.

[0041] In some embodiments, components for testing that may not be easily and / or practically implemented through semiconductor processes for the tester wafer 106, such as one or more resistors, capacitors, inductors, loads, relays, etc., may be provided on the device interface board 110. In some embodiments, micro-electromechanical systems (MEMS) technology for manufacturing tens of thousands or more probes, relays, and / or miniature passive electronic components may enable testing of the complete wafer 116 with one touch-down.

[0042] In some embodiments, each tester die 126a-n, its associated test components on the device interface board 110 and / or the probe card 112 and / or the probes 114 form an independent tester resource. The system 100 may include multiple (e.g., large quantities, etc.) independent tester resources, with up to one or more independent tester resources for each DUT 116a-n of the wafer 116. In some embodiments, by using independent tester resources for specific high-volume products, the overall requirements may be much simpler compared to other general-purpose ATE (which may have a large number of test resources idle when testing specific products, etc.).

[0043] The present disclosure describes at least two related embodiments of a massive independent tester system (MITS) 100, 400, 500. The system 100 includes a tester wafer 106 mounted on a tester wafer chuck 104a or an integrated component of a tester fixture, etc. The integrated fixture, along with the tester wafer 106, DIB 110, probe card 112 with vertical probes 114, temperature sensing, heating / cooling and inter-DIB interface bus 118, can include a fixed tester structure, etc. (e.g., a tester fixture). The DUT wafer 116 is held on a movable DUT chuck 104b by a vacuum device 124 so that the DUT wafer 116 can be aligned with the probes 114 of the tester fixture, stepped and removed when testing is completed, etc.

[0044] Other embodiments of the large-scale independent tester system 100 are depicted with respect to Figure 4A and Figure 5 In the described systems 400, 500, many tester modules 406a-n may form a large-scale independent tester system 400, 500, rather than a single complete tester wafer 106. The tester modules 406a-n may include, for example, Figure 4B A fully operational tester die 126 as depicted in FIG. Figure 4C 4, such as a random access memory (RAM) 412, a read-only memory (ROM) 414, and / or a field programmable gate array (FPGA) 416 die-let and / or one or more dedicated custom-designed on-a-chip (SOC) 418 die-lets. In some embodiments, Figure 4C The embodiments of the tester modules 406a-n depicted in FIG. 4 may include a custom developed SOC 418 and / or FPGA 416 that may provide flexibility. Figure 1 Although the tester fixture described above for system 100 , in some embodiments, system 400 and / or system 500 may include a tester fixture.

[0045] Figure 2One embodiment of a tester wafer 106 for a large scale standalone tester system is depicted. In the depicted embodiment, the tester wafer 106 includes a tester die 126 and an inter-tester die bus 118. In some embodiments, the size of the tester wafer 106 and / or the tester die 126 can match the size of the DUT wafer 116 and / or the DUT die to enable one touch testing, etc. In embodiments where the tester wafer 106 is smaller than the DUT wafer 116 or the tester die 126 is larger than the DUT die 116, multiple steppings of the DUT chuck 104b can be used to test all the die on the DUT wafer 116, etc.

[0046] In some embodiments, the tester die-to-die bus 118 includes a set of metal and / or other conductors 118, such as a power bus 118 for the tester die 126a-n and the DUT die 116a-n that can be controlled separately, a reference voltage, a timing reference, a data bus 118 for loading test programs to the tester die 126 and reading test results from the tester die 126, a serial bus 118 connected to the main off-wafer controller 102, a connection 118 to the inter-DIB board 110 bus 118 via bumps 108 at various points along the tester die-to-die bus 118, and the like. In some embodiments, one or more functions of the tester die-to-die bus 118 and the inter-DIB board bus 118 can be substantially similar and / or overlapping. In one embodiment, the tester die-to-die bus 118 can communicate with the main off-wafer controller 102 via one or more inter-DIB board buses 118, etc.

[0047] Figure 3 One embodiment of a large-scale standalone tester system 300 is depicted. Depending on the DUT 116a-n functionality to be tested, the tester die 126 may include different components. For example, in some embodiments, the system 300 may include a tester die 126 for a mixed-signal SOC DUT with embedded memory. In the depicted embodiment, the system 300 also includes a DIB 110, a probe card 112 with vertical probes 114, and a DUT wafer 116.

[0048] In one embodiment, memory functions are tested by a memory test unit 306 having address / data generation functions. Digital functions may be tested by test vectors generated by fault coverage software and stored in a test vector RAM 308. Test data, inputs, and expected outputs of the DUTs 116a-n may be selected from the test vector RAM 308 by a multiplexer (MUX) 318 or generated by the memory test function 306. The input data may be further formatted by a timing generator 328, a reference voltage 330, etc. before being sent to the DUTs 116a-n.

[0049] Output data from the DUT 116a-n may be compared to expected data in the test vector RAM 308 and / or the memory test function 306 to determine whether the output data meets timing and / or level requirements, etc. In some embodiments, the tester controller 302 is configured to determine one or more actions to be taken based on the test results. Error data generated by the comparator 314 may be stored in the error RAM 310 and / or may be sent to the main off-wafer controller 102 for data analysis, etc.

[0050] The power supply 326 and / or reference voltage 330 or current for the tester die 126 may be generated on the tester die 126 by a small die on the DIB 110 and / or introduced directly through the tester die inter-bus 118 or through the DIB inter-board bus 118 .

[0051] If the DUT 116a-n has analog functionality, the tester die 126 may include analog test circuits 304 that are compatible with the tester die 126 wafer 106 processing technology, such as digital signal processing (DSP), sampling, digitization functionality, etc. In yet another embodiment, one or more analog test circuits 304 may be implemented as a chiplet and included on the DIB 110.

[0052] Some complex SOC DUTs 116a-n may include multiple SOC functions with built-in self-test (BIST) 320 and repair 322 features (such as JTAG boundary scan, IEEE 1500, and / or other BIST standards). High-density memory chips may also have standard and / or customized BIST 320 and / or repair 322 features. In some embodiments, the BIST 320 and / or repair 322 functional blocks on the tester die 126 may be designed to accommodate the specific BIST 320 and / or repair 322 functions of the DUT 116a-n.

[0053] In some embodiments, one or more temperature sensors 312 may be configured to measure the temperature of the tester die 126 at a certain location. The one or more on-chip temperature sensors 312 may be controlled by one or more serial buses, such as an I2C and / or SPI bus. In some embodiments, the location of each tester die 126 may be programmed as a unique slave address of an I2C bus, a unique chip select of an SPI bus, etc. The reading of a single temperature sensor 312 of a tester die 126 may be read by the master off-wafer controller 102 to adjust the temperature of the entire tester system 300, etc.

[0054] One or more test function blocks 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, 334 may communicate with and / or be controlled by a tester controller 302. In one embodiment, the tester controller 302 stores one or more test programs. The tester controller 302 may control the test sequence and / or test conditions for each test (functional and / or parameter test). In another embodiment, the tester controller 302 may also interface with the main off-wafer controller 102. The tester controller 302 may be configured to operate independently of other tester controllers 302 on other tester dies 126 on the tester wafer 106 or the like.

[0055] As described above, all tester dies 126 on the tester wafer 106 may have access to an inter-tester wafer bus 118, such as a power bus 118, to provide power 326, reference voltage 330 and / or current and timing 328 to the tester dies 126, and / or to provide power 326 to the DUTs 116a-n. One or more data buses 118 and / or serial buses 118 may be used for the tester dies 126 to communicate with the main off-wafer controller 102 and / or load test programs, etc. In some embodiments, the main off-wafer controller 102 may dynamically select a tester die 126 to run test of the DUTs 116a-n, to control temperature, etc.

[0056] Some components, such as a power supply 326, a phase-locked loop (PLL) within the timing generator 328 that can act as a multiplier or divider for the timing generator 328, reference V / I voltages and currents 330, and / or a precision measurement unit (PMU) 332 for various tester resources, may be located on the tester die 126 and / or on the DIB board 110.

[0057] Certain tester components (e.g., macros, VHSIC hardware description language (VHDL) models, and / or firmware, etc.) may be standardized and reusable for different families of DUTs 116a-n. In such embodiments, it may not be necessary to generate new tester components for each new product or other new DUTs 116a-n. In some embodiments, some customization at the DIB 110 level or even at the probe card 112 level may cover the entire product family.

[0058] The tester components may be individually tested (e.g., by ATE, etc.) to determine which tester components are good or repaired or replaced with good components to form a functionally good tester die 126 that will be connected to the functionally good components on the DIB board 110. The removal or repair of defective tester components may be accomplished by one or more methods, such as laser cutting, blowing fuses, and / or thin oxide devices. In some embodiments, an additional metal mask may be used to connect good tester components, program unique slave addresses for different tester dies 126, and / or connect the tester inter-die bus 118 to the tester dies 126. This additional metal mask may be of low resolution, on the order of a few microns or tens of microns, so that the additional metal mask may not significantly increase the overall cost.

[0059] Bumps 108 and / or microbumps 108 may be added for interconnection to one or more DIBs 110. The functional tester die 126 combined with verified functional components on the DIB 110 that complement the tester die 126 may form a large scale standalone tester system 100, 300.

[0060] In some embodiments, a large portion of the tester die 126 may include a test vector RAM 308. The test vector RAM 308 may be partitioned to store test programs and / or error data. In one embodiment, all or most of the other logic functions on the tester die 126 may be programmed into an FPGA or the like. Thus, in some embodiments, a logic process that is compatible with the test vector RAM 308 (e.g., SRAM) and the FPGA may be selected for the tester die 126 wafer 106 processing technology.

[0061] In one embodiment, using MEMS and / or small die technology, one or more active components that are not compatible with the tester die 126 wafer 106 process, along with passive loads and / or relays, can be built on the DIB 110 and / or a group of smaller DIBs 110. In some embodiments, a vertical probe 114 probe card 112 with MEMS technology can be used for one-touch testing of an entire wafer 116 (e.g., a 200 mm or 300 mm sized wafer 116, etc.).

[0062] The DIB inter-board bus 118 may be directly connected to the master off-wafer controller 102 , which may include a decision controller 102 and / or other functional components for the DIB inter-board bus 118 functions as previously described.

[0063] A small fast buffer RAM 336 chiplet that is as fast as or faster than the DUT 116a-n may be provided on the DIB 110. For example, if the tester die 126 wafer 106 technology is not as advanced as the DUT wafer 116 technology, a small fast buffer RAM 336 provided on the DIB 110 may be able to test at the DUT 116a-n speed. This may maintain low cost and / or longer reusability of the tester die 126 wafer 106. The area of ​​the fast buffer RAM 336 chip may be relatively small. For example, the SRAM may be obtained by a foundry shuttle run without incurring the entire mask set and wafer run costs, etc. One or more temperature sensors 312 may also be mounted at different locations of the DIB 110.

[0064] Figure 4A One embodiment of a large-scale independent tester system 400 is depicted. It can be challenging to manufacture an entire tester wafer 106 with functional tester dies 126a-n that match all of the dies 116a-n on the DUT wafer 116. In one embodiment, the system 400 includes multiple functional tester modules 406a-n that can be individually verified to build a MITS, rather than a single individual tester wafer 106. Figure 4A A MITS having one tester module 406 a - n for testing a number of DUTs 116 a - n by stepping through them with a plurality of probe cards 112 is depicted.

[0065] Figure 51 shows a MITS with one tester module 406a-n for testing several DUTs 116a-n with one touch by sequencing the testing of each DUT 116a-n with relays and / or switches. In some embodiments, these tester modules 406a-n can completely fill the allowed space, rather than Figure 4A 10 with spaces between adjacent modules 406a-n. One or more technologies, such as redistribution layers (RDL), bridging, through silicon vias (TSV), etc., can connect fully functional chiplets of different process technologies side by side or on top of each other to make fully functional tester modules 406a-n. MEMS relays, switches, and / or functional dielets can also be built on the DIB 110 to supplement the tester modules 406a-n and / or tester die 126a-n as previously described.

[0066] Figure 4B One embodiment of a tester module 406a-n for a large-scale stand-alone tester system is depicted. In different embodiments, the fully functional tester module 406 can be implemented in two or more different ways. In one embodiment, the fully functional tester module 406a-n can include the previously described (e.g., with or without repair) disposed on the substrate 402 or the like and Figure 4B Validated tester die 126 is depicted in FIG.

[0067] Figure 4C Yet another embodiment of tester modules 406a-n for use in a large-scale standalone tester system is depicted. Figure 4C The tester modules 406a-n may include a plurality of different independent product dies 412, 414, 416, 418, etc., such as FPGA 412, volatile memory 414, non-volatile memory 416, and / or SOC 418. The programmable FPGA 412 (e.g., as a chiplet) may provide flexibility to the tester modules 406a-n and / or reduce the need for a new tester SOC 418. The tester SOC 418 may include Figure 3 Some or all of the components of the tester die 126 may include fewer functions that can be performed by FPGA 412, RAM 414 and / or ROM 416 or NAND flash memory 416, each of which may be a separate small die, etc., disposed on the substrate 402 and communicating through the bus 118, etc.

[0068] These components can be fully tested before being assembled into the tester modules 406a-n. The actual input / output circuits 334 that the DUTs 116a-n interface with in the system application can be incorporated into the device interface board 110. In this way, in some embodiments, the DUTs 116a-n can be tested in an environment that is very similar to their actual application. A ROM 416 or NAND flash memory 416 can be included to serve as a boot ROM for the FPGA 412. Test programs can be programmed and loaded into the RAM 414. Intermediate test results can be stored in the RAM 414 or NAND flash memory 416 to reduce traffic on the inter-tester module or DIB board bus 118. This data can be uploaded to the main off-wafer controller 102 during non-testing times (such as wafer 116 setup or unload or temperature transition times, etc.). Some or all power supplies or signals associated with the tester modules 406 a - n may be connected to the inter-tester module bus 118 via the tester module baseboard 402 and / or also connected to the DIB inter-board bus 118 via the DIB 110 .

[0069] Figure 4C The tester inter-module bus 118 can function with Figure 4B The tester inter-die bus 118 may be used to communicate with the main off-wafer controller 102, etc. In some embodiments, some power lines in this bus 118 may be minimized and / or reduced by using backside power delivery through PowerVia, etc. This bus 118 may be segmented to reduce its overall load. As described above, by preloading the test program in ROM 416 or NAND flash memory 416, the test program data lines in this bus 118 may be reduced.

[0070] In some embodiments, the frequency multiplier or divider may allow each tester module 406a-n to operate at a different test frequency, thereby having different power consumption. As described above, in other embodiments, one or more components of DIB 110 may be located on tester modules 406a-n, or vice versa.

[0071] Figure 5 One embodiment of a large-scale independent tester system 500 is depicted. In some embodiments, for a one-touch embodiment, the fast buffer RAM 336 on the DIB 110 may also be organized as one per DUT 116a-n, one per tester module 406a-n, and so on. Tester resources for tester modules 406a-n with one or more power supplies and their associated test components may be provided on the DIB 110, including vertical probes 114 capable of independently testing the DUTs 116a-n. Figure 4A As shown in , tester resources can be used by surrounding dies and the like.

[0072] Figure 6 One embodiment of a probe card 112 with probes 114 and a DUT wafer 116 is depicted. The tester resources indicated at the locations with vertical probes 114 may be as shown in FIG. Figure 6 After testing the first DUT 116a-n, eight DUTs 116a-n surrounding the DUT 116a-n with the vertical probe 114 may be tested by stepping eight times. The arrangement of the tester resources may be accomplished in many different ways, Figure 6 This is just an example. Figure 5 As depicted in FIG. 1 , a touch test may be performed for each DUT 116a-n using the vertical probe 114. Tester resources may be brought to each DUT 116a-n in sequence via relays or the like.

[0073] Fig. 7A One embodiment of a chuck 700 is depicted, Figure 7B One embodiment of a chuck 710 is depicted, Figure 7C One embodiment of a chuck 720 is depicted, and Fig.7D One embodiment of a chuck 730 is depicted, each embodiment being used in a large scale standalone tester system. In some embodiments, the DUT chuck 104b and the tester wafer chuck 104a may be similar in function. Fig. 7A DUT chuck 104b is depicted. Both DUT chuck 104b and tester wafer chuck 104a may have heating 122, cooling 120, and temperature measurement 122 capabilities. DUT chuck 104b may also include vacuum equipment 124 capabilities to hold DUT wafer 116. Tester wafer 106 or tester module substrate 402 may be permanently mounted on tester wafer chuck 104a, which may be an integral part of the tester fixture, rather than using vacuum equipment 124 (although not shown in the figure), including DIB 110 and vertical probe 114. For this reason, vacuum equipment 124 capabilities may not be required on tester wafer chuck 104a. Temperature sensor 312 may be designed on tester die 126a-n and / or tester module 406a-n. For this reason, tester wafer chuck 104a may not require temperature sensor 312. The DUT wafer chuck 104b can be stepped and rotated in the X and / or Y directions to align the DUT pads or bumps with the vertical probes 114 and move up and down to make contact or separate.

[0074] Both the DUT wafer chuck 104b and the tester wafer chuck 104a (e.g., via the tester dies 126a-n and / or the tester modules 406a-n) may have temperature sensors 312 embedded at different locations. In this embodiment, the temperature of a local area may be measured by a single sensor slave address that may be selected by the serial bus 122 to save the number of select lines required, such as Fig. 7A The two-wire I2C with extended slave address shown in FIG. Fig.7D As depicted in , the same is true for the heating elements 732 in each local area.

[0075] The temperature of the DUT wafer 116 and / or DUT chuck 104b can be completely heated using the heat dissipated by the DUTs 116a-n being tested. Computer simulation based on the thermal characteristics of the system can determine the maximum number and location of the DUTs 116a-n being tested, while having the cooling 120 capability to cool to the desired test temperature, etc.

[0076] In some embodiments, the heating element 732 around the edge of the DUT chuck 104b can be adjusted higher (e.g., using switch 734) so ​​that the temperature of the DUT 116a-n is not affected by the exposed edge, etc. Figure 7C As depicted in FIG. 1 , multiple coolant paths 120 in combination with local temperature sensors 312 and heating elements 732 allow all of the DUTs 116a - n under test to be controlled within a desired temperature range.

[0077] The footprint and / or cost of conventional wafer sorting equipment may limit testing to a single pass at room temperature. Therefore, a "good die" after a single sort at room temperature may not be ideal for a known good die (KGD). Additional temperature testing and wafer level burn-in may be required.

[0078] Many chiplet applications can be in 3D multi-chip package systems. A bad chiplet can ruin the entire system, and the entire system cost is much higher than the cost of a single package. Even worse, a chiplet that has soft failures or deterioration during its normal life can result in a bad 3D multi-chip package system in actual applications at a much higher cost.

[0079] In some embodiments, the MITS described herein provides solutions to these problems. For example, in some embodiments, multiple temperature wafer sorting may be possible. In yet another embodiment, aging type stresses are also possible. In some embodiments, operating temperature guard bands are possible. Power supplies for DUTs 116a-n and tester outputs may be set at different levels as guard bands, etc.

[0080] When testing a large number of dies 116a-n, or even an entire wafer 116, simultaneously, the ultimate limiting factor may be the heat generated by the DUTs 116a-n and / or the tester resources. Because the individual tester resources of the described MITS can be individually controlled, high power generation tests (such as high frequency AC testing at some tester resources) can be staggered with low power generation tests (such as DC testing or low frequency functional testing at other tester resources). Low frequency functional testing can eliminate certain leakage-related issues that high frequency functional testing cannot perform and that normal test protocols cannot afford to perform. This allows more DUTs 116a-n to be tested simultaneously and with better quality.

[0081] When the vertical probe 114 and the probe pad (or bump) of the DUT wafer 116 are transferred to a new test temperature, the vertical probe 114 and the probe pad of the DUT wafer 116 can be separated. When they reach a predefined temperature difference range, they can be contacted to ensure less damage to the probe and the pad (or bump).

[0082] Calibration wafers and / or substrates with verified resistor, inductor and / or capacitor values ​​can be used to calibrate the DC test functions. Calibration equipment with the help of DIB inter-board bus 118, tester inter-die bus 118 and / or tester inter-module bus 118 can also be used to calibrate the DC test functions. This calibration wafer or substrate can also have functional blocks and / or loopback features to test and calibrate AC timing and digital functions. Through appropriate adapters, this test system can be configured to test 3D package units and / or subsystem components.

[0083] Figure 8 One embodiment of a method 800 for a large-scale standalone tester system is depicted. The method 800 begins with the controller 102, 302 heating 802 the first and second temperature-controlled chucks 104a-b, respectively, to a preset temperature range. The controller 102, 302 contacts 804 probe pads of a device wafer 116 under test with a vertical probe 114 in communication with the tester die 126a-n and / or the tester module 406a-n. The controller 102, 302 tests 806 a first plurality of devices 116a-n of the device wafer 116 under test.

[0084] The controller 102, 302 introduces more devices 116a-n (or reduces 808 the number of devices 116a-n) of the device wafer 116 under test in stages 808 for testing up to a maximum number of devices 116a-n that the controller 102, 302 can maintain within a preset temperature range or another desired temperature range of the DUT 116a-n and / or the second temperature controlled chuck 104b while testing the maximum number of devices 116a-n. The controller 102, 302 causes the vertical probe 114 to disengage 810 from contact 804 with the probe pad.

[0085] The controller 102, 302 determines 812 whether each device 116a-n of the device wafer 116 under test has been tested, and the method 800 ends in response to each device 116a-n being tested. The controller 102, 302 iteratively moves 814 the test to one or more other locations on the device wafer 116 under test in response to each device 116a-n of the device wafer 116 under test being at the current contact position of the vertical probe 114 under test and the probe pad until each device 116a-n of the device wafer 116 under test has been tested.

[0086] The present invention may be implemented in other specific forms without departing from the spirit or essential features of the present invention. The described embodiments are to be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description. All changes within the meaning and scope of the equivalents of the claims should be included within the scope of the claims.

Claims

1. A device comprising: Controller; substrate; Device interface board; a plurality of tester modules mounted on the base plate, one or more components in communication with the tester modules mounted on the device interface board, the tester modules configured to perform both stand-alone functional tests and parametric tests; as well as One or more interface buses communicate with the controller and one or more of the plurality of tester modules and the device interface board, the one or more interface buses providing one or more of power and a communication link.

2. The device according to claim 1, wherein: The plurality of tester modules each include one or more of the following: Custom tester system on chip; Volatile memory; Field Programmable Gate Arrays; and Non-volatile memory including one or more of a read-only memory chiplet and a NAND flash memory chiplet.

3. The device according to claim 2, wherein: Each of the plurality of tester modules includes one or more of a single dielet and a single die.

4. The device according to claim 1, wherein: The plurality of tester modules each include a custom tester system-on-chip, the custom tester system-on-chip including one or more of: Tester controller; Testing procedures; Memory test address generator; Data generator; Test vectors for digital circuits; Error random access memory; Comparator; Pin electronics and switches; power supply; Reference power supply; Phase-locked loop; frequency and timing generators; Simulation test function; Built-in self-test; Repair function; Precision measuring unit; actual input or output circuitry of the device under test in actual use of the device under test; as well as Temperature sensor.

5. The device according to claim 1, wherein: The device interface board includes one or more of the following: Probe card; Probe; Relay; Passive load; Active load; Power bus; Timing generator; Phase-locked loop; volatile buffer memory; and The actual input or output circuit of the device under test in its actual application.

6. The device according to claim 1, wherein: The device interface board includes one or more of a temperature sensor and an alignment mechanism.

7. The apparatus of claim 1, further comprising a first temperature-controlled chuck and a second temperature-controlled chuck, the base plate and the device interface board being coupled to the first temperature-controlled chuck, and a device wafer under test being coupled to the second temperature-controlled chuck.

8. The apparatus of claim 7, wherein the first temperature-controlled chuck and the second temperature-controlled chuck each include a local temperature control element, and the second temperature-controlled chuck includes a vacuum apparatus and a plurality of temperature sensors configured to couple the device under test wafer to the second temperature-controlled chuck.

9. The device according to claim 8, wherein: The controller communicates with the plurality of tester modules via the one or more interface buses, and the controller is configured to: Heating the first temperature-controlled chuck and the second temperature-controlled chuck to a preset temperature range respectively; contacting a probe pad of the device under test wafer with a vertical probe in communication with the tester module; testing a first plurality of devices on the device under test wafer; adjusting the number of devices of the device under test wafer to test up to a maximum number of devices that the controller can maintain within a preset temperature range of the second temperature-controlled chuck; causing the vertical probe to break contact with the probe pad; and In response to each device of the device under test wafer being at a current contact position of the probe pad and vertical probe being tested, iteratively moving testing to one or more other locations on the device under test wafer until each device of the device under test wafer is tested.

10. The device according to claim 8, wherein: The controller is configured to stagger one or more high power tests performed by one or more of the multiple tester modules with one or more low power tests performed by one or more other tester modules of the multiple tester modules during testing to reduce the total power generated by the device of the device chip under test and by the tester resources during testing.

11. The device according to claim 8, wherein: The device interface board includes a buffer memory that is compatible with and at least as fast as the devices of the device wafer under test.

12. The device according to claim 11, wherein The buffer memory communicates directly with the vertical probe of the device interface board.

13. The apparatus according to claim 1, wherein: The substrate includes a single chip on-die system including a second controller, a random access memory, and a multiplexer.

14. The apparatus according to claim 1, wherein: One or more of the first temperature-controlled chuck, the second temperature-controlled chuck, and the plurality of tester modules include a plurality of temperature sensors and heating and cooling elements, and the controller is configured to adjust the independent heating and cooling elements to maintain one or more preset temperature ranges.

15. The apparatus according to claim 1, wherein: The controller is configured to adjust clock frequencies of devices of the device wafer under test to maintain one or more preset temperature ranges.

16. An apparatus comprising: Controller; Tester wafer; Device interface board; a plurality of independent tester dies of the tester wafer, one or more components in communication with the tester dies mounted on the device interface board, the tester dies configured to perform both independent functional and parametric testing; as well as One or more interface buses in communication with the controller and the plurality of independent tester dies, the one or more interface buses providing one or more of power and a communication link for the plurality of independent tester dies and the controller.

17. The apparatus of claim 16, further comprising a first temperature-controlled chuck to which the tester wafer and the device interface board are coupled and a second temperature-controlled chuck to which a device wafer under test can be selectively coupled.

18. The apparatus according to claim 17, wherein: The controller communicates with the plurality of independent tester dies via the one or more interface buses, and the controller is configured to: Heating the first temperature-controlled chuck and the second temperature-controlled chuck to a preset temperature range respectively; contacting a probe pad of the device under test wafer with a vertical probe in communication with the tester die; testing a first plurality of devices on the device under test wafer; adjusting the number of devices of the device under test wafer to test up to a maximum number of devices that the controller can maintain within a preset temperature range of the second temperature-controlled chuck; causing the vertical probe to break contact with the probe pad; and In response to each device of the device under test wafer being at a current contact position of a probe pad and a vertical probe being tested, iteratively moving testing to one or more other locations on the device under test wafer until each device of the device under test is tested.

19. A system comprising: First temperature control chuck; a base plate coupled to the first temperature-controlled chuck; a device interface board coupled to the base plate; a plurality of independent tester resource sites configured to perform independent functional and parametric tests, the independent tester resource sites being disposed on one or more of the base plate and the device interface board; one or more interface buses in communication with the plurality of independent tester resource sites to provide one or more of power and communication links to the independent tester resource sites; and A controller communicates with the plurality of independent tester resource sites via the one or more interface buses.

20. The system of claim 19, further comprising a second temperature controlled chuck coupled to the device under test wafer, wherein the controller is configured to: Heating the first temperature-controlled chuck and the second temperature-controlled chuck to a preset temperature range respectively; contacting probe pads of the device under test wafer with a vertical probe in communication with the plurality of independent tester resource sites; testing a first plurality of devices on the device under test wafer; adjusting the number of devices of the device under test wafer to be used for testing up to a maximum number of devices that the controller can maintain within the preset temperature range of the second temperature-controlled chuck; causing the vertical probe to break contact with the probe pad; and In response to each device of the device under test wafer being at a current contact position of the probe pad and vertical probe being tested, iteratively moving testing to one or more other locations on the device under test wafer until each device of the device under test wafer is tested.

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