Array substrate, display panel, display device and driving method

Abstract

The invention discloses an array substrate, a display panel, a display device and a driving method. The array substrate comprises: a substrate (1); a plurality of gate lines (2); at least one grid line (2) in the plurality of grid lines (2) comprises a plurality of grid line groups (20) which are sequentially distributed along a first direction; the grid line group (20) comprises a first grid line part (21), a second grid line part (22) and a third grid line part (23) which extend along a first direction and are distributed in sequence; the extension line of the first grid line part (21) does not coincide with the extension line of the second grid line part (22), and the extension direction of the third grid line part (23) intersects with the first direction. The maximum length of the pixel electrode (4) in the first direction is larger than the maximum length of the pixel electrode (4) in the second direction; and the orthographic projections of the plurality of pixel electrodes (4) on the substrate (1) are at least partially overlapped with the orthographic projections of the first grid line part (21) and the second grid line part (22) on the substrate (1).

Description

Array substrate, display panel, display device and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the international application filed with the State Intellectual Property Office of China on September 15, 2023, with application number PCT / CN2023 / 119203 and application name “Array substrate, display panel, display device and driving method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, a display device, and a driving method. Background Art

[0004] Compared to the conventional pixel drive structure of one gate line and one data line (1G1D), special pixel drive structures are sometimes used to reduce the number of data lines and increase the number of scan lines. These special pixel drive structures are the dual-gate pixel drive structure (Dual Gate) and the triple-gate pixel drive structure (Triple Gate). In a display panel of the same size, compared to the 1G1D pixel drive structure, the triple-gate pixel drive structure increases the number of scan lines by two times, while the number of data lines is reduced to one-third of the original. If a drive structure in which the gate drive circuit is integrated into the display panel (Gate on Array, GOA) is used, the increase in the number of scan lines does not require additional driver circuit costs, while the reduction in the number of data lines can reduce the number of driver ICs, thus having a cost advantage.

[0005] Summary of the Invention

[0006] The present disclosure provides an array substrate, a display panel, a display device, and a driving method. The array substrate includes:

[0007] substrate;

[0008] A plurality of gate lines are located on one side of a substrate, the plurality of gate lines extending along a first direction; at least one gate line among the plurality of gate lines includes a plurality of gate line groups sequentially distributed along the first direction; the gate line group includes: a first gate line portion extending along the first direction and sequentially distributed, a second gate line portion, and a third gate line portion located between the first gate line portion and the second gate line portion and connecting the first gate line portion and the second gate line portion; an extension line of the first gate line portion does not overlap with an extension line of the second gate line portion, and an extension direction of the third gate line portion intersects the first direction;

[0009] a plurality of data lines, located on the same side of the substrate as the plurality of gate lines, and extending along a second direction;

[0010] A plurality of pixel electrodes, wherein at least a portion of an orthographic projection of at least one pixel electrode among the plurality of pixel electrodes is located in an area formed by the intersection of the gate line and the data line on the substrate; a maximum length of the pixel electrode in the first direction is greater than a maximum length in the second direction; and the orthographic projections of the plurality of pixel electrodes on the substrate at least partially overlap with the orthographic projections of the first gate line portion and the second gate line portion on the substrate.

[0011] In a possible implementation manner, the third gate line portion extends along the second direction, and an extension line of the third gate line portion passes through a central area of ​​the pixel electrode.

[0012] In a possible implementation manner, a length of the gate line group in the first direction is substantially equal to a length of the pixel electrode in the first direction.

[0013] In a possible implementation manner, a length of the first gate line portion in the first direction is less than or equal to a maximum length of the second gate line portion in the first direction.

[0014] In a possible embodiment, the gate line further includes: a gate line connecting portion located between adjacent gate line groups and connecting adjacent gate line groups; the gate line connecting portion extends along the first direction, and an extension line is located between the first gate line portion and the second gate line portion.

[0015] In a possible embodiment, the gate line connection portion includes: a first gate line connection portion, a second gate line connection portion, and a third gate line connection portion distributed in sequence along the first direction; the length of the second gate line connection portion in the second direction is greater than the length of the first gate line connection portion in the second direction, and greater than the length of the third gate line connection portion in the second direction.

[0016] In a possible embodiment, in the same gate line group, the orthographic projection of the first gate line portion on the substrate is covered by the orthographic projection of one pixel electrode on the substrate, and the orthographic projection of the second gate line portion on the substrate is covered by the orthographic projection of another adjacent pixel electrode in the second direction on the substrate.

[0017] In a possible implementation, the array substrate includes: a first axis located between two adjacent pixel electrodes and extending along the second direction;

[0018] At least one data line among the multiple data lines includes: multiple data groups distributed in sequence along the second direction; the data group includes: a first data portion located on one side of the first axis, and a second data portion located on the other side of the first axis; the orthographic projections of the multiple pixel electrodes on the substrate at least partially cover the orthographic projections of the first data portion and the second data portion on the substrate.

[0019] In a possible implementation manner, the data group further includes: a third data portion connecting the first data portion and the second data portion, and an extension direction of the third data portion intersects with the second direction.

[0020] In a possible embodiment, in the same data group, the orthographic projection of the first data portion on the substrate is at least partially covered by the orthographic projection of one pixel electrode on the substrate, and the orthographic projection of the second data portion on the substrate is at least partially covered by the orthographic projection of another adjacent pixel electrode in the first direction on the substrate.

[0021] In a possible implementation manner, the length of the data group in the second direction is less than or equal to the maximum length of the pixel electrode in the second direction.

[0022] In a possible implementation, the first data portion and the second data portion both extend along the second direction, and an extension line of the first data portion does not overlap with the second data portion.

[0023] In a possible implementation, the array substrate includes: a second axis extending along the first direction and passing through the center of the pixel electrode;

[0024] The first data portion and the second data portion are respectively located on different sides of the second axis; and the second axis passes through the center of the third data portion.

[0025] In a possible implementation manner, an extension line of the second data portion overlaps with the first data portion in the adjacent data group.

[0026] In a possible implementation manner, the first data portion and the second data portion are symmetrical about the first axis.

[0027] In a possible embodiment, the first data portion and the second data portion both include: a first sub-data portion, a second sub-data portion, and a third sub-data portion extending along the second direction and distributed in sequence; the extension line of the first sub-data portion coincides with the extension line of the third sub-data portion, and the extension line of the second sub-data portion is located on the side of the first sub-data portion away from the first axis.

[0028] In a possible implementation manner, the first data portion and the second data portion further include: a fourth sub-data portion extending along the first direction, and a fifth sub-data portion;

[0029] The fourth sub-data portion connects the first sub-data portion and the second sub-data portion; the fifth sub-data portion connects the second sub-data portion and the third sub-data portion.

[0030] In a possible implementation manner, the third data portion extends along the first direction and connects the two fifth sub-data portions of the same data group.

[0031] In a possible implementation, the array substrate includes: a second axis extending along the first direction and passing through the center of the pixel electrode; and the second axis passes through a central area of ​​the second sub-data portion.

[0032] In a possible implementation manner, the first data portion is symmetrical about the second axis; and the second data portion is symmetrical about the second axis.

[0033] In a possible implementation manner, the length of the first sub-data portion in the second direction is substantially equal to the length of the third sub-data portion in the second direction.

[0034] In a possible implementation manner, the length of the first sub-data portion in the second direction is one third to two thirds of the length of the second sub-data portion in the second direction.

[0035] In a possible embodiment, the data line further includes: a data connection portion connecting adjacent data groups, the data connection portion including: two sub-data connection portions extending along the second direction and arranged along the first direction; the sub-data connection portion connects the third sub-data portion and the first sub-data portion of the adjacent data groups.

[0036] In a possible implementation manner, a length of the sub-data connection portion in the first direction is smaller than a length of the first sub-data portion in the first direction.

[0037] In one possible embodiment, the array substrate further includes: a plurality of transistors; at least one of the plurality of transistors includes: a control electrode, an active pattern, and a first electrode, a second electrode, and a third electrode sequentially distributed along the first direction; orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the control electrode on the substrate; and orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the active pattern on the substrate;

[0038] The first stage multiplexes one of the sub-data connection parts in the data connection part; the third stage multiplexes another sub-data connection part in the data connection part;

[0039] The second pole includes: a second pole first portion extending along the second direction, and a second pole overlapping portion connected to one end of the second pole first portion; the second pole first portion is located between the two first sub-data portions of the data group in the orthographic projection of the substrate; the second pole overlapping portion is located between the two second sub-data portions of the data group in the orthographic projection of the substrate.

[0040] In a possible implementation manner, a length of the second pole overlapping portion in the first direction is smaller than a minimum distance between two second sub-data portions in the data group.

[0041] In a possible implementation, the pixel electrode includes: a pixel electrode body, and a pixel electrode overlapping portion extending from one side of the pixel electrode body along the first direction;

[0042] The orthographic projection of the pixel electrode overlapping portion on the substrate has an overlapping area with the orthographic projection of the second electrode overlapping portion on the substrate.

[0043] In a possible implementation manner, the pixel electrode body has a recessed portion at a location where the pixel electrode overlap portion is located. The recessed portion is projected orthogonally on the substrate and surrounds the pixel electrode overlap portion.

[0044] In one possible embodiment, the outer edge of the second sub-data portion is projected onto the substrate, and is located on the side of the outer edge of the recessed portion on the substrate projection away from the first axis; the outer edge of the recessed portion is projected onto the substrate, and is located on the side of the outer edge of the second pole overlap portion on the substrate projection away from the first axis.

[0045] In a possible implementation, the data line includes: a first data portion and a second data portion alternately distributed along the second direction; wherein the first data portion is located in a region between two adjacent pixel electrodes in the first direction; and an orthographic projection of the second data portion on the substrate overlaps with an orthographic projection of the gate line on the substrate.

[0046] The second data portion includes: two first sub-data portions and a second sub-data portion extending along the second direction and distributed sequentially along the first direction; one end of the first sub-data portion and one end of the second sub-data portion are both connected to one first data portion, and the other end of the first sub-data portion is connected to another adjacent first data portion.

[0047] In a possible implementation manner, a maximum length of the second sub-data portion in the second direction is smaller than a maximum length of the first sub-data portion in the second direction.

[0048] In a possible implementation, the array substrate includes: a first axis located between two adjacent pixel electrodes and extending along the second direction;

[0049] In two adjacent second data portions, the two second sub-data portions are respectively located on different sides of the first axis; and the two first sub-data portions are respectively located on different sides of the first axis.

[0050] In a possible implementation, the array substrate further includes: a first conductive line extending along the second direction; an orthographic projection of the first conductive line on the substrate covers an orthographic projection of the data line on the substrate.

[0051] In a possible implementation, the array substrate further includes: a plurality of transistors; at least one of the plurality of transistors includes: a control electrode, an active pattern, a first electrode, and a second electrode; an orthographic projection of the first sub-data portion on the substrate does not overlap with an orthographic projection of the active pattern on the substrate;

[0052] The first stage multiplexes the second sub-data portion;

[0053] The second pole includes: a second pole first portion extending along the second direction, a second pole second portion extending along the first direction, and a second pole overlapping portion connected to the second pole second portion; the orthographic projection of one end of the second pole first portion on the substrate overlaps with the orthographic projection of the gate line on the substrate; the other end of the second pole first portion is connected to one end of the second pole second portion.

[0054] In a possible implementation, at least one data line among the plurality of data lines includes: first data portions and second data portions alternately distributed along the second direction; in the second direction, extensions of two first data portions on both sides of the second data portion do not overlap;

[0055] The second data portion includes: a first sub-data portion, a second sub-data portion, and a third sub-data portion; the first sub-data portion extends along the first direction; the second sub-data portion and the third sub-data portion extend along the second direction and are located on the same side of the first sub-data portion;

[0056] One end of the first sub-data portion is connected to one end of the second sub-data portion, and the other end is connected to one end of the third sub-data portion and one of the first data portions; the other end of the second sub-data portion is connected to another of the first data portions.

[0057] In a possible implementation manner, the orthographic projection of the first data portion on the substrate is located in a region between the orthographic projections of two adjacent pixel electrodes on the substrate in the first direction;

[0058] An orthographic projection of the second data portion on the substrate has an overlapping area with an orthographic projection of the gate line on the substrate.

[0059] In a possible implementation, a length of the first data portion in the second direction is less than or equal to a maximum length of the pixel electrode in the second direction.

[0060] In a possible implementation manner, orthographic projections of the plurality of pixel electrodes on the substrate do not overlap with orthographic projections of the first data portion and the second data portion on the substrate.

[0061] In one possible embodiment, the array substrate further includes: a plurality of transistors; at least one of the plurality of transistors includes: a control electrode, an active pattern, and a first electrode, a second electrode, and a third electrode sequentially distributed along the first direction; orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the control electrode on the substrate; and orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all overlap with an orthographic projection of the active pattern on the substrate;

[0062] The first stage multiplexes the second sub-data portion; the third stage multiplexes the third sub-data portion;

[0063] The second pole includes: a second pole first portion extending along the second direction, and a second pole overlapping portion connected to one end of the second pole first portion; the part of the second pole first portion on the orthographic projection of the substrate is located between the second sub-data portion and the third sub-data portion on the orthographic projection of the substrate.

[0064] In a possible implementation manner, a length of the second pole overlapping portion in the second direction is substantially equal to a length of the first data portion in the second direction.

[0065] In a possible implementation, a width of the second pole overlapping portion in the first direction is greater than a width of the second pole first portion in the first direction.

[0066] In a possible embodiment, the array substrate further includes: a first common routing line extending along the first direction, and a common overlapping portion connected to the first common routing line; the first common routing line is an orthographic projection of the substrate, passing through the central area of ​​the orthographic projection of the pixel electrode on the substrate.

[0067] In a possible implementation, the array substrate further includes: a second common wiring extending along the second direction; the second common wiring is disconnected at a position where it intersects with the gate line.

[0068] In a possible embodiment, the array substrate further includes: a fifth common routing line electrically connected to at least a portion of the first common routing line and extending along the second direction; the orthographic projection of the fifth common routing line on the substrate covers at least a portion of the orthographic projection of the gap between the data line and the pixel electrode on the substrate.

[0069] In one possible embodiment, the array substrate includes: a second common routing group extending along the second direction; the second common routing group is disconnected at a position intersecting the gate line; the second common routing group includes: a first sub-common routing group and a second sub-common routing group arranged along the first direction, wherein a length of the first sub-common routing group in the second direction is less than a length of the second sub-common routing group in the second direction, and in the second direction, the first sub-common routing group and the second sub-common routing group are alternately arranged;

[0070] The array substrate further includes: a common compensation portion connected to a side of the first sub-common routing line away from the second sub-common routing line; and the fifth common routing line includes the first sub-common routing line and the common compensation portion.

[0071] In a possible implementation manner, the fifth common line has a fifth outer edge extending along the second direction; and extension lines of the fifth outer edges of two adjacent fifth common lines in the second direction do not overlap.

[0072] In a possible implementation, the fifth common line includes: a line body, and a line protrusion extending from at least one side of the line body along the second direction;

[0073] The array substrate further includes a transistor, which includes a first electrode, a second electrode, and a third electrode. The orthographic projection of the routing protrusion on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

[0074] In a possible implementation manner, the orthographic projection of the fifth common line on the substrate does not overlap with the orthographic projection of the data line on the substrate, and has an overlapping area with the orthographic projection of the pixel electrode on the substrate.

[0075] In a possible implementation manner, the maximum length of the fifth common line in the second direction is less than the minimum distance between two adjacent gate lines in the second direction;

[0076] A width of the fifth common line in the first direction is greater than a width of the second sub-common line in the first direction.

[0077] In a possible implementation, the array substrate further includes: a third common line extending along the first direction; the third common line is disconnected at a position where it intersects with the data line; and the third common line passes through the center of the third gate line portion.

[0078] In a possible embodiment, the array substrate further includes: a fourth common routing line extending along the second direction; the fourth common routing line is an orthographic projection of the substrate, passing through the central area of ​​the orthographic projection of the pixel electrode on the substrate; and the plurality of third common routing lines between two adjacent data lines are all connected to the fourth common routing line.

[0079] In a possible implementation, the plurality of pixel electrodes include: pixel electrode rows extending along the first direction, and pixel electrode columns extending along the second direction;

[0080] The pixel electrodes in the same pixel electrode row have the same light wavelength range;

[0081] The pixel electrode column includes a plurality of pixel electrode groups distributed in sequence along the second direction, and the pixel electrode groups include: a first pixel electrode, a second pixel electrode, and a third pixel electrode distributed in sequence along the second direction; the light band range emitted by the first pixel electrode is greater than the light band range emitted by the second pixel electrode, and the light band range emitted by the second pixel electrode is greater than the light band range emitted by the third pixel electrode.

[0082] In a possible implementation, in the pixel electrode column, two adjacent pixel electrodes are electrically connected to different data lines respectively; and in the pixel electrode row, all the pixel electrodes are electrically connected to the same gate line.

[0083] In a possible implementation, the array substrate further includes: a color resist layer; the color resist layer includes: a first color resist stripe, a second color resist stripe, and a third color resist stripe extending along the first direction and sequentially distributed along the second direction;

[0084] The orthographic projection of the first color-blocking strip on the substrate covers the orthographic projection of the first pixel electrode on the substrate; the orthographic projection of the second color-blocking strip on the substrate covers the orthographic projection of the second pixel electrode on the substrate; the orthographic projection of the third color-blocking strip on the substrate covers the orthographic projection of the third pixel electrode on the substrate.

[0085] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes: an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0086] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0087] The present disclosure further provides a display panel driving method as provided in the present disclosure, which includes:

[0088] Controlling a plurality of gate lines to load scanning signals row by row, and controlling the gate lines to load the scanning signals for a duration greater than 1H;

[0089] During at least a portion of a period in which the gate line is loaded with a scan signal, the data line is controlled to be loaded with a data signal.

[0090] In a possible implementation manner, controlling the gate line to be loaded with the scanning signal for a duration greater than 1H includes:

[0091] The duration of controlling the gate line to load the scanning signal is 4H. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG1A is a schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0093] FIG1B is a schematic diagram of a single film layer where the gate lines are located in FIG1A;

[0094] FIG1C is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0095] FIG1D is a schematic diagram of a single film layer where the data line is located in FIG1A;

[0096] FIG1E is a schematic diagram of a single film layer where the pixel electrode is located in FIG1A ;

[0097] FIG1F is an enlarged schematic diagram of the transistor T in FIG1A ;

[0098] FIG1G is a schematic cross-sectional view of the dashed line AA′ in FIG1A ;

[0099] FIG1H is a schematic cross-sectional view of the dashed line BB′ in FIG1A ;

[0100] FIG2A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0101] FIG2B is a schematic diagram of a single film layer where the gate lines are located in FIG2A;

[0102] FIG2C is a schematic diagram of a single film layer of the active layer in FIG2A ;

[0103] FIG2D is a schematic diagram of a single film layer where the data line is located in FIG2A;

[0104] FIG2E is a schematic diagram of a single film layer where the pixel electrode is located in FIG2A ;

[0105] FIG3A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0106] FIG3B is a schematic diagram of a single film layer where the gate lines are located in FIG3A;

[0107] FIG3C is a schematic diagram of a single film layer of the active layer in FIG3A ;

[0108] FIG3D is a schematic diagram of a single film layer where the data line is located in FIG3A;

[0109] FIG3E is a schematic diagram of a single film layer where the pixel electrode is located in FIG3A ;

[0110] FIG3F is an enlarged schematic diagram of the transistor T in FIG3A ;

[0111] FIG3G is an enlarged schematic diagram of the dotted box S1 in FIG3A ;

[0112] FIG4A is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0113] FIG4B is a schematic diagram of a single film layer where the gate lines are located in FIG4A;

[0114] FIG4C is a schematic diagram of a single film layer of the active layer in FIG4A ;

[0115] FIG4D is a schematic diagram of a single film layer where the data line is located in FIG4A;

[0116] FIG4E is a schematic diagram of a single film layer where the pixel electrode is located in FIG4A ;

[0117] FIG5 is a schematic diagram of a pixel driving architecture provided by an embodiment of the present disclosure;

[0118] FIG6 is a schematic diagram of a color resist layer provided by an embodiment of the present disclosure;

[0119] FIG7 is a schematic diagram of a method for driving a display panel according to an embodiment of the present disclosure;

[0120] FIG8A is a schematic diagram of a driving process according to an embodiment of the present disclosure;

[0121] FIG8B is a driving timing diagram provided by an embodiment of the present disclosure;

[0122] FIG9A is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0123] FIG9B is a schematic diagram of a single film layer where the gate lines are located in FIG9A;

[0124] FIG9C is a schematic diagram of a single film layer of the active layer in FIG9A;

[0125] FIG9D is a schematic diagram of a single film layer where the data line is located in FIG9A;

[0126] FIG9E is a schematic diagram of a single film layer where the pixel electrode is located in FIG9A ;

[0127] FIG9F is an enlarged schematic diagram of the transistor T in FIG9A . DETAILED DESCRIPTION

[0128] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. The implementation method can be implemented in a variety of different forms. Ordinary technicians in the relevant technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0129] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0130] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%. In this specification, "approximately the same" may refer to values ​​that are within 10% of each other.

[0131] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0132] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0133] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0134] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0135] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0136] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0137] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0138] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0139] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0140] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0141] Low cost has become a must for LCD panel development. The triple-gate pixel driver structure can effectively reduce the number of COF ICs, but the pixel aperture ratio will be seriously affected by the change from vertical to horizontal pixel arrangement.

[0142] 1A to 1H, 2A to 2E, 3A to 3G, and 4A to 4E, wherein FIG1A is one of the schematic diagrams of the array substrate provided in an embodiment of the present disclosure, FIG1B is a schematic diagram of a single film layer of the layer where the gate line is located in FIG1A, FIG1C is a schematic diagram of a single film layer of the active layer in FIG1A, FIG1D is a schematic diagram of a single film layer of the layer where the data line is located in FIG1A, FIG1E is a schematic diagram of a single film layer of the layer where the pixel electrode is located in FIG1A, FIG1F is an enlarged schematic diagram of the transistor T in FIG1A, FIG1G is a cross-sectional schematic diagram at the dotted line A-A' in FIG1A, FIG1H is a cross-sectional schematic diagram at the dotted line B-B' in FIG1A, FIG2A is a second schematic diagram of the array substrate provided in an embodiment of the present disclosure, FIG2B is a schematic diagram of a single film layer of the layer where the gate line is located in FIG2A, FIG2C is a schematic diagram of a single film layer of the active layer in FIG2A, FIG2D is a schematic diagram of a single film layer of the layer where the data line is located in FIG2A, and FIG2 E is a schematic diagram of a single film layer where the pixel electrode is located in FIG2A , FIG3A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure, FIG3B is a schematic diagram of a single film layer where the gate line is located in FIG3A , FIG3C is a schematic diagram of a single film layer where the active layer is located in FIG3A , FIG3D is a schematic diagram of a single film layer where the data line is located in FIG3A , FIG3E is a schematic diagram of a single film layer where the pixel electrode is located in FIG3A , FIG3F is an enlarged schematic diagram of the transistor T in FIG3A , FIG3G is an enlarged schematic diagram of the dotted box S1 in FIG3A , FIG4A is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure, FIG4B is a schematic diagram of a single film layer where the gate line is located in FIG4A , FIG4C is a schematic diagram of a single film layer where the active layer is located in FIG4A , FIG4D is a schematic diagram of a single film layer where the data line is located in FIG4A , and FIG4E is a schematic diagram of a single film layer where the pixel electrode is located in FIG4A . An embodiment of the present disclosure provides an array substrate, which includes:

[0143] Substrate 1;

[0144] A plurality of gate lines 2 are located on one side of a substrate 1, and the plurality of gate lines 2 extend along a first direction X; at least one gate line 2 among the plurality of gate lines 2 includes a plurality of gate line groups 20 sequentially distributed along the first direction X; the gate line group 20 includes: a first gate line portion 21 extending along the first direction X and sequentially distributed, a second gate line portion 22, and a third gate line portion 23 located between the first gate line portion 21 and the second gate line portion 22 and connecting the first gate line portion 21 and the second gate line portion 22; an extension line of the first gate line portion 21 does not coincide with an extension line of the second gate line portion 22, and an extension direction of the third gate line portion 23 intersects the first direction X; specifically, the first gate line portion 21 and the second gate line portion 22 may not be located on the same straight line, and in unconventional technology, the entire gate line is a horizontal straight line; the first gate line portion 21, the third gate line portion 23, and the second gate line portion 22 may form a "Z"-shaped pattern;

[0145] A plurality of data lines 3 are located on the same side of the substrate 1 as the plurality of gate lines 2 , and the plurality of data lines 3 extend along a second direction Y;

[0146] The plurality of pixel electrodes 4 include at least one pixel electrode 4 of the plurality of pixel electrodes 4, and at least a portion of its orthographic projection on the substrate 1 is located in the region formed by the intersection of the gate line 2 and the data line 3. The maximum length a1 of the pixel electrode 4 in the first direction X is greater than the maximum length a2 in the second direction Y. That is, the long side direction of the pixel electrode 4 is the same as the extension direction of the gate line 2. The orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 at least partially overlap with the orthographic projections of the first gate line portion 21 and the second gate line portion 22 on the substrate 1. Specifically, the orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 may cover the orthographic projections of the first gate line portion 21 and the second gate line portion 22 on the substrate 1.

[0147] In the embodiment of the present disclosure, the maximum length a1 of the pixel electrode 4 in the first direction X is greater than the maximum length a2 in the second direction Y, and a triple gate pixel drive (Triple Gate) structure is adopted. The gate line group 20 includes: a first gate line portion 21 and a second gate line portion 22 extending and sequentially distributed along the first direction X; the extension line of the first gate line portion 21 does not overlap with the extension line of the second gate line portion 22, and the orthographic projection of the plurality of pixel electrodes 4 on the substrate 1 at least partially overlaps with the orthographic projection of the first gate line portion 21 and the second gate line portion 22 on the substrate 1, and can overlap with the UV2A edge. The pixel electrode 4 can shield the electric field on the gate line 2 to avoid light leakage at the gate line 2 of the array substrate. The width of the black matrix directly above the gate line 2 can be reduced to a certain extent or no longer needs to be set, which greatly improves the aperture ratio. Moreover, the position of the gate line 2 can overlap with the part of the UV2A dark pattern, which can further improve the transmittance.

[0148] It should be noted that, in the embodiment of the present disclosure, the pixel electrode 4 may be designed as a whole piece; in another possible implementation manner, the pixel electrode 4 may also be a structure including slits and strip electrodes, which is not limited here.

[0149] In addition, in the embodiment of the present disclosure, there is no light-shielding pattern between the two pixel electrodes 4 in the second direction Y, and no other conductive wires are required to shield the electric field (such as the conductive wire extending along the first direction X on the same layer as the pixel electrode 4, Gate BM Less, GBS line), thereby reducing the gap between the two pixel electrodes 4 (it is expected to be reduced from about 20 μm (depending on the line width of the gate line 2) to about 5 μm (depending on the process capability of preventing connection when the pixel electrode 4 layer is patterned), and the aperture ratio is almost unaffected by the line width of the gate line 2, thereby improving the transmittance of the product; the gate line 2 and UV2A The dark patterns of the characters overlap, and the transmittance loss of the metal opaqueness can be minimized, thereby improving the product transmittance. The width of the gate line 2 can be changed freely for transmittance, and the width of the gate line 2 can be adjusted for display panels of different product specifications without losing transmittance. Compared with the traditional gate line 2, the width increases and the transmittance decreases proportionally, which has a great advantage. The gate line 2 does not require a black matrix design, avoiding the problem of light leakage at the edge of the black matrix caused by unstable liquid crystal alignment at the black matrix corner (Taper corner).

[0150] It should be noted that, in the embodiment of the present disclosure, the gate line 2 extends along the first direction X, which can be understood as the overall extension direction of the gate line 2 extending along the first direction X, but there may be bends at specific local positions; similarly, the data line 3 extends along the second direction Y, which can be understood as the overall extension direction of the data line 3 extending along the second direction Y, but there may be bends at specific local positions; specifically, when the data line 3 is a straight line, the data line 3 extends along the second direction Y, which can also be understood as the data line 3 extending along the second direction Y at all positions.

[0151] In a possible implementation, referring to Figures 1A-1H, 2A-2E, 3A-3G, and 4A-4E, the third gate line portion 23 extends along the second direction Y, and the extension line of the third gate line portion 23 passes through the central area of ​​the pixel electrode 4.

[0152] In one possible embodiment, the third gate line portion 23 may also form an angle of 30° to 60° with the second direction Y. In another possible embodiment, the third gate line portion 23 may also form an angle of 45° with the second direction Y. In another possible embodiment, the third gate line portion 23 may also be in the shape of an S-shaped curve, an arc, or a broken line.

[0153] In one possible embodiment, referring to FIG. 1A , FIG. 1B , and FIG. 1E , a length a3 of the gate line group 20 in the first direction X is less than or equal to a maximum length a1 of the pixel electrode 4 in the first direction X. That is, the gate line 2 can be arranged in a Z-shaped structure having a first gate line portion 21 , a third gate line portion 23 , and a second gate line portion 22 in the region corresponding to the pixel electrode 4 .

[0154] In a possible implementation, referring to FIG. 1A and FIG. 1B , a length a4 of the first gate line portion 21 in the first direction X is substantially equal to a length a5 of the second gate line portion 22 in the first direction X.

[0155] In a possible embodiment, referring to Figures 1A-1H, 2A-2E, 3A-3G, and 4A-4E, the gate line 2 further includes: a gate line connecting portion 24 located between adjacent gate line groups 20 and connecting adjacent gate line groups 20; the gate line connecting portion 24 extends along the first direction X, and the extension line is located between the first gate line portion 21 and the second gate line portion 22.

[0156] In a possible embodiment, referring to Figures 1A-1H, 2A-2E, 3A-3G, and 4A-4E, the gate line connection portion 24 includes: a first gate line connection portion 241, a second gate line connection portion 242, and a third gate line connection portion 243 distributed in sequence along the first direction X; the length a7 of the second gate line connection portion 242 in the second direction Y is greater than the length a6 of the first gate line connection portion 241 in the second direction Y, and greater than the length a8 of the third gate line connection portion 243 in the second direction Y.

[0157] In a possible implementation, referring to FIG. 1A-FIG , FIG. 2A-FIG , FIG. 3A-FIG , and FIG. 4A-FIG , the second gate line connection portion 242 may be reused as the control electrode TA (ie, the gate) of the transistor T. As shown in FIG.

[0158] In one possible embodiment, referring to Figures 1A to 1H, 2A to 2E, 3A to 3G, and 4A to 4E, in the same gate line group 20, the orthographic projection of the first gate line portion 21 on the substrate 1 is covered by the orthographic projection of a pixel electrode 4 on the substrate 1, and the orthographic projection of the second gate line portion 22 on the substrate 1 is covered by the orthographic projection of another adjacent pixel electrode 4 on the substrate 1 in the second direction Y. For example, as shown in Figure 1A, the orthographic projection of the first gate line portion 21 of the second gate line 2 in the top-to-bottom direction on the substrate 1 is covered by the orthographic projection of the first pixel electrode 4 in the top-to-bottom direction on the substrate 1, and the orthographic projection of the second gate line portion 22 of the second gate line 2 in the top-to-bottom direction on the substrate 1 is covered by the orthographic projection of the second pixel electrode 4 in the top-to-bottom direction on the substrate 1.

[0159] In one possible embodiment, referring to Figures 2A-2E, 3A-3G, and 4A-4E, the array substrate includes: a first axis k1 located between two adjacent pixel electrodes 4 and extending along a second direction Y; at least one data line 3 among the plurality of data lines 3 includes: a plurality of data groups 30 sequentially distributed along the second direction Y; the data group 30 includes: a first data portion 31 located on one side of the first axis k1, and a second data portion 32 located on the other side of the first axis k1; and the orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 at least partially cover the orthographic projections of the first data portion 31 and the second data portion 32 on the substrate 1. Specifically, the orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 cover the orthographic projections of the first data portion 31 and the second data portion 32 on the substrate 1.

[0160] In the embodiment of the present disclosure, the data line 3 includes: a plurality of data groups 30; the data group 30 includes: a first data portion 31 located on one side of the first axis k1, and a second data portion 32 located on the other side of the first axis k1; the orthographic projections of the plurality of pixel electrodes 4 on the substrate 1 at least partially cover the orthographic projections of the first data portion 31 and the second data portion 32 on the substrate 1, that is, the data line 3 is designed to be a "Z"-shaped structure and is covered by the pixel electrode 4, while being aligned with the UV2A edge. The dark lines of the characters overlap partially, that is, the pixel electrode 4 can shield the electric field at the data line 3, avoiding light leakage at the data line 3 of the array substrate. The width of the black matrix directly above the data line 3 can be reduced to a certain extent or no longer required, which greatly improves the aperture ratio. Moreover, in conventional technology, the pixel electrodes 4 in the same row have pixel electrodes with different light-emitting colors. When the data line 3 passes through different colors at the same time, when the panel is lit to test a monochrome screen, the data line 3 needs to be given a signal. When the data line 3 passes through other colors, because the first coupling capacitor C between the pixel electrode 4 and the data line 3 pd The influence of the light will pull the color of the sub-pixel that will not be lit, thereby forming color crosstalk. However, in the embodiment of the present disclosure, since the light output colors of the pixel electrodes 4 in the same row are the same, the data lines 3 and the pixel electrodes 4 overlap, and the problem of color crosstalk will not occur.

[0161] In one possible implementation, referring to Figures 2A-2E, 3A-3G, and 4A-4E, in the same data group 30, the orthographic projection of the first data portion 31 on the substrate 1 is at least partially covered by the orthographic projection of a pixel electrode 4 on the substrate 1, and the orthographic projection of the second data portion 32 on the substrate 1 is at least partially covered by the orthographic projection of another adjacent pixel electrode 4 on the substrate 1 in the first direction X. Specifically, for example, in Figure 2A, the orthographic projection of the first data portion 31 of the first data line 3 on the left on the substrate 1 is covered by the orthographic projection of the pixel electrode 4 on the left on the substrate 1, and the orthographic projection of the second data portion 32 of the first data line 3 on the left on the substrate 1 is covered by the orthographic projection of the pixel electrode 4 in the middle on the substrate 1.

[0162] In a possible embodiment, referring to Figures 2A-2E, 3A-3G, and 4A-4E, the data group 30 further includes: a third data portion 33 connecting the first data portion 31 and the second data portion 32, and the extension direction of the third data portion 33 intersects with the second direction Y.

[0163] In one possible embodiment, the third data portion 33 may also form an angle of 30° to 60° with the first direction X. In another possible embodiment, the third data portion 33 may also form an angle of 45° with the first direction X. In another possible embodiment, the third data portion 33 may also be in the shape of an S-shaped curve, an arc, or a broken line.

[0164] In one possible implementation, referring to Figures 2A to 2E, 3A to 3G, and 4A to 4E, a length a9 of the data group 30 in the second direction Y is less than or equal to a maximum length a2 of the pixel electrode 4 in the second direction Y. That is, the data line 3 can be arranged in a Z-shaped region corresponding to the pixel electrode 4, including a first data portion 3, a second data portion 32, and a third data portion 33.

[0165] In one possible embodiment, as shown in Figures 2A-2E , the first data portion 31 and the second data portion 32 both extend along the second direction Y, and the extension line of the first data portion 31 does not overlap with the second data portion 32. That is, the first data portion 31 and the second data portion 32 both extend along the second direction Y, but the first data portion 31 and the second data portion 32 are not located on the same straight line and are staggered.

[0166] In a possible embodiment, referring to Figures 2A-2E, the array substrate includes: a second axis k2 extending along the first direction X and passing through the center of the pixel electrode 4; the first data portion 31 and the second data portion 32 are respectively located on different sides of the second axis k2; and the second axis k2 passes through the center of the third data portion 33.

[0167] Specifically, the first data portion 31 , the third data portion 33 , and the second data portion 32 are sequentially connected along the second direction Y to form a data group 30 .

[0168] In one possible embodiment, as shown in Figures 2A-2E , the extension line of the second data portion 32 overlaps with the first data portion 31 in the adjacent data group 30. That is, the extension line of the second data portion 32 and the first data portion 31 in the adjacent data group 30 form a straight line structure.

[0169] In one possible embodiment, referring to FIG. 2A to FIG. 2E , the array substrate further includes: a plurality of transistors T; at least one of the plurality of transistors T includes: a control electrode TA, an active pattern 50, a first electrode TC1, and a second electrode TC2; an orthographic projection of the first sub-data portion 301 on the substrate 1 does not overlap with an orthographic projection of the active pattern 5 on the substrate 1;

[0170] The first stage TC1 multiplexes one of the first data portion 31 and the second data portion 32;

[0171] The second pole TC2 includes: a second pole first portion TC21 extending along the second direction Y, a second pole second portion TC22 extending along the first direction X, and a second pole overlapping portion TC2D connected to the second pole second portion TC22; the orthographic projection of one end of the second pole first portion TC21 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1; the other end of the second pole first portion TC21 is connected to one end of the second pole second portion TC22.

[0172] In one possible implementation, as shown in FIG2A to FIG2E , the second electrode overlap portion TC2D may overlap the center area of ​​the orthographic projection of the substrate 1 with the center area of ​​the orthographic projection of the pixel electrode 4. Specifically, the second electrode overlap portion TC2D and the pixel electrode 4 may be electrically connected by drilling in the overlapping area to achieve electrical connection between the pixel electrode 4 and the transistor T.

[0173] In a possible implementation, as shown in FIG. 2D , the second pole TC2 may further include: a second pole third portion TC23 extending along the second direction Y and connected to the other end of the second pole second portion TC22 .

[0174] In a possible implementation, referring to FIG. 2A to FIG. 2E , the length of the second portion TC22 of the second electrode in the first direction X may be substantially equal to the length of the pixel electrode 4 in the first direction X.

[0175] In one possible embodiment, referring to FIG1A to FIG1H , the length of the second portion TC22 of the second electrode in the first direction X may be one-third to two-thirds of the length of the pixel electrode 4 in the first direction X. In one possible embodiment, referring to FIG1A to FIG1H , the length of the second portion TC22 of the second electrode in the first direction X may be one-half of the length of the pixel electrode 4 in the first direction X.

[0176] In a possible implementation, referring to FIG. 3A to FIG. 3G and FIG. 4A to FIG. 4E , the first data portion 31 and the second data portion 32 are symmetrical about the first axis k1 .

[0177] In a possible embodiment, referring to FIG3D and FIG4D , the first data portion 31 and the second data portion 32 both include: a first sub-data portion 301, a second sub-data portion 302, and a third sub-data portion 303 extending along the second direction Y and distributed in sequence; the extension line of the first sub-data portion 301 coincides with the extension line of the third sub-data portion 303, and the extension line of the second sub-data portion 302 is located on the side of the first sub-data portion 301 away from the first axis k1.

[0178] In a possible embodiment, referring to FIG3D and FIG4D , the first data portion 31 and the second data portion 32 further include: a fourth sub-data portion 304 extending along the first direction X, and a fifth sub-data portion 305; the fourth sub-data portion 304 connects the first sub-data portion 301 and the second sub-data portion 302; and the fifth sub-data portion 305 connects the second sub-data portion 302 and the third sub-data portion 303.

[0179] In the disclosed embodiment, the first data portion 31 and the second data portion 32 both include: a first sub-data portion 301, a second sub-data portion 302, a third sub-data portion 303 extending along the second direction Y and distributed in sequence, a fourth sub-data portion 304 extending along the first direction X, and a fifth sub-data portion 305. Changing the "Z"-shaped data line 3 to a bilateral routing method can reduce the line width on one side, and the bilateral parallel method can make the resistance of the data line 3 smaller. At the same time, the bilateral routing improves the yield, and a single-side break does not affect the drive and load of the overall data line 3.

[0180] 3D and 4D , the fourth sub-data portion 304 , the third sub-data portion 303 , and the fifth sub-data portion 305 are sequentially connected to form a half-frame pattern; the first data portion 31 and the second data portion 32 are respectively connected to both sides of the half-frame pattern.

[0181] In a possible implementation, referring to FIG. 3D and FIG. 4D , the third data portion 33 extends along the first direction X and connects two fifth sub-data portions 305 of the same data group 30 .

[0182] In a possible implementation, referring to FIG. 3A-FIG , and FIG. 4A-FIG , the array substrate includes: a second axis k2 extending along the first direction X and passing through the center of the pixel electrode 4 ; the second axis k2 passes through the central area of ​​the second sub-data portion 302 .

[0183] In a possible implementation, referring to FIG. 3D and FIG. 4D , the first data portion 31 is symmetrical about the second axis k2 ; and the second data portion 32 is symmetrical about the second axis k2 .

[0184] In a possible implementation, referring to FIG. 3D and FIG. 4D , a length b1 of the first sub-data portion 301 in the second direction Y is substantially equal to a length b3 of the third sub-data portion 303 in the second direction Y.

[0185] In one possible embodiment, referring to FIG3D and FIG4D , the length b1 of the first sub-data portion 301 in the second direction Y is one-third to two-thirds of the length b2 of the second sub-data portion 302 in the second direction Y. In one possible embodiment, referring to FIG3D and FIG4D , the length b1 of the first sub-data portion 301 in the second direction Y is one-half of the length b2 of the second sub-data portion 302 in the second direction Y.

[0186] In a possible embodiment, referring to FIG3D and FIG4D , the data line 3 further includes: a data connection portion 34 connecting adjacent data groups 30, the data connection portion 34 including: two sub-data connection portions 340 extending along the second direction Y and arranged along the first direction X; the sub-data connection portion 340 connects the third sub-data portion 303 and the first sub-data portion 301 of the adjacent data group 30.

[0187] In one possible implementation, as shown in FIG3D and FIG4D , a length b4 of the sub-data connection portion 340 in the first direction X is less than a length b5 of the first sub-data portion 301 in the first direction X. This reduces the overlapping area between the gate line 2 and the data line 3 to prevent excessive overlapping area and the resulting excessive overlapping capacitance, which could affect signal transmission between the gate line 2 and the data line 3 and affect the charging rate of the pixel.

[0188] In one possible embodiment, as shown in conjunction with FIG3D and FIG3F , the array substrate further includes: a plurality of transistors T; at least one of the plurality of transistors T includes: a control electrode TA, an active pattern 50, and a first electrode TC1, a second electrode TC2, and a third electrode TC3 sequentially distributed along a first direction X; orthographic projections of the first electrode TC1, the second electrode TC2, and the third electrode TC3 on the substrate 1 all overlap with the orthographic projection of the control electrode TA on the substrate 1; and orthographic projections of the first electrode TC1, the second electrode TC2, and the third electrode TC3 on the substrate 1 all overlap with the orthographic projection of the active pattern 50 on the substrate 1.

[0189] a sub-data connection portion 340 in the first-stage TC1 multiplexed data connection portion 34; another sub-data connection portion 340 in the third-stage TC3 multiplexed data connection portion 34;

[0190] The second pole TC2 includes: a second pole first portion TC21 extending along the second direction X, and a second pole overlapping portion TC2D connected to one end of the second pole first portion TC21; the orthographic projection of the second pole first portion TC21 on the substrate 1 is located between the two first sub-data portions 301 of the data group 30; the orthographic projection of the second pole overlapping portion TC2D on the substrate 1 is located between the two second sub-data portions 302 of the data group 30.

[0191] In the embodiment of the present disclosure, the transistor T includes: a first electrode TC1, a second electrode TC2, and a third electrode TC3. The dual-source design can reduce the second electrode TC of the transistor T and the structure electrically connected to the second electrode TC (such as the pixel electrode 4, the active pattern 5), and the coupling capacitance Cgs formed with the gate line 20 under the condition that the width (W value) of the same transistor T is constant, thereby improving the charging rate.

[0192] Specifically, the control electrode TA of the transistor T can reuse the second gate line connection portion 242 in the gate line connection portion 24. Specifically, the first electrode TC1 and the third electrode TC3 can serve as the source of the transistor T, and the second electrode TC2 can serve as the drain of the transistor T.

[0193] In one possible implementation, as shown in FIG3D and FIG4D , the length b6 of the second electrode connection portion TC2D in the first direction X is less than the minimum spacing b7 between two second sub-data portions 302 in the data group 30. This prevents the second electrode connection portion TC2D and the second sub-data portion 302 located on the same layer from being connected, thereby affecting the performance of the transistor T.

[0194] In one possible embodiment, as shown in FIG3F , at least a portion of the outer edge of the first electrode TC1, as projected onto the substrate 1, overlaps with at least a portion of the outer edge of the active pattern 50, as projected onto the substrate 1; and at least a portion of the outer edge of the third electrode TC3, as projected onto the substrate 1, overlaps with at least a portion of the outer edge of the active pattern 50, as projected onto the substrate 1. This minimizes the line widths of the first and third electrodes TC1 and TC3, reduces the parasitic capacitance between the layer containing the data line 3 and the layer containing the gate line 2, and achieves a high brush charge rate.

[0195] In one possible embodiment, as shown in Figures 3A, 3E, and 3G, the pixel electrode 4 includes a pixel electrode body PA and a pixel electrode lap portion PB extending from one side of the pixel electrode body PA along a first direction X. The orthographic projection of the pixel electrode lap portion PB on the substrate 1 overlaps with the orthographic projection of the second electrode lap portion TC2D on the substrate 1. In this way, the pixel electrode lap portion PB and the second electrode lap portion TC2D can be connected by drilling at the overlapping portion, further achieving electrical connection between the transistor T and the pixel electrode 4.

[0196] In a possible implementation, referring to FIG. 3A , FIG. 3E , and FIG. 3G , the orthographic projection of the second electrode lap portion TC2D on the substrate 1 may cover the orthographic projection of the pixel electrode lap portion PB on the substrate 1 .

[0197] In one possible implementation, as shown in FIG3A , the pixel electrode main body PA has a recessed portion PC at the location where the pixel electrode overlapping portion PB is located. The recessed portion PC is projected orthographically on the substrate 1 and surrounds the pixel electrode overlapping portion PB. In the disclosed embodiment, the pixel electrode main body PA has the recessed portion PC to provide space for the pixel electrode overlapping portion PB to achieve further electrical connection with the transistor T.

[0198] In a possible implementation, as shown in FIG. 3A , the recessed portions PC of two adjacent pixel electrodes 4 may form a frame pattern with openings at certain positions, and the pixel electrode bridging portion PB may be located in the frame pattern.

[0199] In a possible embodiment, referring to FIG3A , the pixel electrode overlapping portions PB of two adjacent pixel electrodes 4 are respectively located on different sides of the pixel electrode body PA. For example, in FIG3E , in the first pixel electrode 4 from top to bottom, the pixel electrode overlapping portion PB is located on the left side of the pixel electrode body PA, and in the second pixel electrode 4 from top to bottom, the pixel electrode overlapping portion PB is located on the right side of the pixel electrode body PA.

[0200] In a possible embodiment, referring to FIG3G , the outer edge w1 of the second sub-data portion 302 is projected on the substrate 1, and the outer edge w2 of the recessed portion PC is located on the side of the substrate 1 projected away from the first axis k1; the outer edge w2 of the recessed portion PC is projected on the substrate, and the outer edge w3 of the second pole overlap portion TC2D is located on the side of the substrate projected away from the first axis k1.

[0201] In one possible embodiment, referring to FIG. 1A to FIG. 1H , the data line 3 includes: a first data portion 31 and a second data portion 32 alternately distributed along the second direction Y; wherein the first data portion 31 is located in the region between two adjacent pixel electrodes 4 in the first direction X; the orthographic projection of the second data portion 32 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1; specifically, the first data portion 31 may be a portion of the data line 3 at a region corresponding to the pixel electrode 4, and the second data portion 32 may be a portion of the data line 3 at a region overlapping with the gate line 2;

[0202] The second data portion 32 includes a first sub-data portion 301 and a second sub-data portion 302 extending along the second direction Y and arranged sequentially along the first direction X. One end of the first sub-data portion 301 and one end of the second sub-data portion 302 are both connected to a first data portion 31, and the other end of the first sub-data portion 301 is connected to another adjacent first data portion 31. The other end of the second sub-data portion 302 is open and not connected to any other structure.

[0203] In the disclosed embodiment, the second data portion 32 includes: two first sub-data portions 301 and second sub-data portions 302 extending along the second direction Y and sequentially distributed along the first direction X. When a sub-pixel at that location has poor light emission, the second sub-data portion 302 can be cut off (as shown by the thick solid line in FIG1F ), thereby cutting off the transistor T at that location, so that the sub-pixel at that location is in a non-luminous state (actively luminous or passively luminous). Since the data line also has the first sub-data portion 301, cutting off the second sub-data portion 302 at that location will not affect the overall signal transmission of the data line 3. That is, when a local defect occurs, a large-area display defect problem of the display panel can be avoided at a lower repair cost.

[0204] In a possible implementation, as shown in FIG. 1D , a maximum length c1 of the second sub-data portion 302 in the second direction Y is smaller than a maximum length c2 of the first sub-data portion 301 in the second direction Y.

[0205] In a possible embodiment, as shown in Figure 1D, the array substrate includes: a first axis k1 located between two adjacent pixel electrodes 4 and extending along the second direction Y; in two adjacent second data parts 32, two second sub-data parts 302 are respectively located on different sides of the first axis k1; and two first sub-data parts 301 are respectively located on different sides of the first axis k1.

[0206] In one possible implementation, referring to Figures 1A-1H , the array substrate further includes: a first conductive line 29 extending along a second direction Y; the orthographic projection of the first conductive line 29 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1. In the disclosed embodiment, the orthographic projection of the first conductive line 29 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1, thereby shielding the electric field on the data line 3 and preventing light leakage. This eliminates the need for a black matrix directly above the data line 3, thereby improving the pixel aperture ratio.

[0207] In a possible implementation, the first conductive line 29 may be made of the same layer and material as the pixel electrode 4 .

[0208] In one possible embodiment, as shown in Figures 1A-1H , the first conductive line 29 may include: a first conductive portion 291 and a second conductive portion 292 alternately distributed along the second direction Y; the orthographic projection of the first conductive portion 291 on the substrate 1 is located in the region between the orthographic projections of two adjacent pixel electrodes 4 on the substrate 1 in the first direction X; the orthographic projection of the second conductive portion 292 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1. Specifically, the orthographic projection of the second conductive portion 292 on the substrate 1 may cover the orthographic projection of the second data portion 32 on the substrate 1.

[0209] In a possible implementation, referring to FIG. 1A to FIG. 1H , a maximum length d1 of the first conductive portion 291 in the first direction X is smaller than a maximum length d2 of the second conductive portion 292 in the first direction X.

[0210] In one possible embodiment, as shown in Figures 1A to 1H, the orthographic projection of the second conductive portion 291 on the substrate 1 may be a diamond shape, which can well cover the transistor; the orthographic projection of the first conductive portion 291 on the substrate 1 may be a rectangle, and the length of the first conductive portion 291 along the second direction Y is greater than the length along the first direction X. In one possible embodiment, the orthographic projection of the second conductive portion 291 on the substrate 1 may also be a rectangle, a circle, an ellipse, a trapezoid, or a triangle. In the embodiment of the present disclosure, the provision of the first conductive portion 291 and the second conductive portion 292 can reduce the coupling capacitance between the gate line 2 and the pixel electrode 4.

[0211] In one possible embodiment, referring to FIG. 1A to FIG. 1H , the array substrate further includes: a plurality of transistors T; at least one of the plurality of transistors T includes: a control electrode TA, an active pattern 50, a first electrode TC1, and a second electrode TC2; an orthographic projection of the first sub-data portion 301 on the substrate 1 does not overlap with an orthographic projection of the active pattern 50 on the substrate 1;

[0212] The first stage TC1 multiplexes the second sub-data portion 302;

[0213] The second pole TC2 includes: a second pole first portion TC21 extending along the second direction Y, a second pole second portion TC22 extending along the first direction X, and a second pole overlapping portion TC2D connected to the second pole second portion TC22; the orthographic projection of one end of the second pole first portion TC21 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1; the other end of the second pole first portion TC21 is connected to one end of the second pole second portion TC22, and the other end of the second pole second portion TC22 is connected to the second pole overlapping portion TC2D.

[0214] In one possible implementation, as shown in FIG1A to FIG1H , the second electrode overlap portion TC2D may overlap with the pixel electrode 4 in the center region of the orthographic projection of the substrate 1. Specifically, the second electrode overlap portion TC2D and the pixel electrode 4 may be electrically connected by punching a hole in the insulating layer at the overlapping region to achieve electrical connection between the pixel electrode 4 and the transistor T.

[0215] In one possible embodiment, referring to FIG1A to FIG1H , the length of the second portion TC22 of the second electrode in the first direction X may be one-third to two-thirds of the length of the pixel electrode 4 in the first direction X. In one possible embodiment, referring to FIG1A to FIG1H , the length of the second portion TC22 of the second electrode in the first direction X may be one-half of the length of the pixel electrode 4 in the first direction X.

[0216] In a possible embodiment, referring to FIG9A to FIG9E , at least one data line 3 among the plurality of data lines 3 includes: a first data portion 31 and a second data portion 32 alternately distributed along the second direction Y; in the second direction Y, the extension lines of the two first data portions 31 on both sides of the second data portion 32 do not overlap, that is, the data line 3 is distributed in a meandering shape; the second data portion 32 includes: a first sub-data portion 301, a second sub-data portion 302, and a third sub-data portion 303; the first sub-data portion 301 extends along the first direction X; the second sub-data portion 302 and the third sub-data portion 303 extend along the second direction Y and are located on the same side of the first sub-data portion 301; one end of the first sub-data portion 301 is adjacent to the second sub-data portion 302. 2, and the other end is connected to one end of the third sub-data part 303 and a first data part 31; the other end of the second sub-data part 302 is connected to another first data part 31. Specifically, taking the second second data part 32 from top to bottom in FIG. 9D as an example, the right end of the first sub-data part 301 is connected to the lower end of the second sub-data line 302, and the left end is connected to the lower end of the third sub-data part 303 and the first data line part 31 below. The upper end of the second sub-data part 302 is connected to the first data line part 31 above. The other end of the third sub-data part 303 is in an open state and is not connected to other structures. The first sub-data part 301, the second sub-data part 302, and the third sub-data part 303 form a U-shaped pattern as a whole.

[0217] In the embodiment of the present disclosure, the second data portion 32 includes: a first sub-data portion 301, a second sub-data portion 302, and a third sub-data portion 303, which form a U-shaped pattern. Among them, the second sub-data portion 302 and the third sub-data portion 303 can reuse the first electrode TC1 and the third electrode TC3 of the transistor, so that the transistor has a dual-source design. Under the condition that the width (W value) of the same transistor T is constant, the source of the transistor T and the structure electrically connected to the source (such as the pixel electrode 4, the active pattern 5), and the coupling capacitance Cgs formed with the gate line 2 can be reduced, thereby improving the charging rate.

[0218] In one possible implementation, referring to Figures 9A-9E , the orthographic projection of the first data portion 31 on the substrate 1 is located between the orthographic projections of two adjacent pixel electrodes 4 on the substrate 1 in the first direction Y. The orthographic projection of the second data portion 32 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1. Optionally, the orthographic projection of the first data portion 31 on the substrate 1 does not overlap with the orthographic projection of the gate line 2 on the substrate 1.

[0219] Optionally, the data line 3 at a position corresponding to the pixel electrode 4 may be used as the first data portion 31 , and the data line 3 at a position corresponding to the gap between two adjacent rows of pixel electrodes 4 may be used as the second data portion 32 .

[0220] In one possible embodiment, as shown in Figures 9A and 9D, the orthographic projection of the first data part 31 and / or the second data part 32 on the substrate 1 does not overlap with the orthographic projection of the pixel electrode 4 on the substrate 1, which can reduce the coupling capacitance between the data line 3 and the pixel electrode 4, and effectively improve the crosstalk caused by the coupling capacitance between the data line 3 and the pixel electrode 4; at the same time, it reduces the overall load of the data line 3, and effectively improves the charging bottleneck problem of the three-gate pixel driving structure.

[0221] In a possible implementation, referring to FIG. 9A to FIG. 9E , a length f1 of the first data portion 31 in the second direction Y is less than or equal to a maximum length f2 of the pixel electrode 4 in the second direction Y.

[0222] In one possible embodiment, referring to FIG. 9A to FIG. 9E and FIG. 9F , FIG. 9F is an enlarged schematic diagram of the transistor T in FIG. 9A , and the array substrate further includes: a plurality of transistors T; at least one of the plurality of transistors T includes: a control electrode TA, an active pattern 50, and a first electrode TC1, a second electrode TC2, and a third electrode TC3 sequentially distributed along a first direction X; orthographic projections of the first electrode TC1, the second electrode TC2, and the third electrode TC3 on the substrate 1 all overlap with the orthographic projection of the control electrode TA on the substrate 1; and orthographic projections of the first electrode TC1, the second electrode TC2, and the third electrode TC3 on the substrate 1 all overlap with the orthographic projection of the active pattern 50 on the substrate 1.

[0223] The first stage TC1 multiplexes the second sub-data portion 302; the third stage TC3 multiplexes the third sub-data portion 303;

[0224] The second pole TC2 includes: a second pole first portion TC21 extending along the second direction Y, and a second pole overlapping portion TC2D connected to one end of the second pole first portion TC21; the part of the orthographic projection of the second pole first portion TC21 on the substrate 1 is located between the orthographic projections of the second sub-data portion 302 and the third sub-data portion 303 on the substrate 1.

[0225] In the embodiment of the present disclosure, the transistor T includes: a first electrode TC1, a second electrode TC2, and a third electrode TC3. The dual-source design can reduce the second electrode TC of the transistor T and the structure electrically connected to the second electrode TC (such as the pixel electrode 4, the active pattern 5), and the coupling capacitance Cgs formed with the gate line 2 under the condition that the width (W value) of the same transistor T is constant, thereby improving the charging rate.

[0226] In a possible embodiment, referring to FIG9A to FIG9E , the length f3 of the second overlap portion TC2D in the second direction Y is substantially equal to the length f1 of the first data portion 31 in the second direction Y. In the embodiment of the present disclosure, by setting the second overlap portion TC2D longer in the second direction Y, the storage capacitance Cst formed between the pixel electrode 4 and the common electrode layer of the opposite substrate can be increased (because the second overlap portion TC2D is electrically connected to the pixel electrode 4 through a transistor, the second overlap portion TC2D can be used as a structure integrated with the pixel electrode 4). Without affecting the aperture ratio, increasing the storage capacitance Cst formed between the pixel electrode 4 and the common electrode layer of the opposite substrate can effectively improve crosstalk, afterimages, leakage caused by frequency conversion (leakage is more serious at low frequencies), vertical lines caused by the polarity reversal of the chip on flex (COF), and other display defects.

[0227] In a possible implementation, as shown in FIG. 9A to FIG. 9E , a width f4 of the second pole overlapping portion TC2D in the first direction X is greater than a width f5 of the second pole first portion TC21 in the first direction X.

[0228] In a possible implementation, as shown in FIG. 9A , the orthographic projection of the second electrode overlapping portion TC2D on the substrate 1 may overlap with the orthographic projection of the pixel electrode 4 on the substrate 1 .

[0229] In one possible embodiment, as shown in conjunction with FIG. 9A and FIG. 9E , the pixel electrode 4 includes: a pixel electrode body PA; and a pixel electrode lap portion PB extending from one side of the pixel electrode body PA along a first direction X. The orthographic projection of the pixel electrode lap portion PB on the substrate 1 overlaps with the orthographic projection of the second electrode lap portion TC2D on the substrate 1. In this way, the pixel electrode lap portion PB and the second electrode lap portion TC2D can be connected by drilling at the overlapping portion, further achieving electrical connection between the transistor T and the pixel electrode 4.

[0230] In a possible implementation, as shown in FIG. 9E , the orthographic projection of the second electrode overlapping portion TC2D on the substrate 1 may cover the orthographic projection of the pixel electrode overlapping portion PB on the substrate 1 .

[0231] 9A and 9F , the control electrode TA of the transistor T can reuse the gate line 2. Specifically, the first electrode TC1 and the third electrode TC3 can serve as the source of the transistor T, and the second electrode TC2 can serve as the drain of the transistor T.

[0232] In one possible embodiment, referring to Figures 1A-1H, 2A-2E, 3A-3G, and 4A-4E, the array substrate further includes: a first common trace 61 extending along a first direction X, and a common lap portion 60 connected to the first common trace 61; the orthographic projection of the first common trace 61 on the substrate 1 passes through the central area of ​​the orthographic projection of the pixel electrode 4 on the substrate 1. In one possible embodiment, referring to Figures 1A and 1B, the orthographic projection of the first common trace 61 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a first storage capacitor is formed by the first common trace 61 and the pixel electrode 1.

[0233] In one possible embodiment, referring to Figures 1A to 1H and Figures 2A to 2E, the common overlap portion 60 in the central area of ​​the orthographic projection of the substrate 1 may overlap with the central area of ​​the orthographic projection of the pixel electrode 4 in the substrate 1; in one possible embodiment, referring to Figures 3A to 3G and Figures 4A to 4E, the common overlap portion 60 in the central area of ​​the orthographic projection of the substrate 1 may overlap with the gap between two adjacent pixel electrodes 4 in the first direction X in the central area of ​​the orthographic projection of the substrate 1.

[0234] In one possible embodiment, referring to Figures 3A-3G and 4A-4E, the orthographic projection of the common overlap portion 60 on the substrate 1 may overlap with the orthographic projection of the second pole overlap portion TC2D on the substrate 1; in one possible embodiment, referring to Figures 3A-3G and 4A-4E, the orthographic projection of the common overlap portion 60 on the substrate 1 covers the orthographic projection of the second pole overlap portion TC2D on the substrate 1.

[0235] In one possible implementation, referring to Figures 1A-1H, 2A-2E, 3A-3G, and 4A-4E, the array substrate further includes: a second common trace 62 extending along the second direction Y; the second common trace 62 is disconnected at a location where it intersects with the gate line 2. Specifically, an orthographic projection of the second common trace 62 on the substrate 1 at least partially overlaps with an orthographic projection of a gap between adjacent pixel electrodes 4 in the first direction X on the substrate 1.

[0236] In one possible embodiment, referring to Figures 1A-1H , the array substrate further includes: a second common routing group 620 extending along a second direction Y; the second common routing group 620 is disconnected at a location where it intersects with the gate line 2, and the second common routing group 620 includes two second common routing lines 62 extending along the second direction Y. Referring to Figure 1A , the two second common routing lines 62 are disposed on both sides of the data line and can be used to shield the coupling capacitance between the data line and the pixel electrode.

[0237] In one possible embodiment, referring to Figures 1A to 1H and Figures 9A to 9E, the two second common routing lines 62 of the same second common routing line group 620 may be a first sub-common routing line 621 and a second sub-common routing line, respectively, wherein the length of the first sub-common routing line 621 in the second direction Y may be less than the length of the second sub-common routing line 622 in the second direction Y, and in the second direction Y, the first sub-common routing line 621 and the second sub-common routing line 622 are alternately arranged; specifically, in combination with Figure 1A, the orthographic projection of the first sub-common routing line 621 on the substrate 1 , is opposite to the orthographic projection of the first sub-data portion 301 on the substrate 1, and the orthographic projection of the second sub-common routing 622 on the substrate 1 is opposite to the orthographic projection of the second sub-data portion 302 on the substrate 1. Since the maximum length of the first sub-data portion 301 in the second direction Y is greater than the maximum length of the second sub-data portion 302 in the second direction Y, by making the length of the first sub-common routing 621 in the second direction Y less than the length of the second sub-common routing 622 in the second direction Y, it is possible to avoid overlapping of the first sub-common routing 621 and the first sub-data portion 301 and affecting the transistor performance.

[0238] In one possible embodiment, referring to Figures 9A-9E , the array substrate further includes: a fifth common trace 65 electrically connected to at least a portion of the first common trace 61 and extending along the second direction Y; the orthographic projection of the fifth common trace 65 on the substrate 1 covers at least a portion of the orthographic projection of the gap between the data line 3 and the pixel electrode 4 on the substrate 1. In the disclosed embodiment, the array substrate further includes a fifth common trace 65; the orthographic projection of the fifth common trace 65 on the substrate 1 covers at least a portion of the orthographic projection of the gap between the data line 3 and the pixel electrode 4 on the substrate 1. This can shield or reduce the lateral parasitic capacitance between the data line 3 and the pixel electrode 4, thereby improving a series of image quality issues such as crosstalk caused by the lateral parasitic capacitance between the data line 3 and the pixel electrode 4, vertical lines caused by COF polarity reversal, and mixed color vertical lines.

[0239] In a possible embodiment, in combination with Figures 9A-9E, the array substrate further includes: a common compensation portion 650 connected to the side of the first sub-common routing 621 away from the second sub-common routing 622; the fifth common routing 65 includes the first sub-common routing 621 and the common compensation portion 650.

[0240] In one possible implementation, as shown in FIG9B , adjacent fifth common traces 65 are staggered along the second direction Y. Specifically, the fifth common traces 65 have fifth outer edges w5 extending along the second direction Y. Extensions of the fifth outer edges w5 of two adjacent fifth common traces 65 in the second direction Y do not overlap. This adapts to the bend of the data line 3 and avoids overlap with the data line 3.

[0241] In one possible embodiment, referring to Figures 9A, 9B, and 9F, the fifth common trace 65 includes: a trace body 651, and a trace protrusion 652 extending from at least one side of the trace body 651 along the second direction Y; the array substrate also includes: a transistor; the transistor includes: a first electrode TC1, a second electrode TC2, and a third electrode TC3; the orthographic projection of the trace protrusion 652 on the substrate 1 overlaps with the orthographic projection of the second electrode TC2 on the substrate 1.

[0242] In a possible embodiment, referring to Figures 9A and 9B, in the second direction Y, the number of routing protrusions 652 of two adjacent fifth common routing lines 65 may be different. For example, in Figure 9B, the first fifth common routing line 65 on the right side from top to bottom has one routing protrusion 652 on the upper side and one routing protrusion 652 on the lower side; while the second fifth common routing line 65 on the right side from top to bottom has one routing protrusion 652 on the upper side and two routing protrusions 652 on the lower side to adapt to other structures at different positions (for example, the first fifth common routing line 65 on the right side from top to bottom has one routing protrusion 652 on the lower side to adapt to the shape of the gate line 2 at that position to avoid overlapping with the gate line 2).

[0243] In the disclosed embodiment, the driving architecture is a Z architecture, and one data line 3 drives the pixel electrodes 4 on the left and right sides of the data line 3. The number of routing protrusions 652 of different fifth common routing lines 65 can be different, so that the fifth common routing line 65 can match the structure between the first data part 31, the second data part 32 and the gate line 2, and the area of ​​the fifth common routing line 65 can be maximized as much as possible without affecting other structural functions.

[0244] In a possible embodiment, referring to FIG. 9A to FIG. 9E , the orthographic projection of the fifth common trace 65 on the substrate 1 does not overlap with the orthographic projection of the data line 3 on the substrate, and has an overlapping area with the orthographic projection of the pixel electrode 4 on the substrate 1 .

[0245] In one possible embodiment, referring to FIG9A , the orthographic projection of the fifth common trace 65 on the substrate 1 has an overlapping area with the orthographic projection of the second electrode lap portion TC2D of the second electrode TC2 of the transistor on the substrate 1; optionally, the orthographic projection of the fifth common trace 65 on the substrate 1 covers the orthographic projection of the second electrode lap portion TC2D on the substrate 1.

[0246] In a possible embodiment, referring to FIG9B , the maximum length e1 of the fifth common routing 65 in the second direction Y is less than the minimum distance e2 between two adjacent gate lines 2 in the second direction Y; in this way, cross-connection with the gate lines 2 is avoided; the width e3 of the fifth common routing 65 in the first direction X is greater than the width e4 of the second sub-common routing 621 in the first direction X; in a possible embodiment, the width e3 of the fifth common routing 65 in the first direction X can be 2 to 10 times the width e4 of the second sub-common routing 621 in the first direction X; in a possible embodiment, the width e3 of the fifth common routing 65 in the first direction X can be 3 to 5 times the width e4 of the second sub-common routing 621 in the first direction X.

[0247] In one possible implementation, referring to Figures 1A-1H, 2A-2E, 3A-3G, and 4A-4E, the orthographic projection of the second common signal line 62 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a second storage capacitor is formed by the second common signal line 62 and the pixel electrode 4.

[0248] In a possible embodiment, referring to Figures 1A to 1H, 2A to 2E, 3A to 3G, and 4A to 4E, the array substrate further includes: a third common trace 63 extending along the first direction X; the third common trace 63 is disconnected at the position where it intersects with the data line 3; and the third common trace 63 passes through the center of the third gate line portion 33. In the disclosed embodiment, the array substrate further includes: a third common trace 63 extending along the first direction X, which can prevent cross-color between sub-pixels of different colors in the second direction Y. Moreover, when the gate line 2 crosses two pixel electrodes 4 in the second direction Y and passes through the gap between the two pixel electrodes 4, the signal electric field of the gate line 2 may affect the steering of the liquid crystal because there is no driving electric field of the pixel electrode 4. At this time, the third common trace 63 can be used for light shielding, without the need for black matrix light shielding, thereby greatly improving the aperture ratio and transmittance.

[0249] In a possible implementation, in order to prevent the signal electric field of the gate line 2 from affecting the direction of the liquid crystal, a metal layer other than the layer where the floating data line 3 is located may be used for light shielding.

[0250] In one possible embodiment, as shown in FIG1A and FIG1B , the orthographic projection of the third common line 63 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a third storage capacitor is formed by the third common line 63 and the pixel electrode 4.

[0251] In a possible implementation, referring to FIG. 1A to FIG. 1H , FIG. 2A to FIG. 2E , FIG. 3A to FIG. 3G , and FIG. 4A to FIG. 4E , the third common trace 63 may be made of the same layer and material as the data line 3 .

[0252] In one possible embodiment, as shown in Figures 4A-4E , the array substrate further includes: a fourth common routing line 64 extending along the second direction Y; the orthographic projection of the fourth common routing line 64 on the substrate 1 passes through the central area of ​​the orthographic projection of the pixel electrode 4 on the substrate 1; and multiple third common routing lines 63 between two adjacent data lines 3 are all connected to the fourth common routing line 64. The third common routing lines 63 and the fourth common routing lines 64 can form a mesh structure as a whole, thereby improving the uniformity of the common signal of the display panel.

[0253] In a possible implementation, the fourth common line 64 may be made of the same layer and material as the data line 3 .

[0254] In one possible implementation, as shown in FIG1D , the third common routing line 63 may be provided with a third common routing bump 630. The third common routing bump 630 may be located in an area where the third common routing line 63 overlaps with the fourth common routing line 64. Specifically, the width of the third common routing bump 630 in the second direction Y may be greater than the width of the third common routing line 63 in the second direction Y, so as to facilitate overlapping with the fourth common routing line 64 in a sufficient area.

[0255] In one possible implementation, the third common trace 63 and / or the fourth common trace 64 can be electrically connected to the first common trace 61 in a peripheral area outside the display area. Specifically, the two can be electrically connected by punching holes. In this way, the first common trace 61, the second common trace 62, the third common trace 63, and the fourth common trace 64 can form an integrated connection structure, all of which transmit common signals.

[0256] Specifically, as shown in Figure 7, the first storage capacitor, the second storage capacitor and the third storage capacitor can form a storage capacitor Ccs, which is used to drive the deflection of the liquid crystal; the second electrode TC of the transistor T and the structure electrically connected to the second electrode TC (such as the pixel electrode 4, the active pattern 5) and the gate line 20 can form a coupling capacitor Cgs, and Clc can be the capacitance generated by the liquid crystal between the array substrate and the opposite substrate, which is used to drive the deflection of the liquid crystal.

[0257] In a possible implementation, as shown in FIG5 , the plurality of pixel electrodes 4 include: pixel electrode rows 410 extending along a first direction X, and pixel electrode columns 420 extending along a second direction;

[0258] The pixel electrodes 4 of the same pixel electrode row 410 emit light with the same wavelength range;

[0259] The pixel electrode array 420 includes a plurality of pixel electrode groups 400 sequentially distributed along the second direction Y. The pixel electrode groups 400 include a first pixel electrode 41, a second pixel electrode 42, and a third pixel electrode 43 sequentially distributed along the second direction Y. The first pixel electrode 41 emits a greater wavelength range of light than the second pixel electrode 42, and the second pixel electrode 42 emits a greater wavelength range of light than the third pixel electrode 43. Specifically, the first pixel electrode 41 may emit red light, the second pixel electrode 42 may emit green light, and the third pixel electrode 43 may emit blue light.

[0260] In a possible implementation, as shown in FIG. 5 , in a pixel electrode column 420 , two adjacent pixel electrodes 4 are electrically connected to different data lines 3 ; in a pixel electrode row 410 , all pixel electrodes 4 are electrically connected to the same gate line 2 .

[0261] In one possible embodiment, as shown in FIG6 , the array substrate further includes: a color resist layer 7; the color resist layer 7 includes: a first color resist strip 71, a second color resist strip 72, and a third color resist strip 73 extending along a first direction X and sequentially distributed along a second direction Y; the orthographic projection of the first color resist strip 71 on the substrate 1 covers the orthographic projection of the first pixel electrode 41 on the substrate 1; the orthographic projection of the second color resist strip 72 on the substrate 1 covers the orthographic projection of the second pixel electrode 42 on the substrate 1; and the orthographic projection of the third color resist strip 73 on the substrate 1 covers the orthographic projection of the third pixel electrode 43 on the substrate 1. In the embodiment of the present disclosure, the array substrate further includes the color resist layer 7. On the one hand, because the color resist layer is thicker, the distance between the data line 3 and the layer where the pixel electrode 4 is located can be increased, thereby reducing the parasitic capacitance between the data line 3 and the pixel electrode 4; on the other hand, for curved products, when the color resist layer 7 is provided on the array substrate, when the array substrate is bent, the pixel electrode 4 and the color resist layer 7 move simultaneously, thereby avoiding color mixing problems.

[0262] In addition, in the embodiment of the present disclosure, the gate line 2 passes through the first parasitic capacitor C of the two pixel electrodes 4. gp 自 and the second parasitic capacitance C gp他 , the first parasitic capacitance C gp自 The effect is on the feed-through voltage of the self-pixel (i.e. the current sub-pixel), and the second parasitic capacitance C gp他 That is, when the signal voltage acting on the gate line 2 changes, the pulling effect on the potential of other pixels (that is, the sub-pixels adjacent to the current sub-pixel) can be effectively reduced by using the color resist layer 7 to be set on the array substrate (COA technology). gp自 and the second parasitic capacitance C gp他 .

[0263] In a possible implementation, the first color resist 71 may be a red color resist, the second color resist 72 may be a green color resist, and the third color resist 73 may be a blue color resist.

[0264] In one possible embodiment, as shown in conjunction with Figures 1G and 1H , a color resist overlapping portion 74 may be provided between adjacent first color resists 71 and second color groups 72, a color resist overlapping portion 74 may be provided between adjacent second color resists 72 and third color groups 73, and a color resist overlapping portion 74 may be provided between adjacent third color resists 73 and first color groups 71. In one possible embodiment, as shown in conjunction with Figure 1H , at least a portion of the orthographic projection of the color resist overlapping portion 74 on the substrate 1 may overlap with at least a portion of the orthographic projection of the third common trace 63 on the substrate 1.

[0265] In a possible embodiment, in combination with Figures 1A, 1G and 1H, the layer where the data line 3 is located can be located on the side of the layer where the gate line 2 is located away from the substrate 1, the layer where the pixel electrode 4 is located can be located on the side of the layer where the data line 3 is located away from the layer where the gate line 2 is located, the active pattern 5 can be located between the layer where the data line 3 is located and the layer where the gate line 2 is located (not shown in Figures 1G and 1H), a gate insulating layer 91 can also be provided between the layer where the gate line 2 is located and the layer where the active pattern 5 is located, a passivation layer 92 can also be provided between the layer where the data line 3 is located and the layer where the pixel electrode 4 is located, and a flat layer 93 can also be provided between the passivation layer 92 and the layer where the pixel electrode 4 is located.

[0266] In one possible implementation, the planarization layer 93 may be an organic film layer; in one possible implementation, the passivation layer 92 may be a PVX layer, for example, including a silicon nitride material layer.

[0267] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes: an opposite substrate arranged opposite to the array substrate, the opposite substrate being provided with a common electrode layer.

[0268] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0269] Based on the same inventive concept, referring to FIG8A , an embodiment of the present disclosure further provides a method for driving a display panel, which includes:

[0270] Step S100, controlling the plurality of gate lines to load scanning signals row by row, and controlling the duration of the gate lines loading the scanning signals to be greater than 1H;

[0271] Step S200 : controlling the data lines to load data signals during at least a portion of a period in which the gate lines are loaded with scan signals.

[0272] Since the number of row scan lines in the three-gate pixel driving structure has doubled, and the number of data lines has become one-third of the original number, if a GOA (Gate on Array) driving structure is adopted, the increase in the number of scan lines does not require additional cost of the driving circuit, and the reduction in the number of data lines can reduce the number of driving ICs, thus having a cost advantage; however, compared with the 1G1D structure, the row write time in the three-gate pixel driving structure is reduced to one-third of the original time, which will directly affect the performance of the entire display panel. In the embodiment of the present disclosure, by controlling the duration of the gate line loading the scan signal to be greater than 1H and pre-charging the gate line, the problem of the reduced row write time in the three-gate pixel driving structure affecting the performance of the entire display panel can be improved.

[0273] In a possible implementation, step S100, controlling the gate line to load the scanning signal for a duration greater than 1H, includes:

[0274] The duration of the control gate line loading scan signal is 4H.

[0275] Specifically, as shown in FIG8B , the scan signal may include a first period T1 and a second period T2, wherein the second period T2 is delayed from the first period T1. Specifically, the first period T1 may be a precharge period, which may be 3 hours, and the second period T2 may be 1 hour. Specifically, the data line may be controlled to load a data signal during the second period T2.

[0276] Specifically, H may represent the charging time of one row, which is calculated based on the resolution and refresh rate of the display panel.

[0277] In the disclosed embodiment, the "Z"-shaped routing shape of the gate line 2 will span two sub-pixels, the self-pixel and the other-pixel. When the other-pixel is a pixel in the previous row of the self-pixel, when the signal of the gate line 2 is turned off, there will be a pull-down signal to the other-pixel. At this time, the signal waveform of the gate line 2 is required to be 1H without pre-charge, so that the rising edge and falling edge of the signal of the gate line 2 will act on the other-pixel at the same time, and finally the effects of the pull-up and pull-down will cancel each other out; when the other-pixel is a pixel in the next row of the self-pixel, the signal waveform of the gate line 2 can be an nH signal with pre-charge, for example, referring to Figure 8B, pre-charged for 3H, when the signal of the gate line 2 is turned off, the other-pixel will continue to charge and will not be affected by the change in the signal waveform of the gate line 2. Therefore, the "Z"-shaped routing shape of the signal of the gate line 2 of this structure that spans other pixels is the best for driving pixels in the next row.

[0278] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0279] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction; At least one of the plurality of gate lines comprises a plurality of gate line groups sequentially distributed along the first direction; the gate line group comprises: a first gate line portion extending along the first direction and sequentially distributed, a second gate line portion, and a third gate line portion located between the first gate line portion and the second gate line portion and connecting the first gate line portion and the second gate line portion; an extension line of the first gate line portion does not overlap with an extension line of the second gate line portion, and an extension direction of the third gate line portion intersects with the first direction; a plurality of data lines, located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending along a second direction; A plurality of pixel electrodes, wherein at least a portion of at least one pixel electrode among the plurality of pixel electrodes, in an orthographic projection on the substrate, is located in an area formed by the intersection of the gate line and the data line; a maximum length of the pixel electrode in the first direction is greater than a maximum length in the second direction; and an orthographic projection of the plurality of pixel electrodes on the substrate at least partially overlaps with an orthographic projection of the first gate line portion and an orthographic projection of the second gate line portion on the substrate.

2. The array substrate according to claim 1, wherein: The third gate line portion extends along the second direction, and an extension line of the third gate line portion passes through a central area of ​​the pixel electrode.

3. The array substrate according to claim 1, wherein: The third gate line portion extends along the third direction, and the third direction intersects the first direction and the second direction.

4. The array substrate according to any one of claims 1 to 3, wherein: The length of the gate line group in the first direction is substantially equal to the length of the pixel electrode in the first direction.

5. The array substrate according to claim 4, wherein: A length of the first gate line portion in the first direction is less than or equal to a maximum length of the second gate line portion in the first direction.

6. The array substrate according to any one of claims 1 to 5, wherein: The gate line further includes: a gate line connection portion located between adjacent gate line groups and connecting adjacent gate line groups; the gate line connection portion extends along the first direction, and an extension line is located between the first gate line portion and the second gate line portion.

7. The array substrate according to claim 6, wherein: The gate line connection portion includes: a first gate line connection portion, a second gate line connection portion, and a third gate line connection portion distributed in sequence along the first direction; a length of the second gate line connection portion in the second direction is greater than a length of the first gate line connection portion in the second direction, and greater than a length of the third gate line connection portion in the second direction.

8. The array substrate according to any one of claims 1 to 7, wherein: In the same gate line group, the orthographic projection of the first gate line portion on the substrate is covered by the orthographic projection of a pixel electrode on the substrate, and the orthographic projection of the second gate line portion on the substrate is covered by the orthographic projection of another adjacent pixel electrode on the substrate in the second direction.

9. The array substrate according to any one of claims 1 to 8, wherein: The array substrate comprises: a first axis located between two adjacent pixel electrodes and extending along the second direction; At least one data line among the multiple data lines includes: multiple data groups distributed in sequence along the second direction; the data group includes: a first data portion located on one side of the first axis, and a second data portion located on the other side of the first axis; the orthographic projections of the multiple pixel electrodes on the substrate at least partially cover the orthographic projections of the first data portion and the second data portion on the substrate.

10. The array substrate according to claim 9, wherein: The data group further includes: a third data portion connecting the first data portion and the second data portion, and an extending direction of the third data portion intersects with the second direction.

11. The array substrate according to claim 9 or 10, wherein: In the same data group, the orthographic projection of the first data portion on the substrate is at least partially covered by the orthographic projection of one pixel electrode on the substrate, and the orthographic projection of the second data portion on the substrate is at least partially covered by the orthographic projection of another adjacent pixel electrode in the first direction on the substrate.

12. The array substrate according to any one of claims 9 to 11, wherein: The length of the data group in the second direction is less than or equal to the maximum length of the pixel electrode in the second direction.

13. The array substrate according to any one of claims 10 to 12, wherein: The first data portion and the second data portion both extend along the second direction, and an extension line of the first data portion does not overlap with the second data portion.

14. The array substrate according to claim 13, wherein: The array substrate comprises: a second axis extending along the first direction and passing through the center of the pixel electrode; The first data portion and the second data portion are respectively located on different sides of the second axis; and the second axis passes through the center of the third data portion.

15. The array substrate according to claim 13 or 14, wherein: An extension line of the second data portion overlaps with the first data portion in the adjacent data group.

16. The array substrate according to any one of claims 9 to 12, wherein: The first data portion and the second data portion are symmetrical about the first axis.

17. The array substrate according to claim 16, wherein: The first data portion and the second data portion both include: a first sub-data portion, a second sub-data portion, and a third sub-data portion extending along the second direction and distributed in sequence; an extension line of the first sub-data portion coincides with an extension line of the third sub-data portion, and an extension line of the second sub-data portion is located on a side of the first sub-data portion away from the first axis.

18. The array substrate according to claim 17, wherein: The first data portion and the second data portion further include: a fourth sub-data portion extending along the first direction, and a fifth sub-data portion; The fourth sub-data portion connects the first sub-data portion and the second sub-data portion; the fifth sub-data portion connects the second sub-data portion and the third sub-data portion.

19. The array substrate according to claim 17 or 18, wherein: The third data portion extends along the first direction and connects two fifth sub-data portions of the same data group.

20. The array substrate according to any one of claims 17 to 19, wherein: The array substrate comprises: a second axis extending along the first direction and passing through the center of the pixel electrode; and the second axis passes through the central area of ​​the second sub-data portion.

21. The array substrate according to claim 20, wherein: The first data portion is symmetrical about the second axis; and the second data portion is symmetrical about the second axis.

22. The array substrate according to any one of claims 17 to 21, wherein: The length of the first sub-data portion in the second direction is substantially equal to the length of the third sub-data portion in the second direction.

23. The array substrate according to claim 22, wherein: The length of the first sub-data portion in the second direction is one third to two thirds of the length of the second sub-data portion in the second direction.

24. The array substrate according to any one of claims 17 to 23, wherein: The data line further includes: a data connection portion connecting adjacent data groups, the data connection portion including: two sub-data connection portions extending along the second direction and arranged along the first direction; the sub-data connection portion connects the third sub-data portion and the first sub-data portion of the adjacent data groups.

25. The array substrate according to claim 24, wherein: A length of the sub-data connection portion in the first direction is smaller than a length of the first sub-data portion in the first direction.

26. The array substrate according to any one of claims 17 to 25, wherein: The array substrate further comprises: a plurality of transistors; at least one transistor among the plurality of transistors comprises: a control electrode, an active pattern, and a first electrode, a second electrode, and a third electrode sequentially distributed along the first direction; the orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all have overlapping areas with the orthographic projections of the control electrode on the substrate; the orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all have overlapping areas with the orthographic projections of the active pattern on the substrate; The first stage multiplexes one of the sub-data connection parts in the data connection part; the third stage multiplexes another sub-data connection part in the data connection part; The second pole includes: a second pole first portion extending along the second direction, and a second pole overlapping portion connected to one end of the second pole first portion; the second pole first portion is located between the two first sub-data portions of the data group in the orthographic projection of the substrate; and the second pole overlapping portion is located between the two second sub-data portions of the data group in the orthographic projection of the substrate.

27. The array substrate according to claim 26, wherein: A length of the second pole overlapping portion in the first direction is smaller than a minimum distance between two of the second sub-data portions in the data group.

28. The array substrate according to claim 26 or 27, wherein: The pixel electrode comprises: a pixel electrode body, and a pixel electrode lap portion extending from one side of the pixel electrode body along the first direction; The orthographic projection of the pixel electrode overlapping portion on the substrate has an overlapping area with the orthographic projection of the second electrode overlapping portion on the substrate.

29. The array substrate according to claim 28, wherein: The pixel electrode body has a recessed portion at a position where the pixel electrode overlap portion is located. The recessed portion is projected orthogonally on the substrate and surrounds the pixel electrode overlap portion and is projected orthogonally on the substrate.

30. The array substrate according to claim 29, wherein: The outer edge of the second sub-data portion is projected onto the substrate, and is located on the side of the outer edge of the recessed portion that is projected onto the substrate away from the first axis; the outer edge of the recessed portion is projected onto the substrate, and is located on the side of the outer edge of the second pole overlap portion that is projected onto the substrate away from the first axis.

31. The array substrate according to any one of claims 1 to 8, wherein: The data line comprises: a first data portion and a second data portion which are alternately distributed in sequence along the second direction; wherein the first data portion is located in a region between two adjacent pixel electrodes in the first direction; and an orthographic projection of the second data portion on the substrate has an overlapping region with an orthographic projection of the gate line on the substrate; The second data portion includes: two first sub-data portions and a second sub-data portion extending along the second direction and distributed sequentially along the first direction; one end of the first sub-data portion and one end of the second sub-data portion are both connected to one of the first data portions, and the other end of the first sub-data portion is connected to another adjacent first data portion.

32. The array substrate according to claim 31, wherein: A maximum length of the second sub-data portion in the second direction is smaller than a maximum length of the first sub-data portion in the second direction.

33. The array substrate according to claim 31 or 32, wherein: The array substrate comprises: a first axis located between two adjacent pixel electrodes and extending along the second direction; In two adjacent second data portions, two second sub-data portions are located on different sides of the first axis; and two first sub-data portions are located on different sides of the first axis.

34. The array substrate according to any one of claims 31 to 33, wherein: The array substrate further includes: a first conductive line extending along the second direction; an orthographic projection of the first conductive line on the substrate covers an orthographic projection of the data line on the substrate.

35. The array substrate according to any one of claims 31 to 34, wherein: The array substrate further comprises: a plurality of transistors; at least one transistor among the plurality of transistors comprises: a control electrode, an active pattern, a first electrode, and a second electrode; an orthographic projection of the first sub-data portion on the substrate does not overlap with an orthographic projection of the active pattern on the substrate; The first stage multiplexes the second sub-data portion; The second pole includes: a second pole first portion extending along the second direction, a second pole second portion extending along the first direction, and a second pole overlapping portion connected to the second pole second portion; the orthographic projection of one end of the second pole first portion on the substrate overlaps with the orthographic projection of the gate line on the substrate; the other end of the second pole first portion is connected to one end of the second pole second portion.

36. The array substrate according to any one of claims 1 to 8, wherein: At least one data line among the plurality of data lines comprises: a first data portion and a second data portion alternately distributed along the second direction; in the second direction, the extension lines of the two first data portions on both sides of the second data portion do not overlap; The second data portion includes: a first sub-data portion, a second sub-data portion, and a third sub-data portion; the first sub-data portion extends along the first direction; the second sub-data portion and the third sub-data portion extend along the second direction and are located at the same side of the first sub-data portion; One end of the first sub-data portion is connected to one end of the second sub-data portion, and the other end is connected to one end of the third sub-data portion and one of the first data portions; the other end of the second sub-data portion is connected to another of the first data portions.

37. The array substrate according to claim 36, wherein: The orthographic projection of the first data portion on the substrate is located in a region between the orthographic projections of two adjacent pixel electrodes on the substrate in the first direction; The orthographic projection of the second data portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

38. The array substrate according to claim 36 or 37, wherein: A length of the first data portion in the second direction is less than or equal to a maximum length of the pixel electrode in the second direction.

39. The array substrate according to any one of claims 36 to 38, wherein: The orthographic projections of the plurality of pixel electrodes on the substrate do not overlap with the orthographic projections of the first data portion and the second data portion on the substrate.

40. The array substrate according to any one of claims 36 to 39, wherein: The array substrate further comprises: a plurality of transistors; at least one transistor among the plurality of transistors comprises: a control electrode, an active pattern, and a first electrode, a second electrode, and a third electrode sequentially distributed along the first direction; the orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all have overlapping areas with the orthographic projections of the control electrode on the substrate; the orthographic projections of the first electrode, the second electrode, and the third electrode on the substrate all have overlapping areas with the orthographic projections of the active pattern on the substrate; The first stage multiplexes the second sub-data portion; the third stage multiplexes the third sub-data portion; The second pole includes: a second pole first portion extending along the second direction, and a second pole overlapping portion connected to one end of the second pole first portion; the part of the second pole first portion on the orthographic projection of the substrate is located between the second sub-data portion and the third sub-data portion on the orthographic projection of the substrate.

41. The array substrate according to claim 40, wherein: The length of the second pole overlapping portion in the second direction is substantially equal to the length of the first data portion in the second direction.

42. The array substrate according to claim 40 or 41, wherein: The width of the second pole overlapping portion in the first direction is greater than the width of the second pole first portion in the first direction.

43. The array substrate according to any one of claims 1 to 42, wherein: The array substrate further includes: a first common wiring extending along the first direction, and a common lap portion connected to the first common wiring; the first common wiring is an orthographic projection of the substrate, passing through a central area of ​​the orthographic projection of the pixel electrode on the substrate.

44. The array substrate according to claim 43, wherein: The array substrate further includes: a second common wiring extending along the second direction; the second common wiring is disconnected at a position where it intersects with the gate line.

45. The array substrate according to claim 43 or 44, wherein: The array substrate also includes: a fifth common line electrically connected to at least part of the first common line and extending along the second direction; the orthographic projection of the fifth common line on the substrate covers at least part of the orthographic projection of the gap between the data line and the pixel electrode on the substrate.

46. ​​The array substrate according to claim 45, wherein: The array substrate comprises: a second common routing group extending along the second direction; the second common routing group is disconnected at a position where it intersects with the gate line; the second common routing group comprises: a first sub-common routing and a second sub-common routing arranged along the first direction, wherein the length of the first sub-common routing in the second direction is less than the length of the second sub-common routing in the second direction, and in the second direction, the first sub-common routing and the second sub-common routing are alternately arranged; The array substrate further includes: a common compensation portion connected to a side of the first sub-common routing line away from the second sub-common routing line; and the fifth common routing line includes the first sub-common routing line and the common compensation portion.

47. The array substrate according to claim 46, wherein: The fifth common routing line has a fifth outer edge extending along the second direction; and the fifth outer edge extension lines of two adjacent fifth common routing lines in the second direction do not overlap.

48. The array substrate according to any one of claims 45 to 47, wherein: The fifth common wiring includes: a wiring body, and a wiring protrusion extending from at least one side of the wiring body along the second direction; The array substrate further comprises a transistor; the transistor comprises a first electrode, a second electrode and a third electrode; the orthographic projection of the routing protrusion on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

49. The array substrate according to any one of claims 45 to 48, wherein: The orthographic projection of the fifth common line on the substrate does not overlap with the orthographic projection of the data line on the substrate, and has an overlapping area with the orthographic projection of the pixel electrode on the substrate.

50. The array substrate according to any one of claims 47 to 49, wherein: The maximum length of the fifth common line in the second direction is less than the minimum distance between two adjacent gate lines in the second direction; A width of the fifth common line in the first direction is greater than a width of the second sub-common line in the first direction.

51. The array substrate according to any one of claims 43 to 50, wherein: The array substrate further includes: a third common wiring extending along the first direction; the third common wiring is disconnected at a position where it intersects with the data line; and the third common wiring passes through the center of the third gate line portion.

52. The array substrate according to claim 51, wherein: The array substrate also includes: a fourth common routing line extending along the second direction; the fourth common routing line is an orthographic projection of the substrate, passing through a central area of ​​the orthographic projection of the pixel electrode on the substrate; and a plurality of the third common routing lines between two adjacent data lines are all connected to the fourth common routing line.

53. The array substrate according to any one of claims 1 to 52, wherein: The plurality of pixel electrodes include: pixel electrode rows extending along the first direction, and pixel electrode columns extending along the second direction; The pixel electrodes in the same pixel electrode row have the same light wavelength band range; The pixel electrode column includes a plurality of pixel electrode groups sequentially distributed along the second direction, and the pixel electrode groups include: a first pixel electrode, a second pixel electrode, and a third pixel electrode sequentially distributed along the second direction; a light band range emitted by the first pixel electrode is greater than a light band range emitted by the second pixel electrode, and a light band range emitted by the second pixel electrode is greater than a light band range emitted by the third pixel electrode.

54. The array substrate according to claim 53, wherein: In the pixel electrode column, two adjacent pixel electrodes are electrically connected to different data lines respectively; in the pixel electrode row, all the pixel electrodes are electrically connected to the same gate line.

55. The array substrate according to claim 53 or 54, wherein: The array substrate further comprises: a color resistance layer; the color resistance layer comprises: a first color resistance stripe, a second color resistance stripe, and a third color resistance stripe extending along the first direction and sequentially distributed along the second direction; The orthographic projection of the first color-resistance strip on the substrate covers the orthographic projection of the first pixel electrode on the substrate; the orthographic projection of the second color-resistance strip on the substrate covers the orthographic projection of the second pixel electrode on the substrate; the orthographic projection of the third color-resistance strip on the substrate covers the orthographic projection of the third pixel electrode on the substrate.

56. A display panel, wherein: It comprises the array substrate as described in any one of claims 1 to 55, and further comprises: an opposite substrate arranged opposite to the array substrate, the opposite substrate being provided with a common electrode layer.

57. A display device, wherein: Comprising a display panel as claimed in claim 56.

58. A method for driving a display panel as claimed in claim 56, wherein: include: Controlling a plurality of gate lines to load scanning signals row by row, and controlling the duration of the gate lines loading the scanning signals to be greater than 1H; During at least a portion of a period in which the gate line is loaded with a scan signal, the data line is controlled to be loaded with a data signal.

59. The driving method according to claim 58, wherein: The controlling the gate line to load the scanning signal for a duration greater than 1H comprises: The duration of controlling the gate line to load the scanning signal is 4H.

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