Silicon carbide device for ohmic and schottky contact using single metallization process

Abstract

A semiconductor device includes a semiconductor layer having an active region and an edge termination region, and a first metal region on the semiconductor layer in the active region of the semiconductor layer. The first metal region includes a first metal. The device also includes a second metal region on the semiconductor layer in an edge termination region of the semiconductor layer. The second metal region includes the first metal. The device includes a first metal layer on a semiconductor layer in an active region of the semiconductor layer. The first metal layer includes a second metal, and the metal layer contacts the first metal regions and contacts the semiconductor layer in a space between the first metal regions.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device structures, and in particular to silicon carbide semiconductor devices including both ohmic contacts and Schottky contacts. Background Art

[0002] Narrow bandgap semiconductor materials, such as silicon (Si) and gallium arsenide (GaAs), are widely used in low-power semiconductor devices and, in the case of Si, in low-frequency applications. However, these semiconductor materials may not be well suited for high-power and / or high-frequency applications, for example, because their bandgaps are relatively small (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and their breakdown voltages are relatively small.

[0003] Interest in high-power, high-temperature, and / or high-frequency applications and devices has focused on wide-bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature.) These materials may have higher electric field breakdown strength and higher electron saturation velocity than GaAs and Si.

[0004] An important application of wide bandgap semiconductors such as silicon carbide is the Schottky diode.

[0005] A Schottky diode, also known as a Schottky barrier diode, is a semiconductor diode formed by a junction of a semiconductor and a metal. The metal-semiconductor junction in a Schottky diode (rather than a semiconductor-semiconductor junction as in a traditional PN junction diode) forms a Schottky barrier. The metal side serves as the anode of the diode, and the n-type semiconductor serves as the cathode of the diode. When sufficient forward voltage is applied to overcome the Schottky barrier of the metal-semiconductor junction, current flows through the device in the forward direction. When a reverse voltage is applied, a depletion region forms in the semiconductor, impeding the flow of current.

[0006] Compared to conventional PN junction diodes, Schottky diodes have a low forward voltage drop and very fast switching action.

[0007] An important difference between a PN junction diode and a Schottky diode is the reverse recovery time (t rr ), which is the time required for a diode to switch from a conducting (forward biased) state to a non-conducting (reverse biased) state. In the conducting state, a conventional PN junction diode injects minority carriers into a diffusion region on the N side of the junction, where they recombine with majority carriers after diffusion. The reverse recovery time of a PN junction is primarily limited by the diffusion capacitance of minority carriers accumulated in the diffusion region during the conducting state.

[0008] In contrast, the Schottky diode is a unipolar or "majority carrier" device that does not rely on the injection of minority carriers. Instead, in the conducting state, majority carriers (electrons in the case of n-type semiconductor layers) are injected across the junction. Therefore, no recombination time of the injected carriers is required to switch the Schottky diode from the conducting state to the non-conducting state. Instead, the switching speed of the Schottky diode is limited only by the junction capacitance of the device.

[0009] Silicon carbide Schottky diodes are the choice for rectifiers in advanced power electronics devices of 650V and above, primarily because they achieve fast switching speeds and much lower leakage current and capacitance than silicon-based Schottky diodes. Summary of the invention

[0010] According to some embodiments, a method for manufacturing a semiconductor device includes forming a first metal region on a semiconductor layer in a first region of the semiconductor layer. The first metal region includes a first metal. The method includes forming a second metal region on the semiconductor layer in a second region of the semiconductor layer. The second metal region includes a first metal. The semiconductor layer including the first metal region and the second metal region is annealed at a first annealing temperature to convert at least a portion of the first metal region and the second metal region into a first metal silicide region and a second metal silicide region, respectively. The semiconductor layer including the first metal silicide region and the second metal silicide region is annealed at a second annealing temperature to form a Schottky barrier junction between the first metal silicide region and the semiconductor layer. A first metal layer is formed on the semiconductor layer in the first region of the semiconductor layer. The first metal layer includes a second metal, and the metal layer contacts the first metal region and contacts the semiconductor layer in a space between the first metal regions.

[0011] The first metal may include nickel, titanium, molybdenum and / or tungsten, and wherein the second metal includes titanium or titanium nitride.

[0012] The semiconductor layer includes silicon. In some embodiments, the semiconductor layer includes silicon carbide.

[0013] The first metal region and the second metal region may be formed simultaneously.

[0014] The method may further include removing non-silicided portions of the first metal region and the second metal region after annealing the semiconductor layer to form the first metal silicide region and the second metal silicide region.

[0015] The first metal silicide region may form a first Schottky barrier junction with the semiconductor layer, and the metal layer may form a second Schottky barrier junction with the semiconductor layer. The first Schottky barrier junction has a first Schottky barrier height, and the second Schottky barrier junction has a second Schottky barrier height less than the first Schottky barrier height.

[0016] The first Schottky barrier height may be at least about 0.5 eV greater than the second Schottky barrier height. In some embodiments, the first Schottky barrier height may be about 1.6 eV or greater, and the second Schottky barrier height is about 1.2 eV or less.

[0017] The first region of the semiconductor layer may correspond to an active region of the semiconductor device, and the second region of the semiconductor layer may correspond to an edge termination region of the semiconductor device.

[0018] In some embodiments, the first annealing temperature is from about 600°C to about 700°C.

[0019] The semiconductor layer may include a substrate and an epitaxial layer on the substrate. The method may further include forming a second metal layer on a back side of the substrate opposite the epitaxial layer, wherein the second metal layer includes the first metal.

[0020] Annealing the semiconductor layer at a second annealing temperature may include annealing the semiconductor layer including the first metal region and the second metal layer at the second annealing temperature. The second annealing temperature may be sufficient to form a Schottky barrier contact between the first metal region and the semiconductor layer, and sufficient to form an ohmic contact between the second metal layer and the doped region of the semiconductor layer. The second annealing temperature may be from about 850°C to about 900°C.

[0021] The semiconductor layer may be an epitaxial semiconductor layer on the front surface of the semiconductor substrate, and the second metal layer may be formed on the epitaxial semiconductor layer.

[0022] The method may also include forming a first plurality of trenches in the first region of the semiconductor layer, wherein the first metal region is formed in the first plurality of trenches.

[0023] The method may also include forming a second plurality of trenches in the second region of the semiconductor layer, wherein the second metal region is formed in the second plurality of trenches.

[0024] The method may further include forming a plurality of trenches in the second region of the semiconductor layer, wherein the second metal region is formed in the plurality of trenches.

[0025] Forming the first metal region and the second metal region on the semiconductor layer may include forming a mask on the semiconductor layer, forming openings in the mask in the first region and the second region of the semiconductor layer to expose corresponding regions of the semiconductor layer, and depositing an initial layer of the first metal on the semiconductor layer. The initial layer of the first metal contacts the semiconductor layer in the exposed region of the semiconductor layer, and annealing the semiconductor layer so that the portion of the initial layer of the first metal contacting the semiconductor layer becomes silicided. The method may also include, after annealing the semiconductor layer, stripping the mask and the non-silicided portion of the initial layer of the first metal from the semiconductor layer.

[0026] According to some embodiments, a semiconductor device includes a semiconductor layer having an active region and an edge termination region, and a first metal region on the semiconductor layer in the active region of the semiconductor layer, wherein the first metal region includes a first metal. The device also includes a second metal region on the semiconductor layer in the edge termination region of the semiconductor layer, wherein the second metal region includes the first metal, and a first metal layer on the semiconductor layer in the active region of the semiconductor layer. The first metal layer includes the second metal. The first metal layer contacts the first metal region and contacts the semiconductor layer in a space between the first metal regions.

[0027] The first metal may include nickel, titanium, molybdenum and / or tungsten, and wherein the second metal includes titanium or titanium nitride.

[0028] The semiconductor layer includes silicon. In some embodiments, the semiconductor layer includes silicon carbide.

[0029] The first metal region includes a first metal silicide region, and the second metal region includes a second metal silicide region.

[0030] The first metal silicide region may form a first Schottky barrier junction with the semiconductor layer in the first region of the semiconductor layer, wherein the first Schottky barrier junction has a first Schottky barrier height, and the first metal layer may form a second Schottky barrier junction with the semiconductor layer. The second Schottky barrier junction has a second Schottky barrier height that is less than the first Schottky barrier height.

[0031] The first Schottky barrier height is at least about 0.5 eV greater than the second Schottky barrier height. In some embodiments, the first Schottky barrier height is about 1.6 eV or greater, and the second Schottky barrier height is about 1.2 eV or less.

[0032] The semiconductor layer may include an epitaxial layer on the substrate, and the semiconductor device may further include a second metal layer on a back side of the substrate opposite to the epitaxial layer, wherein the second metal layer includes the first metal and forms an ohmic contact with the substrate.

[0033] The semiconductor device may also include a first plurality of trenches in an active region of the semiconductor layer, wherein the first metal region is in the first plurality of trenches.

[0034] The semiconductor device may further include a second plurality of trenches in the edge termination region of the semiconductor layer, wherein the second metal region is in the second plurality of trenches.

[0035] The semiconductor device may further include a plurality of trenches in the edge termination region of the semiconductor layer, wherein the second metal region is in the plurality of trenches. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A Schottky diode is shown in accordance with some embodiments.

[0037] Figures 2A to 2H Operations for forming a Schottky diode are shown in accordance with some embodiments.

[0038] Figures 3A to 3G Operations for forming a Schottky diode according to further embodiments are shown.

[0039] Figure 4 is a flow chart illustrating operation according to some embodiments.

[0040] Figure 5 A Schottky diode structure according to a further embodiment is shown.

[0041] Figures 6A to 6D Operations for forming a Schottky diode according to further embodiments are shown. DETAILED DESCRIPTION

[0042] Embodiments of the inventive concept will now be described with reference to the accompanying drawings.

[0043] SiC Schottky diodes have begun to find use in price-sensitive applications where it is important to reduce the cost of the device, even at the expense of certain performance specifications. Costs can be reduced not only by shrinking the wafer size, but also by reducing the number of manufacturing steps, and in particular eliminating expensive steps such as high-temperature ion implantation and implant annealing.

[0044] Some embodiments provide methods of forming SiC-based Schottky diodes that use the same metallization process to form both Schottky contacts and one or more other contacts (such as ohmic contacts) to the device, which can simplify the manufacturing process. Although methods and devices according to some embodiments may compromise some characteristics of the device, such as blocking voltage or surge current performance, this may be an acceptable trade-off depending on the desired application.

[0045] Some embodiments may reduce the number of mask moves required by up to 40% (e.g., 3 times compared to 5 times in previous methods) and / or may eliminate certain expensive manufacturing steps such as ion implantation, implant activation, wafer thinning and / or laser annealing steps.

[0046] In some embodiments, the same metallization process can be used to form the anode and cathode contacts. In some embodiments, the same metallization process can also be used to form floating equipotential rings in the termination region of the diode.

[0047] Figure 1FIG. 1 shows a Schottky diode 10 according to some embodiments. The Schottky diode 10 includes an active region 10A and an edge termination region 10B (also referred to as a junction termination region, or simply a termination region). Figure 1 The active region 10A and the edge termination region 10B are shown as separate regions in FIG. 1 , but it will be understood that they are part of the same device.

[0048] An n-silicon carbide epitaxial layer 14 is formed on a silicon carbide substrate 12. A metal Schottky contact 26 is formed on a surface of the silicon carbide epitaxial layer 14 opposite to the substrate 12. The Schottky contact 26 and the silicon carbide epitaxial layer 14 form a first Schottky barrier junction J1.

[0049] At the surface of the silicon carbide epitaxial layer 14, a plurality of metal shielding regions 24 are provided in the rounded trenches 23 formed at the surface of the silicon carbide epitaxial layer 14. The metal shielding regions 24 and the silicon carbide epitaxial layer 14 form a second Schottky barrier junction J2.

[0050] The first Schottky barrier junction J1 between the Schottky contact 26 and the silicon carbide epitaxial layer 14 has a smaller Schottky barrier energy than the second Schottky barrier junction J2 between the metal shielding region 24 and the silicon carbide epitaxial layer. This allows the first Schottky barrier junction J1 to be turned on before the second Schottky barrier junction J2 in the forward bias (conduction) state. Conversely, in the reverse bias (non-conduction) state, the first Schottky barrier junction J1 is shielded from the high electric field by the depletion region formed at the interface of the second Schottky barrier junction J2 and the silicon carbide epitaxial layer 14.

[0051] A cathode ohmic contact 22 is formed on the back side of the substrate 12 .

[0052] In the edge termination region 10B, a plurality of floating equipotential rings 32 (also referred to as guard rings or field rings) are formed in corresponding trenches 31 at the surface of the silicon carbide epitaxial layer 14. A silicon nitride passivation layer 25 is formed over the edge termination region 10B and extends onto the Schottky contacts 26 in the active region 10A. A protective layer 27 of a material such as polyimide is formed on the silicon nitride passivation layer 25.

[0053] According to some embodiments, the higher barrier metal in the metal shielding region 24 shields the Schottky contact 26, which is formed of a barrier metal that forms a smaller Schottky junction barrier height than the metal shielding region 24. In some embodiments, the metal in the metal shielding region 24 can be nickel silicide (NiSi), and the metal in the Schottky contact 26 can be a metal such as titanium or titanium nitride. Specifically, the metal of the metal shielding region 24 can have a Schottky barrier height that is at least 0.5 eV greater than the metal forming the Schottky contact 26. Due to this difference in Schottky barrier height, even if the metal shielding region 24 in the trench 23 is exposed to a higher electric field, the leakage current of the device is determined by the barrier formed by the Schottky contact 26.

[0054] Some embodiments use oxide patterns to define regions that prevent silicidation, thereby simultaneously forming metal shielding regions in the active region 10A and equipotential rings 32 in the termination region 10B of the diode 10 .

[0055] Because some embodiments do not use implant regions to form junction barrier Schottky (JBS) regions in the silicon carbide epitaxial layer 14 , high temperature implant and / or implant activation steps may not be required to form the SiC diode structure 10 .

[0056] In some embodiments, a single metallization process may be used to form the cathode ohmic contact 22 to the back side of the substrate 12 and the metal shielding region 24 in the active region, as well as the floating equipotential ring 32 in the termination region 10B. In addition, in some cases, backside thinning and laser annealing may be avoided to form the cathode ohmic contact 22. Thinning and laser annealing may result in wafer breakage, especially when processing large diameter (e.g., 200 mm or larger) wafers.

[0057] Figures 2A to 2H Operations for forming a Schottky diode are shown in accordance with some embodiments.

[0058] refer to Figure 2A , providing a silicon carbide substrate 12. The silicon carbide substrate 12 may have a 2H, 4H, 6H, or 3C polytype, and may have an off-angle orientation of about 0 to 5 degrees. A silicon carbide epitaxial layer 14 is formed on the substrate 12. The substrate 12 and the epitaxial layer 14 are divided into an active region 10A and an edge termination region 10B, and the edge termination region 10B may surround the active region 10A.

[0059] refer to Figure 2B , an oxide mask 41 is formed on the epitaxial layer 14. The mask 41 is patterned to form an opening 43 in the active region 10A and an opening 45 in the termination region 10B.

[0060] refer to Figure 2C, an anisotropic etching process 46 (such as a reactive ion etching process) is performed to form the trench 23 in the epitaxial layer 14 in the active region 10A and to form the trench 31 in the epitaxial layer 14 in the termination region 10B.

[0061] refer to Figure 2D , a metal layer 52 is deposited over the mask 41 and in the trenches 23, 31. A backside metal layer 22 may also be deposited on the bottom of the substrate 12. The metal layer 52 and the backside metal layer 22 may each include a silicide-forming metal (such as nickel). In some embodiments, the metal may include tantalum, titanium, and / or tungsten.

[0062] refer to Figure 2E , a silicidation anneal 55 is performed by heating the structure to a temperature of about 600° C. to about 700° C., and in some cases at least about 650° C. using a rapid thermal anneal to form metal silicide regions 47 in trenches 23 and metal silicide regions 49 in trenches 31. Portions of the backside metal layer 22 in contact with the substrate 12 may also become silicided. However, the upper portion of the metal layer 52 and the portion of the metal layer 52 shielded by the mask 41 may not become silicided.

[0063] refer to Figure 2F , the non-silicided portion of the metal layer 52 can be stripped from the epitaxial layer 14 together with the mask 41, leaving the metal silicide region 24 in the active region 10A of the epitaxial layer 14 and the metal silicide region 32 in the termination region 10B of the epitaxial layer 14. Then, a high temperature annealing 62 is performed on the structure at a temperature of about 850° C. to 900° C., which can form a first Schottky junction J1 between the metal silicide region 24 and the epitaxial layer 14. Annealing 62 can also make the backside contact 22 form an ohmic contact with the n-type silicon carbide substrate 12.

[0064] refer to Figure 2G , a metal layer 64 is formed on the epitaxial layer 14 in the active region 10A. The metal layer 64 may include nickel, titanium, molybdenum, titanium and / or tungsten. The metal layer 54 contacts the epitaxial layer 14 in the gap 14A between the metal silicide regions 24. The metal layer 54 may form a second Schottky junction J2 with the epitaxial layer 14. Compared with the first Schottky junction J1 between the silicide region 24 and the epitaxial layer 14, the second Schottky junction J2 may have a smaller Schottky barrier with the epitaxial layer 14. In some embodiments, after the metal layer 54 is formed, the structure may be annealed at a low temperature (e.g., 250° C. to 500° C.) to wet the metal layer 54 to the upper surface of the epitaxial layer 14.

[0065] refer to Figure 2H A silicon nitride passivation layer 25 is formed over the edge termination region 10B and extends onto the Schottky contact 26 in the active region 10A. A protective layer 27 of a material such as polyimide is formed on the silicon nitride passivation layer 25.

[0066] Figures 3A to 3F Operations for forming a Schottky diode according to further embodiments are shown. Specifically, Figures 3A to 3F shows the formation of a planar Schottky device structure according to some embodiments, which does not include Figure 1 The groove shown in .

[0067] refer to Figure 3A , providing a silicon carbide substrate 12. The silicon carbide substrate may have a 2H, 4H, 6H, or 3C polytype, and may have an off-angle orientation of about 0 to 5 degrees. A silicon carbide epitaxial layer 14 is formed on the substrate 12. The substrate 12 and the epitaxial layer 14 are divided into an active region 10A and an edge termination region 10B, and the edge termination region 10B may surround the active region 10A.

[0068] refer to Figure 3B , an oxide mask 41 is formed on the epitaxial layer 14. The mask 41 is patterned to form an opening 43 in the active region 10A and an opening 45 in the termination region 10B.

[0069] refer to Figure 3C , a metal layer 52 is deposited over the mask 41. The backside metal layer 22 is also deposited onto the bottom of the substrate 12. The metal layer 52 and the backside metal layer 22 may each include a silicide-forming metal such as nickel.

[0070] refer to Figure 3D , a silicidation anneal 55 is performed by heating the structure to a temperature of at least about 650° C. using a rapid thermal anneal to form a metal silicide region in the region where the metal layer 52 contacts the epitaxial layer 14 in the openings 43, 45. The portion of the backside metal layer 22 in contact with the substrate 12 may also become silicided. However, the upper portion of the metal layer 52 and the portion of the metal layer 52 shielded by the mask 41 may not become silicided.

[0071] refer to Figure 3E , the non-silicided portion of the metal layer 52 can be stripped from the epitaxial layer 14 together with the mask 41, thereby leaving the metal silicide region 72 on the epitaxial layer 14 in the active region 10A of the epitaxial layer 14 and the metal silicide region 74 on the epitaxial layer 14 in the termination region 10B of the epitaxial layer 14. Then, a high temperature annealing 62 is performed on the structure at a temperature of about 850° C. to 900° C., which can form a first Schottky junction J1 between the metal silicide region 72 and the epitaxial layer 14. Annealing 62 can also make the backside contact 22 form an ohmic contact with the n-type silicon carbide substrate 12.

[0072] refer to Figure 3F, a metal layer 76 is formed on the epitaxial layer 14 in the active region 10A. The metal layer 64 may include nickel, titanium, molybdenum and / or tungsten. The metal layer 76 contacts the epitaxial layer 14 in the gap 14A between the metal silicide regions 24 and forms a second Schottky junction J2 with the epitaxial layer. Compared with the first Schottky junction J1 between the silicide region 74 and the epitaxial layer 14, the second Schottky junction J2 may have a smaller Schottky barrier with the epitaxial layer 14. In some embodiments, after the metal layer 76 is formed, the structure may be annealed at a low temperature (e.g., 250° C. to 500° C.) to wet the metal layer 76 to the upper surface of the epitaxial layer 14.

[0073] refer to Figure 3G A silicon nitride passivation layer 25 is formed over the edge termination region 10B and extends onto the Schottky contact 26 in the active region 10A. A protective layer 27 of a material such as polyimide is formed on the silicon nitride passivation layer 25.

[0074] Figure 4 is a flow chart illustrating operation according to some embodiments. Figure 4 , a method of manufacturing a semiconductor device includes forming a first metal region on a semiconductor layer in a first region of the semiconductor layer (block 402). The semiconductor layer includes silicon, and wherein the first metal region includes a first metal. The method also includes forming a second metal region on the semiconductor layer in a second region of the semiconductor layer (block 404). The second metal region includes the first metal.

[0075] The semiconductor layer including the first metal region and the second metal region is annealed at a first annealing temperature (block 406), the first annealing temperature being sufficient to convert at least portions of the first metal region and the second metal region into first metal silicide regions and second metal silicide regions, respectively. The first annealing temperature may be about 650° C. Non-silicided portions of the first metal region and the second metal region are then removed (block 408).

[0076] Then, the semiconductor layer including the first metal silicide region and the second metal silicide region is annealed at a second annealing temperature sufficient to form a first Schottky barrier contact between the first metal silicide region and the semiconductor layer (block 410). The second annealing temperature may be from about 850°C to 900°C.

[0077] A metal layer is then formed on the semiconductor layer in the first region of the semiconductor layer (block 412). The metal layer contacts the first metal silicide regions and contacts the semiconductor layer in the spaces between the first metal silicide regions. Optionally, the structure may be annealed at a low temperature (e.g., 250° C. to 500° C.) to wet the metal layer to the semiconductor layer (block 414).

[0078] The metal layer forms a second Schottky junction with the semiconductor layer in the space between the first metal silicide regions. Compared with the first Schottky junction, the second Schottky junction has a smaller Schottky barrier height with the semiconductor layer.

[0079] Figure 5 An alternative Schottky diode structure according to some embodiments is shown. As shown therein, in some embodiments, a cathode ohmic contact 122 can be formed to an exposed portion of the epitaxial layer 14 on a front side of the epitaxial layer 14 opposite the substrate 12 .

[0080] Figures 6A to 6D The operation according to a further embodiment is shown in FIG. Fig. 6A As shown in FIG. 1 , the metal layer 52 is formed on the epitaxial layer 14 without also forming the backside metal layer. That is, when the metal layer 52 is formed on the epitaxial layer 14, the backside metal layer may not be formed at the same time.

[0081] refer to Figure 6B , an annealing process 55 may be formed to cause portions of the metal layer 52 to become silicided in the absence of a backside metal layer.

[0082] refer to Figure 6C , an annealing process 62 may also be performed to allow the silicided region 24 to form a Schottky junction with the epitaxial layer 14 without the presence of a backside metal. Fig.6D After the annealing process 62 , a backside metal layer 222 may be formed on the substrate 12 .

[0083] The substrate 12 may be thinned before depositing the backside metal layer 222. In addition, the backside metal layer may be laser annealed to form an ohmic contact with the substrate 12. The remaining processing steps are similar to the above steps.

[0084] Various test structures including contacts formed as described above were fabricated to demonstrate the performance / cost tradeoffs at different voltage ratings, and the results are shown in Table 1 below. Table 1 - Performance Results type Thinning / substrate thickness V Rating VF VF (potential barrier) VF(Drift) VF(substrate) Leakage Current flat Yes / 180um 650V 1.26V 0.98V 0.12V 0.16V 300uA Grooves Yes / 180um 650V 1.29V 0.98V 0.15V 0.16V 70uA Grooves Yes / 180um 1200V 1.38V 0.96V 0.33V 0.09V 7uA Grooves Yes / 180um 1700V 1.41V 0.92V 0.43V 0.06V 4uA Grooves No / 360um 1700V 1.47V 0.92V 0.43V 0.12V 4uA

[0085] Specifically, Table 1 shows the results for different device structures (planar or trench) with different voltage ratings. Table 1 shows the forward voltage (VF) and leakage current of the device. The forward voltage is decomposed into VF components corresponding to VF in the barrier, drift layer, and substrate.

[0086] As can be seen in Table 1, at higher voltage ratings (e.g., 1700V), the portion of VF in the substrate is lower (<10% for 1700V of full thickness substrate). Therefore, in high voltage devices, substrate thinning is less important for performance. At 650V voltage rating, even with substrate thinning to 180um, more than 13% of VF is in the substrate. Therefore, for low voltage devices, thinning the substrate may be desirable. For planar device structures, eliminating trench etching can improve VF, but may increase leakage current.

[0087] It will be understood that although ordinal terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0088] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top", may be used herein to describe the relationship of one element to another element as shown in the figures. It is understood that relative terms are intended to cover different orientations of the device other than the orientation depicted in the figures. For example, if the device in one figure is turned over, the features described as being on the "lower" side of the element will then be oriented on the "upper" side of the element. Therefore, the exemplary term "lower" can describe both lower and upper orientations, depending on the specific orientation of the device. Similarly, if the device in one figure is turned over, the elements described as being "below" or "below" other elements will then be oriented above those other elements. Therefore, the exemplary terms "below" or "below" can describe both upper and lower orientations.

[0089] The terms used in the description of the present disclosure herein are only used for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the description of the present disclosure and the appended claims, the singular forms "one" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is also understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more related listed items. It will also be understood that when used in this specification, the terms "including" and "comprising" specify the presence of the steps, operations, features, elements and / or components, but do not exclude the presence or addition of one or more other steps, operations, features, elements, components and / or their groups.

[0090] Embodiments of the present disclosure are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments of the present disclosure. Therefore, it is expected that there will be differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown herein, but should include shape deviations, for example, due to manufacturing. The regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the present disclosure, unless otherwise expressly stated. In addition, for illustrative reasons, the straight lines, horizontal lines, or vertical lines that appear in the following figures will generally be inclined, curved, non-horizontal, or non-vertical. In addition, although the thickness of the element is intended to be schematic in nature.

[0091] Unless otherwise defined, all terms used in disclosing the embodiments of the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the relevant art, and are not necessarily limited to specific definitions known at the time of this disclosure. Therefore, these terms may include equivalent terms created after this time. It is further understood that terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in this specification and in the context of the relevant art.

[0092] Although embodiments of the inventive concept have been described in considerable detail with reference to certain configurations of the inventive concept, other versions are possible. Therefore, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first metal region on the semiconductor layer in a first region of the semiconductor layer, wherein the first metal region comprises a first metal; forming a second metal region on the semiconductor layer in a second region of the semiconductor layer, wherein the second metal region includes the first metal; annealing the semiconductor layer including the first metal region and the second metal region at a first annealing temperature; annealing the semiconductor layer at a second annealing temperature different from the first annealing temperature; and A first metal layer is formed on the semiconductor layer and in the first regions of the semiconductor layer, wherein the first metal layer includes a second metal different from the first metal, and wherein the first metal layer contacts the first metal regions and contacts the semiconductor layer in a space between the first metal regions.

2. The method according to claim 1, wherein: The semiconductor layer includes silicon carbide.

3. The method according to claim 1, wherein: The first metal region and the second metal region are formed simultaneously. 4 . The method of claim 1 , the first annealing temperature being sufficient to convert at least portions of the first metal region and the second metal region into first metal silicide regions and second metal silicide regions, respectively.

5. The method according to claim 4, wherein: The second annealing temperature is sufficient to form a Schottky barrier junction between the first metal silicide region and the semiconductor layer. 6 . The method according to claim 4 , further comprising removing non-silicided portions of the first metal region and the second metal region after annealing the semiconductor layer at the first annealing temperature to form the first metal silicide region and the second metal silicide region.

7. The method according to claim 4, wherein: The first metal silicide region forms a first Schottky barrier junction with the semiconductor layer and the first metal layer forms a second Schottky barrier junction with the semiconductor layer, wherein the first Schottky barrier junction has a first Schottky barrier height and the second Schottky barrier junction has a second Schottky barrier height less than the first Schottky barrier height.

8. The method according to claim 7, wherein: The first Schottky barrier height is at least about 0.5 eV greater than the second Schottky barrier height.

9. The method according to claim 7, wherein: The first Schottky barrier height is about 1.6 eV or more, and the second Schottky barrier height is about 1.2 eV or less.

10. The method according to claim 1, wherein: The first region of the semiconductor layer corresponds to an active region of the semiconductor device, and the second region of the semiconductor layer corresponds to an edge termination region of the semiconductor device.

11. The method according to claim 1, wherein: The first annealing temperature is from about 600°C to about 700°C, and the second annealing temperature is from about 850°C to about 900°C.

12. The method according to claim 1, wherein: The semiconductor layer includes a substrate and an epitaxial layer on the substrate, and the method further includes: A second metal layer is formed on a back side of the substrate opposite the epitaxial layer, wherein the second metal layer includes the first metal.

13. The method according to claim 12, wherein: The first metal region and the second metal layer are formed simultaneously.

14. The method according to claim 12, wherein: Annealing the semiconductor layer at the second annealing temperature includes annealing the semiconductor layer including the first metal region and the second metal layer at the second annealing temperature.

15. The method according to claim 13, wherein: The second annealing temperature is sufficient to allow the first metal region to form a Schottky barrier contact with the semiconductor layer and to allow the second metal layer to form an ohmic contact with a doped region of the semiconductor layer.

16. The method according to claim 15, wherein: The second annealing temperature is from about 850°C to about 900°C.

17. The method according to claim 13, wherein: The semiconductor layer includes an epitaxial semiconductor layer on a front surface of a semiconductor substrate, and wherein the second metal layer is formed on the epitaxial semiconductor layer.

18. The method according to claim 1, wherein: The first metal comprises nickel, titanium, molybdenum and / or tungsten, and wherein the second metal comprises titanium or titanium nitride.

19. The method according to claim 1, wherein: The semiconductor layer includes silicon carbide.

20. The method of claim 1, further comprising: A first plurality of trenches are formed in the first region of the semiconductor layer, wherein the first metal region is formed in the first plurality of trenches.

21. The method according to claim 20, further comprising: A second plurality of trenches are formed in the second region of the semiconductor layer, wherein the second metal region is formed in the second plurality of trenches.

22. The method of claim 1, further comprising: A plurality of trenches are formed in the second region of the semiconductor layer, wherein the second metal region is formed in the plurality of trenches.

23. The method according to claim 1, wherein: Forming the first metal region and the second metal region on the semiconductor layer includes: forming a mask on the semiconductor layer; forming openings in the mask in the first region and the second region of the semiconductor layer to expose corresponding regions of the semiconductor layer; depositing an initial layer of the first metal on the semiconductor layer, wherein the initial layer of the first metal contacts the semiconductor layer in exposed areas of the semiconductor layer, and wherein the semiconductor layer is annealed such that portions of the initial layer of the first metal that contact the semiconductor layer become silicided; and After annealing the semiconductor layer, the mask and the non-silicided portion of the preliminary layer of the first metal are stripped from the semiconductor layer.

24. A semiconductor device comprising: a semiconductor layer including an active region and an edge termination region; a first metal region on the semiconductor layer in the active region of the semiconductor layer, wherein the first metal region comprises a first metal; a second metal region on the semiconductor layer in the edge termination region of the semiconductor layer, wherein the second metal region comprises the first metal; as well as A first metal layer is provided on the semiconductor layer in the active regions of the semiconductor layer, wherein the first metal layer includes a second metal, and wherein the first metal layer contacts the first metal regions and contacts the semiconductor layer in spaces between the first metal regions.

25. The semiconductor device according to claim 24, wherein: The semiconductor layer includes silicon carbide.

26. The semiconductor device according to claim 24, wherein: The first metal region includes a first metal silicide region and the second metal region includes a second metal silicide region.

27. The semiconductor device according to claim 26, wherein: The first metal silicide region forms a first Schottky barrier junction with the semiconductor layer in the first region of the semiconductor layer, wherein the first Schottky barrier junction has a first Schottky barrier height; and The first metal layer and the semiconductor layer form a second Schottky barrier junction, and the second Schottky barrier junction has a second Schottky barrier height that is smaller than the first Schottky barrier height.

28. The semiconductor device according to claim 27, wherein: The first Schottky barrier height is at least about 0.5 eV greater than the second Schottky barrier height.

29. The semiconductor device according to claim 27, wherein: The first Schottky barrier height is about 1.6 eV or more, and the second Schottky barrier height is about 1.2 eV or less.

30. The semiconductor device according to claim 24, wherein The semiconductor layer includes an epitaxial layer on a substrate, and the semiconductor device further includes: A second metal layer on a back side of the substrate opposite the epitaxial layer, wherein the second metal layer includes the first metal.

31. The semiconductor device according to claim 30, wherein: The second metal layer forms an ohmic contact with the substrate.

32. The semiconductor device according to claim 24, wherein: The first metal comprises nickel, titanium, molybdenum and / or tungsten, and wherein the second metal comprises titanium or titanium nitride.

33. The semiconductor device according to claim 24, wherein: The semiconductor layer includes silicon carbide.

34. The semiconductor device according to claim 24, further comprising: A first plurality of trenches are provided in the active region of the semiconductor layer, wherein the first metal region is in the first plurality of trenches.

35. The semiconductor device according to claim 34, further comprising: A second plurality of trenches is provided in the edge termination region of the semiconductor layer, wherein the second metal region is in the second plurality of trenches.

36. The semiconductor device according to claim 24, further comprising: A plurality of trenches are provided in the edge termination region of the semiconductor layer, wherein the second metal region is in the plurality of trenches.

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