Semiconductor substrate, method and apparatus for manufacturing semiconductor substrate, and method for manufacturing semiconductor device

Abstract

The present invention is provided with: a template substrate including a growth suppression region and a first seed region which are arranged side by side in a first direction; and a first semiconductor section that is positioned above the template substrate and that includes a nitride semiconductor. The first semiconductor section has: a first protruding section that extends from the first seed region to a position above the growth suppression region, and a second protruding section that extends from the second seed region to a position above the growth suppression region; a growth suppression film in contact with the first protrusion; a first base part located above the first protruding part; and a first wing section that is connected to the first base section, is separated from the growth-inhibiting region, and is positioned in a gap.

Description

Technical Field

[0001] The present disclosure relates to semiconductor substrates and the like. Background Art

[0002] If a GaN layer is formed on a different substrate, the thickness of the GaN layer will be 10 8 cm -2 The defect density is about 10 9 cm -2 The defect density of about 10000 is caused by threading dislocations from the interface of heterogeneous materials, and the characteristics of the semiconductor element formed on the GaN layer are reduced. Therefore, as a technology for forming a nitride semiconductor layer (such as a GaN layer) with a low defect density on a heterogeneous substrate, the ELO (Epitaxial Lateral Overgrowth) method has been studied. For example, a mask pattern in which a nitride semiconductor layer will not grow is formed on a base substrate including a heterogeneous substrate and a seed layer, and the nitride semiconductor layer is grown laterally on the mask part with the seed layer exposed in the opening part without the mask part as the growth starting point, thereby reducing the defect density of the nitride semiconductor layer on the mask part (Patent Document 1).

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-251304 Summary of the invention

[0006] Problems to be solved by the invention

[0007] The technology of Patent Document 1 has a problem in that the flatness of the nitride semiconductor layer is reduced because the laterally grown nitride semiconductor layer contacts the mask portion.

[0008] Means for solving problems

[0009] The semiconductor substrate involved in the present disclosure comprises: a template substrate including a growth inhibition region and a first seed crystal region arranged side by side in a first direction; and a first semiconductor portion located above the template substrate and including a nitride semiconductor, the first semiconductor portion having: a first protrusion extending from the first seed crystal region to a position above the growth inhibition region; a growth inhibition film connected to the first protrusion; a first base portion located above the first protrusion; and a first wing portion connected to the first base portion, separated from the growth inhibition region and located on the gap.

[0010] Effects of the Invention

[0011] The first semiconductor portion including a nitride semiconductor can be provided with low defect density and high flatness. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view showing the structure of a semiconductor substrate according to the present embodiment.

[0013] Figure 2 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0014] Figure 3 It is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment.

[0015] Figure 4 It is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment.

[0016] Figure 5 It is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment.

[0017] Figure 6 It is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment.

[0018] Figure 7 It is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment.

[0019] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the present embodiment.

[0020] Fig. 9 This is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment.

[0021] Fig.10 It is a block diagram showing a semiconductor substrate manufacturing apparatus according to the present embodiment.

[0022] Fig.11 This is a cross-sectional view showing the structure of the semiconductor substrate of Example 1.

[0023] Fig.12 This is a cross-sectional view showing another structure of the semiconductor substrate of Example 1.

[0024] Fig.13 It is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to Example 1.

[0025] Fig.14 It is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to Example 1.

[0026] Fig.15This is a cross-sectional view showing another structure of the semiconductor substrate of Example 1.

[0027] Fig.16 This is a graph showing the results of XRD scanning measurement in Comparative Examples.

[0028] Fig.17 This is a graph showing the XRD scanning measurement results of Example 1.

[0029] Fig.18 It is a top view of the semiconductor substrate including the upper layer portion.

[0030] Fig.19 It is a cross-sectional view of a semiconductor substrate including an upper layer portion.

[0031] Fig. 20 It is a top view showing the method of separating the elements in Example 1.

[0032] Fig.21 This is a cross-sectional view showing the method of element separation in Example 1.

[0033] Fig. 22 It is a schematic diagram showing the structure of the electronic device involved in Example 1.

[0034] Fig.23 This is a cross-sectional view showing the structure of a semiconductor substrate of Example 2.

[0035] Fig.24 It is a cross-sectional view showing the structure of a semiconductor substrate of Example 4.

[0036] Fig.25 It is a top view showing the structure of the semiconductor substrate of Example 5.

[0037] Fig.26 It is a cross-sectional view showing the structure of a semiconductor substrate of Example 5.

[0038] Fig. 27 It is a cross-sectional view showing a method for manufacturing a semiconductor substrate.

[0039] Fig.28 It is a cross-sectional view showing a method for manufacturing a template substrate.

[0040] Fig.29 It is a cross-sectional view showing a method for manufacturing a template substrate.

[0041] Fig.30 It is a cross-sectional view showing a method for manufacturing a template substrate.

[0042] Fig.31 It is a cross-sectional view showing the structure of the semiconductor substrate of Example 6.

[0043] Fig.32It is a cross-sectional view showing the structure of the semiconductor substrate of Example 6.

[0044] Fig.33 This is a flow chart showing a method for manufacturing a semiconductor device according to a seventh embodiment.

[0045] Fig.34 It is a cross-sectional view showing a method for manufacturing a semiconductor device of Example 7. DETAILED DESCRIPTION

[0046] Figure 1 It is a plan view showing the structure of a semiconductor substrate according to the present embodiment. Figure 2 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 1 as well as Figure 2 As shown, the semiconductor substrate 10 includes: a template substrate TS having a mask pattern 6 including a mask portion 5 and a first opening K1 arranged side by side in a first direction X1; and a first semiconductor portion 8A located above the template substrate TS and including a nitride semiconductor. The first semiconductor portion 8A includes: a first raised portion R1 extending from the first seed crystal region S1 located below the first opening K1 to a position above the upper surface of the mask portion 5; a first base B1 located above the first raised portion R1; and a first wing F1 connected to the first base B1, separated from the mask portion 5, and located on the gap JD. The semiconductor substrate 10 may include a growth inhibiting film 7 in contact with the first raised portion R1. The direction from the main substrate 1 to the first semiconductor portion 8A is set to "upward". Sometimes, observing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including the case of perspective) is called "top view". The mask portion 5 and the first opening K1 may be arranged side by side in the first direction X1 in a plan view.

[0047] The template substrate TS may include: a main substrate 1 having a lattice constant different from that of the first semiconductor portion 8A; and a seed crystal portion 3 including a first seed crystal region S1. The first opening portion K1, the first raised portion R1, and the first base portion B1 may overlap when viewed from above, and the mask portion 5 and the first wing portion F1 may overlap when viewed from above. The first wing portion F1 may not be in contact with the side surface of the first raised portion R1.

[0048] like Figure 1 as well as Figure 2As shown, the semiconductor substrate 10 includes: a template substrate TS including a first seed region S1 (an exposed surface of the seed portion 3) and a growth inhibition region DA (a mask portion 5) arranged side by side in the first direction X1; and a first semiconductor portion 8A located above the template substrate TS and including a nitride semiconductor. The first semiconductor portion 8A includes: a first raised portion R1 extending from the first seed region S1 to a position above the growth inhibition region DA; a first base portion B1 located above the first raised portion R1; and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located on the gap JD. The semiconductor substrate 10 may include a growth inhibition film 7 in contact with the first raised portion R1 at a position above the growth inhibition region DA. The first wing portion F1 may not be in contact with the side surface of the first raised portion R1. The first seed region S1 and the growth inhibition region DA may be arranged side by side in the first direction X1 when viewed from above.

[0049] The first semiconductor portion 8A includes a nitride semiconductor as a main component. Nitride semiconductors can be characterized, for example, as AlxGayInzN (0≤x≤1; 0≤y≤1; 0≤z≤1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0050] The first semiconductor portion 8A may be either a doped type (e.g., an n-type containing a donor) or an undoped type. The so-called semiconductor substrate refers to a substrate containing a semiconductor, and the main substrate 1 of the template substrate TS may contain a semiconductor (e.g., silicon, silicon carbide) or may not contain a semiconductor. As the main substrate 1 not containing a semiconductor, for example, there is a sapphire substrate. The main substrate 1 may be a self-supporting substrate (wafer). Sometimes the main substrate 1 and the seed crystal portion 3 are included and referred to as a base substrate. Sometimes the template substrate TS including the base substrate and the mask pattern 6 is referred to as a growth substrate.

[0051] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor portion 8A. The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor portion 8A (a nitride semiconductor such as GaN). The thickness direction Z of the first semiconductor portion 8A may be the c-axis direction (<1-20> direction) of the first semiconductor portion 8A. <0001> direction).

[0052] The first semiconductor portion 8A can be formed by an ELO (Epitaxial Lateral Overgrowth) method, starting from the first raised portion R1 grown from the seed crystal portion 3 exposed under the first opening K1. The base portion B1 located above the first opening K1 in the first semiconductor portion 8A becomes a dislocation inheritance portion with many threading dislocations, and the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a smaller threading dislocation density than the dislocation inheritance portion.

[0053] In this way, the first raised portion R1 is formed, and the first wing portion F1 is formed by extending laterally (in a direction parallel to the first direction X1) from the first base portion B1 on the first raised portion R1, and is separated from the mask portion 5 and located on the gap JD, thereby forming a wide first wing portion F1 with low defect density and high flatness. The entire first wing portion F1 can be separated from the mask portion 5. That is, the entire first wing portion F1 does not need to be in contact with the mask portion 5. Thus, a wide first wing portion F1 with low defect density and high flatness can be formed.

[0054] The semiconductor substrate 10 may include a second semiconductor portion 8C located above the template substrate TS. The template substrate TS includes a second seed crystal region S2 adjacent to the first seed crystal region S1 via the mask portion 5, and the second semiconductor portion 8C may include: a second raised portion R2 extending from the second seed crystal region S2 to a position above the mask portion 5; a second base portion B2 located above the second raised portion R2; and a second wing portion F2 connected to the second base portion B2, separated from the mask portion 5, and located on the gap JD. The first wing portion F1 and the second wing portion F2 may be arranged side by side in the first direction X1 via the gap GP.

[0055] In the following, the first raised portion R1 and the second raised portion R2 are sometimes collectively expressed as the raised portion R, the first semiconductor portion 8A and the second semiconductor portion 8C are collectively expressed as the semiconductor portion 8, the first wing portion F1 and the second wing portion F2 are collectively expressed as the wing portion F, the first base portion B1 and the second base portion B2 are collectively expressed as the base portion B, the first opening portion K1 and the second opening portion K2 of the mask pattern 6 are collectively expressed as the opening portion K, and the first seed crystal region S1 and the second seed crystal region S2 are collectively expressed as the seed crystal region S.

[0056] The growth inhibiting film 7 may be in contact with the upper surface 5T (growth inhibiting region DA) of the mask portion 5. The first raised portion R1 may be in contact with the upper surface 5T (growth inhibiting region DA) of the mask portion 5. The first raised portion R1 may climb up to the end portion 5E of the mask portion 5. The mask portion 5 and the growth inhibiting film 7 may contain, for example, the same silicon nitride, but in such a case, it is difficult to observe the growth inhibiting film 7 on the mask portion 5 separately from the mask portion 5.

[0057] The first wing portion F1 may have an edge E1 located above the mask portion 5 .

[0058] The growth inhibition film 7 may be in contact with the side surface RS of the first raised portion R1. Thus, since the growth of the semiconductor portion 8 from the side surface RS is suppressed, it is easy to form a gap JD. In addition, in order to achieve the effect of the present embodiment, the growth inhibition film 7 may be formed on at least a portion of the side surface RS of the first raised portion R1, and may include a first film portion 7j in contact with the side surface RS of the first raised portion R1 and a second film portion 7i in contact with the upper surface RT of the first raised portion R1. The growth inhibition film 7 is not necessarily a complete film, but may be a film (a film of an incomplete shape) including one or more tiny openings. By forming the second film portion 7i, the second film portion 7i can be used to suppress threading dislocations propagating from the seed crystal portion 3 to the first raised portion R1, and a new effect of improving the surface flatness and crystallization of the upper surface RT of the first raised portion R1 can be obtained.

[0059] The side surface RS of the first raised portion R1 may be a tapered surface. Thus, with respect to the gap JD, the width of the back surface facing the first wing portion F1 can be made wider than the width facing the upper surface 5T of the mask portion 5, and the first wing portion F1 with low defects can be formed wider. The side surface RS of the tapered surface may intersect with the upper surface 5T (growth inhibition area DA) of the mask portion 5. The growth inhibition film 7 may be in contact with the upper surface RT of the first raised portion R1. The second film portion 7i (the portion in contact with the upper surface RT of the first raised portion R1) located on the upper surface RT of the first raised portion R1 of the growth inhibition film 7 in contact with the first raised portion R1 may be included in the first semiconductor portion 8A. In this way, the stress from the template substrate TS is relieved.

[0060] The first raised portion R1 may have a growth starting point PG of the nitride semiconductor at a position above the mask portion 5. The growth starting point PG may not be in contact with the growth inhibiting film 7, or may be in contact with a portion where the growth inhibiting film 7 is locally thinned. A corner RC where the top surface RT and the side surface RS of the first raised portion R1 intersect may be included in the growth starting point PG. The corner RC may be located above the mask portion 5. That is, the corner RC and the mask portion 5 may overlap in a plan view.

[0061] In this way, by forming the mask pattern 6 having the opening K and then forming the first raised portion R1, the corner RC is formed in the first raised portion R1. Then, by forming the growth inhibition film 7 in contact with the first raised portion R1, the corner RC of the first raised portion R1 can be used as the growth starting point PG. It can be seen that the first raised portion R1 of the nitride semiconductor is formed by crystal growth from the seed portion 3 (seed region) exposed in the opening K, or pattern formation based on dry etching, etc., and the growth starting point PG is formed at the upper end (for example, the two corners) of the first raised portion R1. Therefore, even after the growth inhibition film 7 is formed on the first raised portion R1, a good nitride semiconductor layer (the first base B1 and the first wing F1) will grow, and the threading dislocations on the first raised portion R1 can be reduced.

[0062] By using the two corners of the first raised portion R1 (two corners RC arranged side by side in the first direction X1) as the growth starting point PG, lateral film formation from both sides can be caused, and pores can be formed in the first base B1 (especially the central part). In this way, the first base B1 can include pores, and thus, the stress from the template substrate TS is relieved. The pores can be located above the second film portion 7i of the growth inhibition film 7. The growth inhibition film 7 can be a silicon nitride film. The first direction X1 is the <11-20> direction, the upper surface of the first raised portion R1 is a polar surface, and the side surface of the first raised portion R1 can be a semi-polar surface or a non-polar surface. In this way, by using the raised portion R, the growth inhibition film 7 is formed on the upper part of the raised portion R, and the lateral film formation (growth) of the nitride semiconductor can also be performed above the opening K, and the portion of the semiconductor portion 8 on the growth inhibition film 7 located above the opening K (such as the base B) can also effectively suppress defects.

[0063] The mask portion 5 and the first opening K1 may each be shaped such that the longitudinal direction is a second direction X2 orthogonal to the first direction X1. The main substrate 1 is a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the nitride semiconductor included in the first semiconductor portion 8A may be a GaN-based semiconductor.

[0064] The seed crystal portion 3 may contain 2×10 18 / cm 3 The thickness of the mask portion 5 may be 50 [nm] or less. The thickness of the growth inhibiting film 7 may be thinner than the mask portion 5. Thus, while suppressing the growth on the mask portion, it becomes easy to grow the wing portion F from the raised portion R. The thickness of the growth inhibiting film 7 may be 1 / 3 or less of the thickness of the mask portion 5.

[0065] In the case where the ELO layer contacts the mask portion, the thickness of the mask portion needs to be at least 100 nm, and sometimes the surface flatness of the ELO layer is damaged due to the interference between the mask portion and the ELO layer. However, in Example 1, since the wing portion F floats in mid-air and does not contact the mask portion 5, even if the mask portion 5 is made very thin, the growth of the wing portion F will not be hindered. By thinning the mask portion 5, the flatness of the back of the wing portion F is improved. If the thickness of the mask portion 5 is less than 50 nm, the flatness is improved, and it can also be set to less than 30 nm.

[0066] The c-axis direction of the first base B1 and the c-axis direction of the edge of the first wing F1 may deviate by 0.2 degrees or less. The threading dislocation density in the first base B1 and the threading dislocation density in the first wing F1 may be 5×10 6 〔pcs / cm 2 The first semiconductor portion 8A may include two first wing portions F1 forming a pair and extending from the first base portion B1 in the first direction X1 and in the opposite direction thereof.

[0067] The ratio of the thickness of the gap JD to the width in the first direction X1 (the aspect ratio of the gap) can be 5.0 or more. The so-called gap JD is the space sandwiched by the mask portion 5 (growth inhibition area DA) and the first wing portion F1. The ratio of the thickness of the first wing portion F1 to the width in the first direction X1 can be 2.0 or more, 5.0 times or more, 10 times or more, 20 times or more, or 50 times or more. The width of the first wing portion F1 (the width in the first direction X1) can be 7.0 [μm] or more, 10.0 [μm] or more, 20.0 [μm] or more, or 40.0 [μm] or more. The width of the first wing portion F1 can be 80.0 [μm] or less. Thereby, the possibility of the semiconductor portion 8 warping in the upward direction due to gravity is reduced. The thickness of the first wing portion F1 can be 10.0 [μm] or less, 5.0 [μm] or less, or 2.0 [μm] or less. As Figure 2 As shown in FIG. 1 , the width of gap GP may be greater than the thickness of gap JD. The ratio of the width of the first wing portion F1 to the width of the first base portion B1 may be 3.0 or more. The thickness of gap JD may be 3.0 [μm] or less. In addition, the thickness (height) of gap JD is the distance from the upper surface (growth inhibition area DA) of mask portion 5 to the lower surface (back surface) of semiconductor portion 8. The width of gap JD is the distance in the first direction X1 from the side surface of first raised portion R1 to edge E1 of semiconductor portion 8.

[0068] Figure 3 as well as Figure 4 2 is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment. Figure 3As shown in FIG. 1 , the seed crystal portion 3 is formed in a pattern (eg, stripes arranged in parallel in the first direction X1), and the seed crystal portion 3 can be arranged under the mask portion 5. Figure 4 As shown in FIG. 1 , a buffer portion 2 is formed between the seed crystal portion 3 and the main substrate 1. The buffer portion 2 may be Figure 4 Such a surface shape can also be a pattern shape. Figure 4 In this way, the buffer portion 2 and the seed crystal portion 3 may be planar, the buffer portion 2 and the seed crystal portion 3 may be in the same pattern, or the buffer portion 2 may be planar and the seed crystal portion 3 may be in a pattern. Figure 3 , Figure 4 In this embodiment, a silicon substrate may be used as the main substrate 1 , AlN may be used as the buffer portion 2 , and a GaN-based semiconductor may be used as the seed crystal portion 3 .

[0069] Figure 5 2 is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment. Figure 5 As shown, the first wing portion F1 can be divided into a plurality of portions PA arranged side by side in the second direction X2 orthogonal to the first direction X1.

[0070] Figure 6 It is a cross-sectional view showing another structure of the semiconductor substrate according to the present embodiment. Figure 7 FIG. 2 is a top view showing another structure of the semiconductor substrate according to the present embodiment. Figure 6 as well as Figure 7 As shown, the semiconductor substrate 10 may include an upper layer portion 9 located above the first semiconductor portion 8A and including an active layer and a p-type layer. The upper layer portion 9 may be provided with an anode EA and a cathode EC.

[0071] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the present embodiment. Fig. 9 FIG. 1 is a flow chart showing a method for manufacturing a semiconductor substrate according to the present embodiment. Figure 8 as well as Fig. 9 As shown, the manufacturing method of the semiconductor substrate involved in the present embodiment includes: step S10, preparing a template substrate TS including a growth inhibition area DA (mask portion 5) and a first seed crystal portion S1 (a first opening portion K1 that exposes the seed crystal portion 3) arranged side by side in the first direction X1; step S20, forming a first raised portion R1 that comes from the first seed crystal region S1 to a position above the growth inhibition area DA (the upper surface 5T of the mask portion 5) and includes a nitride semiconductor; step S30, forming a growth inhibition film 7 connected to the first raised portion R1; step S40, forming a first base portion B1 located above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition area DA (mask portion 5) and located on the gap JD, so as to respectively include a nitride semiconductor.

[0072] The first base B1 and the first wing F1 can be formed by using the corner RC where the top surface RT and the side surface RS of the first raised portion R1 intersect as the growth starting point PG. As described above, the first base B1 and the first wing F1 can be formed by using the corner RC as the growth starting point PG, but the present invention is not limited thereto. A defect (e.g., a tiny opening) is formed in the growth inhibiting film 7, and there is no problem in using the defect in the growth inhibiting film 7 as the growth starting point of the first base B1 and the first wing F1.

[0073] The first raised portion R1, the growth inhibiting film 7, the first base portion B1, and the first wing portion F1 are continuously formed using an MOCVD device. The first raised portion R1 includes a GaN-based semiconductor, and the growth inhibiting film 7 is a silicon nitride. The first raised portion R1 is formed by supplying a raw material that serves as a gallium source and a raw material that serves as a nitrogen source. The growth inhibiting film 7 can be formed by supplying a silicon-based material while maintaining the supply of the raw material that serves as a nitrogen source and stopping the supply of the raw material that serves as a gallium source. The first base portion B1 and the first wing portion F1 include a GaN-based semiconductor. The first base portion B1 and the first wing portion F1 can be formed by supplying a raw material that serves as a gallium source while maintaining the supply of the raw material that serves as a nitrogen source and stopping the supply of the silicon-based material. In addition, the supply of a small amount of silicon-based material can be continued at a doping level.

[0074] The growth of the first wing F1 and the second wing F2 may be stopped before the first wing F1 and the second wing F2 growing toward the first wing F1 meet. The template substrate TS has a seed portion 3 including a first seed region S1, and the seed portion 3 is formed by sputtering.

[0075] Fig.10 FIG. 5 is a block diagram showing a semiconductor substrate manufacturing apparatus according to the present embodiment. The semiconductor substrate manufacturing apparatus 50 includes: Fig. 9 The device M10 of step S10 is used for Fig. 9 and a control device MC for controlling the device M10 and the device M45. The device M45 may be a MOCVD device.

[0076] [Example 1]

[0077] As the main substrate 1 , a silicon substrate, a silicon carbide substrate (4H—SiC, 6H—SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, or the like can be used.

[0078] The seed crystal portion 3 is formed above the main substrate 1 and becomes the starting point for the growth of the semiconductor portion 8. The seed crystal portion 3 may be formed at least in a portion of the opening portion K (of the mask pattern 6), and may be in a planar shape or in a patterned shape (e.g., a stripe shape). As the seed crystal portion 3, a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, etc. formed at a low temperature (below 500°C) may be used. The thickness of the seed crystal portion 3 is about 10nm to 500nm.

[0079] A buffer portion 2 can be formed between the main substrate 1 and the seed crystal portion 3 (e.g., a GaN layer), and the buffer portion 2 improves the crystallinity and flatness of the seed crystal portion 3. The buffer portion 2 can be planar or patterned (e.g., stripe-shaped) to match the seed crystal portion 3. As the buffer portion 2, a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, etc. formed at a low temperature (below 500°C) can be used. The thickness of the buffer portion 2 is about 10nm to 500nm. When a silicon substrate is used as the main substrate 1, in order to suppress melting back, it is desired that the buffer portion 2 connected to the silicon substrate does not contain gallium.

[0080] Sometimes the layer between the main substrate 1 and the semiconductor part 8 is called the base layer (including at least one of the buffer part 2 and the seed crystal part 3). As the base layer (such as the seed crystal part 3), a GaN layer can be formed by sputtering. In this case, for example, a sputtering target having gallium nitride as the main component (containing more than 25 atm% gallium) and an oxygen content of less than 5 atm% can be used, and the sputtering gas pressure is set to less than 0.3 Pa. As a sputtering method, DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron cyclotron Resonance) sputtering, RF magnetron sputtering, PSD (Pulsesputter deposition) method, laser ablation method, etc. can be appropriately selected.

[0081] In order to improve the crystallization of the entire film, the sputtering target used is expected to have an oxygen content of less than 5 atm%, less than 3 atm%, or less than 1 atm%. The purity is also expected to be as high as possible, and the content of metal impurities can be less than 0.1% or less than 0.01%. When forming a GaN layer by sputtering, by using a gallium nitride target with a low oxygen content, effects such as surface flatness, improved crystallization, and suppression of the formation of surface hillocks (protrusions) can be seen.

[0082] When a nitride semiconductor (AlN, GaN, etc.) is formed by sputtering as a base layer, the vacuum degree before film formation in the device can be set to 3×10 -5 Pa or less or 1×10 -5Pa or less. The organic layer and bumps on the surface of the base substrate can be removed by pre-treating the base substrate (main substrate, buffered main substrate, etc.) before film formation, so that epitaxial growth can be performed. Specific examples of pre-treatment include reverse sputtering treatment, acid treatment, UV treatment, etc. Reverse sputtering treatment is preferred from the perspective of preventing re-adhesion of impurities, etc. after treatment. The so-called reverse sputtering treatment is a method of cleaning the surface of the base substrate by causing plasmatized atoms to collide with the side of the base substrate. The substrate temperature during film formation can be room temperature, but by performing it under a heated substrate state (for example, 400° to 1000°), the film quality can be further improved.

[0083] The power density during discharge can be set to 5W / cm 2 Below or 1.5W / cm 2 The lower limit of power density can be 0.1 W / cm 2 or 0.3W / cm 2 The power density is the value obtained by dividing the power applied during discharge by the area of ​​the sputtering target. If the power density is too high, the target may be sputtered in a clustered state.

[0084] In Example 1, the base layer (e.g., seed crystal portion) of the GaN layer is formed by RF sputtering. A gallium nitride target (oxygen content: 0.4 atom%) is used, the film forming pressure is set to 0.1 Pa, and 20 to 40 sccm of nitrogen gas is introduced. In Example 1, argon gas is not used, but of course argon gas can also be introduced. The discharge density is 125 W / cm 2 , the film forming temperature is room temperature.

[0085] When the base layer (including at least one of the buffer portion 2 and the seed crystal portion 3) is formed by sputtering, laser ablation, etc., the internal stress can be controlled from compressive stress to tensile stress according to the film forming conditions, so the stress to the semiconductor portion 8 can be controlled. The internal stress can also be controlled by the amount of argon introduced into the base layer. The stress to the semiconductor portion 8 can also be controlled by forming the base layer locally (patterned) on the base substrate.

[0086] The mask pattern 6 is formed on the base substrate using a material that inhibits the longitudinal growth (growth in the c-axis direction) of the nitride semiconductor, thereby achieving lateral growth (for example, growth in the a-axis direction). The opening K of the mask pattern 6 (the exposed portion of the seed crystal portion 3) becomes the growth starting point of the semiconductor portion 8. As materials for the mask portion 5 of the mask pattern 6, silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon oxynitride, etc., silicon-free titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, etc., and further high melting point metals (molybdenum, tungsten, molybdenum, etc.) can be cited. The mask portion 5 can be a single-layer film containing one of these materials, or a multilayer film combining multiple of these materials. The thickness of the mask portion 5 can be about 5nm to 2μm.

[0087] Fig.11 This is a cross-sectional view showing the structure of a semiconductor substrate of Example 1. In Example 1, a silicon substrate is used as a main substrate 1, and an AlN layer as a seed crystal portion 3 is formed on a portion of the main substrate. By forming an Al layer of about 1 to 5 nm between the seed crystal portion 3 (AlN layer) and the main substrate 1 (silicon substrate) as a buffer portion 2, the crystallization of the seed crystal portion 3 (AlN layer) can be improved.

[0088] A mask pattern 6 having a first opening K1 is formed on the seed crystal portion 3. A raised portion R is formed from the opening K. The surface of the raised portion R is located at a height H1 from the upper surface 5T of the mask portion 5. From the perspective of ensuring the crystallinity and surface flatness of the semiconductor portion 8, the raised portion R may be 0.

[0089] ​The base B and the wing F are formed on the upper side of the growth inhibition film 7 on the protrusion R and are completely separated from the mask portion 5. The defect density of the wing F of the semiconductor portion 8 is two orders of magnitude lower than that of the base B on the opening K, and the crystallization is also good, so it is suitable for forming the active region of the upper layer (device layer). The wing F is a region from the edge of the upper surface of the protrusion R to the edge of the semiconductor portion 8, and this region can be set as a device region. Since the back of the wing F is separated from the mask portion 5, the wing F can be formed without affecting the mask portion 5. In Example 1, since the adjacent semiconductor portions 8 are separated without merging with each other, the stress from the main substrate 1 and the seed crystal portion 3 containing a material different from the semiconductor portion 8 can be effectively alleviated. As a result, the suppression of crack generation and the ensuring of the surface flatness of the semiconductor portion 8 can be achieved. In addition, the adjacent semiconductor portions 8 can also be made to meet with each other.

[0090] In Example 1, the width of the opening K is 5 μm, the width of the mask portion 5 is 50 μm, the pitch width RP of the protrusion R is 55 μm, and the height H1 of the protrusion R is 1.5 μm. The back surface of the semiconductor portion 8 is at the same height as the upper surface RT of the protrusion R, and the thickness (height) of the gap JD is 1.5 μm. In addition, the growth of the semiconductor portion 8 is stopped so that the width of the gap GP between adjacent semiconductor portions 8 becomes 10 μm.

[0091] Fig.12 : is a cross-sectional view showing another structure of the semiconductor substrate of Example 1. After the semiconductor portion 8 is formed, the upper portion 9 (device layer) is formed on the semiconductor portion 8. Specifically, a stacked structure of LED, laser, PD, power device, etc. can be formed using MOCVD, MBE, sputtering, etc. At least a part of the active region of the upper portion 9 can be formed on the wing portion F (device region), and in Example 1, the entire active region is formed on the wing portion F. Electrodes ET (anode, cathode, gate, etc.) can be provided on the upper portion 9.

[0092] Fig.13 as well as Fig.14 1 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. Fig.13 As shown, an AlN layer as a seed crystal portion 3 is formed on a main substrate 1 (silicon substrate) by sputtering with a thickness of 100 nm. Next, a mask layer MF (e.g., SiN) with a thickness of 10 nm is formed on the seed crystal portion 3 (AlN layer) by sputtering. Next, a resist Z coated on the mask layer MF is formed in a stripe pattern using a general photolithography method. Thereafter, an opening K and a mask portion 5 are formed in the mask layer MF by dry etching (e.g., ion coupled plasma ICP: Ion Coupled Plasma, etc.) to expose the seed crystal portion 3 (AlN layer). Thereafter, the resist Z is removed to form a template substrate TS.

[0093] After the template substrate TS is transported to the MOCVD device, Fig.14 As shown, the first step of film formation for ELO is performed. Thus, the raised portion R (the first raised portion R1 and the second raised portion R2) is formed. As film formation conditions, the film formation temperature is set to 1100°C, the flow rate of ammonia is set to 7.5 slm, and the flow rate of TMG (trimethylgallium) is set to 5 sccm.

[0094] The raised portion R only needs to extend beyond the upper surface of the mask portion 5, and may extend slightly laterally from the opening portion K, or may be contained within the opening portion K. Fig.14 In the state where the film thickness slightly protrudes laterally from the opening end, it becomes 1.5 μm, thereby hindering the growth of the protrusion R.

[0095] Next, the film forming temperature is lowered by about 150°C from the initial growth temperature, the supply of TMG is stopped, and SiH4 (silane) is supplied at a flow rate of 400 sccm and ammonia (NH3) at a flow rate of 7.5 slm to form a thin SiN layer (about 1 nm). Thus, a growth inhibition film 7 is formed on the side surface RS and the upper surface RT of the protrusion R.

[0096] Next, the film forming temperature was raised by 250° C., and TMG and ammonia were supplied again to form the semiconductor portion 8. At this time, it was found that the film formation of the semiconductor portion 8 was greatly affected by the growth inhibition film 7, and the wing portion F was formed in a state of floating from the mask portion 5 on the raised portion R. That is, the back surface of the wing portion F of the semiconductor portion 8 was completely separated from the mask portion 5.

[0097] It can be seen that the protrusion R is convex in shape, has an upper surface RT and side surface RS, and a corner RC with different crystal orientation planes, thereby more effectively suppressing the growth of the protrusion R toward the side surface RS than the growth of the protrusion R toward the upper surface RT. This unique crystal growth is a new discovery of the inventors. The upper surface RT of the protrusion R is a c-plane (polar plane), and the side surface RS is a semi-polar plane "(11-22) plane, etc." or a non-polar plane "(11-20) plane, etc.", which affects the formation state of the growth inhibition film 7 and the crystal growth state of the semiconductor portion 8. As a result, it is believed that the semiconductor portion 8 will be formed preferentially on the upper surface RT.

[0098] Fig.15 2 is a cross-sectional view showing another structure of the semiconductor substrate of Example 1. Fig.11 In the embodiment, the height of the back surface of the semiconductor portion 8 is formed to be substantially the same as the height of the upper surface RT of the raised portion R. Fig.15In the embodiment, the height of the semiconductor portion 8 is lowered to a position lower than the upper surface of the raised portion R, and the semiconductor portion 8 is formed. This can be selected by controlling the film forming conditions of the semiconductor portion 8 and the film forming conditions of the growth inhibition film 7 (film forming temperature, film forming time, gas flow rate, etc.). In either case, the effect of Example 1 can be obtained. Fig.15 In FIG. 4 , the height H1 of the protrusion R is 1.5 μm. However, since the rear surface of the semiconductor portion 8 is formed at a location 100 nm lower than the height of the upper surface RT of the protrusion R, the thickness (height) of the gap JD is 1.4 μm.

[0099] As can be seen from Example 1, although the wing portion F is formed without interference from the main substrate 1, the seed crystal portion 3, and the mask portion 5, it is very effective in suppressing the deviation of the crystal axis of the wing portion F. That is, in order to suppress the deviation of the crystal axis, the wing portion F can be completely separated from the mask portion 5. In this case, it is better that the wing portion F is only in contact with the protrusion R, the growth inhibition film 7, and the base B.

[0100] Fig.16 is a graph showing the XRD scanning measurement results in Comparative Examples, Fig.17 This is a graph showing the XRD scanning measurement results of Example 1. Fig.16 as well as Fig.17 The measurement result of the (002) plane is that the incident direction of the X-ray is <11-20>. In Example 1, a 1.5 μm GaN layer is used for the seed crystal part 3, and a 200 nm AlN layer is used for the buffer part 2. In the comparative example, the buffer part and seed crystal part same as those in Example 1 are used, and the ELO layer is formed to contact the mask part.

[0101] exist Fig.16 In the figure, three peaks can be seen. The central peak is the peak of the GaN layer (base) on the seed crystal, and the crystal axis of the c-plane is roughly perpendicular to the surface of the mask. The remaining two peaks are the peaks of the GaN layer on the wing, and Δ (peak angle difference) = 0.8 degrees was observed. This means that the c-axes of the two wings on both sides of the base each grow about 0.4° away from the center to the opposite side, indicating a low degree of flatness of the semiconductor portion 8. In contrast, in Example 1, Fig.17 In the graph, the peak is not separated and is essentially a single peak. This means that the crystal axes of the two wings F on both sides of the base B are aligned and the deviation is very small.

[0102] Fig.17The result can be said to be a very good result for the semiconductor part 8 having the wide wing F. It is believed that the back surface of the wing F of the semiconductor part 8 is separated from the mask part 5, and at least one side of the semiconductor part 8 that is in contact with only the raised part R contributes to the suppression of the deviation of the crystal axes of the two wing F on both sides of the base B. In Example 1, it can also be seen that the incorporation of indium (In) during the formation of the upper layer part 9 becomes uniform on the surface of the semiconductor part 8, for example, the yield and luminous efficiency of the light-emitting element are improved.

[0103] The growth inhibition film 7 in contact with the raised portion R also has an effect other than floating the semiconductor portion 8 from the mask portion 5. It is known that when a material different from the semiconductor portion 8 is used in at least one of the main substrate 1, the seed crystal portion 3, and the buffer portion 2, stress caused by the difference in thermal expansion coefficient and lattice constant will be generated in the semiconductor portion 8, but by providing the growth inhibition film 7 between the raised portion R and the semiconductor portion 8 to alleviate such stress, defects, cracks, etc. in the semiconductor portion 8 are greatly suppressed. This effect is very important in improving the quality and yield of the upper portion 9.

[0104] In Example 1, it can be seen that the defect density of the base B and the wing F is greatly reduced. According to the formation state of the growth inhibition film 7, as shown in FIG. Fig.14 As shown, the growth of the base B and the wing F can go through the following growth process: starting from the ends (corners RC) on both sides of the ridge R, the crystals growing from these ends (corners RC) toward the center meet each other near the center of the upper surface of the ridge R. As a result, the defect density of the base B (crystals on the ridge R) can be reduced. By greatly reducing the defect density in the entire area of ​​the semiconductor portion 8 (covering the entire width of the base B and the wing F), the active region of the upper layer portion 9 can also be formed in the base above the opening. Such a method has not been known so far, and it is considered to be a very effective technology in the industry.

[0105] In Example 1, the growth inhibition film 7 is formed by supplying silane gas and ammonia gas, but it can also be formed by other methods. For example, by continuing to flow only ammonia gas and not silane gas for several minutes in a state where the protrusion R is formed, a film (growth inhibition film 7) containing silicon due to residual silicon in the device can be formed to be in contact with the protrusion R. In addition, after the protrusion R is formed, the substrate is temporarily removed from MOCVD and the surface of the protrusion is slightly oxidized, so that the growth inhibition film 7 containing silicon and oxygen can also be formed. In Example 1, a silicon substrate is used as the main substrate 1, but a SiC substrate, a sapphire substrate, etc. can also be used appropriately.

[0106] Fig.18 It is a top view of the semiconductor substrate including the upper layer portion. Fig.19It is a cross-sectional view of a semiconductor substrate including an upper portion. It is also possible to change the film forming conditions (for example, lower the film forming temperature by about 100°C) after stopping the growth of the semiconductor portion 8 to form the upper portion 9 on the semiconductor portion 8. The upper portion 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer in addition to the active layer. Even in the case where the upper portion 9 is formed on the semiconductor substrate 10, the back-winding phenomenon of the upper component material supplied to the back side of the semiconductor portion 8 is greatly suppressed, and the problem of light absorption caused by the back-winding phenomenon is eliminated.

[0107] exist Fig.18 as well as Fig.19 In the semiconductor substrate 10 described above, an anode EA and a cathode EC are formed above the wing F of the semiconductor portion 8. In a general LED, an active region (light-emitting region) is formed directly below the anode EA formed of a transparent electrode such as ITO (indium tin oxide). Since the wraparound phenomenon is suppressed in Example 1, the problem of light emitted from the active region being absorbed by the back side of the wing F is eliminated. At least a portion of the anode EA may be located above the wing F, or the entire anode EA may be located above the wing F. Since the area directly below the cathode EC is generally not an active region, the cathode EC may be formed above the base B. Fig.18 as well as Fig.19 In the embodiment, the anode EA and the cathode EC are formed on the same wing F, but the present invention is not limited thereto. Figure 6 as well as Figure 7 In this way, the anode EA is formed on one of the two wing portions F facing each other with the base portion B interposed therebetween, and the cathode EC is formed on the other.

[0108] In the conventional ELO method, cracks may sometimes occur in the semiconductor layer due to the difference in thermal expansion coefficients between the heterogeneous substrate and the semiconductor layer. On the other hand, in Example 1, the semiconductor portion 8 is located on the gap and is physically separated from the mask portion 5, the bonding between the raised portion R and the semiconductor portion 8 is weak due to the growth inhibition film 7, and the adjacent semiconductor portions 8 do not meet (there is a gap GP). While using a heterogeneous substrate (Si substrate, SiC substrate, etc.), internal stress is effectively relaxed and crack generation is suppressed. In addition, by widening the width of the wing portion F (for example, setting it to 7μm or more), stress relaxation based on the wing portion F can be sought.

[0109] Fig. 20 It is a top view showing the method of separating the elements in Example 1. Fig.21 2 is a cross-sectional view showing the method of separating the components in Example 1. Fig. 20 as well as Fig.21As shown, the element body 20 (including the wing portion F, the upper portion 9, the anode EA, and the cathode EC) is separated from the template substrate. Since there is a gap JD under the wing portion F, by applying downward pressure to the element body 20 with an adhesive pressing body YS (adhesive plate, adhesive sheet, etc.), the root portion of the element body 20 (the portion connected to the template substrate TS) is easily broken, and the element body 20 is separated from the template substrate TS. Specifically, the element body 20 is peeled off from the template substrate TS while being held by the pressing body YS. In this way, the gap JD also functions effectively in the separation of the element body, and the element body 20 can be peeled off without causing damage to the element body 20.

[0110] Specific examples of the element body 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, a transistor (including a power transistor and a high electron mobility transistor), and the like.

[0111] Fig. 22 : is a schematic diagram showing the structure of the electronic device involved in Example 1. The electronic device 30 includes: an element body 20; a drive substrate 23 on which the element body 20 is mounted; and a control circuit 25 that controls the drive substrate 23. The control circuit 25 may include a processor. Examples of the electronic device 30 include a display device, a laser emitting device (including a Fabry-Perot type and a surface emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.

[0112] exist Fig. 22 In the embodiment, the element body 20 is bonded and electrically connected to the drive substrate 23 in a state of being peeled from the template substrate TS, but may be bonded and electrically connected to the drive substrate 23 in an unpeeled state (the template substrate TS and the element body 20 thereon).

[0113] [Example 2]

[0114] Fig.23 : is a cross-sectional view showing the structure of the semiconductor substrate of Example 2. In Example 2, the seed layer 3 does not cover the entire surface of the main substrate 1, but is a point in a strip shape. There is an opening K of the mask pattern 6 on the seed portion 3 (AlN layer). In Example 2, the width of the opening K is slightly narrower than the width of the seed portion 3, and the AlN layer (seed portion 3) is provided under the opening K over the full width of the opening K. Therefore, the raised portion R as the GaN layer and the silicon substrate as the main substrate 1 are spatially separated by the AlN layer, and the remelting of Ga and silicon is suppressed.

[0115] By using a buffer layer locally, the stress from the buffer layer can be relieved. By forming the semiconductor portion 8 and the growth inhibition film 7 by the method shown in Example 1, the wing portion F is completely separated from the mask portion 5, and the wing portion F is only in contact with the raised portion R, and the deviation of the crystal axis of the wing portion F can be suppressed to the same level as in Example 1. In Example 2, a silicon substrate is used as the main substrate 1, but a SiC substrate, a sapphire substrate, etc. can also be said to be suitable for the main substrate 1.

[0116] [Example 3]

[0117] In Example 3, Figure 4 semiconductor substrate. In Example 3, a GaN layer is formed on the AlN layer serving as the buffer portion 2 as a seed crystal portion 3. The GaN layer serving as the seed crystal portion 3 is formed by, for example, sputtering. By forming the semiconductor portion 8 and the growth inhibition film 7 by the method shown in Example 1, the wing portion F is completely separated from the mask portion 5, and the wing portion F is in contact only with the raised portion R, so that the deviation of the crystal axis of the wing portion F can be suppressed to the same level as in Example 1. In Example 2, a silicon substrate is used as the main substrate 1, but a SiC substrate, a sapphire substrate, etc. can also be said to be suitable for the main substrate 1.

[0118] [Example 4]

[0119] Fig.24 : is a cross-sectional image showing the structure of the semiconductor substrate of Example 4. Fig.24 In the semiconductor substrate 10 shown in FIG. 1 , the width Ws (length in the first direction) of the first semiconductor portion 8A is 50.9 [μm], the thickness of the gap JD is 347 [nm], the thickness of the first wing portion F1 is 3.52 [μm], and the opening width (seed region width) is 3.13 [μm]. The threading dislocation density of each of the first base portion B1 and the first wing portion F1 can be 5×10 6 〔pcs / cm 2 The total width Ws (length in the first direction) of the first semiconductor portion 8A may be 5 times or more, 10 times or more, 20 times or more, or 50 times or more the thickness of the first wing portion F1.

[0120] [Example 5]

[0121] Fig.25 It is a top view showing the structure of the semiconductor substrate of Example 5. Fig.26 is a cross-sectional view showing the structure of a semiconductor substrate of Example 5. Fig.25 as well as Fig.26As shown, the semiconductor substrate 10 includes: a template substrate TS including a first seed crystal region S1 and a growth inhibition region (non-seed crystal portion) DA arranged side by side in a first direction X1; and a first semiconductor portion 8A located above the template substrate TS, the first semiconductor portion 8A including: a first raised portion R1 extending from the first seed crystal region S1 to a position above the growth inhibition region DA; a growth inhibition film 7 connected to the first raised portion R1; a first base portion B1 located above the first raised portion R1; and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA and located on the gap JD. The first wing portion F1 may include a wing end (edge) E1 located above the growth inhibition region DA. In this way, the flatness on the first wing portion F1 can be improved.

[0122] In the first semiconductor portion 8A, the raised portion R1 may be formed in a mesa shape on the first seed region S1 and connected to the first base portion B1. The growth inhibiting film 7 may be in contact with the side surface and the upper surface of the raised portion R1, or may be located on the growth inhibiting region DA.

[0123] In the semiconductor substrate 10, the template substrate TS includes a main substrate 1 and a base layer 4. In the first seed crystal region S1, the base layer 4 can be set to be unmodified, and in the growth inhibition region DA, the base layer 4 can be set to be modified. The ratio of the thickness TJ of the gap JD (for example, the thickness under the wing end E1) to the width in the first direction X1 can be 5.0 or more.

[0124] Fig. 27 is a cross-sectional view showing a method for manufacturing a semiconductor substrate. Fig. 27 The method includes the following steps: preparing a template substrate TS including a first seed crystal region S1 and a growth inhibition region DA; forming a protrusion R1 from the first region S1 above the template substrate TS; forming a growth inhibition film 7 connected to the protrusion R1; forming a first base B1 located above the protrusion R1, and a first wing F1 connected to the first base B1, separated from the growth inhibition region DA and located on the gap JD.

[0125] like Fig. 27 As shown in FIG. 1 , the first base B1 and the first wing F1 can be formed with the corner RC of the raised portion R1 as the growth starting point. The corner RC can be used as the growth starting point, but the present invention is not limited thereto. A defect (e.g., a tiny opening) can be formed in the growth inhibition film 7 on the first raised portion R1, and the defect in the growth inhibition film 7 can be used as the growth starting point of the first base B1 and the first wing F1.

[0126] The raised portion R1, the growth inhibiting film 7, the first base portion B1 and the first wing portion F1 can be continuously formed using an MOCVD device. The first raised portion R1 includes a GaN-based semiconductor, and the growth inhibiting film 7 is a silicon nitride. The first raised portion R1 is formed by supplying a raw material that serves as a gallium source (organic raw materials such as trimethyl gallium (TMG) and triethyl gallium (TEG)) and a raw material that serves as a nitrogen source (ammonia gas (NH3)). The growth inhibiting film 7 can also be formed by supplying a silicon-based material (such as SiH4) while maintaining the supply of the raw material that serves as a nitrogen source. The first base portion B1 and the first wing portion F1 include a GaN-based semiconductor. The first base portion B1 and the first wing portion F1 can be formed by supplying a raw material that serves as a gallium source while maintaining the supply of the raw material that serves as a nitrogen source and stopping the supply of the silicon-based material. In addition, a small amount of silicon-based material can be continuously supplied at a doping level.

[0127] By forming the growth inhibition film 7 in this way, the film formation can be continuously performed while forming the gap DJ under the wing portion F without removing the film from the MOCVD device, which can reduce the manufacturing time and manufacturing cost. By forming the gap DJ, the wing portion F is formed without contacting the base layer 4 (growth inhibition area DA), and the stress from the main substrate 1 and the base layer 4 applied to the semiconductor portion 8 can be effectively alleviated.

[0128] Fig.28 is a cross-sectional view showing a method for manufacturing a template substrate. Fig.28 As shown in FIG. 1 , the substrate 4 can be obtained by performing a step of forming a base layer 4 including a base material, a step of forming a film of a resist RZ on the base layer 4, a step of patterning the resist RZ, a step of subjecting the exposed base material to a plasma treatment, and a step of removing the resist RZ. Fig.26 The template substrate TS can also be formed by sputtering.

[0129] In the plasma treatment, for example, by irradiating the exposed surface 4D of the base layer 4 with argon plasma, the surface of the irradiated area is modified to form a growth inhibition area DA. By introducing not only argon gas but also oxygen gas, nitrogen gas, hydrogen gas, etc. into the chamber, in the plasma treatment, in addition to argon plasma, oxygen plasma, nitrogen plasma, hydrogen plasma, or mixed plasma thereof can be used. Thus, the growth inhibition area DA can contain argon, oxygen, nitrogen, etc. as impurities. In such a case, the base material can be aluminum nitride, and the growth inhibition area DA can be aluminum oxynitride. In addition, the base material can be AlScN (aluminum scandium nitride), and the growth inhibition area DA can be AlScON (aluminum scandium oxynitride).

[0130] Fig.29 is a cross-sectional view showing a method for manufacturing a template substrate. Fig.29As shown, the following steps can be performed: forming a resist RZ on the base layer 4 (e.g., AlN layer) in a pattern; forming a film CM (e.g., a silicon nitride film of about 10 nm) covering the base layer 4 and the resist RZ; removing the resist RZ (stripping the pattern to form the film CM); annealing the film CM and the base layer 4 (e.g., heating at 1000°C); and removing the film CM (e.g., removing the silicon nitride film by BHF). In this way, a growth inhibition area DA located under the film CM can be formed on the surface of the base layer 4 through the mutual diffusion phenomenon between the film CM and the base layer 4 during annealing. In addition, by forming the film CM by sputtering, the surface modification under the film CM can be performed even without annealing. The base material can be AlScN, ScN, ZnO, CrN, etc. containing dissimilar materials (e.g., metal elements other than group III) such as Sc (scandium), Zn, and Cr. The base layer 4 can be a single-layer structure or a multi-layer structure. A multilayer structure including a periodic structure is also possible.

[0131] Fig.30 is a cross-sectional view showing a method for manufacturing a template substrate. Fig.30 As shown, the following steps can be performed: patterning a resist RZ on a base layer 4 (e.g., an AlN layer); subjecting the exposed base material to an impurity ion implantation process; and removing the resist RZ. Examples of impurities include Si (silicon), Fe (iron), Mg (magnesium), and the like. During the implantation process, the surface is modified by embedding impurity ions in the exposed surface 4D of the base layer 4 to form a growth inhibition region DA. The base material may be AlScN, ScN, ZnO, CrN, and the like containing heterogeneous materials such as Sc (scandium), Zn, and Cr (e.g., metal elements other than group III). The base layer 4 may be a single-layer structure or a multi-layer structure. It may also be a multi-layer structure containing a periodic structure.

[0132] [Example 6]

[0133] Fig.31 as well as Fig.32 is a cross-sectional view showing the structure of a semiconductor substrate of Example 6. Fig.31 as well as Fig.32As shown, the semiconductor substrate 10 comprises: a template substrate TS including a first seed crystal region S1 and a growth inhibition region (non-seed crystal portion) DA arranged side by side in a first direction X1; and a first semiconductor portion 8A located above the template substrate TS, the first semiconductor portion 8A comprising: a first raised portion R1 extending from the first seed crystal region S1 to a position above the growth inhibition region DA; a growth inhibition film 7 connected to the first raised portion R1; a first base portion B1 located above the first raised portion R1; and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA and located on the gap JD. The first wing portion F1 may include a wing end E1 located above the growth inhibition region DA. In this way, the flatness on the first wing portion F1 can be improved.

[0134] Fig.31 The template substrate TS includes a main substrate 1, a buffer layer 2 and a seed crystal portion 3, wherein the buffer layer 2 may be a growth inhibition layer (a layer that inhibits the growth of nitride semiconductor crystals). The buffer layer 2 may include at least one of a 4H-SiC layer, a 6H-SiC layer, a 3C-SiC layer, a sapphire layer, a diamond layer and a ScAlMgO layer. A seed crystal portion 3 (e.g., AlN) including a first seed crystal region S1 is locally formed on the buffer layer 2, and a region of the buffer layer 2 that does not overlap with the seed crystal portion 3 functions as a growth inhibition region DA. The main substrate 1 may use a Si substrate, a SiC substrate, a sapphire substrate, or the like.

[0135] Fig.32 The template substrate TS includes a main substrate 1 and a seed crystal portion 3. The main substrate 1 can be a growth inhibition substrate (a substrate that inhibits the growth of nitride semiconductor crystals) such as a 3C-SiC substrate, for example, a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, a sapphire substrate, a diamond substrate or a ScAlMgO substrate. A seed crystal portion 3 (for example, AlN) including a first seed crystal region S1 is partially formed on the main substrate 1, and a region on the upper surface of the main substrate 1 that does not overlap with the seed crystal portion 3 functions as a growth inhibition region DA.

[0136] [Example 7]

[0137] Fig.33 This is a flow chart showing a method for manufacturing a semiconductor device according to a seventh embodiment. Fig.34 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 7. Fig.33 as well as Fig.34As shown in the figure, by performing step S60 of preparing the semiconductor substrate 10, step S70 of forming the upper layer 9 above the first wing F1, and step S80 of peeling the first wing F1 from the template substrate TS while keeping the first wing F1 and the upper layer 9 on the transfer substrate PS, the element body 20 (semiconductor device) or the semiconductor device 21 including the element body 20 and the transfer substrate PS can be obtained. The upper layer 9 (functional layer) can be, for example, a nitride semiconductor layer including an active layer (for example, a GaN-based semiconductor layer), and the semiconductor device (20, 21) can include an electrode, an insulating film, etc. located on the upper layer 9.

[0138] exist Fig.34 In the semiconductor substrate 10, since the growth inhibiting film 7 is provided on the raised portion R1, the raised portion R1 is weakly bonded to the first wing portion F1, and the first wing portion F1 can be easily peeled off. The first wing F1 and the first base portion B1 can also be peeled off from the template substrate TS by cleaving the boundary between the first base portion B1 and the first raised portion R1.

[0139] (Additional Notes)

[0140] The above disclosure is for the purpose of illustration and explanation, and is not intended to be limiting. Based on these illustrations and explanations, many modifications are self-evident to those skilled in the art, and therefore, it is to be noted that these modifications are also included in the embodiments.

[0141] Explanation of symbols

[0142] 1 Main base board

[0143] 2 Buffer part (buffer layer)

[0144] 3 Seed crystal

[0145] 5 Mask Department

[0146] 6 Mask Pattern

[0147] 7 Growth inhibition film

[0148] 8A 1st Semiconductor Division

[0149] 8C Semiconductor Division 2

[0150] 10 Semiconductor substrate

[0151] 20 Semiconductor devices (component body)

[0152] 25 Semiconductor devices

[0153] 50 Semiconductor substrate manufacturing device

[0154] DA growth inhibition region

[0155] R1 1st raised part

[0156] R2 2nd ridge

[0157] E1 Edge of the first semiconductor part

[0158] B1 1st base

[0159] B2 Second base

[0160] F1 Wing 1

[0161] F2 2nd Wing

[0162] JD Gap

[0163] S1 1st seed crystal area

[0164] S2 Second seed crystal area

[0165] DA growth inhibition region

[0166] TS template substrate.

Claims

1. A semiconductor substrate comprising: a template substrate including a growth inhibition region and a first seed crystal region arranged side by side in a first direction; and a first semiconductor portion located above the template substrate and including a nitride semiconductor, The first semiconductor portion includes: a first raised portion extending from the first seed crystal region to a position above the growth inhibition region; a growth inhibition film in contact with the first raised portion; a first base portion located above the first raised portion; and A first wing portion is connected to the first base portion, separated from the growth inhibition region and located on the gap.

2. The semiconductor substrate according to claim 1, wherein The first wing portion has a wing end located above the growth inhibition region.

3. The semiconductor substrate according to claim 2, wherein: The growth inhibition film is a film having one or more openings.

4. The semiconductor substrate according to any one of claims 1 to 3, wherein The first wing portion is not in contact with a side surface of the first raised portion.

5. The semiconductor substrate according to claim 4, wherein: The first raised portion climbs up to the end portion of the growth inhibition region.

6. The semiconductor substrate according to any one of claims 1 to 5, wherein The template substrate has: A mask portion functioning as a growth suppression region; and The first opening of the mask portion is absent, The first opening overlaps with the first seed crystal region.

7. The semiconductor substrate according to any one of claims 1 to 6, wherein The semiconductor substrate comprises: a second semiconductor portion located above the template substrate; The template substrate includes: a second seed crystal region adjacent to the first seed crystal region across the growth suppression region; The second semiconductor portion has: a second raised portion extending from the second seed crystal region to a position above the growth inhibition region; a second base portion located above the second raised portion; and a second wing connected to the second base, separated from the growth inhibition region and located on the gap, The first wing portion and the second wing portion are arranged side by side in the first direction with a gap therebetween.

8. The semiconductor substrate according to any one of claims 1 to 7, wherein The growth inhibition film is in contact with a side surface of the first raised portion.

9. The semiconductor substrate according to claim 8, wherein: The side surface is a tapered surface with an upward taper.

10. The semiconductor substrate according to claim 9, wherein The conical surface intersects with an upper surface of the growth inhibition region.

11. The semiconductor substrate according to claim 8, wherein The growth inhibition film is in contact with the upper surface of the first raised portion.

12. The semiconductor substrate according to claim 11, wherein A portion of the growth inhibiting film in contact with the upper surface of the first raised portion is included in the first semiconductor portion.

13. The semiconductor substrate according to claim 8, wherein The first raised portion has a growth starting point of the nitride semiconductor at a position above the growth suppression region.

14. The semiconductor substrate according to claim 13, wherein: The growth starting point is not in contact with the growth inhibition film, or is in contact with a portion where the growth inhibition film is locally thinned.

15. The semiconductor substrate according to claim 13, wherein A corner where the upper surface and the side surface of the first raised portion intersect is included in the growth starting point.

16. The semiconductor substrate according to claim 15, wherein The corner is located above the growth inhibition region.

17. The semiconductor substrate according to claim 2, wherein: The first base includes pores.

18. The semiconductor substrate according to claim 2, wherein: The growth inhibiting film is a silicon nitride film.

19. The semiconductor substrate according to any one of claims 1 to 18, wherein The first direction is the <11-20> direction, The upper surface of the first raised portion is a polar surface. The side surface of the first raised portion is a semipolar surface or a nonpolar surface.

20. The semiconductor substrate according to any one of claims 1 to 19, wherein The growth suppression region and the first seed crystal region each have a shape whose longitudinal direction is a second direction perpendicular to the first direction.

21. The semiconductor substrate according to claim 20, wherein: The first wing portion is divided into a plurality of portions arranged side by side in the second direction.

22. The semiconductor substrate according to any one of claims 1 to 21, wherein The template substrate has: a main substrate having a lattice constant different from that of the first semiconductor portion; and A seed crystal portion including the first seed crystal region.

23. The semiconductor substrate according to claim 22, wherein: The main substrate is a silicon substrate, a sapphire substrate or a silicon carbide substrate, and the nitride semiconductor is a GaN-based semiconductor.

24. The semiconductor substrate according to claim 22 or 23, wherein: The seed crystal portion is not disposed under the growth inhibition region.

25. The semiconductor substrate according to any one of claims 22 to 24, wherein The seed crystal portion contains a nitride semiconductor, and the nitride semiconductor contains 2×10 18 / cm 3 The above argon or oxygen as impurities.

26. The semiconductor substrate according to claim 6, wherein: The thickness of the mask portion is 50 nm or less.

27. The semiconductor substrate according to claim 6, wherein: The growth inhibiting film is thinner than the mask portion.

28. The semiconductor substrate according to claim 2, wherein: The deviation between the c-axis direction of the first base portion and the c-axis direction of the wing tip is 0.2 degrees or less.

29. The semiconductor substrate according to any one of claims 1 to 28, wherein The semiconductor substrate includes an upper layer portion located above the first semiconductor portion and including an active layer and a p-type layer.

30. The semiconductor substrate according to any one of claims 1 to 29, wherein The threading dislocation density in the first base portion and the threading dislocation density in the first wing portion are 5×10 6 〔pcs / cm 2 〕the following.

31. The semiconductor substrate according to any one of claims 1 to 30, wherein The first semiconductor portion includes two first wing portions forming a pair extending from the first base portion in a first direction and in an opposite direction thereof.

32. The semiconductor wafer according to any one of claims 1 to 21, wherein The template substrate comprises a main substrate and a base layer. In the first seed crystal region, the base layer is set to be unmodified, In the growth inhibition region, the base layer is modified.

33. The semiconductor wafer according to any one of claims 1 to 21, wherein The template substrate comprises: a buffer layer; and a seed crystal portion partially located on the buffer layer and including the first seed crystal region, A region of the buffer layer that does not overlap with the seed crystal portion functions as a growth suppression region.

34. A method for manufacturing a semiconductor substrate, comprising: A step of preparing a template substrate including a growth inhibition region and a first seed crystal region arranged side by side in a first direction; forming a first raised portion which is located above the growth suppression region and includes a nitride semiconductor and extends from the first seed crystal region to the upper side of the growth suppression region; forming a growth inhibiting film in contact with the first protrusion; and The step of forming a first base portion located above the first raised portion and a first wing portion connected to the first base portion, separated from the growth suppression region and located on the gap to each include a nitride semiconductor.

35. The method for manufacturing a semiconductor substrate according to claim 34, wherein: The first base portion and the first wing portion are formed by taking the corner where the upper surface and the side surface of the first raised portion intersect as a growth starting point.

36. The method for manufacturing a semiconductor substrate according to claim 34 or 35, wherein: The first protrusion, the growth inhibiting film, the first base, and the first wing are successively formed using an MOCVD apparatus.

37. The method for manufacturing a semiconductor substrate according to claim 36, wherein: The first raised portion includes a GaN-based semiconductor. The growth inhibiting film is silicon nitride, The first raised portion is formed by supplying a raw material that serves as a gallium source and a raw material that serves as a nitrogen source, The growth inhibiting film is formed by stopping the supply of the raw material serving as the gallium source and supplying a silicon-based material while maintaining the supply of the raw material serving as the nitrogen source.

38. The method for manufacturing a semiconductor substrate according to claim 37, wherein: The first base portion and the first wing portion include GaN-based semiconductors. The first base portion and the first wing portion are formed by stopping the supply of the silicon-based material and supplying the raw material serving as the gallium source while maintaining the supply of the raw material serving as the nitrogen source.

39. The method for manufacturing a semiconductor substrate according to any one of claims 34 to 38, wherein: The template substrate includes: a second seed crystal region adjacent to the first seed crystal region across the growth suppression region; A second raised portion extending from the second seed crystal region to a position above the growth inhibition region, a second base portion located above the second raised portion, and a second wing portion connected to the second base portion, separated from the growth inhibition region and located on the gap are formed to each include a nitride semiconductor, Before the first wing portion and the second wing portion growing in a direction approaching the first wing portion meet, the growth of the first wing portion and the second wing portion is stopped.

40. The method for manufacturing a semiconductor substrate according to any one of claims 34 to 39, wherein: The template substrate comprises: a seed crystal portion including the first seed crystal region; The seed crystal portion is formed by a sputtering method.

41. A method for manufacturing a semiconductor device, comprising: A step of preparing a semiconductor substrate according to any one of claims 1 to 33; forming an upper layer portion above the first wing portion; and A step of peeling the first wing portion from the template substrate while the first wing portion and the upper layer portion are held on a transfer substrate.

42. The method for manufacturing a semiconductor device according to claim 41, wherein: The first wing portion is peeled off from the template substrate by cleaving the boundary between the first base portion and the first raised portion.

Images