Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus

Abstract

Provided is a semiconductor device having good electrical characteristics. A semiconductor device includes a transistor, a first interlayer insulating layer, and a second interlayer insulating layer on the first interlayer insulating layer. The transistor includes a first conductive layer serving as one of a source electrode and a drain electrode and a second conductive layer serving as the other of the source electrode and the drain electrode, with first and second interlayer insulating layers disposed between the first conductive layer and the second conductive layer. An opening that reaches the first conductive layer is provided in the first and second interlayer insulating layers and the second conductive layer, and a semiconductor layer, a first gate insulating layer, and a first gate electrode are provided in this order so as to have a region located inside the opening. A second gate electrode is provided between the first interlayer insulating layer and the second interlayer insulating layer so as to cover a side surface of the semiconductor layer. The second gate electrode includes an oxide region having a region in contact with the semiconductor layer. The oxide region is used as a second gate insulating layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a storage device and a method for manufacturing a storage device. Another embodiment of the present invention relates to a transistor and a method for manufacturing a transistor. Another embodiment of the present invention relates to an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), a driving method of the above-mentioned device, and a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.) and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, sometimes storage devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, such as using large-scale integrated circuits (LSI: Large Scale Integration) for semiconductor devices. For example, central processing units (CPU: Central Processing Unit) and memories are used in semiconductor devices. The CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memories) formed by processing a semiconductor wafer to form a chip and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as CPUs and memories are mounted on circuit boards such as printed circuits and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and display devices. As a semiconductor thin film that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor and can retain stored content for a long time.

[0008] In addition, in recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor and a second transistor using an oxide semiconductor, thereby increasing the density of the integrated circuit.

[0009] Furthermore, if a vertical transistor can be realized, the density of integrated circuits can be increased. For example, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered by a gate electrode via a gate insulating layer.

[0010] [Prior technical literature]

[0011] [Patent Document]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 2012 / 257187

[0013] [Patent Document 2] Japanese Patent Application Publication No. 2011 / 151383

[0014] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0015] [Patent Document 4] Japanese Patent Application Publication No. 2013 / 211537

[0016] [Non-patent literature]

[0017] [Non-patent document 1] M. Oota et.al, "3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm", IEDM Tech.Dig., 2019, pp.50-53 Summary of the invention

[0018] Technical problem to be solved by the invention

[0019] The threshold voltage of a transistor affects the operation of the transistor. For example, when the threshold voltage of the transistor is low in an n-channel transistor, the transistor tends to have a normally-on characteristic.

[0020] One of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device capable of controlling the threshold voltage of a transistor. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device driven at high speed. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device capable of miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a small semiconductor device or storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a large-capacity storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or storage device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide an inexpensive semiconductor device or storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with a large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with a small off-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, storage device or transistor.

[0021] One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device capable of controlling the threshold voltage of a transistor. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device having good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device having high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device that can be driven at high speed. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device that can be miniaturized or highly integrated. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a small semiconductor device or a method for manufacturing a storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a large-capacity storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device having low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a storage device having high yield. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a transistor having a large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a transistor having a small off-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a transistor having good electrical characteristics. Furthermore, one of the objects of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device, a method for manufacturing a memory device, or a method for manufacturing a transistor.

[0022] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not necessarily achieve all of the above purposes. In addition, purposes other than the above can be extracted from the description of the specification, drawings, and claims.

[0023] Solutions to technical problems

[0024] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer and a second insulating layer, wherein the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer and a third insulating layer, the first insulating layer is arranged on the first conductive layer, the second conductive layer is arranged on the first insulating layer, the second insulating layer is arranged on the second conductive layer, and the third conductive layer is arranged on the second insulating layer, the first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer are provided with openings reaching the first conductive layer, the second conductive layer is provided with an oxide region including a side surface in the opening, the semiconductor layer is arranged in a manner having a region located inside the opening, the semiconductor layer has a region in contact with the first conductive layer, a region in contact with the oxide region and a region in contact with the third conductive layer, the third insulating layer is arranged on the semiconductor layer in a manner having a region located inside the opening, and the fourth conductive layer is arranged in a manner having a region located inside the opening and having a region opposite to the semiconductor layer with the third insulating layer sandwiched therebetween.

[0025] In the above embodiment, the oxide region may include an oxide of a material included in the second conductive layer.

[0026] In the above aspect, the second conductive layer and the fourth conductive layer may have a region sandwiching a channel formation region of the semiconductor layer inside the opening.

[0027] In the above embodiment, the following structure may be included: the first conductive layer includes a first layer and a second layer, the second layer is provided on the first layer, and the semiconductor layer has a region in contact with a top surface of the first layer and a region in contact with a side surface of the second layer.

[0028] In addition, in the above method, the following structure may also be included: the first insulating layer includes a first layer, a second layer and a third layer, the second insulating layer includes a fourth layer, a fifth layer and a sixth layer, the second layer is arranged on the first layer, the third layer is arranged on the second layer, the fifth layer is arranged on the fourth layer, the sixth layer is arranged on the fifth layer, and the first layer, the third layer, the fourth layer and the sixth layer contain nitrogen.

[0029] In the above embodiment, the second layer and the fifth layer may contain oxygen.

[0030] Furthermore, an electronic device including the semiconductor device and the camera according to one embodiment of the present invention is also one embodiment of the present invention.

[0031] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; forming a third conductive layer on the second insulating layer; forming an opening reaching the first conductive layer in the first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer; forming an oxide region in the second conductive layer by oxidizing the side surfaces in the opening of the second conductive layer; forming a semiconductor layer in a manner having a region located inside the opening and having a region in contact with the first conductive layer, a region in contact with the oxide region and a region in contact with the third conductive layer; forming a third insulating layer on the semiconductor layer in a manner having a region located inside the opening; and forming a fourth conductive layer in a manner having a region located inside the opening and having a region opposite to the semiconductor layer with the third insulating layer sandwiched therebetween.

[0032] In the above embodiment, the oxidation treatment may be performed by microwave treatment in an oxygen-containing atmosphere.

[0033] In addition, the above method may also include the following steps: forming a first layer and a second layer on the first layer as a first conductive layer, and after forming a third conductive layer, forming an opening reaching the second layer in the first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer, and removing the area of ​​the second layer overlapping with the opening after oxidation treatment and before forming a semiconductor layer.

[0034] In the above embodiment, the side surface of the opening of the second conductive layer may be processed after the opening is formed and before the oxide region is formed.

[0035] In the above-mentioned embodiment, processing may be performed by isotropic etching.

[0036] In addition, the above method may also include the following steps: after forming the opening and before forming the oxide region, forming a fourth insulating layer in the opening having an area in contact with the side surface of the second conductive layer and oxidizing the fourth insulating layer to remove the fourth insulating layer to form a semiconductor layer.

[0037] In addition, the above method may also include the following steps: as a first insulating layer, a first layer, a second layer on the first layer, and a third layer on the second layer are formed; as a second insulating layer, a fourth layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer are formed; the fourth insulating layer is formed in a manner having an area in contact with the top surface of the sixth layer; the fourth insulating layer contains oxygen, and the sixth layer contains nitrogen.

[0038] In the above embodiment, the first layer, the third layer, and the fourth layer may contain nitrogen.

[0039] In the above embodiment, the second layer and the fifth layer may contain oxygen.

[0040] In addition, in the above-mentioned manner, the semiconductor layer may also include a metal oxide. The metal oxide may also include one or more selected from indium, zinc and element M, and element M may also be one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony.

[0041] Effects of the Invention

[0042] According to one embodiment of the present invention, a semiconductor device or storage device capable of controlling the threshold voltage of a transistor can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device driven at high speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a small-sized semiconductor device or storage device can be provided. In addition, according to one embodiment of the present invention, a large-capacity storage device can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or storage device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a cheap semiconductor device or storage device can be provided. In addition, according to one embodiment of the present invention, a transistor with large on-state current can be provided. In addition, according to one embodiment of the present invention, a transistor with small off-state current can be provided. In addition, according to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device, storage device or transistor can be provided.

[0043] According to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device capable of controlling the threshold voltage of a transistor can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device with high reliability can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device that can be driven at high speed can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device that can be miniaturized or highly integrated can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a small semiconductor device or a method for manufacturing a storage device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a large-capacity storage device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a method for manufacturing a storage device with high yield can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a transistor with large on-state current can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a transistor with small off-state current can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a transistor with good electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device, a method for manufacturing a memory device, or a method for manufacturing a transistor can be provided.

[0044] Note that the description of these effects does not prevent the existence of other effects. One mode of the invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a perspective view showing a structural example of a semiconductor device.

[0046] Figure 2A1 and Figure 2A2 is a plan view showing a structural example of a semiconductor device. Figure 2B , Figure 2C and Figure 2D is a cross-sectional view showing a structural example of a semiconductor device.

[0047] Figure 3A is a cross-sectional view showing a structural example of a semiconductor device. Figure 3B is a plan view showing a structural example of a semiconductor device.

[0048] FIG. 4A to FIG. 4Cis a cross-sectional view showing a structural example of a semiconductor device.

[0049] FIG. 5A to FIG. 5D is a cross-sectional view showing a structural example of a semiconductor device.

[0050] FIG. 6A to FIG. 6D is a cross-sectional view showing a structural example of a semiconductor device.

[0051] Fig.7A1 and Fig.7A2 is a plan view showing a structural example of a semiconductor device. Figure 7B and Figure 7C is a cross-sectional view showing a structural example of a semiconductor device.

[0052] FIG. 8A to FIG. 8C is a cross-sectional view showing a structural example of a semiconductor device.

[0053] 9A to 9D is a cross-sectional view showing a structural example of a semiconductor device.

[0054] Fig. 10A and Fig. 10B is a plan view showing a structural example of a semiconductor device.

[0055] Fig.11A is a plan view showing a structural example of a semiconductor device. Fig. 11B and Fig. 11C is a cross-sectional view showing a structural example of a semiconductor device.

[0056] Fig. 12A is a plan view showing a structural example of a semiconductor device. Fig. 12B and Fig. 12C is a cross-sectional view showing a structural example of a semiconductor device.

[0057] Fig.13A is a plan view showing an example of a method for manufacturing a semiconductor device. Fig. 13B and Fig. 13C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0058] Fig.14A is a plan view showing an example of a method for manufacturing a semiconductor device. Fig. 14B and Fig. 14C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0059] Fig.15A1 and Fig.15A2 is a plan view showing an example of a method for manufacturing a semiconductor device. Fig. 15B and Fig. 15C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0060] Fig.16A is a plan view showing an example of a method for manufacturing a semiconductor device. Fig. 16B and Fig. 16C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0061] FIG. 17A to FIG. 17F is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0062] Fig.18A1 and Fig.18A2 is a plan view showing an example of a method for manufacturing a semiconductor device. Fig.18B and Fig.18C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0063] Fig.19A1 and Fig.19A2 is a plan view showing an example of a method for manufacturing a semiconductor device. Fig.19B and Fig.19C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0064] Fig.20A1 and Fig.20A2 is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 20B to FIG. 20E is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0065] Fig.21A is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 21B to FIG. 21E is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0066] Fig.22A1 and Fig.22A2 is a plan view showing a structural example of a storage device. Fig. 22B and Fig. 22C is a cross-sectional view showing a structural example of a storage device. Fig.22D1 and Fig.22D2 is a circuit diagram showing a structural example of a storage device.

[0067] Fig.23A is a plan view showing a structural example of a storage device. Fig. 23B and Fig.23C is a cross-sectional view showing a structural example of a storage device.

[0068] Fig.24A is a plan view showing a structural example of a storage device. Fig. 24B is a cross-sectional view showing a structural example of a storage device.

[0069] Fig.25A is a plan view showing a structural example of a storage device. Fig.25Bis a cross-sectional view showing a structural example of a storage device.

[0070] Fig.26A is a plan view showing a structural example of a storage device. Fig.26B is a cross-sectional view showing a structural example of a storage device.

[0071] Fig. 27 is a cross-sectional view showing a structural example of a storage device.

[0072] FIG. 28A to FIG. 28C is a plan view showing a structural example of a storage device.

[0073] FIG. 29A to FIG. 29C is a plan view showing a structural example of a storage device.

[0074] Fig.30 is a block diagram showing a structural example of a storage device.

[0075] Fig.31A is a schematic diagram showing a structural example of a storage device. Fig.31B is a circuit diagram showing a structural example of a storage device.

[0076] Fig.32A and Fig.32B is a schematic diagram showing a structural example of a storage device.

[0077] Fig.33 is a circuit diagram showing a structural example of a storage device.

[0078] Fig.34A and Fig.34B FIG. 1 is a diagram showing an example of a chip on which a storage device is mounted.

[0079] Fig.35A and Fig.35B is a diagram showing an example of an electronic device.

[0080] FIG. 36A to FIG. 36E is a schematic diagram showing an example of a storage device.

[0081] FIG. 37A to FIG. 37H is a diagram showing an example of an electronic device.

[0082] Fig.38 is a diagram showing an example of space equipment.

[0083] Fig.39A is a cross-sectional view showing the structure of the sample. Fig.39B is a schematic diagram showing a measurement system.

[0084] FIG. 40A to FIG. 40C is a cross-sectional STEM image of the sample.

[0085] FIG. 41A to FIG. 41C is a graph showing current-voltage characteristics. DETAILED DESCRIPTION

[0086] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0087] Note that in the invention structure described below, the same symbols are used in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0088] In addition, for ease of understanding, the positions, sizes, and ranges of the components shown in the drawings sometimes do not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to etching or other processes, but this is sometimes not reflected in the drawings for ease of understanding.

[0089] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, process order or stacking order). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0090] A transistor is a type of semiconductor element and can realize functions of amplifying current or voltage, controlling switching operations of conduction or non-conduction, etc. The transistor in this specification includes IGFET (Insulated Gate Field Effect Transistor) and thin film transistor (TFT: Thin Film Transistor).

[0091] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., a channel formation region refers to a region where current mainly flows.

[0092] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used or the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be interchanged.

[0093] Note that the impurities of a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In addition, water sometimes acts as an impurity. In addition, for example, the mixing of impurities sometimes causes oxygen vacancies (also called V) in oxide semiconductors to O )’s formation.

[0094] Note that in this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen in its composition, and an oxynitride refers to a material containing more nitrogen than oxygen in its composition.

[0095] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the film can be analyzed by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (for example, 0.5 atomic% or more or 1 atomic%). On the other hand, SIMS is suitable when the content of the target element is low (for example, 0.5 atomic% or less or 1 atomic%). When comparing the element contents, it is more preferable to use a composite analysis using both SIMS and XPS analysis methods.

[0096] In addition, in this specification, etc., the words "film" and "layer" can be interchanged depending on the situation. For example, sometimes "conductive layer" can be interchanged with "conductive film" and "conductive film" can be interchanged with "conductive layer". Also, for example, sometimes "insulating film" can be interchanged with "insulating layer" and "insulating layer" can be interchanged with "insulating film". Also, for example, sometimes "semiconductor film" can be interchanged with "semiconductor layer" and "semiconductor layer" can be interchanged with "semiconductor film".

[0097] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0098] In addition, in this specification, etc., "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be called "potential". The ground potential does not necessarily mean 0V. In addition, the potential is relative, and changes in the reference potential, such as the potential supplied to the wiring, the potential applied to the circuit, and the potential output from the circuit, also occur.

[0099] In this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes switching elements such as transistors, resistor elements, coils, capacitors, and other elements having various functions in addition to electrodes and wiring.

[0100] In addition, in this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also called the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0101] In this specification, the top surface shape of a component refers to the outline shape of the component when viewed from a plane. In addition, the plane view refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of the support (such as a substrate) on which the component is formed.

[0102] In this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the formed surface. For example, it is preferable to have a region in which the angle (also referred to as a taper angle) formed by the inclined side surface and the substrate surface or the formed surface is less than 90 degrees. Note that the side surface, substrate surface, and formed surface of a constituent element do not necessarily have to be completely flat, and may also be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0103] In this specification and the like, when there is a description that A is in contact with B, at least a portion of A is in contact with B. Therefore, for example, it can be alternatively stated that A has a region in contact with B.

[0104] In this specification and the like, when there is a description that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be alternatively described that A includes a region located on B.

[0105] In this specification and the like, when there is a description that A covers B, at least a portion of A covers B. Therefore, for example, it can be alternatively described that A includes a region covering B.

[0106] In this specification and the like, when there is a description that A overlaps with B, at least a portion of A overlaps with B. Therefore, for example, it can be alternatively stated that A includes a region overlapping with B.

[0107] In addition, in this specification, for the sake of convenience, words and phrases indicating configuration such as "upper", "lower", "left", and "right" are used to describe the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in the specification are not limited, and the words and phrases can be appropriately changed according to the situation.

[0108] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified, for example, into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen are sometimes collectively referred to as metal oxides. In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0109] (Implementation Method 1)

[0110] In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device which is one embodiment of the present invention are described with reference to the drawings.

[0111] One embodiment of the present invention relates to a semiconductor device including a transistor. The transistor may be a transistor in which a semiconductor layer is provided inside an opening in a first interlayer insulating layer formed on a substrate and a second interlayer insulating layer on the first interlayer insulating layer. By adopting such a structure, the channel length direction of the transistor can be along the side of the first and second interlayer insulating layers in the opening. Thus, the channel length is not affected by the performance of an exposure device used when manufacturing the transistor, so the channel length can be made smaller than the limiting resolution of the exposure device. Therefore, the on-state current of the transistor is increased, so that the semiconductor device can be driven at high speed.

[0112] Here, as one of the source electrode and the drain electrode of the transistor, a first conductive layer disposed under the opening is used. Specifically, first and second interlayer insulating layers are disposed on the first conductive layer, and openings are disposed in the first and second interlayer insulating layers in a manner that reaches the first conductive layer. In addition, as the other of the source electrode and the drain electrode of the transistor, a second conductive layer disposed on the second interlayer insulating layer and including an opening that overlaps with the above-mentioned opening is used. Furthermore, a semiconductor layer is disposed in a manner that includes an area in contact with the first conductive layer and an area in contact with the second conductive layer. In addition, a first gate insulating layer is disposed on the semiconductor layer, and a first gate electrode is disposed on the first gate insulating layer.

[0113] On the other hand, in an n-channel transistor, when the channel length of the transistor is reduced, the threshold voltage of the transistor becomes smaller, and sometimes, for example, becomes a normally-on characteristic. Therefore, a second gate electrode is provided in the transistor included in the semiconductor device of one embodiment of the present invention. Thus, for example, the threshold voltage of the transistor can be controlled. Therefore, for example, by making the threshold voltage of the transistor higher than when the second gate electrode is not provided in the transistor, the transistor can be suppressed from becoming a normally-on characteristic. In other words, the transistor can be made to become a normally-off characteristic. Therefore, a semiconductor device with good electrical characteristics can be provided.

[0114] In this specification, etc., a transistor having a normally-on characteristic refers to a state in which a channel exists in the semiconductor layer even if a potential is not supplied to the gate of the transistor, and current flows between the source and drain of the transistor. In addition, a transistor having a normally-off characteristic refers to a state in which a current does not flow between the source and drain of the transistor when a potential is not supplied to the gate of the transistor. Here, it can be said that a transistor having a normally-on characteristic refers to a state in which, in the case where the transistor includes a first gate electrode and a second gate electrode, current flows between the source and drain of the transistor even if a potential is not supplied to the first gate electrode having the function of controlling the magnitude of the current flowing through the channel forming region of the semiconductor layer. In addition, a transistor having a normally-off characteristic refers to a state in which a current does not flow between the source and drain of the transistor when a potential is not supplied to the first gate electrode.

[0115] In a semiconductor device of one embodiment of the present invention, a second gate electrode is disposed between a first interlayer insulating layer and a second interlayer insulating layer. The second gate electrode includes an opening portion overlapping with an opening portion disposed in the first and second interlayer insulating layers, and a side surface in the opening portion and an area near the opening portion are oxide regions. The oxide region is a region whose resistivity is higher than that of the region other than the oxide region of the second gate electrode and has insulating properties. In addition, the oxide region covers a region of the semiconductor layer located inside the opening portion of the second gate electrode. As described above, the oxide region of the second gate electrode is used as a second gate insulating layer.

[0116] When manufacturing a transistor included in a semiconductor device of one embodiment of the present invention, first, a first conductive layer on a substrate, a first interlayer insulating layer on the first conductive layer, a second gate electrode on the first interlayer insulating layer, a second interlayer insulating layer on the second gate electrode, and a second conductive layer on the second interlayer insulating layer are sequentially formed. Next, an opening reaching the first conductive layer is formed in the first interlayer insulating layer, the second gate electrode, the second interlayer insulating layer, and the second conductive layer. Then, an oxidation treatment is performed on the side surface in the opening of the second gate electrode. As an oxidation treatment, microwave treatment in an oxygen-containing atmosphere can be cited, for example. By the oxidation treatment, an oxide region is formed in the second gate electrode, and the oxide region is used as a second gate insulating layer.

[0117] In this specification, etc., microwave treatment refers to treatment using a device including a power supply that generates high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves with a frequency of more than 300 MHz and less than 300 GHz. Microwave treatment can also be referred to as microwave-excited high-density plasma treatment.

[0118] Next, a semiconductor layer, a first gate insulating layer, and a first gate electrode are sequentially formed so as to have a region located inside the opening. As described above, a transistor included in a semiconductor device according to one embodiment of the present invention can be manufactured.

[0119] <Structural Example 1 of Semiconductor Device>

[0120] Figure 1 1 is a perspective view showing a structural example of a semiconductor device according to one embodiment of the present invention, and shows a structural example of a transistor 100 included in the semiconductor device. Figure 2A1 is a diagram showing the Z direction, specifically, the top surface of the Z direction. Figure 1 The plan view of the structure example when Figure 2A1 In the drawings, some components such as an insulating layer are omitted for clarity. Some components are also omitted in the plan views shown below. Figure 2B yes Figure 2A1 The cross-sectional view along the dotted line A1-A2 shown in FIG. Figure 2C yes Figure 2A1 A cross-sectional view along the dashed line A3-A4 is shown.

[0121] exist Figure 1 , Figure 2A1 , Figure 2B as well as Figure 2C In FIG. 1 , the X direction, the Y direction, and the Z direction are shown as coordinate axes. Figure 2A1 , Figure 2B as well as Figure 2C In the figure, the direction of the dotted line A1-A2 is the X direction, the direction of the dotted line A3-A4 is the Y direction, and the direction perpendicular to the XY plane is the Z direction. The X direction, the Y direction, and the Z direction may be directions that intersect each other, and specifically may be directions that are orthogonal to each other. Note that the definitions of the X direction, the Y direction, and the Z direction are also shown in terms of coordinate axes in the following figures, but sometimes the definitions are different from Figure 1 , Figure 2A1 , Figure 2B as well as Figure 2C The definitions in Figure 1 , Figure 2A1 , Figure 2B as well as Figure 2C In the figure, the X direction, the Y direction, and the Z direction are indicated by arrows, but the positive direction and the negative direction are not distinguished unless otherwise specified. The same is true in the following drawings.

[0122] In this specification, one of the X direction, the Y direction, and the Z direction may be referred to as a "first direction". In addition, the other one may be referred to as a "second direction". Furthermore, the remaining one may be referred to as a "third direction".

[0123] A semiconductor device according to one embodiment of the present invention includes an insulating layer 101 on a substrate (not shown) and a transistor 100 on the insulating layer 101. In addition, a semiconductor device according to one embodiment of the present invention includes an insulating layer 103 on the insulating layer 101, an insulating layer 104 on the insulating layer 103, and an insulating layer 107 on the insulating layer 104 and the transistor 100. Here, the insulating layer 101, the insulating layer 103, and the insulating layer 104 are used as interlayer insulating layers. The layers used as interlayer insulating layers including these insulating layers are preferably planarized. Note that the layers used as interlayer insulating layers may not be planarized.

[0124] The transistor 100 includes a conductive layer 111, a conductive layer 112, a semiconductor layer 113, an insulating layer 105, a conductive layer 115, and a conductive layer 117. Figure 2A2 Shown omitted Figure 2A1 A plan view of the conductive layer 115, the semiconductor layer 113, and the conductive layer 112 among the components shown. Figure 2A1 In FIG. 1 , an example is shown in which the conductive layer 115 extends in the X direction and the conductive layer 112 extends in the Y direction. Figure 2A1 and Figure 2A2 , an example in which the conductive layer 117 extends in the Y direction is shown.

[0125] The insulating layer 101, the insulating layer 103, the insulating layer 104, the insulating layer 105, and the insulating layer 107 can use a single layer or a stack of insulators described in [Insulator] to be described later. The conductive layer 111, the conductive layer 112, the conductive layer 115, and the conductive layer 117 can use a single layer or a stack of conductors described in [Conductor] to be described later. The semiconductor layer 113 can use a single layer or a stack of metal oxides described in [Metal Oxide] to be described later. In addition, the semiconductor layer 113 can use a single layer or a stack of materials such as silicon described in [Other Semiconductor Materials] to be described later.

[0126] In this specification and the like, a transistor using a metal oxide for a channel formation region of a semiconductor layer is referred to as an OS transistor. In addition, a transistor using silicon for a channel formation region of a semiconductor layer is referred to as a Si transistor. In the case where a metal oxide is used for the semiconductor layer 113, the transistor 100 may be an OS transistor. In the case where silicon is used for the semiconductor layer 113, the transistor 100 may be a Si transistor.

[0127] The conductive layer 111 is used as one of a source electrode and a drain electrode of the transistor 100. The conductive layer 112 is used as the other of the source electrode and the drain electrode of the transistor 100. The insulating layer 105 is used as a gate insulating layer of the transistor 100. The conductive layer 115 and the conductive layer 117 are used as a gate electrode of the transistor 100.

[0128] Conductive layer 111 is provided on insulating layer 101, insulating layer 103 is provided on insulating layer 101 and conductive layer 111, conductive layer 117 is provided on insulating layer 103, insulating layer 104 is provided on insulating layer 103 and conductive layer 117, and conductive layer 112 is provided on insulating layer 104. Conductive layer 111 and conductive layer 117 may have a region overlapping each other via insulating layer 103. Conductive layer 117 and conductive layer 112 may have a region overlapping each other via insulating layer 104. As described above, conductive layer 111 and conductive layer 112 may have a region overlapping each other via insulating layer 103 and insulating layer 104.

[0129] The insulating layer 103, the conductive layer 117, the insulating layer 104, and the conductive layer 112 include an opening 121 that reaches the conductive layer 111. The opening 121 can be formed by processing a portion of the insulating layer 103, the conductive layer 117, the insulating layer 104, and the conductive layer 112, for example, by etching after forming them. In particular, processing by dry etching is suitable for fine processing and is therefore preferred.

[0130] exist Figure 2A1 and Figure 2A2 , an example is shown in which the shape of the opening 121 when viewed from a plane is circular. By making the planar shape of the opening 121 circular, the processing accuracy when forming the opening 121 can be improved, so that the opening 121 of a fine size can be formed. Note that in this specification, etc., a circle is not limited to a perfect circle. In addition, the planar shape of the opening 121 can be, for example, an ellipse.

[0131] exist Figure 1 , Figure 2A1 as well as Figure 2B , an example is shown in which the side end of the conductive layer 111 is located outside the side end of the conductive layer 117 that does not face the opening 121, and the side end of the conductive layer 117 that does not face the opening 121 is located outside the side end of the conductive layer 112 that does not face the opening 121. That is, in Figure 1 , Figure 2A1 as well as Figure 2B, the following example is shown: in the X direction, the side end of the conductive layer 112 that does not face the opening 121 overlaps with the conductive layer 117 and the conductive layer 111, and the side end of the conductive layer 117 that does not face the opening 121 overlaps with the conductive layer 111, but the side end of the conductive layer 111 does not overlap with the conductive layer 112 and the conductive layer 117, and the side end of the conductive layer 117 that does not face the opening 121 does not overlap with the conductive layer 112. Here, one embodiment of the present invention is not limited to this, for example, the side end of the conductive layer 111 may be located inside the side end of the conductive layer 117 that does not face the opening 121, or may be located inside the side end of the conductive layer 112 that does not face the opening 121. In addition, the side end of the conductive layer 117 may be located inside the side end of the conductive layer 112 that does not face the opening 121.

[0132] The semiconductor layer 113 covers the opening 121 and is provided so as to have a region located inside the opening 121. The semiconductor layer 113 may have a shape along the top surface of the conductive layer 111, the side surface of the insulating layer 103, the side surface of the insulating layer 104, and the side surface and top surface of the conductive layer 112. Thus, the semiconductor layer 113 has a recessed portion at a position overlapping with the opening 121. The semiconductor layer 113 may have a region in contact with the top surface of the conductive layer 111, a region in contact with the side surface of the insulating layer 103, a region in contact with the side surface of the insulating layer 104, a region in contact with the side surface of the conductive layer 112, and a region in contact with the top surface of the conductive layer 112.

[0133] The semiconductor layer 113 preferably covers the side end portion of the conductive layer 112 on the side of the opening 121. Figure 1 , Figure 2A1 , Figure 2B as well as Figure 2C , a structure in which the side end of the semiconductor layer 113 is located on the conductive layer 112 is shown. When this structure is adopted, it can be said that the lower end of the semiconductor layer 113 is in contact with the top surface of the conductive layer 112. In addition, the side end of the semiconductor layer 113 may be located outside the side end of the conductive layer 112 in the X direction. In this case, the semiconductor layer 113 may cover the side of the conductive layer 112 that does not face the opening 121.

[0134] In this specification, the upper end portion refers to the uppermost portion of the side end portion, and the lower end portion refers to the lowermost portion of the side end portion. In other words, both the upper end portion and the lower end portion are part of the side end portion.

[0135] Note that Figure 1 , Figure 2A1 , Figure 2B as well as Figure 2C2 shows an example in which the semiconductor layer 113 is divided into island shapes in both the X direction and the Y direction. Here, the island shape refers to a state in which two or more layers formed using the same process and material are physically separated.

[0136] The insulating layer 105 covers the opening 121 and is provided in a manner having a region located inside the opening 121. The insulating layer 105 is provided on the semiconductor layer 113, the conductive layer 112, and the insulating layer 104. The insulating layer 105 may have a shape along the top surface and side surfaces of the semiconductor layer 113, the top surface and side surfaces of the conductive layer 112, and the top surface of the insulating layer 104. Since the insulating layer 105 has a shape along the top surface and side surfaces of the semiconductor layer 113, the insulating layer 105 has a recessed portion at a position overlapping with the opening 121. The insulating layer 105 may have a region in contact with the top surface of the semiconductor layer 113, a region in contact with the side surfaces of the semiconductor layer 113, a region in contact with the top surface of the conductive layer 112, a region in contact with the side surfaces of the conductive layer 112, and a region in contact with the top surface of the insulating layer 104.

[0137] The conductive layer 115 is provided on the insulating layer 105, and may have a region in contact with the top surface and the side surface of the recess of the insulating layer 105. The conductive layer 115 has a region located inside the opening 121. The conductive layer 115 and the semiconductor layer 113 have regions that are opposite to each other with the insulating layer 105 sandwiched therebetween at positions along the side walls and the bottom of the opening 121. Here, the semiconductor layer 113 may cover the side surface and the bottom surface of the conductive layer 115 via the insulating layer 105 inside the opening 121. For example, the insulating layer 105 may have a region in contact with the side surface of the semiconductor layer 113, a region in contact with the top surface of the recess of the semiconductor layer 113, a region in contact with the side surface of the conductive layer 115, and a region in contact with the bottom surface of the conductive layer 115 inside the opening 121.

[0138] As mentioned above, Figure 1 , Figure 2B as well as Figure 2C The transistor 100 shown is a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are provided inside an opening portion of an interlayer insulating layer. Thus, the channel length direction of the transistor 100 can be a direction along the side surfaces of the insulating layer 103 and the insulating layer 104 in the opening portion 121. Therefore, since the channel length is not affected by the performance of an exposure device used to manufacture the transistor 100, the channel length can be made smaller than the limiting resolution of the exposure device. Thus, the on-state current of the transistor 100 can be made large. Therefore, a semiconductor device that can be driven at high speed can be provided. Note that, for example, in Figure 2A1, an example is shown in which the entire opening portion 121 overlaps with the conductive layer 111 , the semiconductor layer 113 , and the conductive layer 115 , but a portion of the opening portion 121 may not overlap with at least one of the conductive layer 111 , the semiconductor layer 113 , and the conductive layer 115 .

[0139] like Figure 1 , Figure 2B as well as Figure 2C As shown in FIG. 1 , a portion of the conductive layer 115 is located outside the opening 121, that is, on the conductive layer 112 and the insulating layer 104. Figure 2C As shown in FIG. 1 , the side end of the conductive layer 115 is preferably located inside the side end of the semiconductor layer 113. Thus, for example, parasitic capacitance formed by the conductive layer 112, the insulating layer 105, and the conductive layer 115 can be reduced. Note that the side end of the conductive layer 115 may be located outside the side end of the semiconductor layer 113. In this case, the conductive layer 115 may cover the entire semiconductor layer 113.

[0140] In the transistor 100, the conductive layer 117 including the opening 121 is provided between the insulating layer 103 and the insulating layer 104. The insulating layer 104 may cover the top surface and the side surface of the conductive layer 117. Figure 1 , Figure 2A2 , Figure 2B as well as Figure 2C As shown, the side surface of the opening 121 of the conductive layer 117 and the area near it are oxide regions 117ox. The oxide region 117ox is a region having a higher resistivity than the conductive layer 117 and has insulating properties. Here, the oxide region 117ox has insulating properties, so the oxide region 117ox can be a region having a higher resistivity than the semiconductor layer 113. In addition, the oxide region 117ox covers the region of the semiconductor layer 113 located inside the opening 121. Specifically, the oxide region 117ox covers the region of the semiconductor layer 113 located inside the opening 121 provided in the conductive layer 117. For example, in the opening 121, the oxide region 117ox is in contact with the semiconductor layer 113. And, the region of the conductive layer 117 that is not oxidized covers the oxide region 117ox. For example, the region of the conductive layer 117 that is not oxidized does not contact the semiconductor layer 113. As described above, the conductive layer 117 is used as a gate electrode, and the oxide region 117ox is used as a gate insulating layer. In addition, the oxide region 117ox does not need to be oxidized as long as it has insulating properties. The oxide region 117ox can be alternatively referred to as a high resistance region.

[0141] In this specification and the like, the oxide region 117ox is included in the conductive layer 117, that is, the oxide region 117ox may be a part of the conductive layer 117. Note that the oxide region 117ox may not be included in the conductive layer 117.

[0142] As described above, the transistor 100 is a transistor of a dual-gate structure including two gate electrodes, and the conductive layer 115 used as the first gate electrode and the conductive layer 117 used as the second gate electrode are provided in such a manner that a region sandwiching the channel formation region of the semiconductor layer 113 is provided inside the opening 121. Here, for example, the magnitude of the current flowing through the channel formation region of the semiconductor layer 113 can be controlled according to the potential of the conductive layer 115, and the threshold voltage of the transistor 100 can be controlled according to the potential of the conductive layer 117.

[0143] As described above, the channel length of transistor 100 is small, for example, smaller than the limiting resolution of the exposure device. In this case, when transistor 100 is an n-channel transistor, the threshold voltage of transistor 100 becomes small, for example, sometimes transistor 100 becomes a normally-on characteristic. Thus, by controlling the potential of conductive layer 117 to control the threshold voltage of transistor 100, specifically, for example, by increasing the threshold voltage of transistor 100 compared to the case where conductive layer 117 is not provided in transistor 100, transistor 100 can be controlled to become a normally-on characteristic. In other words, transistor 100 can be made to become a normally-off characteristic. In addition, by controlling the threshold voltage of transistor 100, the threshold voltage of transistor 100 can be reduced and the on-state current of transistor 100 can be increased. In addition, by controlling the threshold voltage of transistor 100 according to the potential of conductive layer 117, the non-uniformity of the electrical characteristics of each transistor 100 can be reduced, specifically, the non-uniformity of the threshold voltage of each transistor 100 can be reduced. As described above, a semiconductor device with good electrical characteristics can be provided.

[0144] Note that when the transistor 100 is a channel transistor, one embodiment of the present invention can be applied by, for example, appropriately reversing the magnitude relationship between various potentials and threshold voltages described in this specification to that in the case where the transistor 100 is an n-channel transistor.

[0145] In this specification and the like, the first gate electrode may be referred to as a front gate electrode and the second gate electrode may be referred to as a back gate electrode. In addition, when the conductive layer 115 is referred to as a first gate electrode and the conductive layer 117 is referred to as a second gate electrode, the insulating layer 105 may be referred to as a first gate insulating layer and the oxide region 117ox may be referred to as a second gate insulating layer. Note that the first gate electrode and the second gate electrode may be switched. For example, the conductive layer 115 may be used as a second gate electrode and the conductive layer 117 may be used as a first gate electrode. In this case, the insulating layer 105 may be referred to as a second gate insulating layer and the insulating layer 106 may be referred to as a first gate insulating layer.

[0146] For example, a constant potential may be supplied to the conductive layer 117. For example, by supplying a ground potential or a negative potential to the conductive layer 117, the transistor 100 may be suppressed from becoming a normally-on characteristic. In addition, the conductive layer 117 may be supplied with a potential that is the same as the potential of the conductive layer 115. Thus, for example, the on-state current of the transistor 100 may be increased. In addition, in the case where the transistor 100 is an n-channel transistor, for example, the potential supplied to the conductive layer 117 when the transistor 100 is turned on may be higher than the potential supplied to the conductive layer 117 when the transistor 100 is turned off. For example, a positive potential may be supplied to the conductive layer 117 when the transistor 100 is turned on, and a ground potential or a negative potential may be supplied to the conductive layer 117 when the transistor 100 is turned off.

[0147] A material having insulating properties, for example, is used for the conductive layer 117, whose resistivity increases through a chemical reaction such as oxidation. For example, a metal or a metal nitride can be used as the conductive layer 117. Examples of materials that can be used for the conductive layer 117 include tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, and tungsten.

[0148] The oxide region 117ox includes an oxide of a material included in the conductive layer 117. For example, when tantalum nitride is used as the conductive layer 117, the oxide region 117ox includes tantalum oxide, and when titanium nitride is used as the conductive layer 117, the oxide region 117ox includes titanium oxide. Note that the oxide region 117ox may include nitrogen, for example.

[0149] Here, the electric field from the conductive layer 117 may not reach the region of the semiconductor layer 113 that is not covered by the conductive layer 117. When the resistivity of the region of the semiconductor layer 113 that is not reached by the electric field from the conductive layer 117 is lower than the resistivity of the region that can be reached by the electric field from the conductive layer 117, for example, the on-state current of the transistor 100 can be increased, which is preferable. For example, the resistivity of the region in contact with the insulating layer 103 and the region in contact with the insulating layer 104 is preferably lower than the resistivity of the region in contact with the oxide region 117ox.

[0150] For example, when an insulator containing nitrogen is used as the insulating layer 103 and the insulating layer 104, nitrogen can be supplied to the semiconductor layer 113. Thus, when a metal oxide is used as the semiconductor layer 113, electrons as carriers are sometimes generated in the semiconductor layer 113 to increase the carrier concentration. Therefore, for example, the resistivity of the region in contact with the insulating layer 103 and the region in contact with the insulating layer 104 can be lower than the resistivity of the region in contact with the oxide region 117ox. As an insulator containing nitrogen, for example, silicon nitride can be cited. In addition, as the insulating layer 103 and the insulating layer 104, for example, silicon nitride oxide or aluminum nitride can also be used.

[0151] In addition, an insulator containing oxygen can also be used as the insulating layer 103 and the insulating layer 104. In this case, the insulating layer 103 and the insulating layer 104 arranged near the channel formation region of the semiconductor layer 113 preferably contain oxygen (hereinafter sometimes referred to as excess oxygen) released by heating. By heat treating the insulating layer 103 and the insulating layer 104 containing excess oxygen, oxygen can be supplied from the insulating layer 103 and the insulating layer 104 to the channel formation region of the semiconductor layer 113, thereby reducing oxygen vacancies or hydrogen entering oxygen vacancy defects (hereinafter referred to as VoH). Therefore, the electrical characteristics of the transistor 100 can be stabilized, thereby improving reliability. As an insulator containing oxygen, for example, silicon oxide and silicon oxynitride can be cited.

[0152] Furthermore, an insulator having a function of capturing or fixing hydrogen may be used as the insulating layer 103 and the insulating layer 104 disposed near the channel formation region of the semiconductor layer 113. By adopting such a structure, hydrogen in the channel formation region of the semiconductor layer 113 can be captured or fixed (also called gettering), thereby reducing the hydrogen concentration of the semiconductor layer 113. As the insulating layer 103 and the insulating layer 104 described above, for example, magnesium oxide and aluminum oxide can be cited.

[0153] The oxide region 117ox of the conductive layer 117 can be formed by performing oxidation treatment after the opening 121 is formed in the conductive layer 112, the insulating layer 104, the conductive layer 117, and the insulating layer 103. The oxidation treatment can be, for example, microwave treatment in an oxygen-containing atmosphere.

[0154] Here, when the oxidation treatment is performed after the conductive layers 111 and 112 are formed, the oxidation treatment is performed not only on the conductive layer 117 but also on the conductive layers 111 and 112. Thus, the conductive layers 111 and 112 use a material that is less easily oxidized than the conductive layer 117 or a material that has conductivity even when oxidized. For example, a conductive material containing oxygen can be used for the conductive layers 111 and 112. For example, a single layer or a stacked layer of indium tin oxide (also called ITO), indium tin oxide to which silicon is added (also called ITSO), or indium zinc oxide (also called IZO (registered trademark)) can be used as the conductive layers 111 and 112.

[0155] The insulating layer 107 is provided over the conductive layer 115 and the insulating layer 105. The insulating layer 107 can be provided to cover the top surface and the side surfaces of the conductive layer 115. The insulating layer 107 has a function of suppressing impurities from entering the transistor 100, for example, suppressing impurities from entering the semiconductor layer 113.

[0156] exist Figure 1 , Figure 2B as well as Figure 2C , an example in which the insulating layer 105 is provided in a planar shape is shown, but one embodiment of the present invention is not limited to this. Figure 2D Shown in Figure 2C The side ends of the insulating layer 105 are aligned or substantially aligned with the side ends of the conductive layer 115. For example, by processing the insulating layer 105 using the same pattern as the conductive layer 115, the side ends of the insulating layer 105 can be aligned or substantially aligned with the side ends of the conductive layer 115.

[0157] Figure 3A yes Figure 2C The transistor 100 and its vicinity are shown in an enlarged view. Figure 3B Show Figure 3A FIG. 1 is a plan view of the transistor 100 taken along the XY plane. Note that Figure 3B Conductive layer 111 and conductive layer 117 are not shown.

[0158] like Figure 3A As shown, the semiconductor layer 113 includes a region 113i and a region 113na and a region 113nb provided so as to sandwich the region 113i.

[0159] The region 113na is a region of the semiconductor layer 113 in contact with the conductive layer 111. At least a portion of the region 113na is used as one of the source region and the drain region of the transistor 100. The region 113nb is a region of the semiconductor layer 113 in contact with the conductive layer 112. At least a portion of the region 113nb is used as the other of the source region and the drain region of the transistor 100. Figure 3BAs shown, the conductive layer 112 is in contact with the entire periphery of the semiconductor layer 113. Therefore, the other of the source region and the drain region of the transistor 100 may be formed on the entire periphery of the portion of the semiconductor layer 113 formed in the same layer as the conductive layer 112.

[0160] The region 113i is a region between the region 113na and the region 113nb of the semiconductor layer 113. At least a portion of the region 113i is used as a channel formation region of the transistor 100. That is, the channel formation region of the transistor 100 is located in a region between the conductive layer 111 and the conductive layer 112 in the semiconductor layer 113. In addition, the channel formation region of the transistor 100 can also be said to be located in a region of the semiconductor layer 113 that is in contact with the insulating layer 103 or a region in the vicinity thereof, a region that is in contact with the oxide region 117ox or a region in the vicinity thereof, and a region that is in contact with the insulating layer 104 or a region in the vicinity thereof.

[0161] The channel length of the transistor is the distance between the source region and the drain region. In other words, the channel length of the transistor 100 is determined by the thickness of the insulating layer 103, the oxide region 117ox, and the insulating layer 104 on the conductive layer 111. Figure 3A The dotted double arrow in FIG. 1 shows the channel length L of the transistor 100. The channel length L is the distance between the end of the region where the semiconductor layer 113 contacts the conductive layer 111 and the end of the region where the semiconductor layer 113 contacts the conductive layer 112 when viewed from the cross section. That is, the channel length L is equivalent to the length of the side surface of the insulating layer 103, the oxide region 117ox, and the opening 121 side of the insulating layer 104 when viewed from the cross section.

[0162] In the existing transistors, specifically in the planar transistors, the channel length is set according to the exposure limit of the photolithography, for example, but in the present invention, the channel length can be set according to the thickness of the insulating layer 103, the oxide region 117ox, and the region of the insulating layer 104 that contacts the conductive layer 111. Therefore, the channel length of the transistor 100 can be set to be very fine, that is, below the exposure limit of the photolithography (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm, or below 10nm, and above 1nm or above 5nm). As a result, the on-state current of the transistor 100 is increased. Therefore, a semiconductor device that can be driven at high speed can be provided.

[0163] Here, the OS transistor has a higher resistance to the short channel effect than the Si transistor, which will be described in detail later. Figure 3A and Figure 3B The channel length of the transistor 100 having the structure shown in FIG. 1 is shorter than that of a planar transistor. Figure 3A and Figure 3B In the structure shown in the figure, metal oxide is preferably used for the semiconductor layer 113. Alternatively, a material other than metal oxide such as silicon may be used for the semiconductor layer 113.

[0164] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 121. Therefore, compared with a planar transistor in which a channel formation region, a source region, and a drain region are provided separately on an XY plane, the occupied area of ​​the transistor can be reduced. Thus, the semiconductor device can be miniaturized.

[0165] like Figure 3B As shown, the semiconductor layer 113, the insulating layer 105 and the conductive layer 115 are arranged in a concentric circle shape on the XY plane including the channel formation region of the semiconductor layer 113. Therefore, the side of the conductive layer 115 arranged in the center is opposite to the side of the semiconductor layer 113 through the insulating layer 105. That is, when viewed from a plane, the entire periphery of the semiconductor layer 113 is the channel formation region. At this time, for example, the channel width of the transistor 100 is determined according to the peripheral length of the semiconductor layer 113. In other words, it can be said that the channel width of the transistor 100 is determined by the maximum width of the opening 121 (the maximum diameter when the opening 121 is circular when viewed from a plane). Figure 3A and Figure 3B The maximum width D of the opening 121 is indicated by a double-dashed arrow. Figure 3B The channel width W of the transistor 100 is indicated by a double-pointed arrow.

[0166] The maximum width D of the opening 121 is preferably, for example, greater than 5 nm, greater than 10 nm, or greater than 20 nm and less than 100 nm, less than 60 nm, less than 50 nm, less than 40 nm, or less than 30 nm. In addition, when the opening 121 is circular when viewed from a plane, the maximum width D of the opening 121 is equivalent to the diameter of the opening 121, and the channel width W can be calculated as "D×π". By applying the above-mentioned method for forming an opening of one embodiment of the present invention, the maximum width D of the opening 121 can be easily reduced. Thus, the transistor 100 can be miniaturized. On the other hand, by increasing the size of the maximum width D of the opening 121, the channel width per unit area of ​​the transistor 100 can be increased, thereby increasing the on-state current.

[0167] In a semiconductor device of one embodiment of the present invention, the channel length L of the transistor 100 is preferably at least smaller than the channel width W of the transistor 100. The channel length L of the transistor 100 is greater than 0.1 times and less than 0.99 times, and preferably greater than 0.5 times and less than 0.8 times, the channel width W of the transistor 100. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0168] Since the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged in concentric circles, the distance between the conductive layer 115 and the semiconductor layer 113 is substantially uniform. Therefore, a gate electric field can be applied to the semiconductor layer 113 substantially uniformly.

[0169] The side wall of the opening 121 is preferably perpendicular to the top surface of the conductive layer 111. By adopting such a structure, the transistor 100 can be miniaturized. Alternatively, the side wall of the opening 121 may be tapered.

[0170] Hereinafter, components of a semiconductor device according to one embodiment of the present invention will be described.

[0171] As described above, a single layer or a stack of metal oxides described in [Metal Oxide] can be used as the semiconductor layer 113. Alternatively, a single layer or a stack of materials such as silicon described in [Other Semiconductor Materials] can be used as the semiconductor layer 113.

[0172] When a metal oxide is used for the semiconductor layer 113, specifically, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto can be used as the semiconductor layer 113. In addition, the composition close thereto includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0173] In addition, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0174] The composition of the metal oxide used for the semiconductor layer 113 can be analyzed, for example, using energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), XPS, inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry). Alternatively, a combination of multiple of the above methods can be used for analysis. Note that the actual content of an element with a low content is sometimes different from the content obtained by analysis due to the influence of the analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0175] The metal oxide can be formed appropriately by an atomic layer deposition (ALD: Atomic Layer Deposition) method.

[0176] Alternatively, the metal oxide may be formed by sputtering or chemical vapor deposition (CVD: Chemical Vapor Deposition).

[0177] Note that when the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that in the sputtering target.

[0178] The metal oxide used for the semiconductor layer 113 is preferably crystalline. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used as the semiconductor layer 113, and CAAC-OS is particularly preferably used.

[0179] CAAC-OS preferably has a plurality of layered crystal regions and its c-axis is oriented in the normal direction of the formed surface. For example, the semiconductor layer 113 preferably has layered crystals that are roughly parallel to the side walls of the opening 121, and in particular, layered crystals that are roughly parallel to the insulating layer 103, the oxide region 117ox, and the side of the insulating layer 104. By adopting this structure, the layered crystals of the semiconductor layer 113 are roughly parallel to the channel length direction of the transistor 100, so the on-state current of the transistor 100 can be increased.

[0180] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by performing a heat treatment at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0181] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0182] Furthermore, when a crystalline metal oxide such as CAAC-OS is used as the semiconductor layer 113, oxygen extraction from the source electrode or the drain electrode can be suppressed from the semiconductor layer 113. Therefore, even when heat treatment is performed, oxygen extraction from the semiconductor layer 113 can be suppressed, so that the transistor 100 is stable to high temperature (so-called thermal budget) in the manufacturing process.

[0183] The crystallinity of the semiconductor layer 113 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of a plurality of the above methods.

[0184] The thickness of the semiconductor layer 113 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm, and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0185] Note that Figure 1 , Figure 2B and Figure 2CThe semiconductor layer 113 is shown as a single layer in FIG. 1 , but one embodiment of the present invention is not limited thereto. The semiconductor layer 113 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may be adopted.

[0186] As described above, the semiconductor layer 113 may have a region in contact with the conductive layer 111 and a region in contact with the conductive layer 112. When the semiconductor layer 113 is in contact with the conductive layer 111, a metal compound or oxygen vacancy may be formed, thereby reducing the resistance of the region 113na of the semiconductor layer 113. When the semiconductor layer 113 in contact with the conductive layer 111 is reduced in resistance, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced. Similarly, when the semiconductor layer 113 is in contact with the conductive layer 112, the region 113nb of the semiconductor layer 113 may be reduced in resistance. Therefore, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.

[0187] As the insulating layer 105 functioning as a gate insulating layer, silicon oxide or silicon oxynitride can be used, for example. Silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0188] Alternatively, a material having a high relative dielectric constant, so-called high-k material, described in “Insulator” below may be used as the insulating layer 105. For example, hafnium oxide or aluminum oxide may be used.

[0189] The thickness of the insulating layer 105 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and further preferably 0.5 nm to 10 nm. At least a portion of the insulating layer 105 preferably includes a region having the above thickness.

[0190] The concentration of impurities such as water and hydrogen in the insulating layer 105 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0191] Notice, Figure 1 , Figure 2B as well as Figure 2C The insulating layer 105 is shown as a single layer, but the present invention is not limited thereto. The insulating layer 105 may also have a stacked structure.

[0192] The conductive layer 115 serving as a gate electrode can be made of a conductive material having high conductivity such as tungsten, aluminum, or copper. Alternatively, the conductive layer 115 can be made of an alloy such as an alloy of aluminum and titanium (Al—Ti).

[0193] As the conductive layer 115, it is preferred to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting the diffusion of oxygen. As the conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride) and a conductive material containing oxygen (for example, ruthenium oxide) can be cited. Thus, the conductivity of the conductive layer 115 can be suppressed from decreasing. In addition, as the conductive layer 115, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus or a silicide such as nickel silicide can also be used.

[0194] Note that Figure 1 , Figure 2B and Figure 2C In the figures and the like, the conductive layer 115 is shown as a single layer, but one embodiment of the present invention is not limited thereto. The conductive layer 115 may have a stacked-layer structure.

[0195] The relative dielectric constant of the insulating layer 101 is preferably low. This can reduce the parasitic capacitance generated between wirings. As the insulating layer 101, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0196] In addition, the concentration of impurities such as water and hydrogen in the insulating layer 101 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0197] As the insulating layer 107, an insulator having a barrier property against hydrogen described in [Insulator] described later is preferably used. Thus, diffusion of hydrogen from the outside of the transistor 100 through the insulating layer 105 to the semiconductor layer 113 can be suppressed. Silicon nitride and silicon nitride oxide are characterized in that they rarely release impurities such as water and hydrogen and oxygen and hydrogen do not easily permeate, and therefore can be preferably used for the insulating layer 107.

[0198] As the insulating layer 107, an insulator having a function of capturing hydrogen or fixing hydrogen as described in [Insulator] described later is preferably used. By adopting such a structure, hydrogen is suppressed from diffusing from above the insulating layer 107 to the semiconductor layer 113, and hydrogen in the semiconductor layer 113 is captured or fixed, thereby reducing the hydrogen concentration of the semiconductor layer 113. As the insulating layer 107, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. In addition, for example, as the insulating layer 107, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0199] exist Figure 2B and Figure 2C, etc., show a structure in which the insulating layer 107 is formed on the top surface of the transistor 100, but the present invention is not limited thereto. For example, the insulating layer 107 or an insulating layer having the same function and material as the insulating layer 107 may be formed on the side and bottom surfaces of the transistor 100, and the transistor 100 may be surrounded by the insulating layer 107. By adopting this structure, impurities such as water and hydrogen can be suppressed from entering the interior of the transistor 100.

[0200] <Semiconductor Device Structure Example 2>

[0201] Figure 4A and Figure 4B They are Figure 2B and Figure 2C The conductive layer 111 shown in the figure has a two-layer stacked structure of a conductive layer 111a and a conductive layer 111b on the conductive layer 111a. Figure 4C yes Figure 4B An enlarged view of the conductive layer 111 and the area near it is shown. Figure 4C A region 113 na at least a portion of which is used as one of a source region and a drain region of the transistor 100 and a region 113 i at least a portion of which is used as a channel formation region of the transistor 100 are shown.

[0202] exist FIG. 4A to FIG. 4C In the example shown, the opening 121 is also provided in the conductive layer 111b and reaches the conductive layer 111a. In this case, the semiconductor layer 113 may have a region in contact with the top surface of the conductive layer 111a and a region in contact with the side surface of the conductive layer 111b inside the opening 121.

[0203] In manufacturing FIG. 4A to FIG. 4C In the case of the transistor 100 of the structure shown in the figure, the insulating layer 101, the conductive layer 111a, the conductive layer 111b, the insulating layer 103, the conductive layer 117, the insulating layer 104, and the conductive layer 112 are formed, and then the opening 121 reaching the conductive layer 111b is formed in the conductive layer 112, the insulating layer 104, the conductive layer 117, and the insulating layer 103. Next, the conductive layer 117 is oxidized to form an oxide region 117ox. Next, the region of the conductive layer 111b overlapping with the opening 121 is removed, so that the opening 121 reaches the conductive layer 111a. Then, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are formed in a manner having a region located inside the opening 121. As described above, it is possible to manufacture FIG. 4A to FIG. 4C Transistor 100 having the structure shown. In some cases, a recess having a region overlapping with opening 121 is provided in conductive layer 111a. In some cases, opening 121 does not reach conductive layer 111a, and a recess having a region overlapping with opening 121 is provided in conductive layer 111b.

[0204] The transistor 100 has FIG. 4A to FIG. 4C In the case of the structure shown, a portion of the conductive layer 111b is removed after the above-mentioned oxidation treatment is performed. Thus, even in the case where the conductive layer 111b is oxidized by the above-mentioned oxidation treatment, at least a portion of the oxidized region can be removed by performing the above-mentioned oxidation treatment on the conductive layer 111. Therefore, the resistance of the contact interface between the conductive layer 111 and the semiconductor layer 113 can be reduced. Thus, for example, when the transistor 100 is turned on, it is possible to suppress current from flowing between the conductive layer 111 and the conductive layer 112 in the semiconductor layer 113 and reduce the current flowing. Thus, a semiconductor device with high reliability can be provided. In addition, for example, a material with low oxidation resistance and high conductivity can be used for the conductive layer 111, so the range of selection of the material of the conductive layer 111 can be expanded. In addition, as Figure 1 , Figure 2B as well as Figure 2C For example, when the conductive layer 111 has a single layer, at least a portion of the oxidized region of the conductive layer 111 may be removed after the oxidation treatment. In this case, the conductive layer 111 includes a recess having a region overlapping with the opening 121.

[0205] In addition, Figure 4C In the example shown, the top surface of the conductive layer 111 is located above the bottom surface of the conductive layer 115. Thus, at a position along the side wall of the opening 121, the conductive layer 111 and the conductive layer 115 have a region that is opposed to each other with the semiconductor layer 113 and the insulating layer 105 sandwiched therebetween. Thus, it is possible to prevent the formation of an offset region between the region 113i and the region 113na. In addition, even in the absence of such an opposed region, the length of the offset region between the region 113i and the region 113na can be shortened. As described above, it is possible to suppress the effective channel length of the transistor 100 from being lengthened due to the offset region. Therefore, it is possible to suppress the reduction in the on-state current of the transistor 100.

[0206] Conductive layers 111a and 111b may be any of the conductive materials described in [Conductor] to be described later. For example, a highly conductive material such as tungsten, aluminum, or copper may be used as one or both of the conductive layers 111a and 111b. Figure 2B and Figure 2C Conductive layer 111 shown in the figure can also use a conductive material containing oxygen. For example, tungsten can be used for one of conductive layer 111a and conductive layer 111b, and indium tin oxide added with silicon can be used for the other of conductive layer 111a and conductive layer 111b. In addition, conductive layer 111 can also have a stacked structure of three or more layers.

[0207] Figure 5A and Figure 5B Shown separately Figure 2B and Figure 2C The illustrated example shows an example in which the side wall of the opening 121 has a tapered shape, that is, the side surfaces of the insulating layer 103 , the oxide region 117 ox , the insulating layer 104 , and the conductive layer 112 in the opening 121 have tapered shapes.

[0208] By making the side wall of the opening 121 have a tapered shape, the coverage of the semiconductor layer 113 and the insulating layer 105 is improved, and defects such as voids can be reduced. For example, the angle θ formed by the side surface of the insulating layer 103 in the opening 121 and the top surface of the conductive layer 111 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 75 degrees, and further preferably greater than 45 degrees and less than 65 degrees. In addition, as described above, the side wall of the opening 121 can be perpendicular to the top surface of the conductive layer 111. That is, the angle θ can be 90 degrees.

[0209] Figure 5A and Figure 5B The shape of the opening 121 shown is a truncated cone shape. In this case, the opening 121 is circular when viewed from a plane, and is trapezoidal when viewed from an interface. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the top surface of the opening 121 provided in the conductive layer 112) is larger than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductive layer 111 exposed in the opening 121). In this case, the maximum diameter of the opening 121 can be calculated based on the upper bottom surface of the truncated cone shape.

[0210] In the case where the side wall of the opening 121 has a tapered shape, the channel length can be set according to the thickness of the insulating layer 103, the oxide region 117ox, and the insulating layer 104 in the region overlapping the conductive layer 111 and the angle θ formed by the side surface of the insulating layer 103 in the opening 121 and the top surface of the conductive layer 111. In addition, the outer perimeter of the semiconductor layer 113 when viewed from a plane may be, for example, based on the position of the region in contact with the conductive layer 112 or the position of half the thickness of the conductive layer 117. Note that the perimeter at any position (depth) of the opening 121 may be set as the channel width of the transistor 100 as required. For example, the perimeter of the lowermost portion of the opening 121 may be set as the channel width, and the perimeter of the uppermost portion of the opening 121 may be set as the channel width.

[0211] exist Figure 5A and Figure 5BIn the embodiment, the side surface of the conductive layer 112 in the opening 121, the side surface of the insulating layer 104 in the opening 121, the side surface of the oxide region 117ox in the opening 121, and the side surface of the insulating layer 103 in the opening 121 are preferably aligned, but one embodiment of the present invention is not limited to this. For example, the side surface of the conductive layer 112 in the opening 121 and the side surface of the insulating layer 104 in the opening 121 may also be discontinuous. In addition, at least one of the inclination of the side surface of the conductive layer 112 in the opening 121, the inclination of the side surface of the insulating layer 104 in the opening 121, the inclination of the side surface of the oxide region 117ox in the opening 121, and the inclination of the side surface of the insulating layer 103 in the opening 121 may also be different from the others. In addition, for example, the angle formed by the side surface of the conductive layer 112 in the opening 121 and the top surface of the conductive layer 111 is preferably smaller than the angle θ. By adopting the above structure, the coverage of the semiconductor layer 113 on the side surface of the conductive layer 112 in the opening 121 is improved, thereby reducing defects such as voids.

[0212] like Figure 5A and Figure 5B As shown, the bottom of the conductive layer 115 located inside the opening 121 has a flat region. Note that the bottom of the conductive layer 115 located inside the opening 121 may not have a flat region depending on the maximum width of the opening 121 (the maximum diameter when the opening 121 is circular when viewed from a plane), the thickness of the insulating layer 103, the oxide region 117ox, and the insulating layer 104 in the region overlapping the conductive layer 111 (equivalent to the depth of the opening 121), the thickness of the semiconductor layer 113, and the thickness of the insulating layer 105. Figure 5C and Figure 5D Shown separately Figure 5A and Figure 5B The bottom of the conductive layer 115 located inside the opening 121 is shaped like a needle.

[0213] Here, the needle-like shape refers to a shape that becomes thinner as it approaches the top (closer to the bottom of the conductive layer 115 located inside the opening 121). In addition, the top of the needle-like shape may be an acute angle or a curved shape that is convex downward. In addition, the shape of the needle-like shape having an acute angle at the top may also be called a V-shape.

[0214] The region of the conductive layer 115 located inside the opening 121 and facing the semiconductor layer 113 via the insulating layer 105 is used as a gate electrode. Therefore, the conductive layer 115 embedded in the opening 121 and having a needle-like bottom shape can also be called a needle-shaped gate. Figure 5A and Figure 5BAs shown, even when the bottom of the conductive layer 115 is in a shape having a flat region, it may sometimes be referred to as a needle-shaped gate.

[0215] The side wall of the opening 121 may also be in an inverse tapered shape. In other words, the angle θ may be greater than 90 degrees.

[0216] Here, the inverse cone shape refers to a shape in which the side or top is more protruding than the bottom in a direction parallel to the substrate. At this time, the shape of the opening 121 is a truncated cone. In this case, the opening 121 is circular when viewed from a plane, and is trapezoidal when viewed from a cross section. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the top surface of the opening 121 provided in the conductive layer 112) is smaller than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductive layer 111 exposed in the opening 121). By adopting this structure, the area of ​​the semiconductor layer 113 in contact with the conductive layer 111 can be expanded.

[0217] exist Fig. 6A and Figure 6B middle, Figure 2B and Figure 2C The insulating layer 103 and the insulating layer 104 shown have a three-layer stacked structure. Fig. 6A and Figure 6B In the illustrated example, the insulating layer 103 includes an insulating layer 103a, an insulating layer 103b on the insulating layer 103a, and an insulating layer 103 on the insulating layer 103b. In addition, the insulating layer 104 includes an insulating layer 104a, an insulating layer 104b on the insulating layer 104a, and an insulating layer 104c on the insulating layer 104b.

[0218] As the insulating layer 103a, the insulating layer 103c, the insulating layer 104a, and the insulating layer 104c, for example, an insulator containing nitrogen such as silicon nitride, silicon nitride oxide, or aluminum nitride can be used. In addition, the insulating layer 103b and the insulating layer 104b can be a flattened layer. Preferably, the insulating layer 103b is a layer that is easier to be flattened than the insulating layer 103a, and the insulating layer 104b is a layer that is easier to be flattened than the insulating layer 104a. As the insulating layer 103b and the insulating layer 104b, for example, an insulator containing oxygen such as silicon oxide can be used. In the semiconductor device of the above structure, the resistivity of the semiconductor layer 113 in contact with the insulating layer 103a, the resistivity of the semiconductor layer 113 in contact with the insulating layer 103c, the resistivity of the semiconductor layer 104a, and the resistivity of the semiconductor layer 104c can be lower than the resistivity of the semiconductor layer 113 in contact with the oxide region 117ox, and can be lower than the resistivity of the semiconductor layer 113 in contact with the insulating layer 103b and the resistivity of the semiconductor layer 104b.

[0219] By making the insulating layer 103 and the insulating layer 104 have Fig. 6Aand Figure 6B The structure shown can make the resistivity of the region of the semiconductor layer 113 in contact with the insulating layer 103 and at least a part of the region in contact with the insulating layer 104 lower than the resistivity of the region in contact with the oxide region 117ox, for example, while the insulating layer 103 and the insulating layer 104 are flattened. Thus, a semiconductor device that is easy to manufacture and can be driven at a high speed, for example, compared with a case where the insulating layer 103 and the insulating layer 104 do not include a layer containing nitrogen, can be provided. Note that when the thickness of the insulating layer 103b and the insulating layer 104b is small, the height of the region in the semiconductor layer 113 where the electric field from the conductive layer 117 does not reach and does not contain nitrogen, for example, can be reduced, thereby increasing the on-state current of the transistor 100. On the other hand, when the thickness of the insulating layer 103b is increased, the parasitic capacitance formed by the conductive layer 111, the insulating layer 103, and the conductive layer 117 can be reduced. In addition, when the thickness of the insulating layer 104b is increased, the parasitic capacitance formed by the conductive layer 117, the insulating layer 104, and the conductive layer 112 can be reduced.

[0220] exist Figure 6C and Fig.6D In Fig. 6A and Figure 6B The insulating layer 103b and the insulating layer 104b are not in contact with the semiconductor layer 113. Figure 6C and Fig.6D In the example shown, the top surface of the insulating layer 103a may be consistent or substantially consistent with the top surface of the insulating layer 103b. In addition, the top surface of the insulating layer 104a may be consistent or substantially consistent with the top surface of the insulating layer 104b. The top surface of the insulating layer 103a may have a region in contact with the insulating layer 103c in addition to the region in contact with the insulating layer 103b. In addition, the top surface of the insulating layer 104a may have a region in contact with the insulating layer 104c in addition to the region in contact with the insulating layer 104b.

[0221] exist Figure 6C and Fig.6D In the example shown, Fig. 6A and Figure 6B Compared with the example shown in FIG. 1 , for example, the channel length of the transistor 100 can be reduced, thereby increasing the on-state current of the transistor 100. Fig. 6A and Figure 6B In the example shown, Figure 6C and Fig.6D Compared with the example shown in FIG. 1 , parasitic capacitance formed by the conductive layer 111, the insulating layer 103, and the conductive layer 117 and parasitic capacitance formed by the conductive layer 117, the insulating layer 104, and the conductive layer 112 can be reduced. Fig. 6A and Figure 6BIn the illustrated example, by causing the insulating layer 103b and the insulating layer 104b to contain excess oxygen, VoH in the channel formation region of the semiconductor layer 113 can be reduced. Therefore, the electrical characteristics of the transistor 100 can be stabilized, and reliability can be improved.

[0222] exist FIG. 6A to FIG. 6D In the example shown, the insulating layer 103c may have a region in contact with the bottom surface of the conductive layer 117, and the insulating layer 104a may have a region in contact with the top surface and the side surface of the conductive layer 117. In this case, when the insulating layer 103c and the insulating layer 104a are insulating layers that do not contain oxygen, for example, even when the insulating layer 103b and the insulating layer 104b contain oxygen, oxidation of the region of the conductive layer 117 far from the semiconductor layer 113 can be suppressed. Therefore, an increase in the wiring resistance of the conductive layer 117 can be suppressed. In addition, when the insulating layer 104c is an insulating layer that does not contain oxygen, for example, even when the insulating layer 104b contains oxygen, oxidation of the conductive layer 112 can be suppressed. In addition, the following structure can be adopted: the insulating layer 104c is not provided, and the insulating layer 104 has a two-layer structure of the insulating layer 104a and the insulating layer 104b. By reducing the number of layers of the insulating layer 104, the manufacturing process of the semiconductor device can be simplified.

[0223] Figure 2A1 , Figure 2A2 , Figure 2B and Figure 2C Although the conductive layer 117 is shaped like a strip extending in the Y direction, one embodiment of the present invention is not limited to this. Fig.7A1 , Fig.7A2 , Figure 7B and Figure 7C middle, Figure 2A1 , Figure 2A2 , Figure 2B and Figure 2C The conductive layer 117 shown is in a planar shape. Alternatively, the conductive layer 117 may be in a strip shape extending in the X direction.

[0224] exist Fig. 8A and Figure 8B middle, Figure 2B and Figure 2C The semiconductor layer 113, the insulating layer 105 and the conductive layer 115 shown have a stacked structure. Figure 8C yes Figure 8B An enlarged view of transistor 100 is shown.

[0225] exist FIG. 8A to FIG. 8C In the example shown, the semiconductor layer 113 has a two-layer structure of a semiconductor layer 113a and a semiconductor layer 113b on the semiconductor layer 113a. FIG. 8A to FIG. 8CIn the example shown in FIG. 1 , the insulating layer 105 has a three-layer structure of an insulating layer 105a, an insulating layer 105b on the insulating layer 105a, and an insulating layer 105c on the insulating layer 105b. FIG. 8A to FIG. 8C In the illustrated example, the conductive layer 115 has a two-layer structure of a conductive layer 115 a and a conductive layer 115 b on the conductive layer 115 a .

[0226] The electrical conductivity of the material used for the semiconductor layer 113 a is preferably different from the electrical conductivity of the material used for the semiconductor layer 113 b .

[0227] For example, the semiconductor layer 113a may use a material having a higher conductivity than the semiconductor layer 113b. By using a material having a higher conductivity for the semiconductor layer 113a that contacts the conductive layer 111 and the conductive layer 112, the contact resistance between the semiconductor layer 113 and the conductive layer 111 and the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced. Thus, the transistor 100 having a large on-state current can be realized.

[0228] Here, when a material with high conductivity is used for the semiconductor layer 113b provided on one side of the conductive layer 115, for example, the threshold voltage of the transistor 100 is reduced, and sometimes the transistor 100 becomes a normally-on characteristic. Therefore, it is preferable to use a material with lower conductivity than the semiconductor layer 113a for the semiconductor layer 113b. Therefore, when the transistor 100 is an n-channel transistor, the threshold voltage can be increased, and the transistor 100 can be suppressed from becoming a normally-on characteristic. In other words, the transistor 100 can be made into a normally-off characteristic.

[0229] As described above, by making the semiconductor layer 113 have a stacked structure and using a material having higher conductivity for the semiconductor layer 113a than for the semiconductor layer 113b, the transistor 100 having a normally-off characteristic and a large on-state current can be realized. Thus, a semiconductor device that consumes less power and can be driven at high speed can be provided.

[0230] In addition, the carrier concentration of the semiconductor layer 113a is preferably higher than the carrier concentration of the semiconductor layer 113b. By increasing the carrier concentration of the semiconductor layer 113a and improving the conductivity, the contact resistance between the semiconductor layer 113 and the conductive layer 111 and the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced. Thus, a transistor 100 with a large on-state current can be realized. In addition, by reducing the carrier concentration of the semiconductor layer 113b and lowering the conductivity, the transistor 100 can be made into a normally-off characteristic.

[0231] Here, an example is shown in which the semiconductor layer 113a uses a material with higher conductivity than the semiconductor layer 113b, but one embodiment of the present invention is not limited to this. The semiconductor layer 113a may also use a material with lower conductivity than the semiconductor layer 113b. In this case, the carrier concentration of the semiconductor layer 113a may be lower than the carrier concentration of the semiconductor layer 113b.

[0232] The band gap of the first metal oxide used for the semiconductor layer 113a is preferably different from the band gap of the second metal oxide used for the semiconductor layer 113b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0233] The band gap of the first metal oxide used for the semiconductor layer 113a can be smaller than the band gap of the second metal oxide used for the semiconductor layer 113b. Thus, the contact resistance between the semiconductor layer 113 and the conductive layer 111 and the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced, and a transistor 100 with a large on-state current can be realized. In addition, the threshold voltage of the transistor 100 can be increased to make the transistor 100 a normally-off characteristic.

[0234] Here, an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, but one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be greater than or equal to the band gap of the second metal oxide.

[0235] As described above, the band gap of the first metal oxide used for the semiconductor layer 113a can be smaller than the band gap of the second metal oxide used for the semiconductor layer 113b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the composition of the first metal oxide different from that of the second metal oxide, the band gap can be controlled. For example, the content of the element M of the first metal oxide is preferably lower than the content of the element M of the second metal oxide. Specifically, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide is a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition near it, and the second metal oxide is a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition near it or In:M:Zn=1:3:4 [atomic ratio] or a composition near it. As the element M, it is particularly preferred to use one or more of gallium, aluminum and tin.

[0236] The first metal oxide may not contain the element M. For example, the first metal oxide used for the semiconductor layer 113a may be In-Zn oxide, and the second metal oxide used for the semiconductor layer 113b may be In-M-Zn oxide. Specifically, the first metal oxide may be In-Zn oxide, and the second metal oxide may be In-Ga-Zn oxide. More specifically, the first metal oxide may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, or a composition of In:Zn=4:1 [atomic ratio] or a composition near it, and the second metal oxide may be a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition near it.

[0237] Here, an example is shown in which the content of the element M of the first metal oxide is lower than the content of the element M of the second metal oxide, but one embodiment of the present invention is not limited to this. The content of the element M of the first metal oxide may also be higher than the content of the element M of the second metal oxide. Note that as long as the composition of the first metal oxide and the second metal oxide is different, the content of elements other than the element M of the first metal oxide and the second metal oxide may also be different. For example, the second metal oxide may be used for the semiconductor layer 113a and the first metal oxide may be used for the semiconductor layer 113b.

[0238] The thickness of the semiconductor layer 113 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm, and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0239] The thickness of each layer constituting the semiconductor layer 113 (here, the semiconductor layer 113a and the semiconductor layer 113b) may be determined so that the thickness of the semiconductor layer 113 is within the above range. The thickness of the semiconductor layer 113a may be determined so that the contact resistance between the semiconductor layer 113a and the conductive layer 111 and the contact resistance between the semiconductor layer 113a and the conductive layer 112 are within a desired range. In addition, the thickness of the semiconductor layer 113b may be determined so that the threshold voltage of the transistor 100 is within a desired range. In addition, the thickness of the semiconductor layer 113a may be the same as or different from the thickness of the semiconductor layer 113b.

[0240] FIG. 8A to FIG. 8C Although the semiconductor layer 113 has an example of a two-layer stacked structure of the semiconductor layer 113 a and the semiconductor layer 113 b , one embodiment of the present invention is not limited thereto and the semiconductor layer 113 may have a stacked structure of three or more layers.

[0241] In the case where the semiconductor layer 113 is a three-layer stacked structure, for example, the following structure may be adopted: a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto or a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, and a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto may be provided in order from the conductive layer 111 side. In addition, the following structure may be adopted: a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, and a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto may be provided in order from the conductive layer 111. By adopting the above structure, the on-state current of the transistor 100 can be increased. In addition, the variation in the electrical characteristics of the transistor 100 can be reduced, thereby improving the reliability of the semiconductor device.

[0242] The insulating layer 105a preferably uses an insulator having oxygen barrier properties as described in [Insulator] to be described later. The insulating layer 105a has a region in contact with the semiconductor layer 113. Since the insulating layer 105a has oxygen barrier properties, for example, it is possible to suppress the detachment of oxygen from the semiconductor layer 113 during heat treatment. Thus, the formation of oxygen vacancies in the semiconductor layer 113 can be suppressed. Therefore, the transistor 100 can have good electrical characteristics, and the reliability of the semiconductor device of one embodiment of the present invention can be improved. As the insulating layer 105a, for example, aluminum oxide is preferably used. In this case, the insulating layer 105a contains at least oxygen and aluminum.

[0243] The insulating layer 105b preferably uses a material having a low relative dielectric constant as described in [Insulator] to be described later. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulating layer 105b contains at least oxygen and silicon. By adopting the above structure, the parasitic capacitance between the conductive layer 115 and the conductive layer 112 can be reduced. In addition, the impurity concentration of water, hydrogen, etc. in the insulating layer 105b is preferably reduced.

[0244] The insulating layer 105c is preferably an insulator having hydrogen barrier properties as described in [Insulator] to be described later. This can suppress the diffusion of impurities contained in the conductive layer 115 into the semiconductor layer 113. In particular, silicon nitride has a high hydrogen barrier property and is therefore suitable for the insulating layer 105c. In this case, the insulating layer 105c contains at least nitrogen and silicon.

[0245] The insulating layer 105c may further have an oxygen barrier property. The insulating layer 105c is provided between the insulating layer 105b and the conductive layer 115. Therefore, diffusion of oxygen included in the insulating layer 105b into the conductive layer 115 and oxidation of the conductive layer 115 can be suppressed.

[0246] In addition, an insulator may be provided between the insulating layer 105b and the insulating layer 105c. The insulator is preferably an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later. By providing the insulator, hydrogen contained in the semiconductor layer 113 can be captured or fixed more efficiently. Thus, the hydrogen concentration in the semiconductor layer 113 can be reduced. As the insulator, for example, hafnium oxide is preferably used. In this case, the insulator contains at least oxygen and hafnium. In addition, the insulator may also have an amorphous structure.

[0247] In order to realize miniaturization of the transistor 100, it is preferable that the thickness of the insulating layer 105a to the insulating layer 105c is small and within the above range. Typically, the thicknesses of the insulating layer 105a, the insulating layer 105b, the insulator having the function of capturing or fixing hydrogen, and the insulating layer 105c are set to 1 nm, 2 nm, 2 nm, and 1 nm, respectively. By adopting the above structure, the transistor 100 can have good electrical characteristics even if it is miniaturized.

[0248] FIG. 8A to FIG. 8C The insulating layer 105 is shown to have a three-layer stacked structure of the insulating layers 105a to 105c, but one embodiment of the present invention is not limited thereto. The insulating layer 105 may also have a stacked structure of two or more layers. At this time, each layer included in the insulating layer 105 may be appropriately selected from the insulating layers 105a to 105c and an insulator having a function of capturing or fixing hydrogen.

[0249] When the conductive layer 115 has a two-layer structure of the conductive layer 115a and the conductive layer 115b, for example, titanium nitride is used for the conductive layer 115a and tungsten is used for the conductive layer 115b. In this way, by providing a layer containing tungsten, the conductivity of the conductive layer 115 can be improved, thereby reducing the wiring resistance of the conductive layer 115.

[0250] exist FIG. 8A to FIG. 8C In the embodiment, the conductive layer 115 has a two-layer stacked structure of the conductive layer 115a and the conductive layer 115b, but one embodiment of the present invention is not limited thereto. The conductive layer 115 may have a stacked structure of three or more layers.

[0251] Fig.9A and Fig. 9B The following examples are shown respectively: Figure 2B and Figure 2CIn the opening 121 shown, the side surface of the oxide region 117ox is located on the opposite side of the center of the conductive layer 111, that is, closer to the side surface of the conductive layer 111, than the side surfaces of the insulating layer 103 and the insulating layer 104. Fig.9A and Fig. 9B In the illustrated example, the recess 131 is formed by the insulating layer 103 and the insulating layer 104 and the oxide region 117 ox .

[0252] The details will be described later. In a method for manufacturing a semiconductor device according to one embodiment of the present invention, after forming the opening 121 in the conductive layer 117, the side surface of the conductive layer 117 in the opening 121 is processed by, for example, isotropic etching, and then oxidized to form an oxide region 117ox. In this case, Fig.9A and Fig. 9B As shown, the side surface of the oxide region 117 ox may be located closer to the side surface of the conductive layer 111 than the side surfaces of the insulating layer 103 and the insulating layer 104 .

[0253] exist Fig. 9C and Fig.9D In the Figure 2B and Figure 2C In the example shown in the opening 121, the side surface of the oxide region 117ox is located closer to the center of the conductive layer 111 than the side surfaces of the insulating layer 103 and the insulating layer 104. Fig. 9C and Fig.9D In the illustrated example, the opening 121 has a region where the oxide region 117 ox protrudes, that is, has a convex portion.

[0254] The volume of the conductive layer 117 including the oxide region 117ox may increase by oxidizing the conductive layer 117 to form the oxide region 117ox. Thus, for example, even when the opening 121 is formed in the insulating layer 104, the conductive layer 117, and the insulating layer 103, the side surfaces of the insulating layer 104, the conductive layer 117, and the insulating layer 103 in the opening 121 are aligned, there may be a region in which the oxide region 117ox protrudes in the opening 121.

[0255] Fig. 10A Show Figure 2A2 The opening 121 shown in FIG. 1 is an example of a quadrangular shape when viewed from a plane. Fig. 10A The shape of the middle opening 121 when viewed from a plane is a square, but the shape of the opening 121 is not limited thereto, and for example, the shape when viewed from a plane may also be a rectangle, a rhombus, or a parallelogram. In addition, the shape of the opening 121 when viewed from a plane may be, for example, a triangle or a polygon with more than a pentagon or a star.

[0256] Fig. 10B Show Fig. 10A The corners of the opening 121 shown are curved. Fig. 10B The example in which the shape of the opening 121 when viewed from a plane is a quadrangle with curved corners is shown. Fig. 10B In the figure, the shape of the opening 121 when viewed from a plane is a quadrilateral with curved corners, but the shape of the opening 121 is not limited thereto. For example, the shape of the opening 121 when viewed from a plane is a rectangle with curved corners, a rhombus with curved corners, a parallelogram with curved corners, a triangle with curved corners, a polygon with a pentagon or more with curved corners, or a polygon with curved corners.

[0257] in addition, Figure 2A2 , Fig. 10A and Fig. 10B etc. show an example in which the planar shape of the oxide region 117ox is the same as the planar shape of the opening 121. Specifically, there is shown an example in which the planar shape of the boundary between the oxide region 117ox and the non-oxidized region of the conductive layer 117 is the same as the planar shape of the side surface in the opening 121 of the oxide region 117ox. However, one embodiment of the present invention is not limited to this, and the type of the planar shape of the opening 121 may be different from the type of the planar shape of the oxide region 117ox. For example, the planar shape of the opening 121 may be circular, and the planar shape of the boundary between the oxide region 117ox and the non-oxidized region of the conductive layer 117 may be a quadrangular shape or a quadrangular shape with curved corners. In addition, the planar shape of the opening 121 may be a quadrangular shape, and the planar shape of the boundary between the oxide region 117ox and the non-oxidized region of the conductive layer 117 may be a quadrangular shape with curved corners or a circular shape.

[0258] exist Fig.11A , Fig. 11B and Fig. 11C In the figure, they are shown respectively Figure 2A1 , Figure 2B and Figure 2C The semiconductor layer 113 shown is extended in the Y direction. In other words, Fig.11A , Figure 11 and Fig. 11C 1 shows an example in which the semiconductor layer 113 extends in a direction parallel to the extending direction of the conductive layer 112. Figure 2A1 , Figure 2B and Figure 2C In the example shown, the conductor layer 113 is Fig.11A , Fig. 11B and Fig. 11C In the example shown, the segments are also divided in the X direction.

[0259] Fig. 12A , Fig. 12Band Fig. 12C They are Figure 2A1 , Figure 2B and Figure 2C The example of the modification of the structure shown in FIG. 1 shows an example in which the planar shape of the opening 121 provided in the insulating layer 103, the oxide region 117ox, and the insulating layer 104 does not coincide with the planar shape of the opening 121 provided in the conductive layer 112. FIG. 12A to FIG. 12C In the example, the opening 121 provided in the insulating layer 103, the oxide region 117ox, and the insulating layer 104 is set as the opening 121a, and the opening 121 provided in the conductive layer 112 is set as the opening 121b. FIG. 12A to FIG. 12C In the example shown, the planar shape of the opening 121b is a circle whose radius is larger than that of the opening 121a. In addition, one or both of the planar shape of the opening 121a and the planar shape of the opening 121b may not be a circle. For example, the planar shape of the opening 121a and the planar shape of the opening 121b may be a quadrangular shape or a quadrangular shape with curved corners, which are shapes that the opening 121 may have.

[0260] FIG. 12A to FIG. 12C Although the example in which the area of ​​the opening 121b when viewed from the plane is larger than the area of ​​the opening 121a when viewed from the plane is shown, the area of ​​the opening 121b when viewed from the plane may be smaller than the area of ​​the opening 121a when viewed from the plane. In this case, the conductive layer 112 has a region protruding relative to the side wall of the opening 121a.

[0261] For example, when the opening 121a and the opening 121b are formed using different processes, the planar shape of the opening 121a and the planar shape of the opening 121b may be different. In addition, even when the opening 121a and the opening 121b are formed using the same process, for example, when the etching speed of the conductive layer 112 in the X direction and the Y direction is different from the etching speed of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in the X direction and the Y direction, the planar shape of the opening 121a and the planar shape of the opening 121b may be different. For example, when the etching speed of the conductive layer 112 in the X direction and the Y direction is higher than the etching speed of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in the X direction and the Y direction, even when the opening 121a and the opening 121b are formed using the same process, the area of ​​the opening 121b when viewed from the plane may be larger than the area of ​​the opening 121a when viewed from the plane.

[0262] <Materials Constituting Semiconductor Devices>

[0263] Hereinafter, constituent materials that can be used for semiconductor devices will be described.

[0264] [Substrate]

[0265] As a substrate for forming the transistor 100, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria-stabilized zirconia substrate) and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide and gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator) substrate. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate and a conductive resin substrate can be cited. Alternatively, a substrate containing a metal nitride and a substrate containing a metal oxide can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can also be cited. Alternatively, a substrate having elements provided on these substrates can also be used.

[0266] [Insulator]

[0267] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0268] For example, when miniaturizing transistors, problems such as leakage current sometimes occur due to the thin filmization of the gate insulating layer. By using a high-k material as an insulator used as a gate insulating layer, it is possible to achieve low voltage when the transistor is working while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulating layer can be reduced. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer insulating layer, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferred to select the material according to the function of the insulator. In addition, the material with a low relative dielectric constant is also a material with a large dielectric strength.

[0269] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0270] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon and aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as other inorganic insulating materials with low relative dielectric constants, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, for example, silicon oxide with pores can be cited. Note that these silicon oxides can also contain nitrogen. In addition, silicon oxide can also be formed using organic silanes such as tetraethoxysilane (TEOS), for example.

[0271] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide or metal nitrides such as aluminum nitride, silicon oxynitride and silicon nitride can be used.

[0272] In addition, the insulator in contact with the semiconductor layer or the insulator provided near the semiconductor layer such as the gate insulating layer is preferably an insulator having a region containing excess oxygen. For example, by making the insulator having a region containing excess oxygen contact with the semiconductor layer or providing it near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. As an insulator that easily forms a region containing excess oxygen, silicon oxide, silicon oxynitride, or silicon oxide having pores can be cited.

[0273] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0274] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0275] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties to one or both of oxygen and hydrogen.

[0276] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium and an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. In an oxide having an amorphous structure, an oxygen atom has a dangling bond, and sometimes has the property of capturing or fixing hydrogen by the dangling bond. These oxides preferably have an amorphous structure, and a portion thereof may also be formed with a crystalline region.

[0277] Note that in this specification, etc., a barrier insulating film refers to an insulating film having barrier properties. In addition, barrier properties refer to the property that the corresponding substance does not diffuse easily (also referred to as the property that the corresponding substance does not easily permeate, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing the corresponding substance can also be referred to as barrier properties. Note that hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise specified, the impurity recorded as the corresponding substance refers to an impurity in the channel formation region or the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO and NO2, etc.) and copper atoms. In addition, oxygen recorded as the corresponding substance refers to at least one of oxygen atoms and oxygen molecules, for example. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms and oxygen molecules, etc. is not easy to diffuse.

[0278] [Conductor]

[0279] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0280] In addition, nitrogen-containing conductive materials such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride or titanium and aluminum nitride, oxygen-containing conductive materials such as ruthenium oxide, strontium and ruthenium oxide or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Note that as conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., conductive materials containing oxygen are sometimes referred to as oxide conductors.

[0281] In addition, a conductive material mainly composed of tungsten, copper or aluminum is preferred because of its high conductivity.

[0282] In addition, a plurality of conductors formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0283] In addition, when a metal oxide is used in the channel formation region of a transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0284] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in the metal oxide forming the channel and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Or, hydrogen mixed from an external insulator can sometimes be captured.

[0285] [Metal oxides]

[0286] Metal oxides sometimes have lattice defects. Lattice defects include point defects such as atomic vacancies and singular atoms, line defects such as dislocations, surface defects such as grain boundaries, and body defects such as voids. In addition, the causes of lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or deficiency of constituent atoms) and impurities.

[0287] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with more lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the lattice defects in the metal oxide used for the semiconductor layer of the transistor are small.

[0288] In a transistor using a metal oxide, in particular, when oxygen vacancies (V O ) and impurities, the electrical properties are prone to change, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms V O H and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the metal oxide, the transistor tends to have a normally-on characteristic. Thus, in the channel formation region of the metal oxide, it is preferred to reduce oxygen vacancies and impurities as much as possible. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0289] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0290] The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). As non-single crystal structures, there are CAAC structure, polycrystalline structure, nc structure, amorphous-like (a-like) structure and amorphous structure. The a-like structure has a structure between the nc structure and the amorphous structure.

[0291] In addition, there are voids or low-density areas in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in metal oxides having an a-like structure is higher than that of metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0292] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using the metal oxide in a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0293] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, the mobility of the metal oxide used for the transistor can be increased. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region through which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0294] Here, as the metal oxide having the channel formation region, a metal oxide with high crystallinity is preferably used. Furthermore, the crystal preferably has a crystal structure having multiple layers (for example, a first layer, a second layer, and a third layer) stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal, a layered structure). At this time, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having the crystal include, for example, single crystal oxide semiconductors and CAAC-OS.

[0295] In addition, the c-axis of the crystal is preferably oriented in the normal direction of the formed surface or film surface of the metal oxide. Thus, the multiple layers are arranged in parallel or approximately parallel to the formed surface or film surface of the metal oxide. That is, the multiple layers extend in the channel length direction.

[0296] For example, the three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron in which the metal contained in the first layer exists at the center. The second layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the second layer exists at the center. The third layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the third layer exists at the center.

[0297] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and their deformed structures.

[0298] Furthermore, it is preferred that the first to third layers are all composed of a metal element or a plurality of metal elements having the same valence and oxygen. It is preferred that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferred that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0299] By adopting the above structure, the crystallinity of the metal oxide can be improved and the mobility of the metal oxide can be improved. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased and the electrical characteristics of the transistor can be improved.

[0300] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Element M is a metal element or semi-metal element with a high bond energy with oxygen, for example, a metal element or semi-metal element with a bond energy with oxygen higher than indium. As element M, specifically aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0301] As a metal oxide in one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO) and the like can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide) and the like containing silicon can be cited. Alternatively, the above oxides having an amorphous structure can be used. For example, indium oxide having an amorphous structure or indium tin oxide having an amorphous structure can be used.

[0302] By increasing the ratio of the number of atoms of indium to the total number of atoms of all metal elements in the metal oxide, the field effect mobility of the transistor can be increased.

[0303] Metal oxides may also replace indium and include one or more metal elements with large periodic numbers in the periodic table. Alternatively, metal oxides may also include one or more metal elements with large periodic numbers in addition to indium. Metal oxides have a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements with large periodic numbers, the field effect mobility of transistors can sometimes be improved. As metal elements with large periodic numbers, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0304] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0305] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. As a result, the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved.

[0306] In addition, by increasing the ratio of the number of atoms of the element M to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0307] Furthermore, by increasing the ratio of the number of In atoms to the total number of atoms of all metal elements in the metal oxide, a transistor having a large on-state current and high frequency characteristics can be obtained.

[0308] In this embodiment, In—Ga—Zn oxide is sometimes used as an example for description.

[0309] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. The metal oxide having the layered crystal structure can be easily formed by using the ALD method.

[0310] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0311] The ALD method can deposit atoms layer by layer, so that it can be deposited extremely thin, can be deposited on a structure with a high aspect ratio, can be deposited in a manner with few defects such as pinholes, can be deposited with high coverage, and can be deposited at low temperatures. Because plasma is used, deposition can be performed at a lower temperature, so the PEALD method is sometimes preferred. The precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or SIMS.

[0312] When the ALD method is used as a deposition method for metal oxide, by adopting one or both of high substrate temperature conditions during deposition and implementing impurity removal treatment, the amount of carbon and chlorine in the film can be reduced compared to the case where the ALD method is used without adopting these conditions.

[0313] For example, when depositing a metal oxide, it is preferred to intermittently perform an impurity removal treatment in an oxygen-containing atmosphere. In addition, after depositing the metal oxide, it is preferred to perform an impurity removal treatment in an oxygen-containing atmosphere. By performing an impurity removal treatment during or after the deposition of the metal oxide, impurities in the film can be removed. Thus, impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors can be suppressed from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. In addition, the crystallinity of the metal oxide can be improved. Thus, the metal oxide can be, for example, CAAC-OS, which can provide a semiconductor device with high reliability.

[0314] Examples of the impurity removal treatment include microwave treatment and heating treatment.

[0315] When performing microwave treatment, the substrate temperature is preferably set to be above room temperature (e.g., 25° C.), above 100° C., above 200° C., above 300° C., or above 400° C. and below 500° C. or below 450° C. In addition, the temperature of the heat treatment is preferably set to be above 100° C., above 200° C., above 300° C., or above 400° C. and below 500° C. or below 450° C.

[0316] In particular, it is preferred that the temperature in the impurity removal process be set to a temperature below the maximum temperature in the manufacturing process of the transistor or semiconductor device, because the impurity content of the metal oxide can be reduced without reducing the productivity. For example, by setting the maximum temperature in the manufacturing of the semiconductor device of one embodiment of the present invention to 500° C. or less, preferably 450° C. or less, the productivity of the semiconductor device can be improved.

[0317] Microwave treatment, for example, preferably uses a microwave processing device including a power supply that generates high-density plasma with microwaves. Here, the frequency of the microwave processing device is preferably set to more than 300MHz and less than 300GHz, more preferably more than 2.4GHz and less than 2.5GHz, for example, it can be 2.45GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably more than 1000W and less than 10000W, preferably more than 2000W and less than 5000W. In addition, the microwave processing device may also include a power supply that applies RF (Radio Frequency) to one side of the substrate. In addition, by applying RF to one side of the substrate, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0318] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. In addition, the treatment temperature is preferably room temperature (25° C.) or more and 750° C. or less, more preferably 300° C. or more and 500° C. or less, and further preferably 400° C. or more and 450° C. or less.

[0319] In addition, the heat treatment may be continuously performed after the microwave treatment without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100°C to 750°C, more preferably 300°C to 500°C, and further preferably 400°C to 450°C.

[0320] For example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%.

[0321] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10%. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can be carried out in a nitrogen gas or inert gas atmosphere, and then the heat treatment is carried out in an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10% to fill the oxygen that has been separated. The heat treatment can be carried out in an atmosphere of ultra-dry air (air with a water content of less than 20ppm, preferably less than 1ppm, and more preferably less than 10ppb).

[0322] By performing such a heat treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, the carbon in the metal oxide can be released as CO2 and CO, and the hydrogen in the metal oxide can be released as H2O. In addition, while removing the above impurities, the metal atoms and oxygen atoms are rearranged, thereby improving the crystallinity. Thus, a metal oxide with a layered crystal structure having high crystallinity can be formed, especially a metal oxide with the above CAAC structure.

[0323] For example, unlike a deposition method in which particles released from a target material are deposited, the ALD method is a deposition method in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio, for example. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as sputtering or CVD methods with fast deposition rates. For example, a method in which a first metal oxide is deposited by sputtering and a second metal oxide is deposited on the first metal oxide by the ALD method can be cited. For example, when the first metal oxide has a crystal portion, sometimes crystal growth occurs in the second metal oxide with the crystal portion as the core.

[0324] The ALD method can control the composition of the resulting film according to the amount of source gas introduced. For example, in the ALD method, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying and adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0325] [[Transistor including metal oxide]]

[0326] Next, the case where a metal oxide (oxide semiconductor) is used for a transistor is described.

[0327] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention in a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized transistor can be realized. For example, a transistor with a channel length of more than 2nm and less than 30nm can be manufactured.

[0328] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3Below, preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration of the oxide semiconductor film is to be reduced, it is preferred to reduce the impurity concentration of the oxide semiconductor film to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0329] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density.

[0330] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0331] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0332] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0333] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0334] Note that the short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0335] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0336] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0337] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is also lowered due to the conduction band lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Therefore, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0338] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the OS transistor is miniaturized. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm, and is greater than 1nm, greater than 3nm or greater than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is operating.

[0339] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, the cutoff frequency of the transistor under room temperature can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0340] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0341] [[Impurities in metal oxides]]

[0342] Here, the influence of each impurity in the metal oxide (oxide semiconductor) is described.

[0343] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0344] When an oxide semiconductor contains nitrogen, electrons are generated as carriers, which increases the carrier concentration and is easily converted to n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Alternatively, when an oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, it is further preferred that 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0345] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, thereby sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, an electron as a carrier is sometimes generated. In addition, sometimes electrons as carriers are generated because a portion of hydrogen is bonded to oxygen bonded to a metal atom. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×1019 atoms / cm 3 , and more preferably less than 5×10 18 atoms / cm 3 , preferably less than 1×10 18 atoms / cm 3 .

[0346] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0347] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0348] [Other semiconductor materials]

[0349] The semiconductor layer 113 may be referred to as a semiconductor layer including a channel formation region of the transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. As a semiconductor, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) may also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used for the semiconductor material.

[0350] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonds that are weaker than covalent bonds and ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0351] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0352] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.

[0353] As layered substances, for example, graphene, silicene, boron carbonitride and chalcogenides can be cited. In boron carbonitride as a layered substance, carbon atoms, nitrogen atoms and boron atoms are arranged on a plane in a hexagonal lattice structure. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to the 16th group, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides and 13th group chalcogenides can be cited.

[0354] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As transition metal chalcogenides that can be used for the semiconductor layer, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2) and zirconium selenide (typically ZrSe2) can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a semiconductor device with a large on-state current can be provided.

[0355] <Example 1 of Method for Manufacturing Semiconductor Device>

[0356] Hereinafter, as a method for manufacturing a semiconductor device according to one embodiment of the present invention, Figure 2A1 , Figure 2B and Figure 2C An example of a method for manufacturing a semiconductor device is shown.

[0357] Next, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer can be deposited by appropriately using a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0358] As the sputtering method, there can be RF sputtering method using a high frequency power supply as a sputtering power supply, DC sputtering method using a direct current power supply, and pulsed DC sputtering method changing the voltage applied to the electrode in a pulsed manner. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, or carbides using a reactive sputtering method.

[0359] Note that the CVD method can be divided into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0360] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. For example, the wiring, electrodes, and components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from plasma. At this time, the wiring, electrodes, or components included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur when the thermal CVD method that does not use plasma is used, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0361] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method using a reactant excited by plasma, or the like can be used.

[0362] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have high step coverage. In particular, the ALD method has high step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio, for example. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0363] In addition, when the CVD method is used, a film of any composition can be deposited according to the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while depositing. When depositing while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0364] When the ALD method is used, a film of any composition can be deposited by introducing multiple different precursors at the same time. Alternatively, when introducing multiple different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0365] In the drawings showing the method for manufacturing a semiconductor device according to one embodiment of the present invention, unless otherwise specified, A and A1 of each drawing are plan views. In addition, B of each drawing is a cross-sectional view along the dot-dash line A1-A2 of A and A1 of each drawing, and C of each drawing is a cross-sectional view along the dot-dash line A3-A4 of A and A1 of each drawing.

[0366] First, a substrate (not shown) is prepared, and an insulating layer 101 ( Fig.13A , Fig. 13B and Fig. 13C The insulating material described above can be used as appropriate for the insulating layer 101. The insulating layer 101 can be formed by a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0367] Next, a conductive layer 111 is formed on the insulating layer 101 ( Fig.13A , Fig. 13B and Fig. 13C ). For example, a conductive film to be the conductive layer 111 is formed and the conductive film is processed, whereby the conductive layer 111 can be formed. The conductive material that can be used for the conductive layer 111 described above can be used as appropriate for the conductive film to be the conductive layer 111.

[0368] The conductive film to be the conductive layer 111 can be formed by a deposition method such as sputtering, CVD, MBE, PLD, or ALD as appropriate. After the conductive film to be the conductive layer 111 is formed, a pattern is formed by, for example, photolithography, and the conductive film is processed by dry etching or wet etching according to the pattern, thereby forming the conductive layer 111. Here, processing the conductive film by dry etching is preferred because micro-processing can be performed.

[0369] Note that in the photolithography method, first, a resist is exposed through a mask. Next, a developer is used to remove or leave the exposed area to form a resist mask. Thus, a pattern is formed.

[0370] For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser or EUV light. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid such as water is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0371] Then, etching is performed through the resist mask, thereby processing the conductive film, semiconductor film, insulating film, etc. into a desired shape.

[0372] When dry etching is performed as the above-mentioned etching process, an etching gas containing halogen can be used as the etching gas, specifically, an etching gas containing one or more of fluorine, chlorine and bromine can be used. As the etching gas, for example, one or a mixed gas of two or more of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, NF3 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, CCl4 gas and BBr3 gas can be used. In addition, oxygen gas, carbonic acid gas, nitrogen gas, helium gas, argon gas, hydrogen gas or hydrocarbon gas can be appropriately added to the above-mentioned etching gas. The etching conditions can be appropriately set according to the etching object.

[0373] As a dry etching device, for example, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency voltages with different frequencies are applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used.

[0374] Next, an insulating layer 103 is formed on the insulating layer 101 and the conductive layer 111 ( Fig.13A , Fig. 13B and Fig. 13C). The insulating layer 103 can appropriately use the above-mentioned insulating materials. The insulating layer 103a can be appropriately formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Note that the insulating layer 103 is preferably flattened on its top surface by, for example, performing a chemical mechanical polishing (CMP: Chemical Mechanical Polishing) treatment after deposition. By performing a planarization treatment on the insulating layer 103, the conductive layer 117 can be appropriately formed in a subsequent step. In addition, a planarization treatment can be performed on the insulating layer 103, for example, after aluminum oxide is deposited by a sputtering method until it reaches the insulating layer 103. By performing this planarization treatment, the surface of the insulating layer 103 can be planarized and smoothed. By configuring the aluminum oxide on the insulating layer 103 and performing a planarization treatment, the end point of the planarization treatment can be easily detected.

[0375] Note that sometimes the planarization process may not be performed. In this case, the top surface of the insulating layer 103a has a convex curved surface shape. By not performing the planarization process, the manufacturing cost can be reduced and the yield can be improved. Thus, an inexpensive semiconductor device can be provided.

[0376] Next, a conductive layer 117 ( Fig.13A , Fig. 13B and Fig. 13C ). The conductive layer 117 can be formed by the same method as that which can be used for forming the conductive layer 111. A conductive material that can be used for the conductive layer 117 can be used as appropriate for the conductive film to be the conductive layer 117. Fig.7A1 , Fig.7A2 , Figure 7B and Figure 7C As shown, when the shape of the conductive layer 117 is planar, patterning by photolithography and processing of the conductive film using the pattern may not be necessary.

[0377] Next, an insulating layer 104 is formed on the insulating layer 103 and the conductive layer 117 ( Fig.13A , Fig. 13B and Fig. 13C ). The insulating layer 104 can be formed by the same method as that which can be used for forming the insulating layer 103. The insulating material described above can be used as appropriate for the insulating layer 104.

[0378] Here, the thickness of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in a region overlapping the conductive layer 111 corresponds to the channel length of the transistor 100. Thus, the thicknesses of the insulating layer 103, the conductive layer 117, and the insulating layer 104 can be appropriately set according to a design value of the channel length of the transistor 100.

[0379] Next, a conductive layer 112 is formed on the insulating layer 104 ( Fig.13A , Fig. 13B and Fig. 13C ). The conductive layer 112 can be formed by the same method as that which can be used for forming the conductive layer 111. The conductive material which can be used for the conductive layer 112 described above can be used as appropriate for the conductive film to be the conductive layer 112.

[0380] Next, a portion of the conductive layer 112, a portion of the insulating layer 104, and a portion of the conductive layer 117 are processed to form an opening 121 ( Fig.14A , Fig. 14B and Fig. 14C ). The opening 121 can be formed by, for example, photolithography and etching.

[0381] As described above, the side wall of the opening 121 is preferably perpendicular to the top surface of the conductive layer 111. By adopting this structure, the miniaturization of the transistor 100 can be achieved. In addition, the side wall of the opening 121 may also have a tapered shape. By having the side wall of the opening 121a have a tapered shape, for example, the coverage of the metal oxide film that will become the semiconductor layer 113a described later is improved, and defects such as voids can be reduced. Here, the maximum width of the opening 121 (the maximum diameter when the opening 121 is circular when viewed from a plane) is preferably miniature.

[0382] Since the aspect ratio of the opening 121a is high, it is preferable to process a portion of the conductive layer 112, a portion of the insulating layer 104, a portion of the conductive layer 117, and a portion of the insulating layer 103 by anisotropic etching. Since processing by dry etching is suitable for fine processing, it is particularly preferable. In addition, the structure can be performed under conditions that are different from each other. Note that depending on the processing conditions of the conductive layer 112, a portion of the insulating layer 104, a portion of the conductive layer 117, and a portion of the insulating layer 103, at least one of the inclination of the side surface of the conductive layer 112 of the opening 121, the inclination of the side surface of the conductive layer 117 of the opening 121, and the inclination of the side surface of the insulating layer 103 of the opening 121 may be different from the other inclinations.

[0383] Next, a heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed, for example, in a nitrogen gas or inert gas atmosphere. The heat treatment may also be performed under reduced pressure. By performing the heat treatment, impurities such as water in the insulating layer 103 and the insulating layer 104 may be reduced before the deposition of the metal oxide film that will become the semiconductor layer 113 described later.

[0384] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, for example, it is possible to prevent moisture from being absorbed by the insulating layer 103a as much as possible.

[0385] Next, the side surface of the opening 121 of the conductive layer 117 is oxidized to form an oxide region 117ox ( Fig.15A1 , Fig.15A2 , Fig. 15B and Fig. 15C ). Here, Fig.15A2 is omitted Fig.15A1 1. A plan view of the conductive layer 112 in FIG.

[0386] The oxidation treatment can be performed by microwave treatment in an oxygen-containing atmosphere. Fig. 15B and Fig. 15C The dashed arrows shown represent microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals, etc. In the following figures showing an example of a method for manufacturing a semiconductor device, the dashed arrows also represent microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals, etc.

[0387] For example, the microwave treatment conditions may refer to the microwave treatment conditions described in <Constituent materials of semiconductor device>. Note that the oxidation treatment method is not limited to microwave treatment, and oxygen plasma treatment or thermal oxidation treatment may be used, for example.

[0388] Here, a portion of the conductive layer 111 is exposed in the opening 121. In addition, the conductive layer 112 also has an exposed surface. As described above, the oxidation treatment is performed not only on the conductive layer 117 but also on the conductive layers 111 and 112. Thus, as described above, the conductive layers 111 and 112 can use a material that is less likely to be oxidized than the conductive layer 117 or a material that has conductivity even if oxidized, for example, a conductive material containing oxygen.

[0389] Next, a semiconductor film to be the semiconductor layer 113 is formed in such a manner as to be in contact with the bottom and side walls of the opening 121 and at least a portion of the top surface of the conductive film 112. As the semiconductor film, a semiconductor that can be used for the semiconductor layer 113 can be appropriately used, for example, a metal oxide film can be used. The semiconductor film can be appropriately formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, the semiconductor film is preferably formed in such a manner as to be in contact with the bottom and side walls of the opening 121 having a high aspect ratio. Therefore, when forming the semiconductor film, it is preferred to use a deposition method with good coverage, and more preferably to use a CVD method or an ALD method. The semiconductor film to be the semiconductor layer 113 can be, for example, an In-Ga-Zn oxide deposited by an ALD method.

[0390] In addition, when the semiconductor layer 113 has a stacked structure, the deposition methods of the layers included in the semiconductor layer 113 may be the same or different. FIG. 8A to FIG. 8C In the case of a two-layer structure of the semiconductor layer 113 a and the semiconductor layer 113 b as shown, the film to be the semiconductor layer 113 a may be deposited by sputtering, and the film to be the semiconductor layer 113 b may be deposited by ALD.

[0391] The metal oxide film deposited by the sputtering method tends to have crystallinity. Therefore, by using a crystalline metal oxide film as the semiconductor film to be the semiconductor layer 113a, the crystallinity of the metal oxide film can be improved when the metal oxide film is used as the semiconductor film to be the semiconductor layer 113b. In addition, even if pinholes or breaks are formed in the metal oxide film to be the semiconductor layer 113a deposited by the sputtering method, they can be filled by the metal oxide film to be the semiconductor layer 113b deposited by the ALD method with good coverage. In addition, both the semiconductor layer 113a and the semiconductor layer 113b can be deposited by the ALD method. As a result, in addition to the semiconductor layer 113b, the coverage of the semiconductor layer 113a can also be improved.

[0392] Here, the semiconductor film to be the semiconductor layer 113 is preferably formed in contact with the top surface of the conductive layer 111 in the opening 121, the insulating layer 103 in the opening 121, the oxide region 117ox, the insulating layer 104, and the side surfaces of the conductive layer 112, and the top surface of the conductive layer 112. By forming the semiconductor film in contact with the conductive layer 111, the conductive layer 111 is used as one of the source electrode and the drain electrode of the transistor 100. In addition, by forming the semiconductor film in contact with the conductive layer 112, the conductive layer 112 is used as the other of the source electrode and the drain electrode of the transistor 100.

[0393] In the case where a metal oxide film is used as the semiconductor film to be the semiconductor layer 113, it is preferred to perform the above-mentioned impurity removal treatment after depositing the metal oxide film, specifically, for example, microwave treatment. The details of the microwave treatment can be referred to the above description. Next, a heat treatment is preferably performed. The heat treatment can be performed within a temperature range that does not cause the above-mentioned metal oxide film to be polycrystallized, at a temperature of not less than 250°C and not more than 650°C, preferably not less than 400°C and not more than 600°C. The details of the heat treatment can be referred to the above description. As described above, the metal oxide film can be, for example, CAAC-OS, and a method for manufacturing a semiconductor device with high reliability can be provided.

[0394] Note that in the above process, the heat treatment is performed after the semiconductor film is deposited, but one embodiment of the present invention is not limited to this. Furthermore, the heat treatment may be performed in a later process.

[0395] Next, after the semiconductor film to be the semiconductor layer 113 is patterned by, for example, photolithography, it is processed by etching according to the pattern. Thus, the semiconductor layer 113a ( Fig.16A , Fig. 16B and Fig. 16C ). A portion of the semiconductor layer 113 is formed inside the opening 121. In addition, the semiconductor layer 113 is in contact with a portion of the side surface and the top surface of the conductive film 112. Through the above steps, the semiconductor layer 113 is formed in a manner having a region in contact with the top surface of the conductive layer 111, a region in contact with the side surface of the oxide region 117ox, a region in contact with the side surface of the conductive film 112, and a region in contact with the top surface of the conductive film 112, and having a region located inside the opening 121. In addition, in the opening 121, the semiconductor layer 113 can be formed in a manner having a region in contact with the side surface of the insulating layer 103 and a region in contact with the side surface of the insulating layer 104.

[0396] Next, an insulating layer 105 is formed on the semiconductor layer 113, the conductive layer 112, and the insulating layer 104. Fig.16A , Fig. 16B and Fig. 16C ). The insulating layer 105 can use the above-mentioned insulating materials as appropriate. The insulating layer 105 can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate. Here, the insulating layer 105 is formed in a manner in contact with the semiconductor layer 113 provided in the opening 121 with a high aspect ratio. Therefore, the insulating layer 105 is preferably deposited by a deposition method with good coverage, and more preferably by a CVD method or an ALD method. For example, silicon oxide is deposited as the insulating layer 105 by the ALD method.

[0397] Note that when the side wall of the opening 121 has a tapered shape, the deposition method of the insulating layer 105 is not limited to the CVD method or the ALD method. For example, the insulating layer 105 may be deposited by sputtering.

[0398] Next, the conductive layer 115 is formed so as to have a region located inside the opening 121 and a region facing the semiconductor layer 113 and the insulating layer 105. Fig.16A , Fig. 16B and Fig. 16C ). For example, the conductive layer 115 can be formed by forming a conductive film to be the conductive layer 115 over the insulating layer 105 and processing the conductive film. The conductive material that can be used for the conductive layer 115 described above can be used as appropriate for the conductive film to be the conductive layer 115.

[0399] The conductive film to be the conductive layer 115 can be formed by a deposition method such as sputtering, CVD, MBE, PLD, or ALD as appropriate. Here, the conductive film is preferably formed in contact with the insulating layer 105 provided in the opening 121 having a high aspect ratio. Therefore, when forming the conductive film to be the conductive layer 115, it is preferable to use a deposition method with good coverage or embedding properties, and more preferably, a CVD method, an ALD method, or the like.

[0400] Note that when the conductive film to be the conductive layer 115 is formed by a CVD method, the average surface roughness of the top surface of the conductive film may become large. In this case, for example, the conductive film may be planarized by a CMP method. In this case, a silicon oxide film or a silicon oxynitride film may be deposited on the conductive film to be the conductive layer 115 before the planarization treatment, and the planarization treatment may be performed until the silicon oxide film or the silicon oxynitride film is removed.

[0401] After forming a conductive film to be the conductive layer 115, patterning is performed by, for example, photolithography, and the conductive film is processed by dry etching or wet etching according to the pattern, thereby forming the conductive layer 115. Here, processing the conductive film by dry etching is preferred because micro-processing can be performed.

[0402] Here, if Fig.16A and Fig. 16C As shown, the side end of the conductive layer 115 is preferably located inside the side end of the semiconductor layer 113. Therefore, as described above, for example, parasitic capacitance formed by the conductive layer 112, the insulating layer 105, and the conductive layer 115 can be reduced.

[0403] Through the above steps, the transistor 100 including the conductive layer 111, the conductive layer 112, the semiconductor layer 113, the insulating layer 105, the conductive layer 115, and the conductive layer 117 can be formed. As described above, the conductive layer 111 is used as one of the source electrode and the drain electrode of the transistor 100, the conductive layer 112 is used as the other of the source electrode and the drain electrode of the transistor 100, the insulating layer 105 is used as the first gate insulating layer of the transistor 100, and the conductive layer 115 is used as the first gate electrode of the transistor 100. In addition, the conductive layer 117 is used as the second gate electrode of the transistor 100, and the oxide region 117ox is used as the second gate insulating layer of the transistor 100. Specifically, the region other than the oxide region 117ox of the conductive layer 117 is used as the second gate electrode of the transistor 100, and the oxide region 117ox of the conductive layer 117 is used as the second gate insulating layer of the transistor 100.

[0404] Next, an insulating layer 107 is formed to cover the transistor 100. Specifically, the insulating layer 107 is formed to cover the conductive layer 115 and the insulating layer 105 ( Figure 2A1 , Figure 2B and Figure 2C The above-mentioned insulating materials can be appropriately used for the insulating layer 107. The insulating layer 107 can be appropriately formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0405] As mentioned above, it is possible to produce Figure 2A1 , Figure 2B and Figure 2C A semiconductor device including a transistor 100 is shown.

[0406] <Example 2 of Method for Manufacturing Semiconductor Device>

[0407] Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. FIG. 4A to FIG. 4C An example of a method for manufacturing a semiconductor device is shown.

[0408] First, conduct FIG. 13A to FIG. 13C Here, the conductive layer 111 can be formed by forming a conductive film to be the conductive layer 111a and a conductive film to be the conductive layer 111b on the conductive film and processing the conductive films. As the conductive film to be the conductive layer 111a, a conductive material that can be used for the conductive layer 111a is appropriately used. In addition, as the conductive film to be the conductive layer 111b, a conductive material that can be used for the conductive layer 111b is appropriately used.

[0409] Next, a portion of the conductive layer 112, a portion of the insulating layer 104, a portion of the conductive layer 117, and a portion of the insulating layer 103 are processed to form an opening 121 ( Fig.17A and Fig. 17B ). Note that the floor plan can be referenced Fig.14A . Fig.17A Corresponds to Fig.14A The cross section is shown along the dot-dash line A1-A2. Fig. 17B Corresponds to Fig.14A The opening 121 can be connected with the cross section of the dotted line A3-A4. FIG. 14A to FIG. 14C The method shown is formed in the same way.

[0410] Next, the side surface of the opening 121 of the conductive layer 117 is oxidized to form an oxide region 117ox ( Fig. 17C and Fig.17D ). Note that the floor plan can be referenced Fig.15A1 and Fig.15A2 . Fig. 17C Corresponds to Fig.15A1 The cross section of the dotted line A1-A2 shown, Fig.17D Corresponds to Fig.15A1 The oxidation treatment can be carried out by Fig.15A1 , Fig.15A2 , Fig. 15B and Fig. 15C The method shown is carried out in the same way.

[0411] Next, the area of ​​the conductive layer 111b that overlaps with the opening 121 is removed. Thus, the opening 121 reaches the conductive layer 111a ( Fig.17E and Fig.17F ). Note that the floor plan can be referenced Fig.15A1 and Fig.15A2 . Fig.17E Corresponds to Fig.15A1 The cross section is shown along the dot-dash line A1-A2. Fig.17F Corresponds to Fig.15A1 The cross section is taken along the dashed line A3 - A4 shown in FIG. 1 . In some cases, the opening 121 does not reach the conductive layer 111 a , and a recess having a region overlapping with the opening 121 is formed in the conductive layer 111 b .

[0412] For example, a portion of the conductive layer 111b can be removed by processing the conductive layer 111b using a dry etching method or a wet etching method. Here, it is preferable to process the conductive layer 111b under a condition where the etching selectivity ratio between the conductive layer 111a and the conductive layer 111b is high, that is, under a condition where the conductive layer 111b is easily etched and the conductive layer 111a is not easily etched. In addition, when the conductive layer 111b is processed under a condition where the etching selectivity ratio between the conductive layer 111a and the conductive layer 111b is low, a recess having an area overlapping with the opening 121 is sometimes formed in the conductive layer 111a. In addition, it is preferable to process the conductive layer 111b under a condition where the etching selectivity ratio between the conductive layer 111b and the conductive layer 112 is high, that is, under a condition where the conductive layer 111b is easily etched and the conductive layer 112 is not easily etched. In this case, pattern formation is not required.

[0413] By conducting Fig.17E and Fig.17F In the process shown, even if the conductive layer 111b is oxidized by the above-mentioned oxidation treatment, at least a part of the oxidized region can be removed. As a result, as described above, the resistance of the contact interface between the conductive layer 111 and the semiconductor layer 113 can be reduced. Therefore, for example, when the transistor 100 is in the on state, the following situations can be suppressed: the current does not flow between the conductive layer 111 and the conductive layer 112 of the semiconductor layer 113; and the current flowing is reduced. In this way, a semiconductor device with high reliability can be provided. In addition, for example, a material with low oxidation resistance and high conductivity can be used for the conductive layer 111, thereby expanding the range of selection of the material of the conductive layer 111. As described above, for example, a conductive material with high conductivity can be used for one of the conductive layers 111a and the conductive layer 111b, and a conductive material containing oxygen can be used for the other of the conductive layer 111a and the conductive layer 111b. Note that, for example, in the case where the conductive layer 111 is a single layer, at least a part of the oxidized region of the conductive layer 111 can be removed by, for example, dry etching or wet etching after the above-mentioned oxidation treatment. In this case, a recessed portion having a region overlapping with opening 121 is formed in conductive layer 111 .

[0414] Next, proceed with FIG. 16A to FIG. 16C The steps shown in the figure and the steps thereafter are the same steps. Through the above steps, the following can be manufactured: FIG. 4A to FIG. 4C A semiconductor device including a transistor 100 is shown.

[0415] <Example 3 of Method for Manufacturing Semiconductor Device>

[0416] The following describes FIG. 13A to FIG. 16C The manufacturing method of the semiconductor device shown is an example of a different manufacturing method.

[0417] First, conduct FIG. 13A to FIG. 14C Next, the side surface of the opening 121 of the conductive layer 117 is processed so that the side surface is retreated ( Fig.18A1 , Fig.18A2 , Fig.18B and Fig.18C ). Thus, the recess 132 is formed by the insulating layer 103, the insulating layer 104 and the conductive layer 117. The processing of the above-mentioned side surface can be performed, for example, by isotropic etching. Here, it is preferred that the conductive layer 117 is processed under the condition that the etching selectivity ratio of the conductive layer 117 to the insulating layer 103, the insulating layer 104, the conductive layer 111 and the conductive layer 112 is high, that is, the conductive layer 117 is easily etched and the insulating layer 103, the insulating layer 104, the conductive layer 111 and the conductive layer 112 are not easily etched.

[0418] Fig.18A1 , Fig.18A2 , Fig.18B and Fig.18C The process shown in FIG. 1 can be regarded as a process in which the conductive layer 117 is processed in the horizontal direction (direction perpendicular to the Z direction) so that the side surface of the opening 121 of the conductive layer 117 is retreated. Fig.18A2 In the middle, the dotted line indicates Fig.18A1 The conductive layer 112 is shown without hatching.

[0419] As described above, by oxidizing the conductive layer 117 to form the oxide region 117ox, the volume of the conductive layer 117 including the oxide region 117ox may increase. Fig. 9C and Fig.9D As shown, the oxide region 117ox may have a region protruding in the opening 121. Due to the protruding region, for example, the semiconductor layer 113 may not be in contact with the conductive layer 111. Therefore, by making the side surface of the conductive layer 117 in the opening 121 recede, it is possible to suppress the oxide region 117ox from having a region protruding in the opening 121. Thus, for example, it is possible to suppress the semiconductor layer 113 from not being in contact with the conductive layer 111. Therefore, a method for manufacturing a semiconductor device with high yield can be provided. In addition, a semiconductor device with high reliability can be provided.

[0420] After the side surface of the opening 121 of the conductive layer 117 is retracted, the same process as in FIGS. 15A to 15B is performed. Fig. 16C As described above, it is possible to manufacture a Figure 2A1 , Figure 2B and Figure 2C In addition, when the width of the recess in the opening 121 is large, as shown in FIG. Fig.9A and Fig. 9BAs shown, the side surface of the oxide region 117 ox in the opening 121 may be located closer to the side surface of the conductive layer 111 than the side surfaces of the insulating layer 103 and the insulating layer 104 .

[0421] <Example 4 of Method for Manufacturing Semiconductor Device>

[0422] Hereinafter, as a method for manufacturing a semiconductor device according to one embodiment of the present invention, Fig. 6A and Figure 6B An example of a method for manufacturing a semiconductor device is shown.

[0423] First, conduct FIG. 13A to FIG. 14C Here, after forming the insulating layer 103a and the insulating layer 103b on the insulating layer 103a and planarizing the insulating layer 103b, the insulating layer 103c may be formed on the insulating layer 103b, thereby forming the insulating layer 103. Furthermore, after forming the insulating layer 104a and the insulating layer 104b on the insulating layer 104a and planarizing the insulating layer 104b, the insulating layer 104 may be formed on the insulating layer 104b, thereby forming the insulating layer 104. For example, planarization can be performed by CMP treatment.

[0424] The insulating layers 103a, 103b, 103c, 104a, 104b, and 104c can use the above-mentioned insulating materials as appropriate. For example, an insulator containing nitrogen can be used as the insulating layers 103a, 103c, 104a, and 104c. Alternatively, an insulator containing oxygen can be used as the insulating layers 103b and 104b.

[0425] Next, an insulating layer 106 is formed on the conductive layer 111, the conductive layer 112, and the insulating layer 104c. Fig.19A1 , Fig.19B and Fig.19C ). Here, Fig.19A2 is omitted Fig.19A1 1. The insulating layer 106 is formed so as to have a region in contact with the side surface of the conductive layer 117 at least in the opening 121. In addition, the insulating layer 106 can be formed so as to have a region in contact with the top surface of the conductive layer 111, the side surface of the insulating layer 103, and at least a portion of the side surface of the insulating layer 104 in the opening 121. Furthermore, the insulating layer 106 can be formed so as to have a region in contact with the side surface of the conductive layer 112, the top surface of the conductive layer 112, and at least a portion of the top surface of the insulating layer 104c.

[0426] The insulating layer 106 can use a material that can be used for the insulating layer 105, for example, an insulator containing oxygen can be used. For example, silicon oxide can be used as the insulating layer 106. Note that the insulating layer 106 can be formed by the same method as the method that can be used for forming the insulating layer 105. For example, the insulating layer 106 can be formed by an ALD method or a CVD method.

[0427] Next, the side surface of the opening 121 of the conductive layer 117 is oxidized to form an oxide region 117ox ( Fig.20A1 , Fig. 20B and Fig. 20C ). Here, Fig.20A2 is omitted Fig.20A1 The oxidation treatment can be performed by Fig.15A1 , Fig.15A2 , Fig. 15B and Fig. 15C The oxidation treatment can be carried out, for example, by microwave treatment in an oxygen-containing atmosphere.

[0428] By performing the above-mentioned oxidation treatment after forming the insulating layer 106 in a manner having a region in contact with the conductive layer 117, the oxide region 117ox becomes a region containing the components contained in the conductive layer 117 and the components contained in the insulating layer 106, whereby the conductive layer 117 and the insulating layer 106 can be alloyed. In this case, the oxide region 117ox can be referred to as an alloyed region. For example, when tantalum nitride is used as the conductive layer 117 and silicon oxide is used as the insulating layer 106, the oxide region 117ox can be a region containing tungsten, silicon, oxygen, and nitrogen. In addition, when tungsten is used as the conductive layer 117 and silicon oxide is used as the insulating layer 106, the oxide region 117ox can be a region containing tungsten, silicon, and oxygen.

[0429] Here, when the thickness of the insulating layer 106 is small, the conductive layer 117 is easily oxidized compared to the case where the thickness of the insulating layer 106 is large, thereby easily forming the oxide region 117ox, so it is preferred. The thickness of the insulating layer 106 is preferably greater than 0.1 nm and less than 15 nm, more preferably greater than 0.1 nm and less than 10 nm, further preferably greater than 0.1 nm and less than 5 nm, typically 1 nm. In addition, it is preferred that the thickness of the insulating layer 106 is set to be less than the thickness of the insulating layer 105 to be formed in the subsequent process. Preferably, at least a portion of the region of the insulating layer 106 that contacts the conductive layer 117 is a region having the above thickness.

[0430] Next, the insulating layer 106 ( Fig.20D and Fig.20E ). Fig.20D yes Fig.20A1 The cross-sectional view along the dotted line A1-A2 shown in FIG. Fig.20E yes Fig.20A1 The cross-sectional view along the dotted line A3-A4 shown in FIG. 1 . For example, the insulating layer 106 can be removed by a dry etching method or a wet etching method. Here, in the case where the insulating layer 106 is formed in a manner having a region in contact with the top surface of the insulating layer 104c, it is preferred that the material contained in the insulating layer 106 is different from the material contained in the insulating layer 104c. Furthermore, it is preferred that the insulating layer 106 is removed under a condition where the etching selectivity ratio between the insulating layer 104c and the insulating layer 106 is high, that is, under a condition where the insulating layer 106 is easily etched and the insulating layer 104c is not easily etched. Thus, when the insulating layer 106 is removed, the insulating layer 104 can be suppressed from being processed. In addition, since the insulating layer 106 is removed in the manufacturing process of the semiconductor device, it can be called a sacrificial layer.

[0431] Next, proceed with FIG. 16A to FIG. 16C As described above, it is possible to manufacture a Fig. 6A and Figure 6B 1. A semiconductor device of the transistor 100 shown in FIG. 1. Note that a portion of the insulating layer 106 may remain in the semiconductor device. For example, a portion of the insulating layer 106 may remain on the side wall of the opening 121. In addition, at least a portion of the boundary between the side wall of the opening 121 and the insulating layer 106 may not be confirmed.

[0432] Through and manufacturing Fig. 6A and Figure 6B Compared with the case of the structure shown in the figure, the insulating layer 103b and the insulating layer 104b are planarized for a longer time, and the Figure 6C and Fig.6D In addition, in the manufacturing FIG. 6A to FIG. 6D In the case of a semiconductor device having the structure shown in FIG. 1 , the insulating layer 106 may not be formed and the oxide region 117ox may be formed in the conductive layer 117. FIG. 6A to FIG. 6D In the case of a semiconductor device other than the semiconductor device having the structure shown in the figure, after the insulating layer 106 is formed, the oxide region 117 ox may be formed in the conductive layer 117 , and then the insulating layer 106 may be removed.

[0433] <Example 5 of Method for Manufacturing Semiconductor Device>

[0434] The following describes FIG. 13A to FIG. 16C The manufacturing method of the semiconductor device shown is an example of a different manufacturing method.

[0435] First, conduct FIG. 13A to FIG. 14C Next, by FIG. 16A to FIG. 16CThe semiconductor layer 113 ( Fig.21A , Fig.21B and Fig. 21C Then, the side surface of the opening 121 of the conductive layer 117 is oxidized to form an oxide region 117ox in the conductive layer 117 ( Fig.21D and Fig.21E ). Fig.21D yes Fig.21A The cross-sectional view along the dotted line A1-A2 shown in FIG. Fig.21E yes Fig.21A A cross-sectional view along the dashed line A3-A4 is shown.

[0436] For example, with Fig. 15B and Fig. 15C Likewise, the oxidation treatment can be carried out by microwave treatment in an oxygen-containing atmosphere. Fig.21D and Fig.21E In the illustrated example, the semiconductor layer 113 can be subjected to impurity removal treatment while oxidation treatment is being performed on the conductive layer 117. Heat treatment is preferably performed after oxidation treatment of the conductive layer 117. The oxidation treatment and heat treatment can be described above in detail.

[0437] Then, through FIG. 16A to FIG. 16C The insulating layer 105 and the conductive layer 115 are formed in the same manner as shown in the figure to form the transistor 100. Then, the insulating layer 107 is formed to cover the transistor 100. Through the above steps, a transistor including Figure 2A1 , Figure 2B and Figure 2C A semiconductor device of transistor 100 is shown.

[0438] As described above, in a method for manufacturing a semiconductor device of one embodiment of the present invention, a transistor is formed in a manner that a semiconductor layer, a first gate insulating layer, and a first gate electrode are arranged inside an opening portion in a second interlayer insulating layer formed on a first interlayer insulating layer and the first insulating layer. In addition, a transistor is formed in a manner that one of a source electrode and a drain electrode is arranged under the above-mentioned opening portion and the other of the source electrode and the drain electrode is arranged on the second interlayer insulating layer. In addition, a second gate electrode having the above-mentioned opening portion is formed between the first interlayer insulating layer and the second interlayer insulating layer, and the side surface in the opening portion of the second gate electrode is oxidized to use the oxide region as a second gate insulating layer. Through the above-mentioned process, a transistor having a short channel length and capable of controlling a threshold voltage can be manufactured. Therefore, according to one embodiment of the present invention, for example, a method for manufacturing a semiconductor device that can be driven at high speed and has good electrical characteristics can be provided.

[0439] <Configuration Example of Storage Device>

[0440] Hereinafter, an example in which the semiconductor device according to one embodiment of the present invention is used in a storage device will be described.

[0441] Fig.22A1 1 is a plan view showing a configuration example of a memory device according to one embodiment of the present invention. The memory device according to one embodiment of the present invention includes a memory cell 150 including a transistor 100 and a capacitor 200 . Fig.22A2 is omitted Fig.22A1 1 is a plan view of components of the transistor 100 in FIG. 1 , and shows an example of the structure of the capacitor 200. Fig. 22B yes Fig.22A1 The cross-sectional view along the dotted line A1-A2 shown in FIG. Fig. 22C yes Fig.22A1 A cross-sectional view along the dashed line A3-A4 is shown.

[0442] exist Fig.22A1 , Fig. 22B and Fig. 22C In the memory device shown, a conductive layer 211 and a capacitor 200 on the conductive layer 211 are included between the insulating layer 101, the insulating layer 103, and the conductive layer 111. In addition, the memory device includes an insulating layer 203 on the conductive layer 211 and an insulating layer 209 on the insulating layer 203. Here, the conductive layer 211 can be provided in a planar shape. In addition, the insulating layer 203 and the insulating layer 209 are used as interlayer insulating layers.

[0443] The insulating layer 203 includes an opening 221 that reaches the conductive layer 211 . Fig.22A1 and Fig.22A2 An example is shown in which the shape of the opening 221 when viewed from the plane is circular. When the planar shape of the opening 221 is circular, the processing accuracy when forming the opening 221 can be improved, thereby forming a fine-sized opening 221. Note that the planar shape of the opening 221 is not limited to a circle, and can have the same shape as the shape that the opening 121 can have.

[0444] Capacitor 200 includes conductive layer 214, insulating layer 205, and conductive layer 215. Conductive layer 214 and conductive layer 215 are used as a pair of electrodes of capacitor 200, and insulating layer 205 is used as a dielectric layer of capacitor 200. Capacitor 200 may constitute a MIM (Metal-Insulator-Metal) capacitor.

[0445] The conductive layer 214 covers the opening 221 and is provided to have a region located inside the opening 221. The conductive layer 214 may have a shape along the top surface of the conductive layer 211 and the side and top surfaces of the insulating layer 203. Thus, the conductive layer 214 has a recessed portion at a position overlapping the opening 221. The conductive layer 214 may have a region in contact with the top surface of the conductive layer 211, a region in contact with the side surface of the insulating layer 203, and a region in contact with the top surface of the insulating layer 203.

[0446] The insulating layer 205 covers the opening 221 and is provided so as to have a region located inside the opening 221. The insulating layer 205 is provided on the conductive layer 214 and the insulating layer 203. The insulating layer 205 may have a shape along the top surface and the side surface of the conductive layer 214 and the top surface of the insulating layer 203. Since the insulating layer 205 has a shape along the top surface and the side surface of the conductive layer 214, the insulating layer 205 has a recessed portion at a position overlapping with the opening 221. The insulating layer 205 may have a region in contact with the top surface of the conductive layer 214, a region in contact with the side surface of the conductive layer 214, and a region in contact with the top surface of the insulating layer 203.

[0447] The conductive layer 215 is disposed on the insulating layer 205 and may have an area in contact with the top surface and the side surface of the recess of the insulating layer 205. The conductive layer 215 has an area located inside the opening 221. The conductive layer 215 and the conductive layer 214 are opposed to each other, sandwiching the insulating layer 205 not only at the bottom of the opening 221 but also along the side wall. Thus, the deeper the depth of the opening 221, the larger the capacitance value per unit area of ​​the capacitor 200 can be. Therefore, the read operation of the storage device can be stably performed, and a storage device with high reliability can be provided. In addition, even if the occupied area of ​​the capacitor 200 is small, the capacitance value can be ensured, thereby providing a miniaturized storage device and a highly integrated storage device. As described above, both a small storage device and a large-capacity storage device can be provided. Here, the conductive layer 214 can cover the side and bottom surfaces of the conductive layer 215 through the insulating layer 205 inside the opening 221. For example, inside the opening 221, the insulating layer 205 may have an area in contact with the side of the conductive layer 214, an area in contact with the top surface of the recessed portion of the conductive layer 214, an area in contact with the side of the conductive layer 215, and an area in contact with the bottom surface of the conductive layer 215.

[0448] exist Fig.22A1 , Fig.22A2 , Fig. 22B and Fig. 22C, an example is shown in which the side end of the conductive layer 215 is located inside the side end of the conductive layer 214 in both the X direction and the Y direction. Note that the side end of the conductive layer 215 may be located outside the side end of the conductive layer 214 in one or both of the X direction and the Y direction.

[0449] Capacitor 200 is a capacitor in which conductive layer 214 and insulating layer 205 are stacked along the side surfaces of insulating layer 203 and the top surface of conductive layer 211, and conductive layer 215 is provided on insulating layer 205 so as to fit into opening 221. The capacitor having the above structure can be called a trench capacitor or a trench capacitor.

[0450] The sidewall of the opening 221 is preferably perpendicular to the top surface of the conductive layer 211. In this case, the opening 221 has, for example, a cylindrical shape. By adopting this structure, a miniaturized storage device and a highly integrated storage device can be provided. In addition, the sidewall of the opening 221 can be, for example, FIG. 5A to FIG. 5D The side walls of the opening 121 shown in FIG. 1 are tapered.

[0451] The insulating layer 209 covers the side surface of the conductive layer 215 outside the opening 221. The insulating layer 209 has, for example, a region outside the opening 221 that contacts the side surface of the conductive layer 215. The insulating layer 209 and the conductive layer 215 are flattened, and the top surface of the insulating layer 209 and the top surface of the conductive layer 215 may be consistent or approximately consistent. Note that Fig. 22B and Fig. 22C Although the example in which the insulating layer 205 is provided in a planar shape is shown, the side end of the insulating layer 205 may be aligned or substantially aligned with the side end of the conductive layer 215. For example, by processing the insulating layer 205 using the same pattern as the conductive layer 215, the side end of the insulating layer 205 may be aligned or substantially aligned with the side end of the conductive layer 215.

[0452] In order to form Fig.22A1 , Fig.22A2 , Fig. 22B and Fig. 22C In the capacitor 200 shown, after forming the conductive layer 214 and the insulating layer 205, a conductive film to be the conductive layer 215 is formed on the insulating layer 205. Next, for example, a pattern is formed by photolithography and the conductive film is processed by dry etching or wet etching according to the pattern to form the conductive layer 215. Then, the insulating layer 209 is formed on the conductive layer 215 and the insulating layer 205 and the insulating layer 209 is planarized by, for example, CMP, so that the top surface of the conductive layer 215 is exposed. At this time, for example, in order to easily form the transistor 100 on the capacitor 200, it is preferable to planarize the top surface of the conductive layer 215. The above is an example of a method for manufacturing the capacitor 200.

[0453] Hereinafter, components of a storage device according to one embodiment of the present invention will be described.

[0454] A single layer or a stacked layer of the conductor described in the above-mentioned [Conductor] can be used as the conductive layer 211. For example, a conductive material having high conductivity, such as tungsten, can be used as the conductive layer 211.

[0455] In addition, as the conductive layer 211, a single layer or a stack of a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion can be used. For example, titanium nitride or indium tin oxide with silicon added can also be used. In addition, a structure in which titanium nitride is stacked on tungsten can also be provided. Alternatively, a structure in which a first titanium nitride, tungsten, and a second titanium nitride are stacked in sequence can also be provided. By adopting such a structure, oxidation of the conductive layer 211 by the insulating layer 203 can be suppressed when an oxide insulator is used for the insulating layer 203.

[0456] Since the insulating layer 203 and the insulating layer 209 are used as interlayer insulating layers, their relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer insulating layer, the parasitic capacitance generated between the wirings can be reduced. As the insulating layer 203 and the insulating layer 209, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in the above [Insulator] can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0457] As the conductive layer 214 and the conductive layer 215, a single layer or a stack of the conductive materials described in the above [Conductor] can be used. As the conductive layer 214 and the conductive layer 215, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. In addition, it is also possible to have a structure in which tantalum nitride is stacked on titanium nitride. By adopting such a structure, when an oxide insulator is used for the insulating layer 205, the conductive layer 214 and the conductive layer 215 can be inhibited from being oxidized by the insulating layer 205. In addition, when an oxide insulator is used for the insulating layer 203, the conductive layer 214 can be inhibited from being oxidized by the insulating layer 203. And, when an oxide insulator is used for the insulating layer 209, the conductive layer 215 can be inhibited from being oxidized by the insulating layer 209.

[0458] As the insulating layer 205, it is preferable to use a material having a high relative dielectric constant as described in the above [Insulator], i.e., a so-called high-k material. By using the high-k material for the insulating layer 205, the thickness of the insulating layer 205 can be increased to a level that can suppress leakage current and can fully ensure the capacitance value of the capacitor 200.

[0459] In addition, as the insulating layer 205, it is preferred to stack an insulating layer composed of a high-k material, and it is preferred to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the high-k material. For example, as the insulating layer 205, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide as the insulating layer 205, the dielectric strength of the insulating layer 205 can be increased and the electrostatic destruction of the capacitor 200 can be suppressed.

[0460] Alternatively, a material having ferroelectricity may be used as the insulating layer 205. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J1 to hafnium oxide (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum and strontium, etc.) can be cited. Here, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J2 to zirconium oxide (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum and strontium, etc.) can be cited. In addition, the ratio of the number of atoms of zirconium atoms to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO) or barium titanate with a perovskite structure.

[0461] Fig.22D1 It is shown Fig.22A1 , Fig. 22B and Fig. 22C A circuit diagram showing the connection relationship between the transistor 100 and the capacitor 200 included in the memory cell 150 shown. One of the source and the drain of the transistor 100 is electrically connected to one electrode of the capacitor 200. The other of the source and the drain of the transistor 100 is electrically connected to the wiring BL. The first gate of the transistor 100 is electrically connected to the wiring WL. The second gate of the transistor 100 is electrically connected to the wiring BG. The other electrode of the capacitor 200 is electrically connected to the wiring PL.

[0462] Wiring BL corresponds to conductive layer 112, wiring WL corresponds to conductive layer 117, wiring BG corresponds to conductive layer 117, and wiring PL corresponds to conductive layer 211. In other words, conductive layer 112 has a region used as wiring BL, conductive layer 115 has a region used as wiring WL, conductive layer 117 has a region used as wiring BG, and conductive layer 211 has a region used as wiring PL. In addition, conductive layer 214 may also have a region used as wiring PL.

[0463] The transistor 100 is used as a switch and has a function of controlling writing of data to the memory cell 150 and reading of data from the memory cell 150. By turning on the transistor 100, data is written to the memory cell 150 or read from the memory cell 150. By turning off the transistor 100, data written to the memory cell 150 is retained.

[0464] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of transistor 100 used as a switch. Wiring PL is used as a constant potential line connected to capacitor 200. In addition, the potential of wiring BG is the potential of the second gate of transistor 100.

[0465] Fig.22D2 1 is a circuit diagram showing a configuration example of a memory cell 150A. The memory cell 150A has a Fig.22D1 The memory cell 150 in the embodiment of the present invention has a structure in which a transistor 151 is added. In the memory cell 150A, one of the source and drain of the transistor 100 and one electrode of the capacitor 200 are electrically connected to the gate of the transistor 151. The other of the source and drain of the transistor 100 is electrically connected to the wiring WBL. One of the source and drain of the transistor 151 is electrically connected to the wiring RBL. The other of the source and drain of the transistor 151 is electrically connected to the wiring SL.

[0466] Fig.22D2 Although an example in which the second gate electrode is not provided in the transistor 151 is shown, the second gate electrode may be provided in addition to the first gate electrode in the transistor 151. In this case, for example, a constant potential or a potential that is the same as the potential of the first gate electrode of the transistor 151 may be supplied to the second gate electrode of the transistor 151. In addition, in a case other than the case of reading data from the memory cell 150A, the potential of the second gate potential of the transistor 151 may be made different.

[0467] The wiring WBL is used as a bit line for writing data and is referred to as a write bit line. The wiring RBL is used as a bit line for reading data and is referred to as a read bit line. The wiring SL is used as a constant potential line.

[0468] In the memory cell 150A, when the transistor 100 is turned on, data is written through the wiring WBL. At this time, when the transistor 151 is an n-channel transistor, the potential of the wiring PL is low. In addition, by turning off the transistor 100 and changing the potential of the wiring PL from a low potential to a high potential, a current according to the data stored in the memory cell 150A flows from the wiring SL to the wiring RBL, thereby reading data from the memory cell 150A. Therefore, in the memory cell 150A, the wiring PL is supplied with a pulse signal (a signal whose potential changes during a specific operation). In addition, a pulse signal may be supplied to the wiring SL. In this case, a constant potential may be supplied to the wiring PL.

[0469] The current flowing between the source and the drain of the OS transistor in the off state, that is, the leakage current is extremely small. Therefore, by using the OS transistor as the transistor 100, the charge corresponding to the data stored in the memory cell can be maintained in the capacitor 200 for a long period of time. Therefore, the data can be maintained in the memory cell for a long period of time. Therefore, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be fully reduced. In addition, since the frequency characteristics of the OS transistor are high, data can be written to the memory cell at a high speed and data can be read from the memory cell at a high speed.

[0470] The transistor 151 may be a transistor having a larger on-state current than the OS transistor, for example, a Si transistor. Thus, data can be read out from the memory cell 150A at high speed. In addition, an OS transistor can be used for the transistor 151. In this case, all transistors included in the memory cell 150A can be of the same type. Thus, for example, all transistors included in the memory cell 150A can be formed by the same process.

[0471] Fig.23A , Fig. 23B and Fig.23C Show not set Fig.22A1 , Fig. 22B and Fig. 22C Examples of conductive layer 111 and insulating layer 209 are shown. Fig. 23B and Fig.23C An example is shown in which the opening 121 reaches the conductive layer 215 and the bottom surface of the semiconductor layer 113 is in contact with the conductive layer 215. Fig. 23B and Fig.23C An example is shown in which the insulating layer 103 covers a part of the side surface and the top surface of the conductive layer 215 .

[0472] exist FIG. 23A to FIG. 23CIn the illustrated example, the conductive layer 215 is used as one of the source electrode and the drain electrode of the transistor 100. In this case, the conductive layer 215 is preferably made of the same material as that which can be used for the conductive layer 111. For example, the conductive layer 215 is preferably made of a material that is less likely to be oxidized than the conductive layer 117 or a material that is conductive even when oxidized.

[0473] Fig.24A 1 is a plan view showing an example of a memory device in which two memory cells 150 (hereinafter referred to as a memory cell 150a and a memory cell 150b) are connected to the same wiring. Fig. 24B yes Fig.24A A cross-sectional view along the dashed line A3-A4 is shown.

[0474] Here, Fig.24A and Fig. 24B The memory cell 150a and the memory cell 150b shown in the figure have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 200a and a transistor 100a, and the memory cell 150b includes a capacitor 200b and a transistor 100b. Fig.24A and Fig. 24B In the storage device shown, the Fig.22A1 , Fig. 22B and Fig. 22C Components of the storage device shown in the figure that have the same functions are denoted by the same reference numerals.

[0475] like Fig.24A and Fig. 24B As shown, the conductive layer 115 used as the wiring WL is provided in the memory cell 150a and the memory cell 150b respectively. In addition, the conductive layer 112 used as a part of the wiring BL is provided in both the memory cell 150a and the memory cell 150b. In other words, the conductive layer 112 has a region in contact with the semiconductor layer 113 of the memory cell 150a and a region in contact with the semiconductor layer 113 of the memory cell 150b. In addition, an insulating layer 109 used as an interlayer insulating layer is provided on the insulating layer 107.

[0476] Here, Fig.24A and Fig. 24BThe memory device shown includes a conductive layer 141 and a conductive layer 142 which are electrically connected to the memory cells 150a and the memory cells 150b and are used as plugs (which may also be referred to as connection electrodes). The conductive layer 141 is arranged in an opening formed in the insulating layer 101, the insulating layer 203, the insulating layer 205, the insulating layer 209, the insulating layer 103, and the insulating layer 104, and is in contact with the bottom surface of the conductive layer 112. In addition, the conductive layer 142 is arranged in an opening formed in the insulating layer 109, the insulating layer 107, and the insulating layer 105, and is in contact with the top surface of the conductive layer 112. In addition, as the conductive layer 141 and the conductive layer 142, a conductive material that can be used for the conductive layer 112 can be used.

[0477] Since the insulating layer 109 is used as an interlayer insulating layer, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer insulating layer, the parasitic capacitance generated between the wirings can be reduced. As the insulating layer 109, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in the above [Insulator] can be used.

[0478] Note that the concentration of impurities such as water and hydrogen in the insulating layer 109 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0479] The conductive layers 141 and 142 are used as plugs or wirings for electrically connecting circuit elements, wirings, electrodes or terminals such as switches, transistors, capacitors, inductors, resistors and diodes with the memory cells 150a and 150b. For example, the following structure can be adopted: the conductive layer 141 and the wirings provided at Fig. 24B The read amplifier (not shown) under the storage device shown is electrically connected, and the conductive layer 142 is connected to the Fig. 24B In this case, the conductive layer 141 and the conductive layer 142 are used as a part of the wiring BL. Fig. 24B By arranging a storage device above or below the storage device shown, the storage capacity per unit area can be increased.

[0480] In addition, the memory cell 150a and the memory cell 150b are linearly symmetrical with the perpendicular bisector of the dot-dash line A3-A4 as the axis of symmetry. Therefore, the transistor 100a and the transistor 100b are also arranged at symmetrical positions with the conductive layer 141 and the conductive layer 142 sandwiched therebetween. Here, the conductive layer 112 also serves as the other of the source electrode and the drain electrode of the transistor 100a and the other of the source electrode and the drain electrode of the transistor 100b. In addition, the transistor 100a and the transistor 100b share the conductive layer 141 and the conductive layer 142 used as the plug. In this way, by adopting the above structure as the connection relationship between the two transistors and the plug, a storage device that can achieve miniaturization or high integration can be provided.

[0481] In addition, the conductive layer 211 used as the wiring PL may be provided in each of the memory cells 150a and 150b, or may be provided in both of the memory cells 150a and 150b. Similarly, the conductive layer 117 used as the wiring BG may be provided in each of the memory cells 150a and 150b, or may be provided in both of the memory cells 150a and 150b. Fig. 24B As shown, the conductive layer 211 is provided in a manner separated from the conductive layer 141 to prevent the conductive layer 211 and the conductive layer 141 from being short-circuited. Similarly, the conductive layer 117 is provided in a manner separated from the conductive layer 141 to prevent the conductive layer 117 and the conductive layer 141 from being short-circuited.

[0482] In addition, by arranging the memory cells 150 in a three-dimensional manner and in a matrix, a memory cell array can be formed. As an example of a memory cell array, Fig.25A and Fig.25B An example of a storage device in which two×four×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction is shown. Fig.25A is a plan view showing a structural example of a storage device. Fig.25B yes Fig.25A A cross-sectional view along the dot-dash line A3-A4 in FIG.

[0483] Here, Fig.25A and Fig.25B The memory cells 150a to 150d shown have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 200a and a transistor 100a, the memory cell 150b includes a capacitor 200b and a transistor 100b, the memory cell 150c includes a capacitor 200c and a transistor 100c, and the memory cell 150d includes a capacitor 200d and a transistor 100d. Fig.25A and Fig.25B In the storage device shown, the Fig.22A1 , Fig.22A2 , Fig. 22B and Fig. 22C Components of the storage device shown in the figure that have the same functions are denoted by the same reference numerals.

[0484] Hereinafter, a collection of the plurality of storage cells 150 is referred to as a memory cell. Fig.25A and Fig.25B In the storage device shown, a memory unit 160 including a storage unit 150a, a storage unit 150b, a storage unit 150c, and a storage unit 150d is provided. Fig.25A and Fig.25B Memory cells 160 [1, 1] to 160 [4, 2] are shown. Memory cells 160 [1, 1] to 160 [4, 1] are stacked in sequence. In addition, memory cells 60 [1, 2] to 160 [4, 2] are stacked in sequence. And, in the X direction, memory cells 160 [1, 2] to 160 [4, 2] are adjacent to memory cells 160 [1, 1] to 160 [4, 1].

[0485] like Fig.25B As shown in FIG. 1 , in the memory cell 160 , the memory cell 150 c is arranged outside the memory cell 150 a and the memory cell 150 d is arranged outside the memory cell 150 b with the conductive layer 141 as the center. In other words, it can also be said that Fig.24A and Fig. 24B The storage device shown is in Fig.24A and Fig. 24B The illustrated storage device has a storage unit 150c disposed adjacent to the storage unit 150a and a storage unit 150d disposed adjacent to the storage unit 150b.

[0486] like Fig.25A and Fig.25B As shown, the memory cells 150 adjacent to each other in the X direction share the conductive layer 115 used as the wiring WL. In addition, the conductive layer 112 used as a part of the wiring BL is shared in the same memory cell. In other words, the conductive layer 112 has a region in contact with the semiconductor layer 113 in each of the memory cells 150a to 150d.

[0487] The conductive layer 141 is disposed between the conductive layers 112 included in the memory cells adjacent to each other in the Z direction. Fig.25B As shown in FIG. 1 , the conductive layer 141 is provided in contact with the top surface of the conductive layer 112 in the memory cell 160 [1, 1] and the bottom surface of the conductive layer 112 in the memory cell 160 [2, 1]. In this way, the conductive layer 112 and the conductive layer 141 provided in each memory cell 160 form the wiring BL. The conductive layer 141 is electrically connected to the conductive layer provided in Fig.25BThus, by Fig.25B In the memory device shown, a plurality of memory cells are stacked to increase the storage capacity per unit area.

[0488] In addition, the memory cell 150a and the memory cell 150c and the memory cell 150b and the memory cell 150d are linearly symmetrical with the perpendicular bisector of the dot-dash line A3-A4 as the symmetry axis. Therefore, the transistor 100a and the transistor 100c and the transistor 100b and the transistor 100d are also arranged at symmetrical positions with the conductive layer 141 sandwiched therebetween. Here, the conductive layer 112 is used as the other of the source electrode and the drain electrode of the transistor 100a to the transistor 100d. In addition, the transistor 100a to the transistor 100d share the conductive layer 141 used as a plug. In this way, by adopting the above structure as the connection relationship between the four transistors and the plug, a storage device capable of miniaturization or high integration can be provided.

[0489] like Fig.25B As shown, by stacking a plurality of memory cells 150, the cells can be configured in an integrated manner without increasing the occupied area of ​​the memory cell array. That is, a 3D memory cell array can be constructed. Note that Fig.25A and Fig.25B Although an example of a structure having four stacked layers including two memory cells 160 is shown, one embodiment of the present invention is not limited thereto. The memory device may include one layer including at least one memory cell 150 or two or more layers may be stacked.

[0490] Fig.25A and Fig.25B 1 shows an example of a structure in which a conductive layer 141 serving as a plug is arranged between memory cells 150. In other words, Fig.25B The structure shown is that the conductive layer 141 serving as a plug is arranged inside the memory cell 160. Note that one embodiment of the present invention is not limited to this. The conductive layer 141 may be arranged outside the memory cell.

[0491] As an example of a memory cell array, Fig.26A and Fig.26B An example of a storage device is shown in which three×three×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction. Fig.26A is a plan view showing a structural example of a storage device. Fig.26B yes Fig.26A A cross-sectional view of the dotted line A3-A4. Fig.26B In FIG. 1 , the layer in which the storage unit 150 is provided is the layer 170 , and an example in which the layers 170 [ 1 ] to 170 [ 4 ] are provided in sequence is shown.

[0492] Fig.26A and Fig.26B An example is shown in which the conductive layer 141 is provided outside the region where the memory cell 150 is provided. The conductive layer 141 can be electrically connected to the conductive layer 212 provided in the upper layer of the layer including the conductive layer 141. For example, the conductive layer 141 provided in the layer 170[1] is electrically connected to the conductive layer 212 provided in the layer 170[2]. In addition, for example, the conductive layer 212 provided in the layer 170[2] is provided in the same layer as the conductive layer 211 included in the layer 170[2]. That is, the conductive layer 212 can be formed by the same process as the conductive layer 211.

[0493] Notice, Fig.26A and Fig.26B The structure in which conductive layer 141 is electrically connected to conductive layer 212 disposed on an upper layer of a layer including conductive layer 141 is shown, but one embodiment of the present invention is not limited thereto. For example, conductive layer 141 may be electrically connected to conductive layer 212 disposed in a layer including conductive layer 141. For example, conductive layer 141 disposed in layer 170[1] may be electrically connected to conductive layer 212 disposed in layer 170[1].

[0494] Fig. 27 It is shown Fig.25B FIG. 1 is a diagram showing an example of a structure of a transistor 300 in a lower layer of memory cells 160 [ 1 , 1 ] to 160 [ 4 , 1 ] shown in FIG. Fig. 27 An example in which the gate electrode of the transistor 300 is electrically connected to the conductive layer 141 serving as a part of the wiring BL is shown. The transistor 300 may be a transistor provided in a driver circuit of a circuit having a function of controlling the driving of the semiconductor device of one embodiment of the present invention. For example, Fig. 27 The transistor 300 shown may be a transistor included in a bit line driver circuit that controls writing and reading of data in the memory cell 150 , and may be, for example, a transistor included in an amplifier of the bit line driver circuit.

[0495] The transistor 300 is provided on a substrate 311 and includes a conductive layer 316 used as a gate electrode, an insulating layer 315 used as a gate insulating layer, a semiconductor region 313 formed by a portion of the substrate 311, a low resistance region 314a used as one of a source region and a drain region, and a low resistance region 314b used as the other of the source region and the drain region. The transistor 300 may be an n-channel transistor or a p-channel transistor.

[0496] exist Fig. 27In the example shown, the transistor 300 is provided so as to overlap with the memory cell 160. Thus, the wiring BL used as the bit line can be shortened, and the parasitic capacitance (also referred to as the bit capacitance) formed by the wiring BL can be reduced. Therefore, even if the storage capacitance of the memory cell 150 is reduced, the difference between the potential of the wiring BL when data with a value of "1" is read from the memory cell 150 and the potential of the wiring BL when data with a value of "0" is read from the memory cell 150 can be maintained. Thus, even if the storage capacitance of the memory cell 150 is reduced, the semiconductor device of one embodiment of the present invention can correctly read the data held in the memory cell 150. Since the storage capacitance of the memory cell 150 can be reduced, for example, the capacitance value of the capacitor 200 can be reduced. Therefore, the area occupied by the memory cell 150 can be reduced. As described above, a memory device capable of miniaturization or high integration can be provided.

[0497] Here, Fig. 27 The semiconductor region 313 (a part of the substrate 311) in which the channel is formed of the transistor 300 shown has a convex shape. In addition, a conductive layer 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. In addition, a material that adjusts the work function can also be used for the conductive layer 316. Since this transistor 300 utilizes the convex portion of the semiconductor substrate, it is called a FIN-type transistor. In addition, an insulating layer used as a mask for forming the convex portion can also be included in a manner that contacts the upper portion of the convex portion. In addition, a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, but an SOI substrate can also be processed to form a semiconductor film having a convex shape.

[0498] Notice, Fig. 27 The transistor 300 shown is an example, and therefore the structure is not limited thereto, and an appropriate transistor can be used according to the circuit structure or driving method.

[0499] A wiring layer including an interlayer insulating layer, wiring, and plugs may also be provided between each structure. In addition, a plurality of wiring layers may be provided according to the design. Here, in a conductive layer having the function of a plug or a wiring, the same symbol is sometimes used to represent a plurality of structural elements. In addition, in this specification, a wiring and a plug electrically connected to the wiring may also be one structural element. That is, a part of the conductive layer is sometimes used as a wiring, and a part of the conductive layer is sometimes used as a plug.

[0500] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked as interlayer insulating layers over the transistor 300. Furthermore, a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layers 328 and 330 are used as plugs or wirings.

[0501] As described above, the layer used as the interlayer insulating layer may also be planarized. For example, in order to improve the planarity, the top surface of the insulating layer 322 may also be planarized by a planarization process using a CMP method or the like.

[0502] A wiring layer may also be provided on the insulating layer 326 and the conductive layer 330. Fig. 27 In the embodiment, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. Furthermore, a conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 is used as a plug or a wiring.

[0503] The insulating layer 101 is provided over the insulating layer 354 and the conductive layer 356. Furthermore, the conductive layer 141 is provided over the conductive layer 356. For example, the conductive layer 141 has a region in contact with the top surface of the conductive layer 356, the conductive layer 356 has a region in contact with the top surface of the conductive layer 330, and the conductive layer 330 has a region in contact with the conductive layer 316. Thus, the conductive layer 141 functioning as a part of the wiring BL is electrically connected to the conductive layer 316 functioning as the gate electrode of the transistor 300.

[0504] The insulating layer 352 and the insulating layer 354 which function as interlayer insulating layers can use the same material as that which can be used for the insulating layer 101 , for example.

[0505] As a conductive layer used as a plug or wiring, for example, as conductive layer 328, conductive layer 330, and conductive layer 356, the conductive layer described in the above [Conductor] can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferred. In addition, it is preferably formed using a low-resistance conductive material such as aluminum or copper. When a low-resistance conductive material is used, the wiring resistance can be reduced.

[0506] Fig.28A is a plan view showing a structural example of a storage device according to one embodiment of the present invention, wherein four in the X direction and four in the Y direction, i.e., a total of sixteen Fig.22A1 The area of ​​the storage unit 150 is shown. Fig.28A Conductive layer 115 serving as wiring WL, conductive layer 112 serving as wiring BL, and opening 121 are shown. In addition, memory cell 150 is provided in a region where conductive layer 115, conductive layer 112, and opening 121 overlap with each other. In other words, opening 121 is provided in a region where conductive layer 112 and conductive layer 115 intersect.

[0507] Fig.28AA structure in which the memory cells 150 are arranged in a matrix is ​​shown. In addition, a structure in which the openings 121 are arranged in a matrix is ​​also shown. In addition, a structure in which the conductive layer 115 extends in the X direction and the conductive layer 112 extends in the Y direction is also shown. In other words, a structure in which the conductive layer 115 is orthogonal to the conductive layer 112 is shown. In addition, a structure in which the width of the conductive layer 115 in a direction (Y direction) perpendicular to the extending direction of the conductive layer 115 is constant and the width of the conductive layer 112 in a direction (X direction) perpendicular to the extending direction of the conductive layer 112 is constant is also shown. Note that one embodiment of the present invention is not limited to this.

[0508] Fig.28B is another example of a storage device layout. Fig.28A Likewise, in Fig.28B The plan layout of FIG. 1 shows the conductive layer 115 , the conductive layer 112 , and the opening 121 . Fig.28B The storage device shown is Fig.28A The main differences of the illustrated memory device are: the arrangement of the memory cell 150 (opening 121 ); the shape of the conductive layer 112 ; and the extending direction of the conductive layer 115 .

[0509] like Fig.28B As shown in FIG. 1 , the storage cells 150 (openings 121 ) are arranged in a zigzag shape in the X direction. Fig.28B In the embodiment, the storage unit adjacent to the first storage unit in the Y direction is set as the second storage unit, and the storage unit adjacent to the first storage unit and the second storage unit in the X direction is set as the third storage unit. For example, the center of the third storage unit is preferably located on a straight line passing through the middle of the first storage unit and the second storage unit and parallel to the X direction. In this case, it can also be said that the third storage unit is located at a position halfway between the first storage unit and the second storage unit in the Y direction.

[0510] In addition, if Fig.28B As shown, the conductive layer 112 has a first region and a second region. The first region is the opening 121 and the region in the vicinity thereof, and the width in the X direction in the first region is set to the first width. The first region when viewed from a plane can be said to have a quadrilateral shape with arc-shaped corners. In addition, the second region is the region between adjacent openings 121 in one conductive layer 112, and the width in the X direction in the second region is set to the second width. At this time, the second width is preferably smaller than the first width. By adopting this structure, when the storage unit 150 (opening 121) is configured in a zigzag shape in the X direction, the physical distance between the conductive layers 112 can be reduced. As a result, miniaturization and high integration of the storage device can be achieved.

[0511] In addition, Fig.28BIn the embodiment, the extension direction of the conductive layer 115 is arranged to be inclined with respect to the X direction. That is, depending on the arrangement of the memory cell 150 (opening 121), the extension direction of the conductive layer 115 may not be orthogonal to the extension direction of the conductive layer 112. In other words, the conductive layer 115 may intersect with the conductive layer 112.

[0512] Fig.28C is another example of a storage device layout. Fig.28B Likewise, in Fig.28C The plan layout of FIG. 1 shows the conductive layer 115 , the conductive layer 112 , and the opening 121 . Fig.28C The storage device shown is Fig.28B The main difference in the illustrated memory device is the shape of the first region of the conductive layer 112 .

[0513] Fig.28B The first region of the conductive layer 112 shown has a quadrangular shape with curved corners when viewed from a plane, and one side of the quadrangular shape is parallel to the X direction or the Y direction. Fig.28C The first region of the conductive layer 112 shown has a quadrangular shape with curved corners when viewed from a plane, and the diagonal lines of the quadrangular shape are parallel to the X direction or the Y direction. By adopting this structure, when the memory cells 150 (openings 121) are arranged in a zigzag shape in the X direction, the physical distance between the conductive layers 112 can be reduced. As a result, miniaturization and high integration of the memory device can be achieved.

[0514] Fig.28B and Fig.28C Although an example is shown in which the first region of the conductive layer 112 has a quadrangular shape with curved corners when viewed from a plane, one embodiment of the present invention is not limited to this.

[0515] Fig.29A is another example of a storage device layout. Fig.28B and Fig.28C Likewise, in Fig.29A The plan layout of FIG. 1 shows the conductive layer 115 , the conductive layer 112 , and the opening 121 . Fig.29A The storage device shown is Fig.28B and Fig.28C The main difference in the illustrated memory device is the shape of the first region of the conductive layer 112 .

[0516] Fig.29A The first region of the conductive layer 112 shown has a circular shape when viewed from a plane. By adopting this structure, when the memory cells 150 (openings 121) are arranged in a zigzag shape in the X direction, the physical distance between the conductive layers 112 can be reduced. Thus, miniaturization and high integration of the memory device can be achieved.

[0517] Note that the shape of the first region of the conductive layer 112 when viewed from above is not limited to the above shape. For example, the first region of the conductive layer 112 when viewed from above may have a substantially circular shape such as an ellipse, a polygon such as a quadrangle, or a polygon such as a quadrangle with curved corners.

[0518] in addition, Fig.29A Although the structure in which the width of the conductive layer 115 in the direction perpendicular to the extending direction of the conductive layer 115 is constant is shown, one embodiment of the present invention is not limited to this.

[0519] Fig.29B is another example of a storage device layout. Fig.29A Likewise, in Fig.29B The plan layout of FIG. 1 shows the conductive layer 115 , the conductive layer 112 , and the opening 121 . Fig.29B The storage device shown is Fig.29A The main difference between the illustrated memory devices is the shape of the conductive layer 115 .

[0520] Similar to the conductive layer 112, Fig.29B The conductive layer 115 shown has a first region and a second region. The first region is the opening 121 and the region in the vicinity thereof, and has a circular shape when viewed from a plane. In addition, the second region is the region between adjacent openings 121 in one conductive layer 115. In addition, the first region of the conductive layer 115 overlaps with the first region of the conductive layer 112. By adopting this structure, when the storage cells 150 (openings 121) are arranged in a zigzag shape in the X direction, the physical distance between the conductive layers 112 can be reduced. As a result, miniaturization and high integration of the storage device can be achieved.

[0521] Fig.29C is another example of a storage device layout. Fig.29A Likewise, in Fig.29C The plan layout of FIG. 1 shows the conductive layer 115 , the conductive layer 112 , and the opening 121 . Fig.29C The storage device shown is Fig.29A The main difference between the illustrated memory devices is the shape and extension direction of the conductive layer 115 .

[0522] Fig.29C The conductive layer 115 shown has a meandering shape like a triangular wave when viewed from a plane, and extends in the X direction. By adopting this structure, when the storage cells 150 (openings 121) are arranged in a sawtooth shape in the X direction, the physical distance between the conductive layers 112 can be reduced. As a result, miniaturization and high integration of the storage device can be achieved. In addition, the conductive layer 115 when viewed from a plane is not limited to this, and can also have a meandering shape, for example.

[0523] By adopting the above structure, one or both of the physical distance between the conductive layers 115 and the physical distance between the conductive layers 112 can be reduced, thereby achieving miniaturization and high integration of the storage device.

[0524] A memory device including a 3D memory cell array will be described in detail in the following embodiments.

[0525] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiment modes or examples described in this specification as appropriate.

[0526] (Implementation Method 2)

[0527] In this embodiment mode, a structural example of a memory device using the memory cell described in the above embodiment mode is described. In this embodiment mode, a structural example of a memory device is described in which a layer including a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers including stacked memory cells.

[0528] <Configuration Example of Storage Device>

[0529] Fig.30 : is a block diagram showing a configuration example of a storage device 400 according to one embodiment of the present invention. Fig.30 The memory device 400 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.

[0530] Fig.30 The example in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2) is shown. In addition, as an example, a functional circuit 51 is provided for each wiring BL used as a bit line. Fig.30 An example is shown in which a plurality of functional circuits 51 are provided corresponding to n wirings BL.

[0531] exist Fig.30, the 1st row and 1st column storage cell 10 is represented as storage cell 10[1, 1], and the mth row and nth column storage cell 10 is represented as storage cell 10[m, n]. In addition, for example, in the present embodiment, sometimes the i-th row is recorded to represent an arbitrary row. In addition, sometimes the j-th column is recorded to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, for example, in the present embodiment, the i-th row and j-th column storage cell 10 is represented as storage cell 10[i, j]. Note that, for example, in the present embodiment, when represented as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when represented as "j+α", "j+α" is not less than 1 and not greater than n.

[0532] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. For example, in the present embodiment, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n].

[0533] The plurality of memory cells 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0534] The memory array 20 may use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, and is a memory in which the access transistor is an OS transistor. When the OS transistor is in the off state, the current flowing between the source and the drain, that is, the leakage current is extremely small. In DOSRAM, by turning off the access transistor, the charge according to the data held in the capacitor can be maintained for a long time. Therefore, compared with a DRAM composed of Si transistors, the frequency of refresh operation of DOSRAM can be lower. As a result, low power consumption can be achieved.

[0535] In addition, the memory cell 10 can be stacked by stacking OS transistors as described in Embodiment 1. Fig.30In the memory array 20 shown, a plurality of memory arrays 20[1] to 20[m] may be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the memory density of the memory cell 10 can be increased. In addition, the memory array 20 can be manufactured repeatedly using the same manufacturing process in the vertical direction. The memory device 400 can reduce the manufacturing cost of the memory array 20. Thus, the memory device 400 can be an inexpensive memory device.

[0536] As described in Embodiment 1, wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the on or off state of an access transistor used as a switch. Wiring PL is used as a constant potential line connected to a capacitor.

[0537] The memory cells 10 included in the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the driving circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. In addition, the operation can be performed even if the capacitance value included in the memory cell 10 is reduced.

[0538] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cell 10 included in the memory array 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0539] In addition, the wiring BL is provided in a manner of contacting the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in a manner of contacting a region of the semiconductor layer of the transistor included in the memory cell 10 that functions as a source or a drain. Alternatively, the wiring BL is provided in a manner of contacting a conductive layer that functions as a source or a drain in a region of the semiconductor layer of the transistor included in the memory cell 10. That is, the wiring BL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0540] The memory array 20 can be overlapped on the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 400 can be miniaturized.

[0541] By forming the functional circuit 51 with OS transistors similarly to the transistors included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors similarly to the memory arrays 20[1] to 20[m], thereby making it easy to integrate. By adopting a structure in which the functional circuit 51 amplifies the signal, the circuits such as the sense amplifier 46 of the subsequent circuit can be miniaturized, thereby miniaturizing the memory device 400.

[0542] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31 . The peripheral circuit 31 includes a peripheral circuit 41 , a control circuit 32 (control circuit) and a voltage generation circuit 33 .

[0543] In the storage device 400, each circuit, each signal, and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0544] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 can also be generated in the control circuit 32.

[0545] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 400. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 400. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0546] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0547] The peripheral circuit 41 is a circuit for writing and reading data to the memory cell 10. In addition, the peripheral circuit 41 is a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42 (RowDecoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (ColumnDriver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (SenseAmplifier).

[0548] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0549] The input circuit 47 has a function of holding a signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 400. The data output from the output circuit 48 is a signal RDA.

[0550] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 400 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig.30 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0551] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer greater than or equal to 2) and a functional layer 50. A plurality of layers of memory arrays 20 may be overlapped on the drive circuit 21. By overlapping a plurality of layers of memory arrays 20, the memory density of the memory cell 10 may be increased. Fig.31A 1 is a perspective view of a storage device 400 showing a case where five layers (m=5) of memory arrays 20 [ 1 ] to 20 [ 5 ] and a functional layer 50 are stacked on a drive circuit 21 .

[0552] exist Fig.31A In the embodiment, the memory array 20 provided in the first layer is referred to as the memory array 20[1], the memory array 20 provided in the second layer is referred to as the memory array 20[2], and the memory array 20 provided in the fifth layer is referred to as the memory array 20[5]. Fig.31A The wiring WL and the wiring PL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that in order to make the drawings easier to understand, a part of the wiring WL and the wiring PL included in each of the memory arrays 20 is omitted. Note that Fig.31A Although the wiring PL is extended in the X direction, one embodiment of the present invention is not limited thereto. For example, the wiring PL may be extended in the Y direction, or in both the X and Y directions, or may be provided in a planar shape.

[0553] Fig.31B Yes Description Fig.31A FIG. 1 is a schematic diagram showing an example of a structure of a functional circuit 51 connected to the wiring BL and a memory cell 10 included in the memory array 20 [1] to 20 [5] connected to the wiring BL. Fig.31B The wiring GBL provided between the functional circuit 51 and the driving circuit 21 is shown. In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (memory cells 10) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for improved visibility.

[0554] Fig.31B An example of a circuit structure of a memory cell 10 connected to a wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. With respect to the transistor 11, the capacitor 12, and each wiring (wiring BL, wiring WL, etc.), for example, wiring BL[1] and wiring WL[1] are sometimes referred to as wiring BL and wiring WL, etc.

[0555] Fig.31B The storage unit 10 shown corresponds to the first embodiment, for example, Fig.22D1 The memory cell 150 shown. In addition, the transistor 11 and the capacitor 12 included in the memory cell 10 correspond to the transistor 100 and the capacitor 200, respectively. Fig.31B The example shown is one in which the second gate electrodes of the four transistors 11 are electrically connected to the same wiring BG.

[0556] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 12 .

[0557] Fig.31B The wiring GBL shown is provided so as to electrically connect the driving circuit 21 and the functional layer 50 . Fig.32A FIG. 4 is a schematic diagram showing a memory device 400 with a functional layer 50 and memory arrays 20 [ 1 ] to 20 [ m ] as a repeating unit 70 . Fig.32A One wiring GBL is shown in the figure, but the wiring GBL may be appropriately provided according to the number of functional circuits 51 in the functional layer 50 .

[0558] In addition, the wiring GBL is provided in a manner in contact with the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in a manner in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. Alternatively, the wiring GBL is provided in a manner in contact with a conductive layer that contacts a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. That is, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0559] Alternatively, a structure may be provided in which a repeating unit 70 including a functional circuit 51 and memory arrays 20[1] to 20[m] is stacked. Fig.32B The repeating units 70 [1] to 70 [p] (p is an integer greater than or equal to 2) may be included. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately provided according to the number of functional circuits 51.

[0560] In one embodiment of the present invention, while stacking OS transistors, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the driver circuit 21. By a...

Claims

1. A semiconductor device comprising: transistor; a first insulating layer; as well as The second insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer and a third insulating layer. The first insulating layer is disposed on the first conductive layer, The second conductive layer is disposed on the first insulating layer, The second insulating layer is disposed on the second conductive layer, The third conductive layer is disposed on the second insulating layer, The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are provided with openings reaching the first conductive layer. The second conductive layer is provided with an oxide region including a side surface in the opening, The semiconductor layer is provided so as to have a region located inside the opening, The semiconductor layer has a region in contact with the first conductive layer, a region in contact with the oxide region, and a region in contact with the third conductive layer. The third insulating layer is provided on the semiconductor layer so as to have a region located inside the opening. Furthermore, the fourth conductive layer is provided so as to have a region located inside the opening and a region facing the semiconductor layer with the third insulating layer interposed therebetween.

2. The semiconductor device according to claim 1, The oxide region includes an oxide of a material included in the second conductive layer.

3. The semiconductor device according to claim 1, The second conductive layer and the fourth conductive layer have a region sandwiching a channel formation region of the semiconductor layer inside the opening.

4. The semiconductor device according to claim 1, The first conductive layer includes a first layer and a second layer, The second layer is disposed on the first layer, The semiconductor layer has a region in contact with a top surface of the first layer and a region in contact with a side surface of the second layer.

5. The semiconductor device according to claim 1, The first insulating layer includes a first layer, a second layer and a third layer, The second insulating layer includes a fourth layer, a fifth layer and a sixth layer, The second layer is disposed on the first layer, The third layer is disposed on the second layer, The fifth layer is disposed on the fourth layer, The sixth layer is disposed on the fifth layer, And the first layer, the third layer, the fourth layer and the sixth layer contain nitrogen.

6. The semiconductor device according to claim 5, The second layer and the fifth layer contain oxygen.

7. The semiconductor device according to any one of claims 1 to 6, The semiconductor layer comprises a metal oxide.

8. The semiconductor device according to claim 7, wherein the metal oxide comprises one or more selected from indium, zinc and element M, And the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony.

9. An electronic device, comprising: The semiconductor device according to any one of claims 1 to 6; as well as camera.

10. A method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; forming a third conductive layer on the second insulating layer; forming an opening reaching the first conductive layer in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer; forming an oxide region in the second conductive layer by performing oxidation treatment on the side surface of the opening of the second conductive layer; forming a semiconductor layer so as to have a region located inside the opening and having a region in contact with the first conductive layer, a region in contact with the oxide region, and a region in contact with the third conductive layer; forming a third insulating layer on the semiconductor layer so as to have a region located inside the opening; as well as The fourth conductive layer is formed to have a region located inside the opening and a region facing the semiconductor layer with the third insulating layer interposed therebetween.

11. The method for manufacturing a semiconductor device according to claim 10, The oxidation treatment is performed by microwave treatment in an oxygen-containing atmosphere.

12. The method for manufacturing a semiconductor device according to claim 10, wherein a first layer and a second layer on the first layer are formed as the first conductive layer, After forming the third conductive layer, an opening reaching the second layer is formed in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer. After the oxidation treatment and before forming the semiconductor layer, a region of the second layer overlapping the opening is removed.

13. The method for manufacturing a semiconductor device according to claim 10, After forming the opening and before forming the oxide region, a side surface of the second conductive layer in the opening is processed.

14. The method for manufacturing a semiconductor device according to claim 13, The processing is carried out by isotropic etching.

15. The method for manufacturing a semiconductor device according to claim 11, wherein after forming the opening and before forming the oxide region, a fourth insulating layer having a region in the opening in contact with a side surface of the second conductive layer is formed, Carrying out the oxidation treatment, removing the fourth insulating layer, And forming the semiconductor layer.

16. The method for manufacturing a semiconductor device according to claim 15, Wherein as the first insulating layer, a first layer, a second layer on the first layer, and a third layer on the second layer are formed, As the second insulating layer, a fourth layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer are formed, The fourth insulating layer is formed in a manner to have a region in contact with the top surface of the sixth layer, The fourth insulating layer contains oxygen, And the sixth layer contains nitrogen.

17. The method for manufacturing a semiconductor device according to claim 16, The first layer, the third layer and the fourth layer contain nitrogen.

18. The method for manufacturing a semiconductor device according to claim 17, The second layer and the fifth layer contain oxygen.

19. The method for manufacturing a semiconductor device according to any one of claims 10 to 18, The semiconductor layer comprises a metal oxide.

20. The method for manufacturing a semiconductor device according to claim 19, wherein the metal oxide comprises one or more selected from indium, zinc and element M, And the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony.

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